Method for forming low dielectric materials

Abstract

A semiconductor processing method for forming a low dielectric material is described. This method may include supplying a deposition precursor to a processing region of a semiconductor processing chamber. The deposition precursor may include a silicon-carbon-hydrogen-containing precursor. A substrate may be placed within the processing region. This method may include forming a plasma emission of the deposition precursor. This method may include depositing a layer of silicon-containing material on the substrate. The layer of silicon-containing material may be characterized by a dielectric constant of approximately 4.0 or less.

Description

[Technical Field]

[0001] Cross-reference with related applications

[0001] This application claims the benefit and priority of U.S. Patent Application Publication No. 18 / 139699, filed on 26 April 2023, entitled “METHODS FOR FORMING LOW-K DIELECTRIC MATERIALS” (which is incorporated herein by reference in its entirety).

[0002] Technical field

[0002] The present invention relates to a deposition method and a chamber. More specifically, the present invention relates to a method for producing a low dielectric constant material. [Background technology]

[0003]

[0003] Integrated circuits are realized by a process that generates intricately patterned material layers on the surface of a substrate. Generating patterned material on a substrate requires a controlled method for forming and removing the material. The properties of the material can affect the operation of the device and can also affect how the materials are removed from each other. Plasma-enhanced deposition can generate materials with specific properties that can affect the performance of the device. The properties of the material can be adjusted or improved by changing the deposition conditions, such as the chemical properties and frequency of the plasma.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used in the manufacture of high-quality equipment and structures. The technology of the present invention addresses these and other needs. [Overview of the project]

[0005]

[0005] Embodiments of the present technology include a semiconductor processing method capable of forming a low dielectric constant dielectric material. The method may include supplying a deposition precursor to a processing area of ​​a semiconductor processing chamber. The deposition precursor may include a silicon-carbon-hydrogen-containing precursor. A substrate may be placed within the processing area. The method may include forming a plasma emission of the deposition precursor. The method may include depositing a layer of silicon-containing material on the substrate. The layer of silicon-containing material may be characterized by a dielectric constant of about 4.0 or less.

[0006]

[0006] In some embodiments, the silicon-carbon-hydrogen-containing precursor may be bis(trimethylsilyl)methane or 1,1,3,3-tetramethyl-1,3-disilacyclobutane, or may contain either of these. The silicon-carbon-hydrogen-containing precursor may further contain oxygen. The silicon-carbon-hydrogen-containing precursor may be dimethyldimethoxysilane, 1,1,3,3-tetramethyl-1,3-dimethoxydisiloxane, or methoxy(dimethyl)silylmethane, or may contain any of these. The deposition precursor may further contain a boron-containing precursor, a nitrogen-containing precursor, or both. The boron-containing precursor may be diborane (B2H6), or may contain this. The layer of silicon-containing material may be characterized by a thickness of about 50A or less. The layer of silicon-containing material is about 2.50g / cm 3 The silicon-containing material may be characterized by the above densities. Layers of silicon-containing material may be deposited at a rate of approximately 200 A / min or more. This method may include exposing layers of silicon-containing material to ultraviolet light in order to provide a cured layer of silicon-containing material. The cured layer of silicon-containing material may be characterized by a stress of -150 MPa or less or a stress of approximately -150 MPa.

[0007]

[0007] Some embodiments of the present technology may encompass a semiconductor processing method. The method may include supplying a deposition precursor to a processing area of ​​a semiconductor processing chamber. The deposition precursor may include a silicon-containing precursor and a dopant-containing precursor. A substrate may be placed within the processing area. The method may include forming a plasma emission of the deposition precursor. The method may include depositing a layer of silicon-containing material on the substrate. The layer of silicon-containing material may be characterized by a dielectric constant of about 4.0 or less. The layer of silicon-containing material weighs about 2.30 g / cm 3 It may be characterized by the above densities.

[0008]

[0008] In some embodiments, the silicon-containing precursor may include a silicon-carbon-hydrogen-containing precursor or a silicon-oxygen-carbon-hydrogen-containing precursor. The dopant precursor may be a boron-containing precursor. The flow rate of the dopant precursor can be 1000 sccm or less. The silicon-containing material layer may be characterized by a breakdown voltage of 6.0 MV / cm or more. The silicon-containing material layer may be characterized by a dielectric constant of about 3.3 or less. The temperature in the processing area may be maintained at about 500°C or less.

[0009]

[0009] Some embodiments of the present technology may encompass a semiconductor processing method. The method may include supplying a deposition precursor to a processing area of ​​a semiconductor processing chamber. The deposition precursor may include a silicon-containing precursor and a boron-containing precursor. A substrate may be placed within the processing area. The method may include forming a plasma emission of the deposition precursor. The method may include depositing a layer of silicon-containing material on the substrate. The layer of silicon-containing material may be characterized by a dielectric constant of about 3.5 or less. The layer of silicon-containing material weighs about 2.50 g / cm 3 It may be characterized by the above densities.

[0010]

[0010] In some embodiments, the method may include exposing a layer of silicon-containing material to ultraviolet light in order to provide a cured layer of silicon-containing material. The layer of silicon-containing material may be characterized by a boron concentration of about 20.0 at.% or less.

[0011]

[0011] Such techniques can offer many advantages compared to conventional processing methods. For example, by utilizing silicon-containing precursors containing oxygen, carbon, and / or hydrogen, the atomic structure of the material can be altered, and the dielectric constant of the material can be reduced without affecting mechanical properties such as density. Furthermore, by incorporating dopant precursors, the atomic structure of the material can be further altered, and the dielectric constant of the material can be reduced without affecting mechanical properties. These numerous advantages and features, along with other embodiments, will be described in more detail below in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0012]

[0012] A further understanding of the nature and advantages of the disclosed technology can be obtained by referring to the remainder of this specification and the drawings.

[0013] [Figure 1]

[0013] An exemplary top view of a processing system according to several embodiments of the present technology is shown. [Figure 2]

[0014] A schematic cross-sectional view of an exemplary plasma system according to several embodiments of this technology is shown. [Figure 3]

[0015] The steps of an exemplary method for semiconductor processing according to several embodiments of this technology are shown. [Modes for carrying out the invention]

[0014]

[0016] Some of these figures are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes and that scale should not be taken into account unless otherwise indicated. Further, as schematic diagrams, the figures are provided to aid understanding and may not include all aspects or information compared to actual representations, and may include exaggerated content for illustrative purposes.

[0015]

[0017] In the accompanying drawings, similar components and / or features may have the same reference numerals. Further, various components of the same type can be distinguished according to the reference numerals by letters that distinguish between similar components. When only the first reference numerals are used herein, the description is applicable to any of the similar components having the same first reference numeral, regardless of the letters.

[0016]

[0018] During back-end-of-line (BEOL) semiconductor processing, low dielectric constant materials may perform multiple functions in the manufacture of the metallization layers of integrated circuits. These functions may include incorporating a low dielectric constant material having electrical insulation between conductive metal-containing structures such as interconnect lines, contact holes, vias, etc. These functions may also include partially removing the low dielectric constant material after the formation of the metal structure. One common removal process in BEOL processing is chemical mechanical polishing (CMP), which removes the low dielectric constant material from the substrate surface using a combination of chemical etching and physical polishing.

[0017]

[0019] The low dielectric constant materials used in BEOL processing need to have a low dielectric constant (κ value) compared to undoped silicon oxide and high mechanical stability to withstand breakage during the formation of metal-containing structures and during removal by CMP. However, in low dielectric constant materials, these properties often have an inverse relationship. In many cases, the porosity of the material increases due to the deposition process and the processing steps, and the increase in porosity may reduce the mechanical stability of the material. Furthermore, when the amount of carbon in the material increases, the κ value decreases and the mechanical stability of the material may also decrease. Among the mechanical properties, a decrease in mechanical stability can be measured by the material having a low density.

[0018]

[0020] The present technology can overcome these problems by including embodiments of a semiconductor processing method for forming a low dielectric constant material with excellent mechanical stability. In the embodiments, these low dielectric constant materials can be formed by using specific precursors to modify the atomic structure of the deposited material. The present technology can provide a silicon-containing low dielectric constant material characterized by a low dielectric constant (κ value) of about 4.0 or less. Furthermore, embodiments of the method maintain the mechanical stability of the low dielectric constant (κ value) material. The material may be characterized by a density of about 2.30 g / cm 3 or higher. Additionally, in some embodiments, ultraviolet (UV) treatment can be performed to further enhance the desired properties of the material.

[0019]

[0021] The remaining disclosure repeatedly shows a specific deposition process that utilizes the present disclosed technology, but it will be readily understood that these systems and methods are equally applicable to other deposition chambers and processes that can be performed within the described chamber. Therefore, the present technology should not be considered limited to use only in these specific deposition processes or chambers. In the present disclosure, prior to providing a more detailed description according to embodiments of the present technology, one system and chamber that can be used to execute a deposition process according to embodiments of the present technology will be described.

[0020]

[0022] Figure 1 shows a top view of one embodiment of a processing system 100, which includes a deposition chamber, an etching chamber, a baking chamber, and a UV processing chamber, according to an embodiment. In this figure, a pair of front-opening unified pods 102 supply substrates of various sizes. These substrates are received by a robotic arm 104, placed in a low-pressure holding area 106, and then placed in one of the substrate processing chambers 108a-f located in tandem sections 109a-c. A second robotic arm 110 may be used to transport substrate wafers from the holding area 106 to and from the substrate processing chambers 108a-f. Each substrate processing chamber 108a-f can be configured to perform multiple substrate processing steps, including plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, etching, UV processing, pre-cleaning, degassing, orientation, and other substrate processing (annealing, ashing, etc.).

[0021]

[0023] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, UV treating, and / or etching dielectric or other materials on a substrate. In one configuration, two pairs of processing chambers (e.g., 108c-d and 108e-f) may be used to deposit dielectric material on the substrate. A third pair of processing chambers (e.g., 108a-b) may be used to etch the deposited dielectric. In another configuration, three pairs of chambers, e.g., 108a-f, may all be configured to deposit alternating stacks of dielectric material on the substrate. One or more of the described processes may be performed in chambers separated from the manufacturing system shown in different embodiments. It will be understood that system 100 intends for additional configurations of dielectric material deposition chambers, etching chambers, annealing chambers, and UV treatment chambers.

[0022]

[0024] Figure 2 shows a schematic cross-sectional view of an exemplary plasma system 200 according to several embodiments of the present technology. The plasma system 200 may include a pair of processing chambers 108 that can be attached to one or more of the tandem sections 109 described above, which may include lid stack components according to embodiments of the present technology, and may be described in further detail below. The plasma system 200 may generally include a chamber body 202 having side walls 212, a bottom wall 216, and an internal side wall 201 that define a pair of processing regions 220A and 220B. Each of the processing regions 220A and 220B may be similarly configured and may include the same components.

[0023]

[0025] For example, the processing area 220B may include components that are part of the processing area 220A, and may include a pedestal 228 positioned in the processing area through a passage 222 formed in the bottom wall 216 of the plasma system 200. The pedestal 228 can provide a heater adapted to support a substrate 229 on an exposed surface of the pedestal, such as a body portion. The pedestal 228 may include a heating element 232, such as a resistive heating element, which can heat and control the substrate temperature at a desired processing temperature. The pedestal 228 may be heated by a remote heating element, such as a lamp assembly, or by other heating devices.

[0024]

[0026] The body of the pedestal 228 can be coupled to the stem 226 by a flange 233. The stem 226 can electrically couple the pedestal 228 to a power outlet or power box 203. The power box 203 may include a drive system to control the raising and moving of the pedestal 228 within the processing area 220B. The stem 226 may also include a power interface for supplying power to the pedestal 228. The power box 203 may also include interfaces for power and temperature indicators, such as a thermocouple interface. The stem 226 may include a base assembly 238 adapted to be detachably coupled to the power box 203. A circumferential ring 235 is shown above the power box 203. In some embodiments, the circumferential ring 235 may be a shoulder adapted as a mechanical stopper or land configured to provide a mechanical interface between the base assembly 238 and the top surface of the power box 203.

[0025]

[0027] The rod 230 is provided through a passage 224 formed in the bottom wall 216 of the processing area 220B and can also be used to position the substrate lift pin 261, which is positioned through the body of the pedestal 228. The substrate lift pin 261 can selectively separate the substrate 229 from the pedestal to facilitate replacement with a robot used to move the substrate 229 into and out of the processing area 220B via the substrate transfer port 260.

[0026]

[0028] The chamber lid 204 may be coupled to the top of the chamber body 202. The lid 204 may correspond to one or more precursor distribution systems 208 coupled thereto. The precursor distribution system 208 may include a precursor inlet passage 240 that can deliver reactants and washing precursors into the processing area 220B through a dual-channel showerhead 218. The dual-channel showerhead 218 may include an annular base plate 248 having a blocker plate 244 positioned in the middle of the faceplate 246. A radio frequency ("RF") source 265 may be connected to the dual-channel showerhead 218 to power the dual-channel showerhead 218, thereby facilitating the generation of a plasma region between the faceplate 246 and the pedestal 228 of the dual-channel showerhead 218. The dual-channel showerhead 218 and / or faceplate 246 may include one or more openings that allow the flow of precursors from the precursor distribution system 208 to the processing area 220A and / or 220B. In some embodiments, the opening may include at least one of a linear opening and a conical opening. In some embodiments, an RF source may be connected to other parts of the chamber body 202, such as a pedestal 228, to facilitate plasma generation. A dielectric isolator 258 may be placed between the lid 204 and the dual-channel showerhead 218 to prevent the conduction of RF power to the lid 204. A shadow ring 206 that engages with the pedestal 228 may be placed around the pedestal 228.

[0027]

[0029] To cool the annular base plate 248 during operation, optional cooling channels 247 can be formed within the annular base plate 248 of the precursor distribution system 208. A heat transfer fluid such as water, ethylene glycol, or gas can be circulated through the cooling channels 247 to maintain the base plate 248 at a predetermined temperature. To prevent the side walls 201, 212 from being exposed to the processing environment within the processing area 220B, a liner assembly 227 can be positioned within the processing area 220B in close proximity to the side walls 201, 212 of the chamber body 202. The liner assembly 227 may include a circumferential pumping cavity 225 that can be coupled to a pumping system 264 configured to discharge gases and by-products from the processing area 220B and to control the pressure within the processing area 220B. Multiple exhaust ports 231 can be formed on the liner assembly 227. The exhaust port 231 may be configured to allow gas flow from the processing area 220B to the circumferential pumping cavity 225 in a manner that facilitates processing within the system 200.

[0028]

[0030] Figure 3 shows the steps of an exemplary method 300 for semiconductor processing according to several embodiments of the present technology. The method can be carried out in various processing chambers, including the processing system 200 described above, as well as in any other chamber in which plasma deposition may be performed. Method 300 may include several optional steps, which may or may not be specifically associated with some embodiments of the method according to the present technology.

[0029]

[0031] Method 300 may include a plasma-enhanced chemical vapor deposition (PECVD) process for forming a low dielectric constant material immediately after deposition. Method 300 may include optional steps before starting Method 300, or it may include additional steps after deposition of the low dielectric constant material, such as UV treatment of the low dielectric constant material. In an embodiment, as shown in Figure 3, Method 300 may include supplying a deposition precursor to the processing area of ​​a semiconductor processing chamber in step 305. Once the deposition precursor is supplied into the chamber, the substrate may be housed in the processing area of ​​the semiconductor processing chamber.

[0030]

[0032] In some embodiments, the deposition precursor may include a silicon-containing precursor. Examples of usable silicon-containing precursors include, but are not limited to, silane (SiH4), disilane (Si2H6), or tetraethyl orthosilicate (TEOS). In embodiments, the silicon-containing precursor may further contain carbon and hydrogen. Specific silicon-carbon-hydrogen-containing precursors include, but are not limited to, bis(trimethylsilyl)methane or 1,1,3,3-tetramethyl-1,3-disilacyclobutane. Some silicon-containing precursors may further contain oxygen, carbon, and hydrogen. For example, specific silicon-oxygen-carbon-hydrogen-containing precursors include, but are not limited to, dimethyldimethoxysilane, 1,1,3,3-tetramethyl-1,3-dimethoxydisiloxane, or methoxy(dimethyl)silylmethane.

[0031]

[0033] The deposition precursor may further contain one or more dopant precursors, such as boron-containing precursors. Available boron-containing precursors include, but are not limited to, borane (BH3), diborane (B2H6), trimethylboron ((CH3)3B), and other boron-containing precursors that can be used to form boron-doped silicon-containing materials. In embodiments, the flow rate of the boron-containing precursor to the flow rate of the silicon-containing precursor may be maintained at a flow rate ratio that promotes the formation of a low dielectric constant material having both a low dielectric constant (κ value) and high mechanical stability, particularly reflected in material properties such as refractive index and density. In embodiments, the flow rate ratio of the boron-containing precursor to the silicon-containing precursor may be about 1:5 or less, about 1:6 or less, about 1:7 or less, about 1:8 or less, about 1:9 or less, or about 1:10.

[0032]

[0034] By utilizing silicon-containing precursors containing oxygen, carbon, and / or hydrogen, as well as boron-containing precursors, such as the specific precursors mentioned above, various Si-N, CN, Si-B, and CB bonds can be formed to reduce the dielectric constant of the material. The deposition precursor may also contain one or more carrier gases, such as helium, argon, and nitrogen (N2). One or more carrier gases may be supplied together with other deposition precursors, but the carrier gases can be considered inert gases that do not react in order to form part of the material immediately after deposition. One or more carrier gases may also be supplied together with other deposition precursors to function as diluents.

[0033]

[0035] The flow rate of the silicon-containing precursor can be approximately 100 sccm or more, approximately 125 sccm or more, approximately 150 sccm or more, approximately 175 sccm or more, approximately 200 sccm or more, approximately 250 sccm or more, approximately 300 sccm or more, approximately 400 sccm or more, approximately 500 sccm or more, or higher. The flow rate of the boron-containing precursor can be approximately 5 sccm or more, approximately 10 sccm or more, approximately 15 sccm or more, approximately 20 sccm or more, approximately 25 sccm or more, approximately 30 sccm or more, approximately 35 sccm or more, approximately 40 sccm or more, approximately 45 sccm or more, approximately 50 sccm or more, approximately 55 sccm or more, approximately 60 sccm or more, approximately 65 sccm or more, approximately 70 sccm or more, approximately 75 sccm or more, approximately 80 sccm or more, approximately 90 sccm or more, approximately 100 sccm or more, or higher. The flow rate of the boron-containing precursor may also be approximately 1250 sccm or less, approximately 1000 sccm or less, approximately 750 sccm or less, approximately 500 sccm or less, approximately 400 sccm or less, approximately 300 sccm or less, or less. The flow rate of one or more carrier gases may be approximately 200 sccm or more, approximately 300 sccm or more, approximately 400 sccm or more, approximately 500 sccm or more, approximately 750 sccm or more, approximately 1000 sccm or more, approximately 2000 sccm or more, approximately 3000 sccm or more, approximately 3000 sccm or more, approximately 4000 sccm or more, approximately 5000 sccm or more, or more. The flow rate of the composite deposition precursor may be approximately 250 sccm or more, approximately 500 sccm or more, approximately 750 sccm or more, approximately 1000 sccm or more, approximately 2500 sccm or more, approximately 5000 sccm or more, or more.

[0034]

[0036] In the embodiment, the deposition precursor supplied to the processing area of ​​the semiconductor processing chamber can have its pressure in the chamber changed. During method 300, the pressure in the semiconductor processing chamber can be about 1 Torr or more, about 2 Torr or more, about 3 Torr or more, about 4 Torr or more, about 5 Torr or more, about 6 Torr or more, about 7 Torr or more, about 8 Torr or more, about 9 Torr or more, about 10 Torr or more, or higher.

[0035]

[0037] Embodiments of Method 300 may include forming plasma emitters from a deposited precursor in step 310. Plasma emitters may be generated from deposited precursors within a processing area, for example, by supplying RF power to a faceplate to generate plasma within the processing area of ​​a semiconductor processing chamber. Plasma emitters can be generated at any of the aforementioned frequencies, and can be generated at frequencies below 15 MHz (e.g., 13.56 MHz). Higher frequencies can also be used, but plasma generation at lower frequencies may facilitate carbon removal during processing, unlike high-frequency plasma operation.

[0036]

[0038] Embodiments of Method 300 may include, in step 315, depositing a silicon-containing material onto a substrate. As previously stated, the substrate may be located in the processing area of ​​a semiconductor processing chamber, and the silicon-containing material may be formed from plasma h emissions generated by the deposition plasma, which is also located in the processing area. The processing area, and therefore the substrate, may be characterized by temperatures during deposition of approximately 600°C or less, approximately 580°C or less, approximately 560°C or less, approximately 540°C or less, approximately 520°C or less, approximately 500°C or less, approximately 480°C or less, approximately 460°C or less, approximately 440°C or less, approximately 420°C or less, approximately 400°C or less, approximately 380°C or less, approximately 360°C or less, approximately 340°C or less, approximately 320°C or less, and approximately 300°C or less.

[0037]

[0039] When a dopant precursor such as a boron-containing precursor is provided, the dopant concentration in the material can be controlled based on the flow rate of the precursor. For example, the boron concentration in the material may be about 20.0 at.% or less, about 19.0 at.% or less, about 18.0 at.% or less, about 17.0 at.% or less, about 16.0 at.% or less, about 15.0 at.% or less, about 14.0 at.% or less, about 13.0 at.% or less, about 12.0 at.% or less, about 11.0 at.% or less, about 10.0 at.% or less, about 9.0 at.% or less, about 8.0 at.% or less, about 7.0 at.% or less, about 6.0 at.% or less, about 5.0 at.% or less, about 4.0 at.% or less, or about 3.0 at.% or less.

[0038]

[0040] As described above, embodiments of the method of the present technology include those that utilize deposition precursors and processing conditions to form a low dielectric constant material having a low dielectric constant and high mechanical stability. In an embodiment of method 300, the low dielectric constant material immediately after deposition can be formed as a silicon-containing material having a dielectric constant of about 4.0 or less, about 3.9 or less, about 3.8 or less, about 3.7 or less, about 3.6 or less, about 3.5 or less, about 3.4 or less, about 3.3 or less, about 3.2 or less, about 3.1 or less, about 3.0 or less, about 2.9 or less, about 2.8 or less, about 2.7 or less, about 2.6 or less, about 2.5 or less. In an embodiment, the density of the formed material is about 2.30 g / cm 3 or more, about 2.40 g / cm 3 or more, about 2.50 g / cm 3 or more, about 2.55 g / cm 3 or more, about 2.60 g / cm 3 or more, about 2.65 g / cm 3 or more, about 2.70 g / cm 3 or more, about 2.75 g / cm 3 or more, about 2.80 g / cm 3 or more, about 2.85 g / cm 3 or more, about 2.90 g / cm 3 or more.

[0039]

[0041] Depending on the deposition precursor used, materials with higher compressive properties may be deposited. Low-stress materials can be characterized by an internal stress level close to neutral stress (i.e., 0 MPa). High-stress materials, on the other hand, are characterized by an internal stress level that is significantly above 0 MPa (i.e., high positive (tensile) stress) or significantly below 0 MPa (i.e., high negative (compressive) stress). High positive stress (which can be characterized as tensile stress) can result from the expansion of the material, creating outward pressing forces on adjacent substrate features. High negative stress (which can be characterized as compressive stress) can result from the contraction of the material, creating inward tensile forces on adjacent substrate features. In other words, high-stress materials can be characterized by a stress level whose absolute value is significantly above 0 MPa. Therefore, when a material is characterized by a stress level "above -1000 MPa", this description refers to the absolute value of the stress level, including levels such as -1500 MPa and -2000 MPa. Similarly, when a material is characterized by a stress level "below -1000 MPa", this description refers to a stress level close to the neutral stress (i.e., 0 MPa), including levels such as -500 MPa and -100 MPa, but not to positive values ​​of approximately 1000 MPa or higher. For example, if the deposition precursor contains a boron-containing precursor, increasing the flow rate of the boron-containing precursor may result in the deposition of a more compressed material. In embodiments, the material immediately after deposition may be characterized by a stress of approximately -150 MPa or higher, and may also be characterized by stresses of approximately -175 MPa or higher, approximately -200 MPa or higher, approximately -225 MPa or higher, approximately -250 MPa or higher, approximately -275 MPa or higher, approximately -300 MPa or higher, approximately -325 MPa or higher, approximately -350 MPa or higher, approximately -375 MPa or higher, approximately -400 MPa or higher, or higher. In embodiments, increasing the flow rate of the boron-containing precursor may increase the stress.

[0040]

[0042] Furthermore, increasing the flow rate of the boron-containing precursor may increase the refractive index of the material immediately after deposition. The refractive index serves as an indicator of film composition, and an increase in the refractive index correlates with high-density material. In the embodiment, the refractive index of the material immediately after deposition may be approximately 1.70 or higher, approximately 1.75 or higher, approximately 1.80 or higher, approximately 1.82 or higher, approximately 1.84 or higher, approximately 1.85 or higher, approximately 1.86 or higher, approximately 1.87 or higher, approximately 1.88 or higher, approximately 1.89 or higher, or approximately 1.90 or higher.

[0041]

[0043] Materials according to embodiments of this technology may be characterized by a breakdown voltage of approximately 5.8 MV / cm or higher, or by a breakdown voltage of approximately 5.9 MV / cm or higher, approximately 6.0 MV / cm or higher, approximately 6.1 MV / cm or higher, approximately 6.2 MV / cm or higher, approximately 6.3 MV / cm or higher, approximately 6.4 MV / cm or higher, approximately 6.5 MV / cm or higher, approximately 6.6 MV / cm or higher, approximately 6.7 MV / cm or higher, approximately 6.8 MV / cm or higher, approximately 6.9 MV / cm or higher, approximately 7.0 MV / cm or higher, approximately 7.1 MV / cm or higher, approximately 7.2 MV / cm or higher, or higher. As the flow rate of the boron-containing precursor increases, and therefore the boron concentration in the material increases, the breakdown voltage may decrease. An increase in boron concentration may increase the number of BN bonds in the material, which may result in a decrease in the breakdown voltage.

[0042]

[0044] Depending on the flow rate of the deposition precursor, the delta stress of the material immediately after deposition may be approximately 400 MPa or less. At certain boron-containing precursor flow rates (e.g., approximately 25 sccm or more), the delta stress may reach its upper limit. Furthermore, increasing the flow rate of the nitrogen-containing precursor may also increase the delta stress. By adjusting the flow rate of the deposition precursor, the delta stress of the material immediately after deposition can be maintained at approximately 400 MPa or less. For example, the delta stress can be approximately 375 MPa or less, approximately 350 MPa or less, approximately 325 MPa or less, approximately 300 MPa or less, approximately 275 MPa or less, approximately 250 MPa or less, approximately 225 MPa or less, approximately 200 MPa or less, approximately 175 MPa or less, or even lower. A low delta stress value may correlate with good airtightness of the material.

[0043]

[0045] Embodiments of Method 300 may further include, in an optional step 320, exposure of the silicon-carbon-containing material immediately after deposition to ultraviolet (UV) light. In embodiments, the UV light may be carried out within the semiconductor processing chamber used for deposition of the low dielectric constant material. However, it is also conceivable that the substrate having the low dielectric constant material immediately after deposition be transferred to a separate semiconductor processing chamber in which the UV light process is performed. In embodiments, the UV light in optional step 320 may expose a layer of silicon-containing material to ultraviolet light to provide a cured layer of the silicon-containing material. This process may produce a cured low dielectric constant material characterized by increased porosity and / or decreased dielectric constant (κ value) compared to the material immediately after deposition. The increased porosity of the cured low dielectric constant material may reduce the dielectric constant of the material to about 3.5 or less, about 3.4 or less, about 3.3 or less, about 3.2 or less, about 3.1 or less, about 3.0 or less, about 2.9 or less, about 2.8 or less, about 2.7 or less, about 2.6 or less, or below.

[0044]

[0046] After UV treatment, the cured material can be characterized by a decrease in stress compared to the material immediately after deposition. In embodiments, the cured layer of the silicon-containing material may be characterized by stresses of approximately -200 MPa or less, or by stresses of approximately -175 MPa or less, approximately -150 MPa or less, approximately -125 MPa or less, approximately -100 MPa or less, approximately -75 MPa or less, approximately -50 MPa or less, and approximately -25 MPa or less.

[0045]

[0047] The deposition rate of the silicon-containing material immediately after deposition may exceed 200 A / min, and may be deposited at rates of approximately 225 A / min or more, approximately 250 A / min or more, approximately 275 A / min or more, approximately 300 A / min or more, approximately 325 A / min or more, approximately 350 A / min or more, approximately 375 A / min or more, approximately 400 A / min or more, or higher. The silicon-containing material immediately after deposition may be deposited to a thickness of approximately 10 A or more, approximately 15 A or more, approximately 20 A or more, approximately 25 A or more, approximately 30 A or more, approximately 35 A or more, approximately 40 A or more, approximately 45 A or more, approximately 50 A or more, or higher. In some embodiments, the silicon-containing material immediately after deposition may be deposited to a thickness of approximately 50 A or less, approximately 45 A or less, approximately 40 A or less, approximately 35 A or less, approximately 30 A or less, approximately 25 A or less, approximately 20 A or less, approximately 15 A or less, approximately 10 A or less, or lower. The silicon-containing material immediately after deposition may undergo two or more deposition and UV treatment cycles to form the final UV-treated low-dielectric-constant material. For example, the number of deposition and treatment cycles may be approximately 3 or more, 5 or more, 10 or more, 15 or more, 20 or more, 30 or more, 40 or more, or 50 or more.

[0046]

[0048] In the preceding description, many details have been provided for the purpose of explanation in order to understand the various embodiments of the Technology. However, it will be obvious to those skilled in the art that certain embodiments can be implemented by omitting some of these details or by adding additional details.

[0047]

[0049] While several embodiments have been disclosed, those skilled in the art will understand that various modifications, alternative configurations, and equivalents can be used without departing from the spirit of these embodiments. In addition, some known processes and elements have not been described in order to avoid unnecessarily obscuring the Art. Therefore, the above description does not limit the scope of the Art.

[0048]

[0050] Where a range of values ​​is indicated, each intermediate value between the upper and lower limits of that range (up to the smallest fraction of the lower limit unit, unless otherwise explicitly stated in the context) is understood to be specifically disclosed. Narrower ranges between any stated or unstated intermediate values ​​within the indicated range and any other stated or intermediate values ​​within that indicated range are also included. The upper and lower limits of such narrower ranges may or may not be included in the range individually, and each range in which one or both of the limit values ​​are included or neither of the limit values ​​is also included in the Art, subject to the limit values ​​explicitly excluded from the stated range. If one or both of the limit values ​​are included in the stated range, the range excluding one or both of the included limit values ​​is also included.

[0049]

[0051] As used herein and in the appended claims, the singular forms “a,” “an,” and “the” include multiple references unless otherwise specified in the context. Thus, for example, a reference to “a layer” includes multiple such layers, and a reference to “the precursor” includes one or more precursors and their equivalents known to those skilled in the art, and so on.

[0050]

[0052] Furthermore, the terms “comprise(s),” “comprising,” “contain(s),” “containing,” “include(s),” and “including,” when used herein and in the following claims, are intended to identify the presence of the described features, components, elements, or processes, and do not exclude the presence or addition of one or more other features, elements, components, processes, operations, or groups.

Claims

1. A semiconductor processing method, The method involves supplying a deposition precursor to a processing area of ​​a semiconductor processing chamber, wherein the deposition precursor includes a silicon-carbon-hydrogen-containing precursor, and the substrate is placed within the processing area. Forming plasma ejecta of the aforementioned deposition precursor, A layer of silicon-containing material characterized by a dielectric constant of approximately 4.0 or less is deposited on the aforementioned substrate. A semiconductor processing method, including the following.

2. The semiconductor processing method according to claim 1, wherein the silicon-carbon-hydrogen-containing precursor comprises bis(trimethylsilyl)methane or 1,1,3,3-tetramethyl-1,3-disilacyclobutane.

3. The semiconductor processing method according to claim 1, wherein the silicon-carbon-hydrogen-containing precursor further contains oxygen.

4. The semiconductor processing method according to claim 3, wherein the silicon-carbon-hydrogen-containing precursor comprises dimethyldimethoxysilane, 1,1,3,3-tetramethyl-1,3-dimethoxydisiloxane, or methoxy(dimethyl)silylmethane.

5. The semiconductor processing method according to claim 1, wherein the deposition precursor further comprises a boron-containing precursor, a nitrogen-containing precursor, or both.

6. The boron-containing precursor is diborane (B ２ H ６ The semiconductor processing method according to claim 5, including ).

7. The semiconductor processing method according to claim 1, wherein the layer of silicon-containing material is characterized by having a thickness of about 50A or less.

8. The silicon-containing material of the aforementioned layer is approximately 2.50 g / cm². ３ The semiconductor processing method according to claim 1, characterized by the above density.

9. The semiconductor processing method according to claim 1, wherein the layer of silicon-containing material is deposited at a rate of about 200 A / min or more.

10. A semiconductor processing method according to claim 1, To provide a cured layer of silicon-containing material characterized by a stress of approximately -150 MPa or less, obtained by exposing the layer of silicon-containing material to ultraviolet light. A semiconductor processing method, further including the above.

11. A semiconductor processing method, The method involves supplying a deposition precursor to a processing area of ​​a semiconductor processing chamber, wherein the deposition precursor comprises a silicon-containing precursor and a dopant-containing precursor, and the substrate is placed within the processing area. Forming plasma ejecta of the aforementioned deposition precursor, The substrate is characterized by a dielectric constant of approximately 4.0 or less, and has a density of approximately 2.30 g / cm³. ３ Depositing layers of silicon-containing material characterized by the above densities and A semiconductor processing method, including the following.

12. The semiconductor processing method according to claim 11, wherein the silicon-containing precursor comprises a silicon-carbon-hydrogen-containing precursor or a silicon-oxygen-carbon-hydrogen-containing precursor.

13. The semiconductor processing method according to claim 11, wherein the dopant precursor includes a boron-containing precursor.

14. The semiconductor processing method according to claim 11, wherein the flow rate of the dopant precursor is about 1000 sccm or less.

15. The semiconductor processing method according to claim 11, wherein the layer of silicon-containing material is characterized by a breakdown voltage of about 6.0 MV / cm or more.

16. The semiconductor processing method according to claim 11, wherein the layer of silicon-containing material is characterized by a dielectric constant of about 3.3 or less.

17. The semiconductor processing method according to claim 11, wherein the temperature within the processing area is maintained at approximately 500°C or lower.

18. A semiconductor processing method, The method involves supplying a deposition precursor to a processing area of ​​a semiconductor processing chamber, wherein the deposition precursor comprises a silicon-containing precursor and a boron-containing precursor, and the substrate is placed within the processing area. Forming plasma ejecta of the aforementioned deposition precursor, The substrate is characterized by a dielectric constant of approximately 3.5 or less, and has a density of approximately 2.50 g / cm³. ３ Depositing layers of silicon-containing material characterized by the above densities and A semiconductor processing method, including the following.

19. A semiconductor processing method according to claim 18, To provide a cured layer of silicon-containing material, the layer is exposed to ultraviolet light. A semiconductor processing method, further including the above.

20. The semiconductor processing method according to claim 18, wherein the layer of silicon-containing material is characterized by a boron concentration of about 20.0 at.% or less.

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