Display chip and manufacturing method

Abstract

This application discloses a display chip and a method for manufacturing it, and belongs to the semiconductor technology field. The display chip includes a chip structure comprising a first semiconductor layer, a quantum well light-emitting layer, and a second semiconductor layer, which are sequentially installed, wherein one of the first semiconductor layer and the second semiconductor layer is an n-type semiconductor layer and the other is a p-type semiconductor layer, and the first semiconductor layer, the quantum well light-emitting layer, and the second semiconductor layer are all nitrogen polar film layers.

Description

[Technical Field]

[0001] [Cross-reference of related applications] This application is based on a Chinese application with application number 202311506815.2, filed on November 13, 2023, claiming priority therefrom, and the disclosures of said Chinese application are incorporated into this application in their entirety.

[0002] This application belongs to the field of semiconductor technology, and more particularly to display chips and manufacturing methods. [Background technology]

[0003] Currently, the film layer material used in display devices such as micro-light-emitting diodes (Micro-LEDs) is a gallium polar material. Due to the low growth temperature of the gallium polar film layer, the density of through-dislocations becomes high, and together with the quantum confinement Stark effect caused by the strong polarization electric field in the quantum well, this leads to a decrease in the luminous efficiency of the display device. [Overview of the project]

[0004] According to a first aspect, the present application provides a display chip, the display chip is, The chip structure includes a first semiconductor layer, a quantum well light-emitting layer, and a second semiconductor layer, wherein one of the first and second semiconductor layers is an n-type semiconductor layer and the other is a p-type semiconductor layer. Here, the first semiconductor layer, the quantum well light-emitting layer, and the second semiconductor layer are all nitrogen polar film layers.

[0005] According to one embodiment of the present application, the chip structure further includes a fourth undoped semiconductor layer sequentially placed between the first semiconductor layer and the quantum well light-emitting layer, a first potential barrier layer, a first superlattice layer, and a second superlattice layer. The fourth undoped semiconductor layer, the first potential barrier layer, the first superlattice layer, and the second superlattice layer are all nitrogen polar film layers.

[0006] According to one embodiment of the present application, the fourth undoped semiconductor layer comprises a u-GaN layer, the first potential barrier layer comprises a GaN layer, and the first superlattice layer comprises a u-In a Ga 1-a It includes an N / u-GaN superlattice layer, where 0.01 ≤ a ≤ 0.05, and the second superlattice layer is u-In b Ga 1-b It contains an N / n-GaN superlattice layer, and the b-value is 0.05 ≤ b ≤ 0.1.

[0007] According to one embodiment of the present application, the first semiconductor layer includes a highly doped semiconductor layer and a low-doped semiconductor layer located between the highly doped semiconductor layer and the quantum well light-emitting layer. Both the high-concentration doped semiconductor layer and the low-concentration doped semiconductor layer are nitrogen polar film layers.

[0008] According to one embodiment of this application, the highly doped semiconductor layer is an n-GaN highly doped layer or an n-Al c Ga 1-c It includes an N / n-GaN superlattice layer, where 0.02 ≤ c ≤ 0.15, and the low-concentration doped semiconductor layer is an n-GaN low-concentration doped layer or n-Al g Ga 1-g It contains an N / n-GaN superlattice layer, and the g coefficient is 0.02 ≤ g ≤ 0.08.

[0009] According to one embodiment of the present application, the quantum well light-emitting layer includes a fifth undoped semiconductor layer sequentially placed between the first semiconductor layer and the second semiconductor layer, a first potential well layer, a first cap layer, a second potential barrier layer, a sixth undoped semiconductor layer, a second potential well layer, a second cap layer, and a third potential barrier layer. The fifth undoped semiconductor layer, the first potential well layer, the first cap layer, the second potential barrier layer, the sixth undoped semiconductor layer, the second potential well layer, the second cap layer, and the third potential barrier layer are all nitrogen polar film layers.

[0010] According to one embodiment of the present application, both the fifth non-doped semiconductor layer and the sixth non-doped semiconductor layer include a u-GaN layer, both the first cap layer and the second cap layer include a GaN layer, and the first potential well layer is u-In x Ga 1-x N layer, where 0.1 ≦ x ≦ 0.15, and the second potential barrier layer is a GaN layer or u-In y Ga 1-y N layer, where 0.01 ≦ y ≦ 0.03, and the second potential well layer is u-In z Ga 1-z N layer, where 0.35 ≦ z ≦ 0.4, and the third potential barrier layer is u-Al d Ga 1-d N layer, where 0.3 ≦ d ≦ 0.35.

[0011] According to one embodiment of the present application, the second semiconductor layer includes an electron blocking layer, a hole injection layer, and an ohmic contact layer, which are sequentially disposed on the side away from the first semiconductor layer of the quantum well light-emitting layer. The electron blocking layer, the hole injection layer, and the ohmic contact layer are all nitride-polarity film layers.

[0012] According to one embodiment of the present application, the electron blocking layer includes a p-AlGaN polarization induction layer or a p-Al e Ga 1-e N / p-GaN superlattice layer, where 0.15 ≦ e ≦ 0.25, the hole injection layer includes a p-GaN layer, and the ohmic contact layer includes a p-In f Ga 1-f N / p-GaN superlattice layer, where 0.1 ≦ f ≦ 0.2.

[0013] According to one embodiment of the present application, the chip structure further includes a first transparent conductive layer, a first reflective layer, and a bonding layer, which are sequentially located on the side away from the quantum well light-emitting layer of the second semiconductor layer.

[0014] According to one embodiment of the present application, the chip structure further includes a protective layer located between the quantum well light-emitting layer and the second semiconductor layer.

[0015] According to one embodiment of this application, the quantum well light-emitting layer includes a red light quantum well light-emitting layer.

[0016] According to one embodiment of the present application, the display chip further includes a substrate, the substrate being bonded to the side of the chip structure away from the first semiconductor layer.

[0017] According to one embodiment of the present application, the display chip further comprises a passipation layer and a second reflective layer, The passipation layer is located on the side of the chip structure away from the substrate and covers the sidewall of the chip structure, and the second reflective layer covers the passipation layer.

[0018] According to one embodiment of the present application, the display chip further includes a second transparent conductive layer located on the side of the second reflective layer away from the substrate, and the second transparent conductive layer is connected to the first semiconductor layer through the second reflective layer and the passivation layer.

[0019] According to one embodiment of the present application, the display chip further includes a third reflective layer located on the circumferential side of the chip structure and a microlens located on the side of the second transparent conductive layer away from the chip structure.

[0020] According to a second aspect, the present application provides a method for manufacturing a display chip, the method being Forming the base, A chip structure is formed on one side of the base, and the chip structure includes a first semiconductor layer, a quantum well light-emitting layer, and a second semiconductor layer, which are sequentially installed on one side of the base, wherein one of the first semiconductor layer and the second semiconductor layer is an n-type semiconductor layer and the other is a p-type semiconductor layer, and the first semiconductor layer, the quantum well light-emitting layer, and the second semiconductor layer are all nitrogen polar film layers. This includes removing the aforementioned base.

[0021] According to one embodiment of the present application, the base comprises a substrate, a buffer layer, and a non-doped semiconductor composite layer. The above-mentioned formation of the base is To provide a substrate, A buffer layer is formed on one side of the aforementioned substrate, This includes forming a non-doped semiconductor composite layer on the side of the buffer layer away from the substrate, and the chip structure being located on the side of the non-doped semiconductor composite layer away from the buffer layer. Here, both the buffer layer and the undoped semiconductor composite layer are nitrogen polar film layers.

[0022] According to one embodiment of the present application, the undoped semiconductor composite layer comprises a plurality of stacked undoped semiconductor layers and at least one insertion layer, wherein one insertion layer is located between any two adjacent undoped semiconductor layers. Both the undoped semiconductor layer and the insertion layer are nitrogen polar film layers.

[0023] According to one embodiment of this application, the plurality of undoped semiconductor layers include a first undoped semiconductor layer, a second undoped semiconductor layer, and a third undoped semiconductor layer, and the at least one insertion layer includes a first insertion layer and a second insertion layer, and the first undoped semiconductor layer, the first insertion layer, the second undoped semiconductor layer, the second insertion layer, and the third undoped semiconductor layer are sequentially placed between the buffer layer and the first semiconductor layer. The first undoped semiconductor layer, the second undoped semiconductor layer, and the third undoped semiconductor layer all include a u-GaN layer, and the first insertion layer is porous SiN x The second insertion layer includes an AlN layer.

[0024] According to one embodiment of this application, removing the base is Removing the aforementioned substrate, This includes removing the buffer layer and the undoped semiconductor composite layer.

[0025] According to one embodiment of this application, before removing the base, The further step includes bonding the side of the chip structure that is separated from the base to the substrate.

[0026] According to one embodiment of this application, after removing the base, A passivation layer is formed on the side of the chip structure that is separated from the substrate, covering the side wall of the chip structure. This further includes forming a second reflective layer on the surface of the passivation layer.

[0027] According to one embodiment of this application, the method is A second transparent conductive layer is formed on the side of the second reflective layer away from the substrate, and is connected to the first semiconductor layer by penetrating the second reflective layer and the passipation layer. The further includes forming microlenses on the side of the second transparent conductive layer that is away from the substrate.

[0028] Additional aspects and advantages of this application are given in part in the following description, will become apparent in part in the following description, or will be understood by the practice of this application. [Brief explanation of the drawing]

[0029] The above and / or additional aspects and advantages of this application will become clearer and easier to understand from the description of embodiments combined with the following drawings. [Figure 1] This is a flowchart of the method for manufacturing a display chip according to an embodiment of this application. [Figure 2] This is one of the schematic diagrams of the manufacturing process of a display chip according to an embodiment of this application. [Figure 3] This is the second schematic diagram of the manufacturing process of a display chip according to an embodiment of this application. [Figure 4] This is the third schematic diagram of the manufacturing process of a display chip according to an embodiment of this application. [Figure 5] This is the fourth schematic diagram of the structure in the manufacturing process of a display chip according to an embodiment of this application. [Figure 6] This is the fifth schematic diagram of the structure in the manufacturing process of a display chip according to an embodiment of this application. [Figure 7] This is the sixth schematic diagram of the structure in the manufacturing process of a display chip according to an embodiment of this application. [Figure 8] This is the seventh schematic diagram of the structure in the manufacturing process of a display chip according to an embodiment of this application. [Figure 9] This is the eighth schematic diagram of the structure in the manufacturing process of a display chip according to an embodiment of this application. [Figure 10] This is the ninth schematic diagram of the structure in the manufacturing process of a display chip according to an embodiment of this application. [Figure 11] This is the tenth schematic diagram of the structure in the manufacturing process of a display chip according to an embodiment of this application. [Figure 12] This is the eleventh schematic diagram of the structure in the manufacturing process of a display chip according to an embodiment of this application. [Figure 13] This is the twelfth schematic diagram of the structure in the manufacturing process of a display chip according to an embodiment of this application. [Figure 14] This is a schematic diagram of the structure of a display chip according to an embodiment of this application. [Modes for carrying out the invention]

[0030] The embodiments of this application will be described in detail below, and examples of such embodiments are shown in the drawings, where the same or similar symbols throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the drawings are for illustrative purposes only and should not be understood as limitations thereto.

[0031] The display chip and manufacturing method according to the embodiment of this application will be described below with reference to the drawings.

[0032] Figure 1 is a flowchart of a method for manufacturing a display chip according to an embodiment of this application. Here, the display chip may be a Micro-LED display chip.

[0033] As shown in Figure 1, the method for manufacturing a display chip according to an embodiment of this application includes step 110, step 120, and step 130.

[0034] Step 110: Form the base.

[0035] In some embodiments, as shown in Figure 2, the base 10 may include a substrate 1, a buffer layer 2, and an undoped semiconductor composite layer 3. Forming the base in step 110 includes providing the substrate 1, forming the buffer layer 2 on one side of the substrate 1, and forming the undoped semiconductor composite layer 3 on the side of the buffer layer 2 away from the substrate 1. Here, both the buffer layer 2 and the undoped semiconductor composite layer 3 are nitrogen polar film layers.

[0036] Here, substrate 1 may include a sapphire substrate having a constant bevel angle. Buffer layer 2 may include an undoped GaN (u-GaN) layer, and the thickness of buffer layer 2 may be 15 nm to 35 nm. Undoped semiconductor composite layer 3 may be a film layer with a low dislocation density.

[0037] For example, using an MOCVD (Metal-Organic Chemical Vapor Deposition) system, a hydrogen atmosphere is first provided to substrate 1 at a temperature of 1080°C to 1100°C for a time of 300 to 400 seconds. While maintaining the hydrogen atmosphere, the temperature of the reaction chamber is lowered to 1020°C to 1060°C, and then ammonia is introduced to perform nitriding on the surface of substrate 1.

[0038] Next, a low-temperature buffer layer 2 is grown on one side of substrate 1, the atmosphere is switched from hydrogen to nitrogen, ammonia is introduced, and the temperature of the reaction chamber is lowered to 550°C to 580°C. Maintaining the nitrogen atmosphere, the temperature of the reaction chamber is raised to 1060°C to 1080°C, and annealing treatment is performed on buffer layer 2 for 500s to 600s.

[0039] Note that buffer layer 2 may be manufactured and formed using other processes, and is not specifically limited here.

[0040] An undoped semiconductor composite layer 3 is formed on the side of the buffer layer 2 away from substrate 1. In some embodiments, the undoped semiconductor composite layer 3 includes a plurality of stacked undoped semiconductor layers and at least one insertion layer, with one insertion layer between any two adjacent undoped semiconductor layers, where both the undoped semiconductor layers and the insertion layer are nitrogen polar film layers. The insertion layer can reduce the threading dislocation density in the undoped semiconductor layers and improve the internal quantum efficiency of the chip.

[0041] In some embodiments, as shown in Figure 2, the multiple undoped semiconductor layers include a first undoped semiconductor layer 31, a second undoped semiconductor layer 33, and a third undoped semiconductor layer 35, and at least one insertion layer includes a first insertion layer 32 and a second insertion layer 34. The first undoped semiconductor layer 31, the first insertion layer 32, the second undoped semiconductor layer 33, the second insertion layer 34, and the third undoped semiconductor layer 35 are sequentially installed on the side of the buffer layer 2 away from the substrate 1.

[0042] Here, the first undoped semiconductor layer 31 may include a u-GaN layer, and the thickness of the first undoped semiconductor layer 31 may be 300 nm to 500 nm. The first insertion layer 32 may include a porous SiNx layer. The main role of the first insertion layer 32 is to reduce the defect density and impurity ion concentration of the u-GaN layer, while also reducing the background electron concentration of the nitrogen-polarized u-GaN layer, thereby improving mobility and enhancing luminescence performance.

[0043] The second undoped semiconductor layer 33 may include a u-GaN layer, and the thickness of the second undoped semiconductor layer 33 is 1 μm to 1.2 μm. The second insertion layer 34 may include an AlN layer, and the thickness of the second insertion layer 34 may be 5 nm to 30 nm. The third undoped semiconductor layer 35 may include a u-GaN layer, and the thickness of the third undoped semiconductor layer 35 may be 1.5 μm to 2.5 μm. The overall thickness of the undoped semiconductor composite layer 3 may be 3 μm to 4 μm.

[0044] For example, after growing buffer layer 2, the atmosphere is switched from nitrogen to hydrogen, the temperature of the reaction chamber is raised to 1080°C to 1100°C, and a first undoped semiconductor layer 31 is grown on the side of buffer layer 2 that is separated from substrate 1. Only ammonia (NH3) and silane (SiH4) are introduced, and a first insertion layer 32 is grown on the side of the first undoped semiconductor layer 31 that is separated from buffer layer 2.

[0045] Then, in a hydrogen atmosphere, when the reaction chamber temperature is 1080°C to 1100°C, a second undoped semiconductor layer 33 is grown on the side of the first insertion layer 32 that is separated from the first undoped semiconductor layer 31. Then, the reaction chamber temperature is lowered to 900°C to 1000°C, and a low-temperature second insertion layer 34 is grown on the side of the second undoped semiconductor layer 33 that is separated from the first insertion layer 32. Then, in a hydrogen atmosphere, when the reaction chamber temperature is 1080°C to 1100°C, a third undoped semiconductor layer 35 is grown on the side of the second insertion layer 34 that is separated from the second undoped semiconductor layer 33.

[0046] The undoped semiconductor composite layer 3 may be manufactured and formed using other processes, and is not specifically limited to those processes here.

[0047] Step 120, a chip structure is formed on one side of the base, the chip structure includes a first semiconductor layer, a quantum well light-emitting layer, and a second semiconductor layer, which are sequentially installed on one side of the base, one of the first semiconductor layer and the second semiconductor layer being an n-type semiconductor layer and the other being a p-type semiconductor layer, wherein the first semiconductor layer, the quantum well light-emitting layer, and the second semiconductor layer are all nitrogen polar film layers.

[0048] As shown in Figures 3 to 7, the chip structure 20 includes a first semiconductor layer 4, a quantum well light-emitting layer 5, and a second semiconductor layer 6. Step 120, forming the chip structure on one side of the base, includes forming the first semiconductor layer 4 on one side of the base 10, forming the quantum well light-emitting layer 5 on the side of the first semiconductor layer 4 away from the base 10, and forming the second semiconductor layer 6 on the side of the quantum well light-emitting layer 5 away from the first semiconductor layer 4.

[0049] Here, the first semiconductor layer 4 is an n-type semiconductor layer, and the second semiconductor layer 6 is a p-type semiconductor layer. Alternatively, the first semiconductor layer 4 is a p-type semiconductor layer, and the second semiconductor layer 6 is an n-type semiconductor layer. In some embodiments, the chip structure 20 is a nitrogen-polarized InGaN-based chip structure, where the first semiconductor layer 4 is an n-type semiconductor layer and the second semiconductor layer 6 is a p-type semiconductor layer.

[0050] In some embodiments, as shown in Figure 3, the first semiconductor layer 4 includes a highly doped semiconductor layer 41 and a low-doped semiconductor layer 42. The highly doped semiconductor layer 41 is located on one side of the base 10; for example, the highly doped semiconductor layer 41 is located on the side away from the substrate 1 of the undoped semiconductor composite layer 3, and the low-doped semiconductor layer 42 is located on the side away from the base 10 of the highly doped semiconductor layer 41. Here, both the highly doped semiconductor layer 41 and the low-doped semiconductor layer 42 are nitrogen polar film layers.

[0051] The highly doped semiconductor layer 41 may include an n-GaN highly doped layer, and the electron concentration of the highly doped semiconductor layer 41 is 1 × 10⁻⁶. 18 cm -3 ~2×10 19 cm -3 The thickness of the highly doped semiconductor layer 41 is 0.5 μm to 1.5 μm.

[0052] For example, the reaction chamber temperature is 1080°C to 1100°C, silane is introduced, and a delta-doping method is employed to separate the silane introduction process from the growth process of the highly doped semiconductor layer 41, thereby periodically growing an undoped semiconductor layer. The diffusion of Si atoms during growth achieves n-type doping of the undoped semiconductor layer, obtaining the highly doped semiconductor layer 41. Here, the undoped semiconductor layer may contain a GaN layer, and the highly doped semiconductor layer 41 may contain an n-GaN layer. The periodic thickness of the undoped semiconductor layer may be 10 nm to 30 nm, the silane flow rate may be 2 nmol / min to 80 nmol / min, and the electron concentration of the highly doped semiconductor layer 41 is 1 × 10⁻⁶ 18 cm -3 ~2×10 19 cm -3 This makes it possible to achieve a thickness of 0.5 μm to 1.5 μm for the highly doped semiconductor layer 41.

[0053] While silane is generally selected as the n-type dopant for the GaN layer, uniform silane doping can reduce the mobility of Ga atoms and easily lead to the formation of V-type defects. Therefore, in this embodiment, a delta doping method is employed to avoid V-type defects.

[0054] The highly doped semiconductor layer 41 is n-Al c Ga 1-c It may include an N / n-GaN superlattice layer, where 0.02 ≤ c ≤ 0.15, and the electron concentration is 1 × 10⁻⁶. 18 cm -3 ~2×10 19 cm -3 Here, n-Al c Ga 1-cThe Al component in N is approximately 2% to 15%, and the thickness may be 2 nm to 3 nm, while the thickness of n-GaN may be 2.5 nm to 15 nm. c Ga 1-c By employing an N / n-GaN superlattice layer, the elongation of dislocations can be mitigated and stress can be controlled.

[0055] The low-concentration doped semiconductor layer 42 may also include an n-GaN low-concentration doped layer, and the electron concentration of the low-concentration doped semiconductor layer 42 is 1 × 10⁻¹⁶. 17 cm -3 ~5×10 17 cm -3 The thickness of the low-concentration doped semiconductor layer 42 is 0.2 μm to 0.5 μm.

[0056] For example, the reaction chamber temperature is 1080°C to 1100°C, silane is introduced, and a delta-doping method is employed to periodically grow an undoped semiconductor layer. The undoped semiconductor layer is then doped with n-type ions to obtain a low-concentration doped semiconductor layer 42. Here, the undoped semiconductor layer contains a GaN layer, and the low-concentration doped semiconductor layer 42 contains an n-GaN layer. The periodic thickness of the undoped semiconductor layer is 10 nm to 30 nm, the silane flow rate is 0.1 nmol / min to 1.5 nmol / min, and the electron concentration of the low-concentration doped semiconductor layer 42 is 1 × 10⁻¹⁶. 17 cm -3 ~5×10 17 cm -3 This makes it possible to achieve a thickness of 0.2 μm to 0.5 μm for the low-concentration doped semiconductor layer 42.

[0057] The low-concentration doped semiconductor layer 42 is n-Al g Ga 1-g It may include an N / n-GaN superlattice layer, where 0.02 ≤ g ≤ 0.08, and the electron concentration is 1 × 10⁻⁶. 17 cm -3 ~5×10 17 cm -3 Here, n-Al g Ga 1-gThe Al component in N is approximately 2% to 8%, with a thickness of 2 nm to 3 nm, while the thickness of n-GaN is 2.5 nm to 15 nm.

[0058] In some embodiments, as shown in Figure 4, forming the chip structure in step 120 further includes sequentially forming a fourth undoped semiconductor layer 71, a first potential barrier layer 72, a first superlattice layer 73, and a second superlattice layer 74 on the side of the first semiconductor layer 4 away from the base 10, with the quantum well light-emitting layer 5 located on the side of the second superlattice layer 74 away from the first superlattice layer 73. The fourth undoped semiconductor layer 71, the first potential barrier layer 72, the first superlattice layer 73, and the second superlattice layer 74 are all nitrogen polar film layers.

[0059] Here, the fourth undoped semiconductor layer 71 may include a u-GaN layer, and the thickness of the fourth undoped semiconductor layer 71 may be 10 nm to 30 nm. The first potential barrier layer 72 may include a GaN layer, and the thickness of the first potential barrier layer 72 may be 10 nm to 30 nm. The first superlattice layer 73 has at least one period (e.g., 1 to 3 periods) of u-In a Ga 1-a An N / u-GaN superlattice layer may be included, and 0.01 ≤ a ≤ 0.05. Here, u-In a Ga 1-a The thickness of N may be 2 nm to 3 nm, the In component may be 1% to 5%, and the thickness of u-GaN may be 2.5 nm to 15 nm. The second superlattice layer 74 has at least one period (e.g., 1 to 3 periods) of u-In b Ga 1-b An N / n-GaN superlattice layer may be included, and 0.05 ≤ b ≤ 0.1. Here, the electron concentration of n-GaN is 1 × 10⁻¹⁶. 17 cm -3 ~5×10 17 cm -3 It may also be u-In b Ga 1-bThe thickness of N may be 2 nm to 3 nm, the component In may be 5% to 10%, and the thickness of n-GaN may be 2.5 nm to 15 nm.

[0060] For example, after growing a low-doped semiconductor layer 42, the temperature of the reaction chamber is lowered to 900°C to 1000°C, and a fourth undoped semiconductor layer 71 is grown on the side of the low-doped semiconductor layer 42 that is separated from the high-doped semiconductor layer 41. The fourth undoped semiconductor layer 71 is used to repair corrosion damage caused by hydrogen during the cooling process.

[0061] Then, the atmosphere is switched to nitrogen, the temperature of the reaction chamber is lowered to 800°C to 900°C, and the first potential barrier layer 72 is grown on the side of the fourth undoped semiconductor layer 71 that is separated from the low-concentration doped semiconductor layer 42. Then, the first superlattice layer 73 is grown on the side of the first potential barrier layer 72 that is separated from the fourth undoped semiconductor layer 71. Subsequently, the second superlattice layer 74 is grown on the side of the first superlattice layer 73 that is separated from the first potential barrier layer 72.

[0062] Then, as shown in Figure 5, a quantum well light-emitting layer 5 is formed on the side of the second superlattice layer 74 that is away from the first superlattice layer 73.

[0063] In some embodiments, the quantum well emitting layer 5 includes a red light quantum well emitting layer. This embodiment employs a nitrogen polar film layer, which can mitigate the chip's droop effect during high-current injection and improve the red light emission efficiency.

[0064] In some embodiments, the quantum well light-emitting layer 5 includes at least one periodic structure (e.g., two to three periodic structures), each periodic structure comprising a fifth undoped semiconductor layer sequentially placed between a first semiconductor layer 4 and a second semiconductor layer 6, a first potential well layer, a first cap layer, a second potential barrier layer, a sixth undoped semiconductor layer, a second potential well layer, a second cap layer, and a third potential barrier layer. Here, the fifth undoped semiconductor layer, the first potential well layer, the first cap layer, the second potential barrier layer, the sixth undoped semiconductor layer, the second potential well layer, the second cap layer, and the third potential barrier layer are all nitrogen polar film layers.

[0065] Here, the fifth undoped semiconductor layer may include a low-temperature u-GaN layer, and the thickness of the fifth undoped semiconductor layer may be 2 nm to 3 nm. The first potential well layer is u-In x Ga 1-x The first potential well layer may include an N layer, and the x-value is 0.1 ≤ x ≤ 0.15, and the thickness of the first potential well layer may be 2.5 nm to 3.5 nm. The first cap layer may include a GaN layer, and the thickness of the first cap layer may be 2 nm to 3 nm. The second potential barrier layer may be a GaN layer or u-In y Ga 1-y The N layer may be included, and 0.01 ≤ y ≤ 0.03, and the thickness of the second potential barrier layer may be 10 nm to 15 nm. The sixth undoped semiconductor layer may include a low-temperature u-GaN layer, and the thickness of the sixth undoped semiconductor layer may be 2 nm to 3 nm. The second potential well layer is u-In z Ga 1-z The N layer may be included, and 0.35 ≤ z ≤ 0.4, and the thickness of the second potential well layer may be 2.5 nm to 3.5 nm. The second cap layer may include a GaN layer, and the thickness of the second cap layer may be 2 nm to 3 nm. The third potential barrier layer is u-Al d Ga 1-dAn N layer may be included, 0.3 ≤ d ≤ 0.35, and the thickness of the third potential barrier layer may be 10 nm to 15 nm.

[0066] In some embodiments, as shown in Figure 6, forming the chip structure in step 120 further includes forming a protective layer 75 on the side of the quantum well light-emitting layer 5 away from the first semiconductor layer 4. The protective layer 75 is a nitrogen polar film layer. Here, the protective layer 75 may include a u-GaN layer, and the thickness of the protective layer 75 may be 20 nm to 50 nm.

[0067] For example, in a nitrogen atmosphere, a protective layer 75 is grown on the side of the quantum well light-emitting layer 5 that is separated from the first semiconductor layer 4.

[0068] Then, as shown in Figure 6, a second semiconductor layer 6 is formed on the side of the protective layer 75 that is away from the quantum well light-emitting layer 5.

[0069] In some embodiments, the second semiconductor layer 6 includes an electron blocking layer 61, a hole injection layer 62, and an ohmic contact layer 63, which are sequentially formed on the side of the quantum well light-emitting layer 5 away from the first semiconductor layer 4. The electron blocking layer 61, the hole injection layer 62, and the ohmic contact layer 63 are all nitrogen polar film layers.

[0070] Here, the electron blocking layer 61 may include a p-AlGaN polarization induction layer, the thickness of the p-AlGaN polarization induction layer may be 50 nm to 60 nm, the component Al may increase linearly from 0% to 20% or 30%, and the theoretically calculated film layer hole concentration is 2 × 10⁻⁶. 18 cm -3 ~2.5×10 18 cm -3 The electron blocking layer 61 is made of p-Al e Ga 1-e It may include an N / p-GaN superlattice layer, where 0.15 ≤ e ≤ 0.25, and the hole concentration is 1.5 × 10⁻⁶. 18 cm -3 ~2.5×10 18 cm -3 It may also be p-Ale Ga 1-e In the component Al in GaN is about 15% - 25%, p - Al e Ga 1-e The thickness of GaN may be 2 nm - 3 nm, and the thickness of p - GaN may be 5 nm - 15 nm.

[0071] The hole injection layer 62 may include a p - GaN layer, and the thickness of the hole injection layer 62 may be 100 nm - 140 nm. The ohmic contact layer 63 includes at least one period (for example, 2 - 4 periods) of p - In f Ga 1-f a GaN / p - GaN superlattice layer may be included, and 0.1 ≦ f ≦ 0.2. Here, p - In f Ga 1-f In the component In in GaN is about 10% - 20%, p - In f Ga 1-f The thickness of GaN may be 2 nm - 3 nm, and the thickness of p - GaN may be 5 nm - 15 nm.

[0072] For example, switch to a hydrogen atmosphere and grow an electron blocking layer 61 on the side of the quantum well light - emitting layer 5 of the protective layer 75 away from the protective layer 75. Then, deposit a hole injection layer 62 on the side of the electron blocking layer 61 away from the protective layer 75. Deposit an ohmic contact layer 63 on the side of the hole injection layer 62 away from the electron blocking layer 61.

[0073] Note that the second semiconductor layer 6 may be manufactured and formed by adopting other processes, and is not specifically limited here.

[0074] In some embodiments, as shown in FIG. 7, forming the chip structure in step 120 further includes sequentially forming a first transparent conductive layer 76, a first reflective layer 77, and a bonding layer 78 on the side of the quantum well light - emitting layer 5 of the second semiconductor layer 6 away from the quantum well light - emitting layer 5. The first reflective layer 77 is used to improve the light extraction efficiency of the display chip.

[0075] Here, the first transparent conductive layer 76 may include an ITO (indium tin oxide) layer. The first reflective layer 77 may include a metallic reflective layer, for example, at least one of Ag or Al. The bonding layer 78 may include a metallic layer, for example, at least one of Cr, Pt, Ni, Ti, Ni, and Ag.

[0076] For example, by employing an electron beam deposition or PVD (Physical Vapor Deposition) process, a first transparent conductive layer 76 is deposited on the side of the ohmic contact layer 63 away from the hole injection layer 62, and in combination with an annealing process, the transmittance of the first transparent conductive layer 76 is improved, thereby reducing the electrical resistance of the material.

[0077] Then, using an electron beam deposition or PVD process, a first reflective layer 77 is deposited on the side of the first transparent conductive layer 76 that is away from the ohmic contact layer 63. Then, using an electron beam deposition or PVD process, a bonding layer 78 is deposited on the side of the first reflective layer 77 that is away from the first transparent conductive layer 76.

[0078] The first transparent conductive layer 76 and the first reflective layer 77 may be manufactured and formed using other processes, and are not specifically limited to those processes here.

[0079] Along the growth direction of the c-axis, GaN materials exhibit two types of polarity: gallium polarity and nitrogen polarity. Nitrogen polarity InGaN materials have a higher incorporation efficiency of in compared to gallium polarity, mainly because the in atoms and surface nitrogen atoms in nitrogen polarity InGaN materials can form strong in-n bonds. Furthermore, because there are four in-n bonds around each in atom on the surface of nitrogen polarity InGaN materials, the desorption efficiency of in is lower, which is advantageous for incorporation. Therefore, with the same incorporation, nitrogen polarity InGaN materials may have higher growth temperatures, which is advantageous for improving the crystal quality of potential well layer materials in quantum wells and improving the internal quantum efficiency of chip structures.

[0080] Furthermore, nitrogen polar materials have a polarization direction opposite to that of gallium polar materials, which can lower the potential barrier for carrier injection into quantum wells in the chip and raise the potential barrier for carrier overflow from the quantum wells. As a result, nitrogen polar InGaN-based chips have higher carrier injection efficiency, suppress carrier overflow, mitigate the chip's droop effect at high currents (high current densities) to some extent, and improve the luminous efficiency of the display chip.

[0081] In some embodiments, the method for manufacturing the display chip is as follows: This further includes bonding the substrate to the side away from the base of the chip structure.

[0082] As shown in Figure 8, the chip structure 20 is bonded to the substrate 30 via a bonding layer 78. Here, the substrate 30 may include a silicon substrate or a silicon-based complementary metal oxide semiconductor (CMOS) pixel driving backplane, etc.

[0083] Step 130: Remove the base.

[0084] The base 10 may include a substrate 1, a buffer layer 2, and an undoped semiconductor composite layer 3. Removing the base in the display chip in step 130 includes removing the substrate 1 and removing the buffer layer 2 and the undoped semiconductor composite layer 3.

[0085] As shown in Figure 9, the substrate 1 is removed using laser delamination technology. Here, the selected pulsed laser wavelength may be 355 nm, 266 nm, or 248 nm.

[0086] Then, as shown in Figure 10, the buffer layer 2 and the undoped semiconductor layer composite layer 3 are etched using the ICP-RIE (Inductively Coupled Plasma-Reactive Ion Etching) process until the highly doped semiconductor layer 41 is exposed. The surface of the highly doped semiconductor layer 41 is then mechanically polished. As shown in Figure 11, the chip structure 20 can be etched using photolithography and the ICP-RIE process to meet various pixel size requirements.

[0087] In some embodiments, as shown in Figure 11, the method for manufacturing the display chip further includes forming a passipation layer 81 covering the sidewall of the chip structure 20 on the side of the chip structure 20 away from the substrate 30, and forming a second reflective layer 82 on the surface of the passipation layer 81. The passipation layer 81 is located on the side of the highly doped semiconductor layer 41 away from the substrate 30 and on the sidewall of the chip structure 20, and the second reflective layer 82 is located on the surface of the passipation layer 81. The second reflective layer 82 can further improve the light extraction efficiency of the chip.

[0088] Here, the passivation layer 81 is made of SiO2, SiN x The material may also contain at least one of Al2O3, the thickness of the passipation layer 81 may be 10 nm to 40 nm, and the second reflective layer 82 may include a DBR (Distributed Bragg Reflection) layer, the DBR layer may contain TiO2 / SiO2 or Ta2O5 / SiO2, etc.

[0089] For example, wet corrosion (e.g., a 25% TMAH solution) is used to repair the sidewalls of the chip structure 20, and then an ALD (Advanced Laser Deposition) device is used to deposit a passipation layer 81. Then, a second reflective layer 82 is deposited using PVD, electron beam deposition, or ALD device.

[0090] For example, a plasma of a PE-ALD apparatus is also used to process the sidewalls of the chip structure 20. The gas may include O2, Ar, H2, NH3, N2, etc., and the passivation layer 81 is deposited. Then, a second reflective layer 82 is deposited by employing PVD, electron beam evaporation, or an ALD apparatus.

[0091] For example, a protective layer is deposited on the chip structure 20 by employing a PECVD process through a photolithography process. The thickness of the protective layer is 10 nm to 40 nm. A plasma of a PE-ALD apparatus is used to process the sidewalls of the chip structure 20. The gas may include O2, Ar, H2, NH3, N2, etc., and the passivation layer 81 is deposited. Then, a second reflective layer 82 is deposited by employing PVD, electron beam evaporation, or an ALD apparatus.

[0092] In some embodiments, as shown in FIG. 12, the method for manufacturing the display chip further includes forming a first isolation layer 83 on the peripheral side of the chip structure 20. Here, the first isolation layer 83 may include at least one of SiO2 and SiN x and the like.

[0093] For example, an ICP-RIE process is employed to etch isolation grooves on the peripheral side of the chip structure 20. Then, a photolithography process and a PECVD apparatus are used to form the first isolation layer 83 in the grooves. An acetone solution is used to remove the photoresist, ultrasonic cleaning is performed using ethanol and deionized water, and drying is carried out with nitrogen.

[0094] Note that the first isolation layer 83 may also be manufactured and formed by employing other processes, and is not specifically limited here.

[0095] In some embodiments, as shown in Figure 13, the method for manufacturing the display chip further includes forming a second transparent conductive layer 84 on the side of the second reflective layer 82 away from the substrate 30, which penetrates the second reflective layer 82 and the passipation layer 81 and is connected to the first semiconductor layer 4. As shown in Figure 13, the second transparent conductive layer 84 is located on the side of the second reflective layer 82 away from the substrate 30 and on the side of the first isolation layer 83 away from the substrate 30, and the second transparent conductive layer 84 penetrates the second reflective layer 82 and the passipation layer 81 and is connected to the highly doped semiconductor layer 41 in the first semiconductor layer 4.

[0096] Here, the second transparent conductive layer 84 may include an ITO layer, and the thickness of the second transparent conductive layer 84 may be 100 nm to 400 nm.

[0097] For example, a photolithography process and an ICP-RIE etching process are used to etch the second reflective layer 82 and passipation layer 81 on the side of the highly doped semiconductor layer 41 that is separated from the substrate 30, thereby exposing the highly doped semiconductor layer 41. An electron beam deposition or PVD process is used to deposit a second transparent conductive layer 84, and in combination with an annealing process, the transmittance of the second transparent conductive layer 84 is improved, thereby reducing the electrical resistance of the material.

[0098] In some embodiments, as shown in Figure 14, the method for manufacturing the display chip further includes forming an n-type ohmic contact electrode and a third reflective layer 85 on the circumferential side of the chip structure 20, wherein the n-type ohmic contact electrode and the third reflective layer 85 are located on the side of the second transparent conductive layer 84 away from the substrate 30. The third reflective layer 85 can reduce optical crosstalk and light divergence angle between pixels and improve light extraction efficiency.

[0099] Here, the n-type ohmic contact electrode includes a metal layer, such as Ti / Al / Ti / Au. The third reflective layer may also include a metal layer, such as at least one of Ag or Al.

[0100] For example, n-type ohmic contact electrodes are manufactured using a photolithography process and electron beam deposition. A third reflective layer is deposited using an electron beam deposition or PVD process. Note that the n-type ohmic contact electrodes and the third reflective layer 85 may be manufactured and formed using other processes, and are not specifically limited here.

[0101] In some embodiments, as shown in Figure 14, the method for manufacturing the display chip further includes forming a second isolation layer 86 on the periphery of the chip structure 20 and forming a micro-lens 85 on the side of the second transparent conductive layer 84 away from the substrate 30. Here, the second isolation layer 86 covers the second transparent conductive layer 84, the n-type ohmic contact electrode, and the third reflective layer 85, and the surface of the second isolation layer 86 away from the substrate 30 may be flush with the surface of the second transparent conductive layer 84 away from the substrate 30. The first isolation layer 83 and the second isolation layer 86 are used to achieve electrical insulation between pixel mesas. The second isolation layer 86 is made of SiO2 or SiN x It may include at least one of the following. The positions of the microlens 85 and the chip structure 20 correspond, and the microlens 85 is used to increase light collection from the chip. The microlens 85 may contain SiO2 or the like.

[0102] For example, a second isolation layer 86 is deposited using a photolithography process and PECVD equipment. Microlenses 87 are deposited using PECVD equipment.

[0103] According to the method for manufacturing a display chip in the embodiment of this application, the first semiconductor layer, the quantum well light-emitting layer, and the second semiconductor layer are all nitrogen polar film layers, and the nitrogen polar film layer can be grown at high temperatures, improves the crystal quality of the potential well layer material in the quantum well, improves the injection efficiency of chip carriers, effectively suppresses carrier overflow, mitigates the chip's droop effect during high-current injection, improves the light-emitting efficiency of the display chip, and further improves the display effect of the display chip.

[0104] Accordingly, embodiments of this application further provide a display chip that can be manufactured by the above-described method for manufacturing a display chip. Here, the display chip may be a Micro-LED display chip.

[0105] As shown in Figure 14, the display chip includes a chip structure 20, which includes a first semiconductor layer 4, a quantum well light-emitting layer 5, and a second semiconductor layer 6. The quantum well light-emitting layer 5 is located on one side of the first semiconductor layer 4, and the second semiconductor layer 6 is located on the side of the quantum well light-emitting layer 5 away from the first semiconductor layer 4.

[0106] One of the first semiconductor layer 4 and the second semiconductor layer 6 is an n-type semiconductor layer, and the other is a p-type semiconductor layer; that is, the first semiconductor layer 4 is an n-type semiconductor layer and the second semiconductor layer 6 is a p-type semiconductor layer, or the first semiconductor layer 4 is a p-type semiconductor layer and the second semiconductor layer 6 is an n-type semiconductor layer.

[0107] Here, the first semiconductor layer 4, the quantum well light-emitting layer 5, and the second semiconductor layer 6 are all nitrogen polar film layers.

[0108] In this embodiment, the first semiconductor layer 4, the quantum well light-emitting layer 5, and the second semiconductor layer 6 are all nitrogen polar film layers. Nitrogen polar film layers can be grown at high temperatures, improving the crystal quality of the potential well layer material in the quantum well, improving the injection efficiency of chip carriers, effectively suppressing carrier overflow, mitigating the chip's droop effect during high-current injection, and improving the luminous efficiency of the display chip.

[0109] In some embodiments, the chip structure 20 is a nitrogen-polarized InGaN-based chip structure, the first semiconductor layer 4 is an n-type semiconductor layer, and the second semiconductor layer 6 is a p-type semiconductor layer.

[0110] In some embodiments, as shown in Figure 14, the first semiconductor layer includes a highly doped semiconductor layer 41 and a low-doped semiconductor layer 42. The low-doped semiconductor layer 42 is located between the highly doped semiconductor layer 41 and the quantum well light-emitting layer 5. Here, both the highly doped semiconductor layer 41 and the low-doped semiconductor layer 42 are nitrogen polar film layers.

[0111] The highly doped semiconductor layer 41 may include an n-GaN highly doped layer, and the electron concentration of the highly doped semiconductor layer 41 is 1 × 10⁻⁶. 18 cm -3 ~2×10 19 cm -3 The thickness of the highly doped semiconductor layer 41 is 0.5 μm to 1.5 μm. The highly doped semiconductor layer 41 is made of n-Al c Ga 1-c It may include an N / n-GaN superlattice layer, where 0.02 ≤ c ≤ 0.15, and the electron concentration is 1 × 10⁻⁶. 18 cm -3 ~2×10 19 cm -3 Here, n-Al c Ga 1-c The Al component in N is approximately 2% to 15%, and the thickness may be 2 nm to 3 nm, while the thickness of n-GaN may be 2.5 nm to 15 nm. c Ga 1-c By employing an N / n-GaN superlattice layer, the elongation of dislocations can be mitigated and stress can be controlled.

[0112] The low-concentration doped semiconductor layer 42 may also include an n-GaN low-concentration doped layer, and the electron concentration of the low-concentration doped semiconductor layer 42 is 1 × 10⁻¹⁶. 17 cm -3 ~5×10 17 cm -3 The thickness of the low-concentration doped semiconductor layer 42 is 0.2 μm to 0.5 μm. The low-concentration doped semiconductor layer 42 is n-Al g Ga 1-g It may include an N / n-GaN superlattice layer, where 0.02 ≤ g ≤ 0.08, and the electron concentration is 1 × 10⁻⁶. 17 cm -3 ~5×1017 cm -3 Here, n-Al g Ga 1-g The Al component in N is approximately 2% to 8%, with a thickness of 2 nm to 3 nm, while the thickness of n-GaN is 2.5 nm to 15 nm.

[0113] In some embodiments, as shown in Figure 14, the chip structure 20 further includes a fourth undoped semiconductor layer 71, a first potential barrier layer 72, a first superlattice layer 73, and a second superlattice layer 74, which are sequentially placed between the first semiconductor layer 4 and the quantum well light-emitting layer 5. Specifically, the fourth undoped semiconductor layer 71 is located between the low-concentration doped semiconductor layer 42 and the quantum well light-emitting layer 5, the first potential barrier layer 72 is located between the fourth undoped semiconductor layer 71 and the quantum well light-emitting layer 5, the first superlattice layer 73 is located between the first potential barrier layer 72 and the quantum well light-emitting layer 5, and the second superlattice layer 74 is located between the first superlattice layer 73 and the quantum well light-emitting layer 5. The fourth undoped semiconductor layer 71, the first potential barrier layer 72, the first superlattice layer 73, and the second superlattice layer 74 are all nitrogen polar film layers.

[0114] Here, the fourth undoped semiconductor layer 71 may include a u-GaN layer, and the thickness of the fourth undoped semiconductor layer 71 may be 10 nm to 30 nm. The first potential barrier layer 72 may include a GaN layer, and the thickness of the first potential barrier layer 72 may be 10 nm to 30 nm. The first superlattice layer 73 has at least one period (e.g., 1 to 3 periods) of u-In a Ga 1-a An N / u-GaN superlattice layer may be included, and 0.01 ≤ a ≤ 0.05. Here, u-In a Ga 1-a The thickness of N may be 2 nm to 3 nm, the component In may be 1% to 5%, and the thickness of u-GaN may be 2.5 nm to 15 nm. The second superlattice layer 74 has at least one period (e.g., 1 to 3 periods) of u-In b Ga 1-bAn N / n-GaN superlattice layer may be included, and 0.05 ≤ b ≤ 0.1. Here, the electron concentration of n-GaN is 1 × 10⁻¹⁶. 17 cm -3 ~5×10 17 cm -3 It may also be u-In b Ga 1-b The thickness of N may be 2 nm to 3 nm, the component In may be 5% to 10%, and the thickness of n-GaN may be 2.5 nm to 15 nm.

[0115] In some embodiments, the quantum well light emission layer 5 includes a red light quantum well light emission layer.

[0116] In some embodiments, the quantum well light-emitting layer 5 includes at least one periodic structure (e.g., two to three periodic structures), each periodic structure comprising a fifth undoped semiconductor layer sequentially placed between a first semiconductor layer 4 and a second semiconductor layer 6, a first potential well layer, a first cap layer, a second potential barrier layer, a sixth undoped semiconductor layer, a second potential well layer, a second cap layer, and a third potential barrier layer. Here, the fifth undoped semiconductor layer, the first potential well layer, the first cap layer, the second potential barrier layer, the sixth undoped semiconductor layer, the second potential well layer, the second cap layer, and the third potential barrier layer are all nitrogen polar film layers.

[0117] Here, the fifth undoped semiconductor layer may include a low-temperature u-GaN layer, and the thickness of the fifth undoped semiconductor layer may be 2 nm to 3 nm. The first potential well layer is u-In x Ga 1-x The first potential well layer may include an N layer, and the x-value is 0.1 ≤ x ≤ 0.15, and the thickness of the first potential well layer may be 2.5 nm to 3.5 nm. The first cap layer may include a GaN layer, and the thickness of the first cap layer may be 2 nm to 3 nm. The second potential barrier layer may be a GaN layer or u-In y Ga 1-yThe N layer may be included, and 0.01 ≤ y ≤ 0.03, and the thickness of the second potential barrier layer may be 10 nm to 15 nm. The sixth undoped semiconductor layer may include a low-temperature u-GaN layer, and the thickness of the sixth undoped semiconductor layer may be 2 nm to 3 nm. The second potential well layer is u-In z Ga 1-z The N layer may be included, and 0.35 ≤ z ≤ 0.4, and the thickness of the second potential well layer may be 2.5 nm to 3.5 nm. The second cap layer may include a GaN layer, and the thickness of the second cap layer may be 2 nm to 3 nm. The third potential barrier layer is u-Al d Ga 1-d An N layer may be included, 0.3 ≤ d ≤ 0.35, and the thickness of the third potential barrier layer may be 10 nm to 15 nm.

[0118] This embodiment employs a nitrogen polar film layer, which allows the quantum well light-emitting layer to be grown at high temperatures, improving the crystal quality of the potential barrier layer material in the quantum well light-emitting layer. This lowers the potential barrier for carrier injection into the quantum well light-emitting layer on the chip, while simultaneously raising the potential barrier for carrier overflow from the quantum well light-emitting layer. In other words, it improves carrier injection efficiency, suppresses carrier overflow, and mitigates the chip's droop effect during high-current injection.

[0119] In some embodiments, as shown in Figure 14, the chip structure 20 may further include a protective layer 75 located between the quantum well light-emitting layer 5 and the second semiconductor layer 6. The protective layer 75 is a nitrogen polar film layer. Here, the protective layer 75 includes a u-GaN layer, and the thickness of the protective layer 75 is 20 nm to 50 nm.

[0120] In some embodiments, as shown in Figure 14, the second semiconductor layer 6 includes an electron blocking layer 61, a hole injection layer 62, and an ohmic contact layer 63, which are sequentially installed on the side of the quantum well light-emitting layer 5 away from the first semiconductor layer 4. The electron blocking layer 61, the hole injection layer 62, and the ohmic contact layer 63 are all nitrogen polar film layers.

[0121] Here, the electron blocking layer 61 may include a p-AlGaN polarization induction layer, the thickness of the p-AlGaN polarization induction layer may be 50 nm to 60 nm, the component Al may increase linearly from 0% to 20% or 30%, and the theoretically calculated film layer hole concentration is 2 × 10⁻⁶. 18 cm -3 ~2.5×10 18 cm -3 The electron blocking layer 61 is made of p-Al e Ga 1-e It may include an N / p-GaN superlattice layer, where 0.15 ≤ e ≤ 0.25, and the hole concentration is 1.5 × 10⁻⁶. 18 cm -3 ~2.5×10 18 cm -3 It may also be p-Al e Ga 1-e The component Al in N is approximately 15% to 25%, and p-Al e Ga 1-e The thickness of N may be 2nm to 3nm, and the thickness of p-GaN may be 5nm to 15nm.

[0122] The hole injection layer 62 may include a p-GaN layer, and the thickness of the hole injection layer 62 may be 100 nm to 140 nm. The ohmic contact layer 63 has at least one period (e.g., 2 to 4 periods) of p-In f Ga 1-f It may include an N / p-GaN superlattice layer, and 0.1 ≤ f ≤ 0.2. f Ga 1-f The component In in N is approximately 10% to 20%, and p-In f Ga 1-f The thickness of N may be 2nm to 3nm, and the thickness of p-GaN may be 5nm to 15nm.

[0123] In some embodiments, the chip structure 20 further includes a first transparent conductive layer 76, a first reflective layer 77, and a bonding layer 78, which are sequentially located on the side of the second semiconductor layer 6 away from the quantum well light-emitting layer 5, namely the first transparent conductive layer 76 located on the side of the ohmic contact layer 63 away from the hole injection layer 62, the first reflective layer 77 located on the side of the first transparent conductive layer 76 away from the ohmic contact layer 63, and the bonding layer 78 located on the side of the first reflective layer 77 away from the first transparent conductive layer 76. The first reflective layer 77 is used to improve the light extraction efficiency of the display chip, and the bonding layer 78 is used to bond the display chip to another substrate.

[0124] Here, the first transparent conductive layer 76 may include an ITO (indium tin oxide) layer. The first reflective layer 77 may include a metallic reflective layer, for example, at least one of Ag or Al. The bonding layer 78 may include a metallic layer, for example, at least one of Cr, Pt, Ni, Ti, Ni, and Ag.

[0125] Along the growth direction of the c-axis, GaN materials exhibit two types of polarity: gallium polarity and nitrogen polarity. Nitrogen polarity InGaN materials have a higher incorporation efficiency of in compared to gallium polarity, mainly because the in atoms and surface nitrogen atoms in nitrogen polarity InGaN materials can form strong in-n bonds. Furthermore, because there are four in-n bonds around each in atom on the surface of nitrogen polarity InGaN materials, the desorption efficiency of in is lower, which is advantageous for incorporation. Therefore, with the same incorporation, nitrogen polarity InGaN materials may have higher growth temperatures, which is advantageous for improving the crystal quality of potential well layer materials in quantum wells and improving the internal quantum efficiency of chip structures.

[0126] Furthermore, nitrogen polar materials have a polarization direction opposite to that of gallium polar materials, which can lower the potential barrier for carrier injection into quantum wells in the chip and raise the potential barrier for carrier overflow from the quantum wells. Therefore, nitrogen polar InGaN-based chip structures have higher carrier injection efficiency, suppress carrier overflow, mitigate the chip's droop effect at high currents (high current densities) to some extent, and improve the luminous efficiency of the display chip.

[0127] In some embodiments, as shown in Figure 14, the display chip further includes a substrate 30. The substrate 30 is bonded to the side of the chip structure 20 away from the first semiconductor layer 4.

[0128] In some embodiments, the substrate 30 is located on the side of the bonding layer 78 away from the first semiconductor layer 4, and the substrate 30 is bonded to the chip structure 20 via the bonding layer 78.

[0129] Here, the substrate 30 may include a silicon substrate or a silicon-based complementary metal oxide semiconductor (CMOS) pixel driving backplane.

[0130] In some embodiments, as shown in Figure 14, the display chip further includes a passipation layer 81 and a second reflective layer 82. The passipation layer 81 is located on the side of the chip structure 20 away from the substrate 30 and covers the sidewall of the chip structure 20; that is, the passipation layer 81 is located on the side of the highly doped semiconductor layer 41 away from the substrate 30 and on the sidewall of the chip structure 20. The second reflective layer 82 covers the passipation layer 81; that is, the second reflective layer 82 is located on the surface of the passipation layer 81.

[0131] Here, the passivation layer 81 is made of SiO2, SiN xThe material may also contain at least one of Al2O3, the thickness of the passipation layer 81 may be 10 nm to 40 nm, and the second reflective layer 82 may contain a DBR layer, the DBR layer may contain TiO2 / SiO2 or Ta2O5 / SiO2, etc.

[0132] In some embodiments, the display chip further includes a first isolation layer 83, which is located on the periphery of the chip structure 20. Here, the first isolation layer 83 is made of SiO2 and SiN x It may include at least one of the following:

[0133] In some embodiments, the display chip further includes a second transparent conductive layer 84, the second transparent conductive layer 84 located on the side of the second reflective layer 82 away from the substrate 30 and the side of the first isolation layer 83 away from the substrate 30, and the second transparent conductive layer 84 penetrates the second reflective layer 82 and the passipation layer 81 to connect to the highly doped semiconductor layer 41 in the first semiconductor layer 4.

[0134] Here, the second transparent conductive layer 84 may include an ITO layer, and the thickness of the second transparent conductive layer 84 may be 100 nm to 400 nm.

[0135] In some embodiments, the display chip further includes an n-type ohmic contact electrode, which is located on the circumferential side of the chip structure 20 and on the side of the second transparent conductive layer 84 away from the substrate 30. Here, the n-type ohmic contact electrode includes a metal layer, such as Ti / Al / Ti / Au.

[0136] In some embodiments, as shown in Figure 14, the display chip further includes a third reflective layer 85, the third reflective layer 85 located on the periphery side of the chip structure 20 and on the side of the second transparent conductive layer 84 away from the substrate 30. The third reflective layer 85 can reduce optical crosstalk and light divergence angle between pixels and improve the light extraction efficiency of the chip. The third reflective layer 85 may include a metal layer, for example, at least one of Ag or Al.

[0137] In some embodiments, the display chip further includes a second isolation layer 86, which is located on the periphery of the chip structure 20 and covers the second transparent conductive layer 84 and the third reflective layer 85. The surface of the second isolation layer 86 away from the substrate 30 may be flush with the surface of the second transparent conductive layer 84 away from the substrate 30. The second isolation layer 86 may be made of SiO2 or SiN x It may include at least one of the following. The first isolation layer 83 and the second isolation layer 86 are used to achieve electrical insulation between pixel mesas.

[0138] In some embodiments, the display chip further includes a microlens 85, the microlens 85 located on the side of the second transparent conductive layer 84 away from the chip structure 20, and the positions of the microlens 85 and the chip structure 20 correspond. The microlens 85 is used to increase light collection from the chip. The microlens 85 contains SiO2 or the like.

[0139] According to the display chip of the embodiment of this application, the first semiconductor layer 4, the quantum well light-emitting layer 5, and the second semiconductor layer 6 are all nitrogen polar film layers, which can be grown at high temperatures, improve the crystal quality of the potential well layer material in the quantum well, improve the injection efficiency of chip carriers, effectively suppress carrier overflow, mitigate the chip's droop effect during high-current injection, improve the light-emitting efficiency of the display chip, and further improve the display effect of the display chip.

[0140] The terms "first," "second," etc., used in the specification and claims of this application are intended to distinguish similar objects and not to describe a specific order or sequence. The data used in this manner are interchangeable where appropriate, so that the embodiments of this application may be carried out in an order other than those illustrated or described herein, and the objects distinguished as "first," "second," etc., are generally of the same kind and do not limit the number of objects; for example, the first object may be one or multiple.

[0141] In the description of this application, "multiple" means two or more.

[0142] In this specification, the terms “one example,” “several examples,” “exemplary example,” “example,” “specific example,” or “several examples” mean that the specific features, structures, materials, or properties described in conjunction with the example are included in at least one example of this application. In this specification, exemplary expressions for the above terms do not necessarily refer to the same example. The specific features, structures, materials, or properties described may be combined in an appropriate manner in any one or more examples.

[0143] Although the embodiments of this application have been described, those skilled in the art will understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of this application, and that the scope of this application is limited by the claims and their equivalents.

Claims

1. It is a display chip, The chip structure includes a first semiconductor layer, a quantum well light-emitting layer, and a second semiconductor layer, which are installed sequentially, wherein one of the first and second semiconductor layers is an n-type semiconductor layer and the other is a p-type semiconductor layer. The display chip is characterized in that the first semiconductor layer, the quantum well light-emitting layer, and the second semiconductor layer are all nitrogen polar film layers.

2. The chip structure further includes a fourth undoped semiconductor layer sequentially placed between the first semiconductor layer and the quantum well light-emitting layer, a first potential barrier layer, a first superlattice layer, and a second superlattice layer. The display chip according to claim 1, characterized in that the fourth undoped semiconductor layer, the first potential barrier layer, the first superlattice layer, and the second superlattice layer are all nitrogen polar film layers.

3. The first semiconductor layer includes a highly doped semiconductor layer and a low-doped semiconductor layer located between the highly doped semiconductor layer and the quantum well light-emitting layer. The display chip according to claim 1 or 2, characterized in that both the high-concentration doped semiconductor layer and the low-concentration doped semiconductor layer are nitrogen polar film layers.

4. The quantum well light-emitting layer includes a fifth undoped semiconductor layer sequentially placed between the first semiconductor layer and the second semiconductor layer, a first potential well layer, a first cap layer, a second barrier layer, a sixth undoped semiconductor layer, a second potential well layer, a second cap layer, and a third potential barrier layer. The display chip according to any one of claims 1 to 3, characterized in that the fifth undoped semiconductor layer, the first potential well layer, the first cap layer, the second potential barrier layer, the sixth undoped semiconductor layer, the second potential well layer, the second cap layer, and the third potential barrier layer are all nitrogen polar film layers.

5. The second semiconductor layer includes an electron blocking layer, a hole injection layer, and an ohmic contact layer, which are sequentially installed on the side of the quantum well light-emitting layer away from the first semiconductor layer. The display chip according to any one of claims 1 to 4, characterized in that the electron blocking layer, the hole injection layer, and the ohmic contact layer are all nitrogen polar film layers.

6. The display chip according to any one of claims 1 to 5, characterized in that the chip structure further includes a first transparent conductive layer, a first reflective layer, and a bonding layer, which are sequentially located on the side of the second semiconductor layer away from the quantum well light-emitting layer.

7. The display chip according to any one of claims 1 to 6, wherein the chip structure further includes a protective layer located between the quantum well light-emitting layer and the second semiconductor layer.

8. The display chip further includes a substrate, The display chip according to any one of claims 1 to 7, characterized in that the substrate is bonded to the side of the chip structure away from the first semiconductor layer.

9. The display chip further includes a passivation layer and a second reflective layer, The display chip according to claim 8, characterized in that the passipation layer is located on the side of the chip structure away from the substrate and covers the side wall of the chip structure, and the second reflective layer covers the passipation layer.

10. The display chip according to claim 9, further comprising a second transparent conductive layer located on the side of the second reflective layer away from the substrate, wherein the second transparent conductive layer is connected to the first semiconductor layer through the second reflective layer and the passivation layer.

11. The display chip according to claim 10, further comprising a third reflective layer located on the periphery of the chip structure and a microlens located on the side of the second transparent conductive layer away from the chip structure.

12. The display chip according to any one of claims 1 to 11, characterized in that the quantum well light-emitting layer includes a red light quantum well light-emitting layer.

13. A method for manufacturing a display chip, Forming the base, A chip structure is formed on one side of the base, and the chip structure includes a first semiconductor layer, a quantum well light-emitting layer, and a second semiconductor layer, which are sequentially installed on one side of the base, with one of the first semiconductor layer and the second semiconductor layer being an n-type semiconductor layer and the other being a p-type semiconductor layer, wherein the first semiconductor layer, the quantum well light-emitting layer, and the second semiconductor layer are all nitrogen polar film layers. A method for manufacturing a display chip, characterized by including the removal of the base.

14. The base includes a substrate, a buffer layer, and a non-doped semiconductor composite layer. The above-mentioned formation of the base is To provide a substrate, A buffer layer is formed on one side of the aforementioned substrate, This includes forming a non-doped semiconductor composite layer on the side of the buffer layer away from the substrate, and the chip structure being located on the side of the non-doped semiconductor composite layer away from the buffer layer. The method for manufacturing a display chip according to claim 13, characterized in that both the buffer layer and the undoped semiconductor composite layer are nitrogen polar film layers.

15. The undoped semiconductor composite layer includes a plurality of stacked undoped semiconductor layers and at least one insertion layer, and there is one insertion layer between any two adjacent undoped semiconductor layers. The method for manufacturing a display chip according to claim 14, characterized in that both the undoped semiconductor layer and the insertion layer are nitrogen polar film layers.

16. The plurality of undoped semiconductor layers include a first undoped semiconductor layer, a second undoped semiconductor layer, and a third undoped semiconductor layer, and the at least one insertion layer includes a first insertion layer and a second insertion layer, and the first undoped semiconductor layer, the first insertion layer, the second undoped semiconductor layer, the second insertion layer, and the third undoped semiconductor layer are sequentially placed between the buffer layer and the first semiconductor layer. The first undoped semiconductor layer, the second undoped semiconductor layer, and the third undoped semiconductor layer all include a u-GaN layer, and the first insertion layer is porous SiN. ｘ The method for manufacturing a display chip according to claim 15, characterized in that it includes a layer, and the second insertion layer includes an AlN layer.

17. Removing the aforementioned base is Removing the aforementioned substrate, A method for manufacturing a display chip according to any one of claims 14 to 16, characterized by comprising removing the buffer layer and the undoped semiconductor composite layer.

18. Before removing the aforementioned base, A method for manufacturing a display chip according to any one of claims 13 to 17, further comprising bonding the side of the chip structure that separates from the base to a substrate.

19. After removing the base as described above, A passivation layer is formed on the side of the chip structure that is separated from the substrate, covering the side wall of the chip structure. The method for manufacturing a display chip according to claim 18, further comprising forming a second reflective layer on the surface of the passipation layer.

20. A second transparent conductive layer is formed on the side of the second reflective layer away from the substrate, and is connected to the first semiconductor layer by penetrating the second reflective layer and the passipation layer. The method for manufacturing a display chip according to claim 19, further comprising forming a microlens on the side of the second transparent conductive layer that is away from the substrate.

Images