Memory and its manufacturing method, electronic device

Abstract

The present invention discloses a memory, a method for manufacturing the same, and an electronic device. The memory includes a first semiconductor structure and a second semiconductor structure coupled to the first semiconductor structure. The first semiconductor structure includes a plurality of memory arrays arranged in an array and spaced apart from each other, each memory array includes a plurality of memory cells arranged in an array, each memory cell includes a vertical transistor extending along a first direction and a capacitor coupled to the vertical transistor, the capacitor includes a first electrode and a second electrode facing each other, the first electrode is coupled to the vertical transistor, the second semiconductor structure includes a peripheral circuit and is provided on the side of the vertical transistor away from the capacitor in the first direction, the first semiconductor structure further includes a common electrode electrically connected to the second electrode of the capacitors in the plurality of memory arrays and a common electrode contact plug provided together with the vertical transistor on the same side of the common electrode in the first direction, the common electrode is coupled to the peripheral circuit via the common electrode contact plug.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to memories, their manufacturing methods, and electronic devices.

Background Art

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. Compared with static memory, DRAM memory has the advantages of a relatively simple structure, low manufacturing cost, and high memory density. With the development of technology, the application of DRAM memory is becoming increasingly widespread.

[0003] Current DRAMs usually include a plurality of memory banks, each memory bank includes a plurality of memory arrays, each memory array shares the same common electrode, the common electrodes corresponding to different memory arrays are separated from each other, and other functional elements (usually including passive elements such as decoupling capacitors) are provided between adjacent memory arrays. However, such a configuration also limits the reduction of the memory chip size.

Summary of the Invention

[0004] According to a first aspect of an embodiment of the present disclosure, a memory is provided, the memory includes a first semiconductor structure and a second semiconductor structure, The first semiconductor structure includes a plurality of memory arrays arranged in an array and spaced apart from each other. Each memory array in the plurality of memory arrays includes a plurality of memory cells arranged in an array. Each memory cell in the plurality of memory cells includes a vertical transistor extending along a first direction and a capacitor coupled to the vertical transistor. The capacitor includes a first electrode and a second electrode facing each other. The first electrode is coupled to the vertical transistor. ​The second semiconductor structure is bonded to the first semiconductor structure and includes peripheral circuits, and the second semiconductor structure is provided on the side of the vertical transistor away from the capacitor in the first direction. The first semiconductor structure further includes a common electrode and a common electrode contact plug, the common electrode being electrically connected to the second electrode of the capacitor in the plurality of memory arrays, the common electrode contact plug and the vertical transistor being located on the same side of the common electrode in a first direction, and the common electrode being coupled to the peripheral circuit via the common electrode contact plug.

[0005] In some embodiments, the common electrode includes a plurality of first plate-like portions corresponding one-to-one to the plurality of memory arrays, and a second plate-like portion connecting the plurality of first plate-like portions, wherein the second plate-like portion is provided between adjacent memory arrays and is closer to the second semiconductor structure than the plurality of first plate-like portions.

[0006] In some embodiments, the orthographic projection of the common electrode contact plug along the first direction lies within the orthographic projection of the second plate-like portion along the first direction.

[0007] In some embodiments, the plurality of first plate-like portions are integrally molded with the second plate-like portion.

[0008] In some embodiments, the orthographic projection of the common electrode contact plug along the first direction lies within a region defined by the four adjacent vertex angles of the orthographic projections of the four adjacent memory arrays along the first direction.

[0009] In some embodiments, the capacitor further includes a capacitor dielectric layer provided between the first electrode and the second electrode, the capacitor dielectric layers in the plurality of memory arrays are integrally molded, and the common electrode contact plug penetrates the capacitor dielectric layer and is coupled to the common electrode.

[0010] In some embodiments, the capacitor further includes a capacitor dielectric layer provided between the first electrode and the second electrode, the capacitor dielectric layers in each memory array are integrally molded, and the capacitor dielectric layers in the plurality of memory arrays are separated from each other.

[0011] In some embodiments, the second electrodes in each memory array are integrally molded, and the second electrodes in the plurality of memory arrays are either integrally molded or separated from each other.

[0012] In some embodiments, the second electrode in the plurality of memory arrays is integrally molded with the common electrode.

[0013] In some embodiments, each memory array further includes a plurality of word lines extending along a second direction and a plurality of bit lines extending along a third direction, wherein each word line of the plurality of word lines is coupled to a row of vertical transistors arranged along the second direction, and each bit line of the plurality of bit lines is coupled to a column of vertical transistors arranged along the third direction, the second direction being perpendicular to the first direction, the third direction being perpendicular to the first direction, and the third direction intersecting the second direction.

[0014] In some embodiments, the word lines in adjacent memory arrays are spaced apart from each other, and the bit lines in adjacent memory arrays are spaced apart from each other.

[0015] In some embodiments, the first semiconductor structure further includes a plurality of first contact plugs coupled in one-to-one correspondence to the plurality of word lines in each memory array, wherein each first contact plug in the plurality of first contact plugs is provided on the side of the corresponding word line closer to the second semiconductor structure, and a plurality of second contact plugs coupled in one-to-one correspondence to the plurality of bit lines in each memory array, wherein each second contact plug in the plurality of second contact plugs is provided on the side of the corresponding bit line closer to the second semiconductor structure.

[0016] In some embodiments, the first semiconductor structure further includes a first interconnection layer, the first interconnection layer being located on the side of the plurality of memory arrays closer to the second semiconductor structure in the first direction, the second semiconductor structure further includes a second interconnection layer, the second interconnection layer being located on the side of the peripheral circuitry closer to the first semiconductor structure in the first direction, and the memory further includes a junction interface provided between the first interconnection layer and the second interconnection layer.

[0017] In some embodiments, the second semiconductor structure further includes a third interconnection layer, the third interconnection layer being located on the side of the peripheral circuit away from the first semiconductor structure, and the third interconnection layer being used to couple the peripheral circuit to an external circuit.

[0018] According to a second aspect of the embodiments of this disclosure, a method for manufacturing a memory is provided, and the method is The present invention provides a first semiconductor structure, wherein the first semiconductor structure includes a plurality of memory arrays arranged in an array and spaced apart from each other, each memory array in the plurality of memory arrays includes a plurality of memory cells arranged in an array, each memory cell in the plurality of memory cells includes a vertical transistor extending along a first direction and a capacitor coupled to the vertical transistor, the capacitor includes a first electrode and a second electrode facing each other, the first electrode is coupled to the vertical transistor, the first semiconductor structure further includes a common electrode and a common electrode contact plug, the common electrode is electrically connected to the second electrode of the capacitor in the plurality of memory arrays, and the common electrode contact plug and the vertical transistor are provided on the same side of the common electrode in the first direction. To provide a second semiconductor structure including peripheral circuits, The first semiconductor structure is joined to the second semiconductor structure such that the common electrode is coupled to the peripheral circuit via the common electrode contact plug, wherein the second semiconductor structure is provided on the side of the vertical transistor away from the capacitor in the first direction.

[0019] According to a third embodiment of the embodiments of this disclosure, an electronic device is provided, the electronic device is, Processor and A memory provided in any one embodiment of the present disclosure, the memory comprising a memory coupled to the processor.

[0020] In the embodiments of this disclosure, multiple memory arrays share the same common electrode, and accordingly, the remaining functional elements (e.g., decoupling capacitors) can be provided on the outer periphery of the multiple memory arrays. This reduces the spacing between adjacent memory arrays, reduces the overall size of the first semiconductor structure, and is advantageous for reducing the chip size of the memory. [Brief explanation of the drawing]

[0021] [Figure 1] A schematic diagram showing a cross-sectional structure of a memory provided in some embodiments of the present disclosure. [Figure 2] A schematic diagram showing an arrangement of a plurality of memory arrays in a memory provided in some embodiments of the present disclosure. [Figure 3a] A schematic diagram showing a cross-sectional structure of a memory provided in some embodiments of the present disclosure cut along the line A1A2 in FIG. 2. [Figure 3b] A schematic diagram showing a cross-sectional structure of a memory provided in some embodiments of the present disclosure cut along the line B1B2 in FIG. 2. [Figure 4] A schematic diagram showing a planar structure of an interconnection wiring provided in some embodiments of the present disclosure. [Figure 5a] A schematic diagram showing a partial cross-sectional structure of a memory provided in some other embodiments of the present disclosure cut along the line A1A2 in FIG. 2. [Figure 5b] A schematic diagram showing a partial cross-sectional structure of a memory provided in some other embodiments of the present disclosure cut along the line B1B2 in FIG. 2. [Figure 6a] A schematic diagram showing a partial cross-sectional structure of a memory provided in some further other embodiments of the present disclosure cut along the line A1A2 in FIG. 2. [Figure 6b] A schematic diagram showing a partial cross-sectional structure of a memory provided in some further other embodiments of the present disclosure cut along the line B1B2 in FIG. 2. [Figure 7] A flowchart of a manufacturing method of a memory provided in some embodiments of the present disclosure. [Figure 8] A block diagram showing a configuration of an electronic device provided in some embodiments of the present disclosure.

Modes for Carrying Out the Invention

[0022] The technical solutions of this disclosure will be described in more detail below with reference to the drawings and embodiments. While the drawings illustrate exemplary embodiments of this disclosure, it should be understood that this disclosure is achievable in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to allow for a more complete understanding of this disclosure and to fully convey its scope to those skilled in the art.

[0023] The present invention will be described more specifically in the following paragraphs with reference to the drawings. The advantages and features of this disclosure will become clearer from the following description and claims. The drawings are in a highly simplified form and do not use accurate scale, and are used solely to easily and clearly illustrate the purpose of the embodiments of this disclosure.

[0024] For the purposes of understanding, the terms “on,” “above,” and “above” in this disclosure should be interpreted in the broadest sense, and the meaning of “on” includes not only the meaning of being “on top of” something without any intervening features or layers (i.e., directly on top of something), but also the meaning of being “on top of” something with intervening features or layers.

[0025] In the embodiments of this disclosure, terms such as "first," "second," and "third" are not intended to limit a specific order or sequence, but rather to distinguish similar objects.

[0026] In the embodiments of this disclosure, the term “layer” refers to a portion of a material that includes a region having thickness. A layer may extend over the entirety of a lower or upper structure, or it may have a smaller extent than the extent of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal planes on the top and bottom surfaces of a continuous structure. A layer may extend along horizontal, vertical, and / or inclined planes. A layer may include a plurality of sublayers.

[0027] In embodiments of this disclosure, the term “coupled” means that two (or more) conductive structures are operably connected to one another, and may include, but are not limited to, the following situations as required by the actual circumstances: 1) Two conductive structures are directly electrically connected; 2) Two conductive structures are indirectly electrically connected (through another conductive structure); 3) Two conductive structures are not electrically connected to one another (e.g., an insulating layer is provided between them), but one of the two conductive structures can control the electrical properties of the other conductive structure in response to an electrical signal. For example, a gate (or word line) is coupled to an active region (or channel region).

[0028] Furthermore, the technical solutions and technical features described in the embodiments of this disclosure can be combined in any way without contradiction.

[0029] At least some embodiments of the present disclosure provide a memory. The memory includes a first semiconductor structure and a second semiconductor structure coupled to the first semiconductor structure. The first semiconductor structure includes a plurality of memory arrays arranged in an array and spaced apart from each other, each memory array in the plurality of memory arrays includes a plurality of memory cells arranged in an array, each memory cell in the plurality of memory cells includes a vertical transistor extending along a first direction and a capacitor coupled to the vertical transistor, the capacitor includes a first electrode and a second electrode facing each other, the first electrode is coupled to the vertical transistor, the second semiconductor structure includes a peripheral circuit, the second semiconductor structure is provided on the side of the vertical transistor away from the capacitor in the first direction, the first semiconductor structure further includes a common electrode and a common electrode contact plug, the common electrode is electrically connected to the second electrode of the capacitor in the plurality of memory arrays, the common electrode contact plug and the vertical transistor are provided on the same side of the common electrode in the first direction, and the common electrode is coupled to the peripheral circuit via the common electrode contact plug. In the embodiments of this disclosure, multiple memory arrays share the same common electrode, and accordingly, the remaining functional elements (e.g., decoupling capacitors) can be provided on the outer periphery of the multiple memory arrays. This reduces the spacing between adjacent memory arrays, reduces the overall size of the first semiconductor structure, and is advantageous for reducing the chip size of the memory.

[0030] Figure 1 is a schematic diagram showing the cross-sectional structure of a memory provided in some embodiments of the present disclosure; Figure 2 is a schematic diagram showing the arrangement of multiple memory arrays within a memory provided in some embodiments of the present disclosure; Figure 3a is a schematic diagram showing the cross-sectional structure of a memory provided in some embodiments of the present disclosure cut along the line A1A2 in Figure 2; and Figure 3b is a schematic diagram showing the cross-sectional structure of a memory provided in some embodiments of the present disclosure cut along the line B1B2 in Figure 2.

[0031] For example, as shown in Figures 1, 2, 3a, and 3b, the memory 10 may include a first semiconductor structure 100 and a second semiconductor structure 200. The first semiconductor structure 100 may include a plurality of memory arrays 105 arranged in an array and spaced apart from each other, and the second semiconductor structure 200 may include peripheral circuits 205. The first semiconductor structure 100 and the second semiconductor structure 200 are joined to each other via a junction interface 300, so that the plurality of memory arrays 105 are each coupled to the peripheral circuits 205.

[0032] For example, as shown in Figures 2, 3a, and 3b, each memory array 105 may include a plurality of memory cells arranged in an array, each memory cell including a vertical transistor 110 extending along a first direction Z and a capacitor 120 coupled to the vertical transistor 110. The second semiconductor structure 200 can be provided on the side of the vertical transistor 110 away from the capacitor 120 in the first direction Z.

[0033] Note that the number of memory arrays in the drawings is illustrative, and the embodiments of this disclosure are not limited thereto. For example, in some examples, memory 10 may include m × n memory arrays 105, where m represents the number of memory arrays 105 in the row direction (e.g., the second direction X described later) and n represents the number of memory arrays 105 in the column direction (e.g., the third direction Y described later), and for example, both m and n are positive integers of 2 or greater. Figure 2 shows the case where both m and n are 2.

[0034] For example, in some examples, as shown in Figures 2, 3a, and 3b, the vertical transistor 110 includes an active pillar 111 extending along a first direction Z, a gate electrode 112 covering the sidewall of the active pillar 111, and a gate dielectric layer 113 located between the active pillar 111 and the gate electrode 112. For example, the material of the active pillar 111 may include any suitable semiconductor material, such as silicon, germanium, gallium arsenide, oxide semiconductor material, etc. For example, oxide semiconductor material may include, but is not limited to, indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium zinc oxide (IZO), etc. For example, the material of the gate electrode 112 may include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicide, doped polysilicon, or any combination thereof. For example, the material of the gate dielectric layer 113 may include any suitable dielectric material, such as silicon oxide, silicon nitride, high-dielectric constant (high-K) dielectric material, or any combination thereof. For example, high-dielectric constant dielectric materials may include, but are not limited to, hafnium oxide (HfO2) or zirconium oxide (ZrO2). Note that the vertical transistor 110 in the drawings is illustrative, and the embodiments of this disclosure do not limit the structure of the vertical transistor 110. For example, the vertical transistor 110 may be a gate-all-around (GAA) transistor (as shown in the drawings), a single-gate transistor, a double-gate (e.g., opposing-gate) transistor, or a triple-gate transistor.

[0035] For example, as shown in Figures 3a and 3b, the capacitor 120 includes a first electrode 121 and a second electrode 122 facing each other, and a capacitor dielectric layer 123 provided between the first electrode 121 and the second electrode 122. For example, the materials of the first electrode 121 and the second electrode 122 include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicide, doped polysilicon, or any combination thereof. For example, the material of the capacitor dielectric layer 123 includes any suitable dielectric material, such as silicon oxide, silicon nitride, high dielectric constant dielectric material, or any combination thereof. For example, the material of the capacitor dielectric layer 123 may further include a dielectric material having ferroelectric or antiferroelectric properties, such as ferroelectric phase hafnium oxide or ferroelectric phase hafnium zirconium oxide, i.e., the capacitor 120 may be a ferroelectric capacitor.

[0036] For example, in some embodiments, as shown in Figures 3a and 3b, the first electrode 121 may be coupled to the vertical transistor 110 via a contact pad 115. For example, the first electrode 121 is coupled to the first source / drain electrode of the vertical transistor 110. For example, the material of the contact pad 115 may include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicide, doped polysilicon, or any combination thereof. For example, the shape and structure of the contact pad 115 can be set as needed to match the arrangement of the multiple capacitors 120 in the memory array 105 (e.g., a four-way arrangement or a six-way dense arrangement). In some other embodiments, the contact pad 115 may be omitted, i.e., the first electrode 121 may be directly coupled to the vertical transistor 110.

[0037] For example, as shown in Figures 2, 3a, and 3b, the first semiconductor structure 100 further includes a common electrode 124 and a common electrode contact plug 150. The common electrode 100 is electrically connected to the second electrode 122 of the capacitors 120 in the multiple memory arrays 105, i.e., the multiple memory arrays 105 share the same common electrode 100. The common electrode contact plug 150 and the vertical transistor 105 are located on the same side of the common electrode 124 in the first direction Z. The common electrode 124 is coupled to a peripheral circuit 205 (e.g., the ground terminal of the peripheral circuit 205) via the common electrode contact plug 150.

[0038] In related memory technologies, each memory array shares the same common electrode, while common electrodes corresponding to different memory arrays are separated from each other, and the remaining functional elements (usually including passive elements such as decoupling capacitors) are provided between adjacent memory arrays. However, such a configuration also limits the reduction of the memory chip size. In the embodiments of this disclosure, multiple memory arrays 105 share the same common electrode 100, and the remaining functional elements (e.g., decoupling capacitors) can be provided on the outer periphery of the multiple memory arrays 105. This reduces the spacing between adjacent memory arrays 105, reduces the overall size of the first semiconductor structure 100, and is advantageous for reducing the chip size of the memory 10.

[0039] For example, the material of the common electrode 124 may include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, doped polysilicon, silicon germanium (SiGe), or any combination thereof. For example, the material of the common electrode contact plug 150 may include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, cobalt, metal silicide, or any combination thereof.

[0040] For example, in some cases, as shown in Figures 3a and 3b, the second electrode 122 in each memory array 105 is integrally molded, the capacitor dielectric layer 123 in each memory array 105 is integrally molded, and furthermore, the second electrode 122 in multiple memory arrays 105 and the capacitor dielectric layer 123 in multiple memory arrays 105 are integrally molded, thereby simplifying the manufacturing process of the first semiconductor structure 100. That is, both the second electrode 122 and the capacitor dielectric layer 123 can be shared by multiple memory arrays 105. In this case, as shown in Figures 3a and 3b, one end of the common electrode contact plug 150 penetrates the shared capacitor dielectric layer 123 and makes contact with the shared second electrode 122, thereby realizing an electrical connection between the common electrode contact plug 150 and the common electrode 124. To make it clear, based on the embodiments shown in Figures 3a and 3b, one end of the common electrode contact plug 150 may further penetrate the shared second electrode 122 and directly contact the common electrode 124. Furthermore, to make it clear, in some examples the second electrodes 122 in multiple memory arrays 105 can be separated from each other, so that one end of the common electrode contact plug 150 may penetrate the shared capacitor dielectric layer 123 and then directly contact the common electrode 124.

[0041] For example, in some cases, as shown in Figures 3a and 3b, the common electrode 124 may include a plurality of first plate-like portions 124a that correspond one-to-one with a plurality of memory arrays 105, and a second plate-like portion 124b that connects the plurality of first plate-like portions 124a, the second plate-like portion 124b being provided between adjacent memory arrays 105, and the second plate-like portion 124b being closer to the second semiconductor structure 200 than the plurality of first plate-like portions 124. For example, the orthogonal projection of the second plate-like portion 124b along the first direction Z may exhibit a grid pattern. In this disclosure, an orthogonal projection along a certain direction refers to an orthogonal projection into a virtual plane perpendicular to that direction.

[0042] For example, in some cases, as shown in Figures 3a and 3b, the common electrode 124 may further include an extended portion 124c extending along a first direction Z, the extended portion 124c being provided on the side wall of the first electrode 121 and connected to a corresponding first plate-like portion 124a, the first plate-like portion 124a being connected to a second plate-like portion 124b via the extended portion 124c.

[0043] For example, in some cases, as shown in Figures 3a and 3b, a recess 124R is formed within the common electrode 124, the first plate-like portion 124a is located on both sides of the opening of the recess 124R, the second plate-like portion 124b is located at the bottom of the recess 124R, and a portion of the extended portion 124c is located on the side wall of the recess 124R. For example, in some cases, the first semiconductor structure may further include a planarizing layer (not shown) provided on the side of the common electrode 124 away from the second semiconductor structure 200 and filling the recess 124R.

[0044] For example, in some cases, as shown in Figures 3a and 3b, the multiple first plate-like portions 124a, second plate-like portions 124b, and extended portions 124c may be integrally molded. For example, in some cases, as shown in Figures 2, 3a, and 3b, the orthographic shape of the common electrode along the first direction Z may be a closed figure (e.g., without internal voids and / or gaps).

[0045] For example, in some cases, as shown in Figures 3a and 3b, the orthographic projection of the common electrode contact plug 150 along the first direction Z may be located within the orthographic projection of the second plate-like portion 124b along the first direction. That is, the common electrode contact plug 150 is coupled to the second plate-like portion 124b, thereby achieving coupling with the common electrode 124, which is advantageous in shortening the transmission path of the common electrode contact plug 150 and reducing the transmission resistance of the common electrode contact plug 150. For example, in some cases, the first semiconductor structure 100 may include a plurality of common electrode contact plugs 150, and the orthographic projection of at least one common electrode contact plug 150 along the first direction Z may be located within the orthographic projection of the second plate-like portion 124b along the first direction.

[0046] For example, as shown in Figures 2, 3a, and 3b, each memory array 105 may further include a plurality of word lines 130 extending along a second direction X and a plurality of bit lines 140 extending along a third direction Y. In each memory array 105, each word line 130 is coupled to a row of vertical transistors 110 arranged along the second direction X, for example, the word line 130 is coupled to the gate electrode of the vertical transistor 110, or the gate electrode of the vertical transistor 110 is part of the word line 130. Each bit line 140 is coupled to a column of vertical transistors 110 arranged along the third direction Y, for example, the bit line 140 is coupled to the second source / drain electrode of the vertical transistor. For example, the second direction X is perpendicular to the first direction Z, and the third direction Y is perpendicular to the first direction Z. For example, the third direction Y intersects with the second direction X, and for example, the third direction Y may be perpendicular to the second direction X. In this disclosure, the definitions of rows and columns are relative and interchangeable.

[0047] For example, the material of word wire 130 may include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicide, doped polysilicon, or any combination thereof. For example, the material of bit wire 140 may include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicide, doped polysilicon, or any combination thereof.

[0048] For example, as shown in Figures 2, 3a, and 3b, in each memory array 105, multiple word lines 130 may be arranged at intervals along the third direction Y, multiple bit lines 140 may be arranged at intervals along the second direction X, word lines 130 in adjacent memory arrays 105 may be arranged at intervals from each other, and bit lines 140 in adjacent memory arrays 105 may be arranged at intervals from each other. In other words, two word lines 130 located on the same straight line (for example, a straight line extending along the second direction X) in adjacent memory arrays 105 can be controlled independently, and two bit lines 140 located on the same straight line (for example, a straight line extending along the third direction Y) in adjacent memory arrays 105 can be controlled independently.

[0049] For example, in some cases, as shown in Figures 3a and 3b, the bit wire 140 is coupled to a vertical transistor via a bit wire contact plug 116. For example, the material of the bit wire contact plug 116 may include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicide, doped polysilicon, or any combination thereof.

[0050] For example, as shown in Figures 2, 3a, and 3b, the first semiconductor structure may further include a plurality of first contact plugs 160 coupled in one-to-one correspondence to a plurality of word lines 130 in each memory array 105, and a plurality of second contact plugs 170 coupled in one-to-one correspondence to a plurality of bit lines 140 in each memory array 105. Each first contact plug 160 is provided on the side of the corresponding word line 130 closer to the second semiconductor structure 200, and each second contact plug 170 is provided on the side of the corresponding bit line 140 closer to the second semiconductor structure 200.

[0051] For example, in some cases, as shown in Figures 2, 3a, and 3b, within each memory array 105, the first end of an odd-numbered word line 130 (e.g., the left end in Figure 2) is coupled to the corresponding first contact plug 160, the second end of an even-numbered word line 130 (e.g., the right end in Figure 2) is coupled to the corresponding first contact plug 160, the first end of an odd-numbered bit line 140 (e.g., the bottom end in Figure 2) is coupled to the corresponding second contact plug 170, and the second end of an even-numbered bit line 140 (e.g., the top end in Figure 2) is coupled to the corresponding second contact plug 170. This allows for an expansion of the process window for the first contact plug 160 and the second contact plug 170 during the manufacturing process.

[0052] For example, in some cases, the first contact plug 160, the second contact plug 170, and the common electrode contact plug 150 may be formed simultaneously, that is, these three may have substantially the same structure and material composition.

[0053] For example, in some cases, as shown in Figures 2, 3a, and 3b, the orthographic projection of the common electrode contact plug 150 along the first direction Z lies within a region defined by the four adjacent vertex angles of the orthographic projections of the four adjacent memory arrays 105 along the first direction Z. This allows the common electrode contact plug 150 to be provided with a larger cross-sectional area, which helps to reduce the transmission resistance of the common electrode contact plug 150.

[0054] For example, in some cases, as shown in Figures 2, 3a, and 3b, the orthographic area of ​​the common electrode contact plug 150 along the first direction Z can be larger than the orthographic area of ​​the first contact plug 160 along the first direction Z, and also larger than the orthographic area of ​​the second contact plug 170 along the first direction Z.

[0055] For example, in some cases, as shown in Figures 3a and 3b, the first semiconductor structure 100 may further include a first interconnection layer 180, the first interconnection layer 180 being located on the side of the multiple memory arrays 105 closer to the second semiconductor structure 200 in the first direction Z, the second semiconductor structure 200 may further include a second interconnection layer 220, the second interconnection layer 220 being located on the side of the peripheral circuit 205 closer to the first semiconductor structure in the first direction Z, and the memory 10 may further include a junction interface 300 provided between the first interconnection layer 180 and the second interconnection layer 220. For example, the first interconnection layer 180 and the second interconnection layer 220 are joined via the junction interface 300 to realize the junction between the first semiconductor structure 100 and the second semiconductor structure 200. For example, the above junction can be achieved by employing hybrid bonding technology.

[0056] For example, in some cases, as shown in Figures 3a and 3b, the first interconnection layer 180 may include multiple layers of first interconnection wiring 181, first interconnection vias 182 provided between adjacent layers of first interconnection wiring 181, and a plurality of first bonding pads 183. Similarly, the second interconnection layer 220 may include multiple layers of second interconnection wiring 221, second interconnection vias 222 provided between adjacent layers of second interconnection wiring 221, and a plurality of second bonding pads 223. Here, the plurality of first bonding pads 183 and the plurality of second bonding pads 223 are bonded to each other via a bonding interface 300. For example, each of the common electrode contact plug 150, the first contact plug 160, and the second contact plug 170 is coupled to the peripheral circuit 205 via the first interconnection wiring 181, the first interconnection via 182, the first bonding pad 183, the second bonding pad 223, the second interconnection via 222, and the second interconnection wiring 221.

[0057] For example, in some cases, as shown in Figures 3a and 3b, the second semiconductor structure 200 may include a semiconductor substrate 201, and the peripheral circuit 205 may include a plurality of transistors 210 at least partially provided within the semiconductor substrate 201, which are used to realize the structure and function of control circuits such as word line drivers (e.g., sub-word line drivers) and sense amplifiers (SAs). For example, as shown in Figures 3a and 3b, the transistor 210 may include an active region 211 located within the substrate, a gate electrode 212 provided in the active region 211, and a gate dielectric layer 213 located between the active region 211 and the gate 212, and trench isolation structures 207 defining each active region 211 may be provided within the semiconductor substrate 201. For example, the material of the semiconductor substrate 201 may include any suitable semiconductor material, such as silicon, germanium, gallium arsenide, oxide semiconductor material, etc. For example, the material of the gate electrode 212 may include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicide, doped polysilicon, or any combination thereof. For example, the material of the gate dielectric layer 213 may include any suitable dielectric material, such as silicon oxide, silicon nitride, high dielectric constant dielectric material, or any combination thereof. Note that the transistor 210 in the drawings is illustrative, and the embodiments of this disclosure do not limit the structure of the transistor 210. For example, the transistor 210 may be a planar transistor (as shown in the drawings), a fin-type transistor (FinFET), or the like.

[0058] For example, in some cases, as shown in Figures 3a and 3b, the second semiconductor structure may further include a plurality of third contact plugs 230 provided between the peripheral circuit 205 and the second interconnection layer 220, which are used to achieve coupling between the peripheral circuit 205 and the second interconnection layer 220.

[0059] For example, in some cases, as shown in Figures 3a and 3b, the second semiconductor structure 200 may further include a third interconnection layer 280, the third interconnection layer 280 being located on the side of the peripheral circuit 205 away from the first semiconductor structure 100, and the third interconnection layer 280 being used to connect the peripheral circuit 205 to an external circuit. For example, as shown in Figures 3a and 3b, the peripheral circuit 205 and the second interconnection layer 220 are located on the first surface (such as the front) of the semiconductor substrate 201, and the third interconnection layer 280 is located on the second surface (such as the back) of the semiconductor substrate 201.

[0060] For example, in some cases, as shown in Figures 3a and 3b, the third interconnection layer 280 may include multiple layers of third interconnection wiring 281, third interconnection vias 282 provided between adjacent layers of third interconnection wiring 281, and multiple lead pads 283.

[0061] For example, in some cases, as shown in Figures 3a and 3b, the second semiconductor structure may further include a plurality of fourth contact plugs 250 penetrating the semiconductor substrate 201, which are used to achieve coupling between the second interconnection layer 220 and the third interconnection layer 280. To understand this, a separation layer (not shown) may be provided between the fourth contact plugs 250 and the semiconductor substrate 201 to achieve electrical insulation between the fourth contact plugs 250 and the semiconductor substrate 201.

[0062] For example, in some cases, as shown in Figures 3a and 3b, the peripheral circuit 205 is coupled to the external circuit via a third contact plug 230, a second interconnection layer 220 (e.g., a second interconnection wire 221 therein, or a second interconnection wire 221 and a second interconnection via 222 therein), a fourth contact plug 250, and a third interconnection layer 280 (e.g., a third interconnection wire 281, a third interconnection via 282, and a lead pad 283 therein).

[0063] Figure 4 is a schematic diagram showing the planar structure of an interconnect wiring provided in some embodiments of the present disclosure. For example, as shown in Figure 4, a first interconnect wiring 181 is coupled to a first contact plug 160 (or second contact plug 170) and a first interconnect via 182 located on either side thereof, and the width of the first interconnect wiring 181 is advantageous in increasing the contact area and reducing contact resistance by having a local maximum at the connection point with the first contact plug 160 (or second contact plug 170) and the first interconnect via 182. As shown in Figure 4, the first interconnect wiring 181 extends along a third direction E1, the width of the first interconnect wiring 181 refers to the size of the first interconnect wiring 181 in a third direction E2 perpendicular to the third direction E1, and the local maximum refers to the width of a section of the first interconnect wiring 181 being greater than the width of other sections near the section (which may not be all of the remaining sections, but for example, some sections on either side of the section). For example, both the third direction E1 and the fourth direction E2 are parallel to the plane defined by the second direction X and the third direction Y, and the third direction E1 may be parallel to the second direction X or the third direction Y, or it may intersect with both. In Figure 4, the first interconnection wiring 181, the first contact plug 160 (or the second contact plug 170), and the first interconnection via 182 are explained as examples, but the remaining interconnection wiring and the contact plugs / interconnection vias on both sides thereof can also be provided by referring to Figure 4.

[0064] In this disclosure, the interconnection layers (e.g., first interconnection layer 180, second interconnection layer 220, third interconnection layer 280) may include one or more interlayer dielectric layers, and interconnection wiring (e.g., first interconnection wiring 181, second interconnection wiring 221, third interconnection wiring 281), interconnection vias (e.g., first interconnection via 182, second interconnection via 222, third interconnection via 282), pads (e.g., first bonding pad 183, second bonding pad 223, lead pad 283), etc., may all be formed within the one or more interlayer dielectric layers. For example, the material of the interconnection wiring and interconnection vias may include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, aluminum, cobalt, copper, metal silicide, doped polysilicon, or any combination thereof. For example, the material of the pads may include, but are not limited to, any suitable conductive material, such as copper. The material of the interlayer dielectric layer may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-dielectric constant (low-K) dielectric materials, or any combination thereof.

[0065] The structure of the capacitor 120 in the drawings of this disclosure is illustrative, and the embodiments of this disclosure are not limited to the structure of the capacitor 120. The arrangement of the first electrode 121, the second electrode 122, and the capacitor dielectric layer 123 may be such that the capacitor 120 can be formed. For example, the first electrode 121 may be columnar (as shown in the drawings), plate-shaped, U-shaped, or any other suitable shape. The second electrode 122 conformally covers the sidewall and / or top surface of the first electrode 121, and the capacitor dielectric layer 123 is located between the first electrode 121 and the second electrode 122. For example, in some examples, the first semiconductor structure 100 may have one or more support layers for supporting the first electrode, the support layers may be lattice-shaped, and the capacitor dielectric layer 123 and the second electrode 122 may partially cover the support layers.

[0066] Figure 5a is a schematic diagram showing a partial cross-sectional structure of a memory provided in some other embodiments of the present disclosure, cut along the line A1A2 in Figure 2, and Figure 5b is a schematic diagram showing a partial cross-sectional structure of a memory provided in some other embodiments of the present disclosure, cut along the line B1B2 in Figure 2. For simplicity, compared to Figures 3a and 3b, only some of the memory structures are shown in Figures 5a and 5b, and structures not shown in Figures 5a and 5b can be referred to by the corresponding structures in Figures 3a and 3b.

[0067] The main difference between the memory in the embodiment shown in Figures 5a and 5b and the memory in the embodiment shown in Figures 3a and 3b is that, in the memory in the embodiment shown in Figures 5a and 5b, the second electrode 122 in each memory array 105 is integrally molded, the capacitor dielectric layer 123 in each memory array 105 is integrally molded, and furthermore, the second electrode 122 in multiple memory arrays 105 is integrally molded, but the capacitor dielectric layers 123 in multiple memory arrays 105 are separated from each other. In this case, as shown in Figures 5a and 5b, one end of the common electrode contact plug 150 can be directly contacted with the shared second electrode 122 without penetrating the capacitor dielectric layer 123. To understand this, based on the embodiment shown in Figures 5a and 5b, one end of the common electrode contact plug 150 can penetrate the shared second electrode 122 and be directly contacted with the common electrode 124. Furthermore, to make it clearer, in some examples, the second electrodes 122 in multiple memory arrays 105 can be separated from each other, thereby allowing one end of the common electrode contact plug 150 to be directly connected to the common electrode 124.

[0068] The remaining structural features of the memory in the embodiment shown in Figures 5a and 5b can be found in the description of Figures 3a and 3b above and will not be repeated here.

[0069] Figure 6a is a schematic diagram showing a partial cross-sectional structure of a memory provided in several other embodiments of this disclosure, cut along the line A1A2 in Figure 2, and Figure 6b is a schematic diagram showing a partial cross-sectional structure of a memory provided in several other embodiments of this disclosure, cut along the line B1B2 in Figure 2. Note that, as with Figures 5a and 5b, for simplicity, only a portion of the memory structure is shown in Figures 6a and 6b, and structures not shown in Figures 6a and 6b can be referred to in the corresponding structures in Figures 3a and 3b.

[0070] The main difference between the memory in the embodiment shown in Figures 6a and 6b and the memory in the embodiment shown in Figures 5a and 5b is that in the memory in the embodiment shown in Figures 6a and 6b, the second electrode 122 and the common electrode 124 are integrally molded, thereby simplifying the process steps. That is, the second electrode 122 and the common electrode 124 are formed as a single structure, and the two are not strictly distinguished, or are both considered to be part of the integral structure. For example, in some examples, the second electrode 122 and the common electrode 124 in the embodiment shown in Figures 3a and 3b can be considered as a single structure, that is, the integral structure may be a multilayer structure and does not necessarily have to be a single layer structure.

[0071] The remaining structural features of the memory in the embodiment shown in Figures 6a and 6b can be found in the description of Figures 3a and 3b above and will not be repeated here.

[0072] For example, in some embodiments, the memory 10 may include multiple memory banks, each memory bank including multiple memory arrays (i.e., multiple memory arrays 105), where the multiple memory arrays within each memory bank share the same common electrode (i.e., common electrode 124), meaning that each memory bank corresponds to one common electrode, and common electrodes corresponding to different memory banks are separated from each other. For example, passive elements may be provided between adjacent memory banks, and these passive elements include, but are not limited to, decoupling capacitors.

[0073] For example, the memory 10 may be a dynamic random access memory (DRAM) or a ferroelectric random access memory (Fe-RAM), but is not limited to these.

[0074] For clarity and conciseness, most insulating layers and / or dielectric layers in the first and second semiconductor structures are omitted from the drawings; for example, the packing layer and support layer mentioned above are omitted.

[0075] At least some embodiments of the present disclosure further provide a method for manufacturing a memory, the manufacturing method which can be used to manufacture the memory in the above embodiments. Figure 7 is a flowchart of a method for manufacturing a memory provided in some embodiments of the present disclosure. For example, as shown in Figure 7, the manufacturing method may include the following steps S100 to S300.

[0076] In step S100, a first semiconductor structure is provided, the first semiconductor structure includes a plurality of memory arrays arranged in an array and spaced apart from each other, each memory array in the plurality of memory arrays includes a plurality of memory cells arranged in an array, each memory cell in the plurality of memory cells includes a vertical transistor extending along a first direction and a capacitor coupled to the vertical transistor, the capacitor includes a first electrode and a second electrode facing each other, the first electrode is coupled to the vertical transistor, the first semiconductor structure further includes a common electrode and a common electrode contact plug, the common electrode is electrically connected to the second electrode of the capacitor in the plurality of memory arrays, and the common electrode contact plug and the vertical transistor are provided on the same side of the common electrode in the first direction.

[0077] For example, in some cases, taking the first semiconductor structure 100 shown in Figures 2, 3a, and 3b as an example, providing the first semiconductor structure may include forming a vertical transistor 110, a word line 130, a contact pad 115, a capacitor 120, and a common electrode 124 on a first surface (such as the front) of the substrate, and thinning or removing the substrate from a second surface (such as the back) to form a bit line 140, a common electrode contact plug 150, a first contact plug 160, a second contact plug 170, and a first interconnection layer 180.

[0078] In step S200, a second semiconductor structure is provided, the second semiconductor structure including peripheral circuits.

[0079] For example, in some cases, taking the second semiconductor structure 200 shown in Figures 2, 3a, and 3b as an example, providing the second semiconductor structure may include forming peripheral circuits 205 (as shown by the transistor 210 in the figure), a third contact plug 230, and a second interconnection layer 220 on the first surface (front, etc.) of the semiconductor substrate 201, and thinning the semiconductor substrate 201 from the second surface (back, etc.) to form a fourth contact plug 250 and a third interconnection layer 280.

[0080] In step S300, the first semiconductor structure and the second semiconductor structure are joined so that the common electrode is coupled to the peripheral circuit via a common electrode contact plug, and the second semiconductor structure is provided on the side of the vertical transistor away from the capacitor in the first direction.

[0081] For example, hybrid bonding technology can be used to bond the first semiconductor structure and the second semiconductor structure.

[0082] For example, in some cases, taking the memory 10 shown in Figures 2, 3a, and 3b as an example, joining the first semiconductor structure 100 and the second semiconductor structure 200 may include joining the first interconnection layer 180 and the second interconnection layer 220 to achieve a junction between the first semiconductor structure 100 and the second semiconductor structure 200, where the junction interface 300 is located between the first interconnection layer 180 and the second interconnection layer 220.

[0083] Furthermore, one or more steps of the above manufacturing method may include multiple substeps, and these substeps may be performed sequentially or in parallel, depending on the actual requirements. Also, substeps in different steps may be performed sequentially, in parallel, or alternately, depending on the actual requirements.

[0084] For example, in some embodiments, a first semiconductor structure may be provided first, followed by an initial second semiconductor structure. That is, peripheral circuits 205 (as shown by transistor 210 in the figure), a third contact plug 230, and a second interconnection layer 220 may be formed on the first surface (front, etc.) of the semiconductor substrate 201, then the first semiconductor structure and the initial second semiconductor structure may be joined together, and finally, the semiconductor substrate 201 of the initial second semiconductor structure may be thinned from the second surface (back, etc.) to form a fourth contact plug 250 and a third interconnection layer 280.

[0085] Further details and technical effects of the manufacturing methods provided in the embodiments of this disclosure can be found in the relevant descriptions in the above-described embodiments of memory, and will not be repeated here.

[0086] At least some embodiments of the present disclosure further provide electronic devices. Figure 8 is a block diagram showing the configuration of an electronic device provided in some embodiments of the present disclosure. As shown in Figure 8, the electronic device 1 includes a processor 20 and a memory 10 in the above embodiments, the memory 10 being coupled to the processor 20.

[0087] For example, the processor 20 may include, but is not limited to, a central processing unit (CPU) or a graphics processing unit (GPU). The memory 10 may be configured to store data processed by the processor 20 and / or data processed by the processor.

[0088] For example, electronic device 1 includes, but is not limited to, mobile phones, tablets, smart bands, wearable electronic devices, virtual reality devices, augmented reality devices, in-vehicle equipment, servers, workstations, etc.

[0089] The foregoing describes only specific embodiments of the Disclosure, and the scope of protection of the Disclosure is not limited thereto. Any modifications or substitutions that a person skilled in the art could easily conceive of within the technical scope disclosed herein should be included within the scope of protection of the Disclosure. Accordingly, the scope of protection of the Disclosure shall be subject to the scope of protection of the claims.

Claims

1. Memory (10), The present invention comprises a first semiconductor structure (100) and a second semiconductor structure (200), The first semiconductor structure (100) includes a plurality of memory arrays (105) arranged in an array and spaced apart from each other, each memory array in the plurality of memory arrays includes a plurality of memory cells arranged in an array, each memory cell in the plurality of memory cells includes a vertical transistor (110) extending along a first direction (Z) and a capacitor (120) coupled to the vertical transistor, the capacitor includes a first electrode (121) and a second electrode (122) facing each other, the first electrode is coupled to the vertical transistor, The second semiconductor structure (200) is bonded to the first semiconductor structure and includes a peripheral circuit (205), the second semiconductor structure is provided on the side of the vertical transistor away from the capacitor in the first direction, The first semiconductor structure further includes a common electrode (124) and a common electrode contact plug (150), wherein the common electrode is electrically connected to the second electrode of the capacitor in the plurality of memory arrays, the common electrode contact plug and the vertical transistor are provided on the same side of the common electrode in the first direction, and the common electrode is coupled to the peripheral circuit via the common electrode contact plug, memory (10).

2. The common electrode includes a plurality of first plate-shaped portions (124a) corresponding one-to-one to the plurality of memory arrays, and a second plate-shaped portion (124b) connecting the plurality of first plate-shaped portions, wherein the second plate-shaped portion is provided between adjacent memory arrays and is closer to the second semiconductor structure than the plurality of first plate-shaped portions. The memory according to claim 1.

3. The orthographic projection of the common electrode contact plug along the first direction is located within the orthographic projection of the second plate-shaped portion along the first direction. The memory according to claim 2.

4. The common electrode further includes an extended portion (124c) extending along the first direction, the extended portion being provided on the side wall of the first electrode and connected to the corresponding first plate-like portion, and the first plate-like portion being connected to the second plate-like portion via the extended portion. The memory according to claim 2 or 3.

5. The plurality of first plate-like portions are integrally molded with the second plate-like portion. The memory according to claim 2 or 3.

6. The orthographic projection of the common electrode contact plug along the first direction lies within a region defined by the four adjacent vertex angles of the orthographic projections of the four adjacent memory arrays along the first direction. The memory according to any one of claims 1 to 5.

7. The capacitor further includes a capacitor dielectric layer (123) provided between the first electrode and the second electrode, the capacitor dielectric layers in the plurality of memory arrays are integrally molded, and the common electrode contact plug penetrates the capacitor dielectric layer and is coupled to the common electrode. The memory according to any one of claims 1 to 6.

8. The capacitor further includes a capacitor dielectric layer provided between the first electrode and the second electrode, the capacitor dielectric layers in each memory array are integrally molded, and the capacitor dielectric layers in the plurality of memory arrays are separated from each other. The memory according to any one of claims 1 to 6.

9. The second electrodes in each of the memory arrays are integrally molded, and the second electrodes in the plurality of memory arrays are either integrally molded or separated from each other. The memory according to any one of claims 1 to 8.

10. The second electrode in the plurality of memory arrays is integrally molded with the common electrode. The memory according to any one of claims 1 to 8.

11. Each of the memory arrays further includes a plurality of word lines (130) extending along a second direction (X) and a plurality of bit lines (140) extending along a third direction (Y), In each of the memory arrays, each word line of the plurality of word lines is coupled to a row of vertical transistors arranged along the second direction, and each bit line of the plurality of bit lines is coupled to a column of vertical transistors arranged along the third direction. The second direction is perpendicular to the first direction, the third direction is perpendicular to the first direction, and the third direction intersects with the second direction. The memory according to any one of claims 1 to 10.

12. The word lines in adjacent memory arrays are spaced apart from each other, and the bit lines in adjacent memory arrays are spaced apart from each other. The memory according to claim 11.

13. The first semiconductor structure is, A plurality of first contact plugs (160) coupled in a one-to-one correspondence with the plurality of word lines in each memory array, wherein each of the plurality of first contact plugs is provided on the side of the corresponding word line closer to the second semiconductor structure, A plurality of second contact plugs (170) coupled in a one-to-one correspondence with the plurality of bit lines in each memory array, wherein each second contact plug in the plurality of second contact plugs is provided on the side of the corresponding bit line closer to the second semiconductor structure, further comprising: The memory according to claim 11 or 12.

14. The first semiconductor structure further includes a first interconnection layer (180), the first interconnection layer being provided on the side of the plurality of memory arrays closer to the second semiconductor structure in the first direction, The second semiconductor structure further includes a second interconnection layer (220), the second interconnection layer being provided on the side of the peripheral circuit closer to the first semiconductor structure in the first direction, The memory further includes a bonding interface (300) provided between the first interconnection layer and the second interconnection layer. The memory according to any one of claims 1 to 13.

15. The second semiconductor structure further includes a third interconnection layer (280), the third interconnection layer being provided on the side of the peripheral circuit away from the first semiconductor structure, and the third interconnection layer being used to connect the peripheral circuit to an external circuit. The memory according to any one of claims 1 to 14.

16. Electronic device (1), Processor (20) and An electronic device (1) comprising a memory (10) according to any one of claims 1 to 13, wherein the memory (10) is coupled to the processor.

17. A method for manufacturing memory, The present invention provides a first semiconductor structure, wherein the first semiconductor structure includes a plurality of memory arrays arranged in an array and spaced apart from each other, each memory array in the plurality of memory arrays includes a plurality of memory cells arranged in an array, each memory cell in the plurality of memory cells includes a vertical transistor extending along a first direction and a capacitor coupled to the vertical transistor, the capacitor includes a first electrode and a second electrode facing each other, the first electrode is coupled to the vertical transistor, the first semiconductor structure further includes a common electrode and a common electrode contact plug, the common electrode is electrically connected to the second electrode of the capacitor in the plurality of memory arrays, and the common electrode contact plug and the vertical transistor are provided on the same side of the common electrode in the first direction. To provide a second semiconductor structure including peripheral circuits, A method for manufacturing a memory, comprising joining the first semiconductor structure to the second semiconductor structure such that the common electrode is coupled to the peripheral circuit via the common electrode contact plug, wherein the second semiconductor structure is provided on the side of the vertical transistor away from the capacitor in the first direction.

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