Devices, systems, and methods for optimizing the characteristics of transistor channels

Abstract

A device and related methods are disclosed. The device may include a gate structure, a first electrode, and a second electrode. In addition, the device may include a multilayer channel structure configured to be in electrical communication with the first electrode and the second electrode. The multilayer channel structure has a carrier-depleted layer and an electron injection layer disposed on the carrier-depleted layer.

Description

Technical Field

[0001] The present disclosure relates to semiconductors. More specifically, the present disclosure relates to devices, systems, and methods for optimizing the characteristics of transistor channels, such as the channels of FeFETs.

Background Art

[0002] Description of the Related Art

[0003] Electron mobility is an important parameter in the design, manufacture, and use of semiconductor devices and materials, and determines how electrons move within a material when an electric field is applied to the material. Electron mobility generally determines the conductivity and performance of various electronic devices, including transistors, diodes, and integrated circuits. Higher electron mobility shortens the switching time and enables the device to operate more efficiently and at higher frequencies.

[0004] In a semiconductor device, the current is mainly determined by the flow of electrons and holes, which are the main charge carriers. These charge carriers move through the material and thus define the amount of current flowing through the material in response to the electric field acting on the charge carriers.

[0005] Electron mobility can be determined by various factors such as material properties, temperature, doping, and scattering mechanisms. Therefore, understanding the behavior of semiconductor devices depends on evaluating the electron mobility characteristics of the semiconductor materials used in the semiconductor devices.

[0006] Unstable electron mobility can lead to inconsistent device performance and premature device failure. In applications where devices are exposed to a wide range of operating conditions, stable electron mobility ensures consistent device performance. Unstable electron mobility can cause device malfunction and performance degradation across its entire operating range, or within specific ranges, thereby reducing its dynamic range.

[0007] Amorphous metal oxide semiconductor materials have long been used in semiconductor devices such as thin-film transistors, but their widespread adoption has been hindered by challenges related to electron mobility stability. These challenges include balancing high electron mobility with the threshold voltage stability of the device within the channel of a TFT device.

[0008] [Overview of the project]

[0009] In one general embodiment, the semiconductor device may include a gate structure. The semiconductor device may also include a first electrode and a second electrode. The semiconductor device may further include a multilayer channel structure configured to be electrically coupled to the first electrode and the second electrode. The multilayer channel structure has a carrier-depleted layer and an electron injection layer disposed on the carrier-depleted layer.

[0010] Additional, optional, and / or alternative embodiments are described below. The semiconductor device may include a dielectric layer disposed between the gate structure and the multilayer channel structure. The dielectric layer may be formed from a ferroelectric material. The multilayer channel may include a plurality of carrier-depleted layers, including a carrier-depleted layer, and a plurality of electron-injection layers, including an electron-injection layer, where the plurality of carrier-depleted layers and the plurality of electron-injection layers are arranged alternately together, thereby forming an alternating multilayer channel structure.

[0011] The semiconductor device may include a ferroelectric layer disposed between a gate structure and an alternating multilayer channel structure. The semiconductor device may include an insulator. The multilayer channel structure may be disposed on the insulator. A first side insulator may be disposed on a first side of the multilayer channel structure. A second side insulator may be disposed on a second side of the multilayer channel structure. The first side insulator may be in contact with the insulator, and the second side insulator may be in contact with the insulator.

[0012] The gate structure may be placed on an insulator. The gate structure may have a trapezoidal cross-sectional shape. A dielectric layer may be placed on the gate structure and the insulator. A multilayer channel structure may be placed on the dielectric layer. The first electrode and the second electrode may be electrically connected to each other via the multilayer channel structure.

[0013] A multilayer channel structure may be placed on an insulator. A dielectric layer may be placed on the multilayer channel structure. A gate structure may be placed on the dielectric layer. The dielectric layer may be made of a ferroelectric material. A first electrode may be in electrical communication with the multilayer channel structure. A first electrode may be in physical contact with the multilayer channel structure. A first electrode may be in physical contact with the dielectric layer. A first electrode may be in physical contact with the insulator. The semiconductor device may include another insulator placed adjacent to the first electrode on the side opposite to the multilayer channel structure. The semiconductor device may include a metal, and the gate structure is placed on the metal. The semiconductor device may include a dielectric layer placed on the gate structure. A first electrode is placed on the multilayer channel structure and the dielectric layer, and a second electrode is placed on the multilayer channel structure and the dielectric layer.

[0014] The semiconductor device may include an intervening insulator disposed between a first electrode and a second electrode. The multilayer channel structure may be arranged on a dielectric layer. The semiconductor device may include a ferroelectric material disposed on a gate structure. The multilayer channel structure may be arranged on a ferroelectric material. The semiconductor device may include a first insulator disposed adjacent to the gate structure on a first side surface and a second insulator disposed adjacent to the gate structure on a second side surface. The first electrode may be a source structure. The second electrode may be a drain structure.

[0015] The carrier-depleted layer may be an indium(III) oxide layer doped with a dopant having a high bond dissociation energy. The dopant to be added may be selected from the group consisting of tungsten(VI) oxide, silicon dioxide, and antimony tetroxide. The electron-injection layer may be pure indium(III) oxide. The electron-injection layer may be indium(III) oxide annealed in air. The electron-injection layer may be indium(III) oxide annealed with a dopant having a low bond dissociation energy.

[0016] The dopant to be added may be titanium dioxide. The device is a thin-film transistor. The device may be located on the back-end obline portion of an integrated circuit. The device may be located on the front-end obline portion of an integrated circuit. The multilayer channel structure may have a thickness of less than 10 nanometers. The carrier depletion layer may have a first thickness, and the electron injection layer may have a second thickness, and the ratio between the first and second thicknesses is predetermined.

[0017] In further embodiments, the integrated circuit system may include at least one integrated circuit having a plurality of devices as described herein.

[0018] Another aspect of the present disclosure describes a method for fabricating an integrated circuit, the method comprising: forming a gate structure; forming a first electrode; forming a second electrode; forming a multilayer channel structure disposed between the first electrode and the second electrode; forming a carrier-depleted layer of the multilayer channel structure; and forming an electron injection layer disposed in contact with the carrier-depleted layer.

[0019] The carrier-deficient layer may be an indium(III) oxide layer, and the method further comprises adding a dopant having a high bond dissociation energy to the indium(III) oxide layer. The dopant may be selected from the group consisting of tungsten(VI) oxide, silicon dioxide, and antimony tetroxide. The electron injection layer may be pure indium(III) oxide. The electron injection layer is indium(III) oxide. The method further comprises annealing the electron injection layer in air.

[0020] The electron injection layer may be indium(III) oxide, and the method may further include annealing the electron injection layer to which a dopant having a low bond dissociation energy is added. The added dopant may be titanium dioxide. The method may form a thin-film transistor. A dielectric layer may be placed between the gate structure and the multilayer channel structure.

[0021] The method may include forming a dielectric layer from a ferroelectric material. Each formation operation may be performed on the back-end obline portion of an integrated circuit. The method may form a multilayer channel structure with a thickness of less than 10 nanometers. The carrier-depleted layer may have a first thickness, and the electron injection layer may have a second thickness. The method may further include forming a predetermined ratio between the first and second thicknesses.

[0022] The method may include forming a plurality of carrier-deficient layers including carrier-deficient layers, forming a plurality of electron injection layers including electron injection layers, and alternately arranging the plurality of carrier-deficient layers and the plurality of electron injection layers to thereby form an alternately arranged multilayer channel structure. The ferroelectric layer may be arranged between the gate structure and the alternately arranged multilayer channel structure.

[0023] The method may further include forming an insulator, forming a gate structure on the insulator, forming a trapezoidal cross-sectional shape of the gate structure, forming a dielectric layer on the gate structure and the insulator, forming a multilayer channel structure on the dielectric layer, and / or electrically connecting between a first electrode and a second electrode through the multilayer channel structure. The multilayer channel structure may be arranged on the insulator.

[0024] The method may include one or more operations of forming a dielectric layer on an insulator, forming a gate structure on the insulator, forming the dielectric layer from a ferroelectric material, and / or electrically connecting a first electrode to the multilayer channel structure.

[0025] The first electrode may physically contact the multilayer channel structure. The first electrode may physically contact the dielectric layer.

[0026]

Brief Description of the Drawings

[0027] These aspects and other aspects will become more apparent from the following detailed description of various embodiments of the present disclosure made with reference to the drawings.

[0028] [Figure 1] FIG. is a cross-sectional view of a thin film transistor having a channel with a carrier-deficient layer and an electron injection layer according to an embodiment of the present invention.

[0029] [Figure 2]This is a cross-sectional view of a thin-film transistor having a channel with a carrier-depleted layer and an electron injection layer, according to one embodiment of the present disclosure.

[0030] [Figure 3] This is a cross-sectional view of a ferroelectric field-effect transistor having a channel with a carrier-depleted layer and an electron injection layer, according to one embodiment of the present disclosure.

[0031] [Figure 4] This is a cross-sectional view of a ferroelectric field-effect transistor having a channel with a carrier-depleted layer and an electron injection layer, according to one embodiment of the present disclosure.

[0032] [Figure 5] This is a cross-sectional view of a thin-film transistor disposed on a metal having a channel with a carrier-depleted layer and an electron injection layer, according to one embodiment of the present disclosure.

[0033] [Figure 6] This is a cross-sectional view of a thin-film transistor disposed on an insulator having a channel with a carrier-depleted layer and an electron injection layer, according to one embodiment of the present disclosure.

[0034] [Figure 7] This is a cross-sectional view of a ferroelectric field-effect transistor disposed on a metal having a channel with a carrier-depleted layer and an electron injection layer, according to one embodiment of the present disclosure.

[0035] [Figure 8] This is a cross-sectional view of a ferroelectric field-effect transistor disposed on an insulator having a channel with a carrier-depleted layer and an electron injection layer, according to one embodiment of the present disclosure.

[0036] [Figure 9] This is a cross-sectional view of a thin-film transistor having a channel with alternatingly arranged carrier-deficient layers and electron injection layers, according to one embodiment of the present disclosure.

[0037] [Figure 10] This is a cross-sectional view of a ferroelectric field-effect transistor having a channel with alternatingly arranged carrier-depleted layers and electron injection layers, according to one embodiment of the present disclosure.

[0038] [Figure 11] This is a cross-sectional view of a thin-film transistor having a channel with alternatingly arranged carrier-deficient layers and electron injection layers, according to one embodiment of the present disclosure.

[0039] [Figure 12] This is a cross-sectional view of a ferroelectric field-effect transistor having a channel with alternatingly arranged carrier-depleted layers and electron injection layers, according to one embodiment of the present disclosure.

[0040] [Figure 13] This graph shows predictive results that can be expected from having a channel layer made of various types of materials according to one embodiment of the present disclosure.

[0041] [Figure 14] This is a flowchart illustrating a method for forming a semiconductor device such as a transistor according to one embodiment of the present disclosure. [Modes for carrying out the invention]

[0042] Figure 1 shows a cross-sectional view of a thin-film transistor 100 having a channel with a carrier depletion layer 104 and an electron injection layer 106, according to one embodiment of the present disclosure. The gate 114 in the transistor 100 may be constructed first within the transistor 100, thereby creating what is commonly known to those skilled in the art as a back-gate transistor or gate-first FET. In some specific embodiments, the transistor 100 may have a trapezoidal cross-sectional shape with respect to the gate 114, as shown in Figure 1 (however, other shapes, designs, and configurations may be used, which are known to those skilled in the art). In some specific embodiments, the transistor 100 may be a thin-film transistor and may be located on the BEOL ("back-end of line") or FEOL ("front-end of line").

[0043] The transistor 100 includes an insulator 112 on which a gate structure 114, which is a type of electrode, is disposed. The transistor 100 also includes a dielectric layer 110 disposed on the gate structure 114 and the insulator 112. The dielectric layer 110 prevents substantial DC current between the gate structure 114 and the source structure 102 and / or between the gate structure 114 and the drain structure 108. The drain structure or source structure disclosed herein may be formed from materials including, but not limited to, Pd, Mo, Al / Ti, W, Cu, TiN, Pt, or several combinations thereof. The gate structure disclosed herein may be formed from materials including, but not limited to, W, Cu, Al, TiN, or several combinations thereof. Between the dielectric and the source structure 102 and the drain structure 108, a channel structure is disposed which includes a carrier depletion layer 104 and an electron injection layer 106. The total thickness of the channel structure, including the carrier-depleted layer 104 and the electron injection layer 106, may be less than 10 nanometers in some specific embodiments. In further embodiments, the thickness ratio of the carrier-depleted layer 104 to the electron injection layer 106 may be a parameter determined during design and manufacturing, which is adjusted to achieve the target operating characteristics.

[0044] The carrier-deficient layer 104 may be an indium(III) oxide layer doped with a dopant having a high bond dissociation energy. The dopant to be added may be selected from the group consisting of tungsten(VI) oxide, silicon dioxide, and antimony tetroxide. The electron injection layer 106 may be pure indium(III) oxide, an indium oxide layer doped with a dopant having a very low oxygen bond dissociation energy, etc. The electron injection layer 106 may be annealed in air and a dopant having a low bond dissociation energy may be added. The dopant to be added may be titanium dioxide.

[0045] In2O3-based oxides provide high electron mobility within the channel, thereby promoting high drive current. Adding dopants with high bond dissociation energy to the system can improve the electrical stability of the channel, as well as its process margin window with respect to annealing time and oxygen flow during channel deposition. Therefore, due to the trade-off with high electron mobility, channel materials with two layers, along with one layer having high carrier injection capability, improve current driving within the device. While the total channel thickness may remain below 10 nm, optimal properties can be achieved by adjusting the thickness ratio of the different layers within the channel.

[0046] Figure 2 shows a cross-sectional view of a thin-film transistor 200 having a channel with a carrier depletion layer 208 and an electron injection layer 204, according to one embodiment of the present disclosure. The transistor 200 has a gate structure 210 located on top of the transistor 200 as the final step of the manufacturing process, thereby forming a top-gate FET device architecture. In certain embodiments, the transistor 200 may be a thin-film transistor and may be located on a BEOL or FEOL.

[0047] The transistor includes an insulator 202 and an electron injection layer 204 disposed thereon. The source structure 206 and drain structure 214 are also partially disposed on the insulator 202. A carrier depletion layer 208 is disposed on the electron injection layer 204. The carrier depletion layer 208 and the electron injection layer 204 form the channel of the transistor 200. The dielectric 212 is disposed on the carrier depletion layer 208 and is partially disposed on the source structure 206 and drain structure 214.

[0048] The total thickness of the channel structure, including the carrier-depleted layer 208 and the electron injection layer 204, may be less than 10 nanometers in some specific embodiments. In further embodiments, the thickness ratio of the carrier-depleted layer 208 to the electron injection layer 204 may be a parameter determined during design and manufacturing, which is adjusted to achieve the target operating characteristics.

[0049] The carrier depletion layer 208 may be an indium(III) oxide layer doped with a dopant having a high bond dissociation energy. The dopant to be added may be selected from the group consisting of tungsten(VI) oxide, silicon dioxide, and antimony tetroxide. The electron injection layer 204 may be pure indium(III) oxide or an indium oxide layer doped with a dopant having a very low oxygen bond dissociation energy. The electron injection layer 204 may be annealed in air and dopants having low bond dissociation energy may be added. The dopant to be added may be titanium dioxide. The Vgs voltage is higher than the Vth voltage, while Vds is higher than zero, which is similar to most MOS transistors.

[0050] Figure 3 shows a cross-sectional view of a ferroelectric field-effect transistor 300 having a channel with a carrier-deficient layer 308 and an electron injection layer 306, according to one embodiment of the present disclosure. Transistor 300 may be similar to transistor 100 in Figure 1, but transistor 300 includes a ferroelectric layer 310. The ferroelectric layer described herein may be made from one or more materials including, but not limited to, lead zirconate titanate (PZT), hafnium zirconium oxide (HZO), barium titanate (BaTiO3), lead titanate (PbTiO3), and doped hafnium dioxide (HfO2). Doped HfO2 may include one or more silicon-doped HfO2, yttrium-doped HfO2, and aluminum-doped HfO2. The properties of the ferroelectric layer 310 may be altered by the application of current to give transistor 300 a kind of memory. In some specific embodiments, the transistor 300 may have a trapezoidal cross-sectional shape relative to the gate structure 312, as shown in Figure 3. In certain embodiments, the transistor 300 may be a thin-film transistor and may be located on the BEOL or FEOL.

[0051] The transistor 300 includes an insulator 314 having a gate structure 312 having a trapezoidal cross-sectional shape. In a particular embodiment shown in Figure 3, the gate structure 312 is located on the insulator 314. The ferroelectric layer 310 of the transistor 300 is located on the gate structure 312 and the insulator 314. The ferroelectric layer 310 prevents substantial DC current between the gate structure 312 and the source structure 302, and / or between the gate structure 312 and the drain structure 304. The ferroelectric layer 310 can maintain the field polarization that affects the behavior of the transistor 300 and can be used to store state or memory within the transistor 300.

[0052] A channel structure comprising a carrier-depleted layer 308 and an electron injection layer 306 is arranged between the ferroelectric layer 310 and the source structure 302 and drain structure 304. In some specific embodiments, the total thickness of the channel structure comprising the carrier-depleted layer 308 and the electron injection layer 306 may be less than 10 nanometers. In further embodiments, the thickness ratio of the carrier-depleted layer 308 to the electron injection layer 306 may be a parameter determined during design and manufacturing, which is adjusted to achieve the target operating characteristics.

[0053] The carrier-deficient layer 308 may be an indium(III) oxide layer doped with a dopant having a high bond dissociation energy. The dopant to be added may be selected from the group consisting of tungsten(VI) oxide, silicon dioxide, and antimony tetroxide. The electron injection layer 306 may be pure indium(III) oxide, an indium oxide layer doped with a dopant having a very low oxygen bond dissociation energy, etc. The electron injection layer 306 may be annealed in air and a dopant having a low bond dissociation energy may be added. The dopant to be added may be titanium dioxide.

[0054] Figure 4 shows a cross-sectional view of a ferroelectric field-effect transistor 400 having a channel with a carrier-depletion layer 408 and an electron injection layer 402, according to one embodiment of the present disclosure. In certain embodiments, the transistor 400 may be a thin-film transistor and may be located on a BEOL or FEOL. The transistor 400 has a channel with a carrier-depletion layer 408 and an electron injection layer 402. The transistor 400 also has a gate structure 412 located on the side opposite to the insulator 404.

[0055] The transistor 400 includes an insulator 404 and an electron injection layer 402 disposed thereon. The source structure 406 and drain structure 414 are also partially disposed on the insulator 404. A carrier depletion layer 408 is disposed on the electron injection layer 402. The carrier depletion layer 408 and the electron injection layer 402 form the channel of the transistor 400. The ferroelectric material 410 is disposed on the carrier depletion layer 408 and is partially disposed on the source structure 406 and drain structure 414.

[0056] The total thickness of the channel structure, including the carrier depletion layer 408 and the electron injection layer 402, may be less than 10 nanometers in some specific embodiments. In further embodiments, the thickness ratio of the carrier depletion layer 408 to the electron injection layer 402 may be a parameter determined during design and manufacturing, which is adjusted to achieve the target operating characteristics.

[0057] The carrier-deficient layer 408 may be an indium(III) oxide layer doped with a dopant having a high bond dissociation energy. The dopant to be added may be selected from the group consisting of tungsten(VI) oxide, silicon dioxide, and antimony tetroxide. The electron injection layer 402 may be pure indium(III) oxide. The electron injection layer 402 may be annealed in air or in any other gaseous environment such as N2 or O2 or a combination thereof, and a dopant having a low bond dissociation energy may be added. The dopant to be added may be titanium dioxide.

[0058] To program the ferroelectric layer 410, Vgs is set higher than Vth, Vds is set higher than 0, and Vds = 0 volts. The erase operation is performed when Vgs is less than 0 and Vds = 0 volts. The read operation can occur when Vds = Vread and Vds = 50 mV.

[0059] Figure 5 shows a cross-sectional view of a thin-film transistor 500 disposed on a metal 506 having a channel with a carrier-depleted layer 508 and an electron injection layer 522, according to one embodiment of the present disclosure. The metals disclosed herein may be any pure metal, any semi-pure metal, any combination of metals, any alloy, any elemental metal, any combination of elemental metals, materials known to those skilled in the art as metals, or some combination thereof. A gate structure 510 is disposed on the metal 506 and has insulators 504, 512 surrounding the gate structure 510. A dielectric 514 is disposed on the gate structure 510. A carrier-depleted layer 508 is disposed on the dielectric 514. A source structure 524 and a drain structure 518 are in contact with the channel formed by the carrier-depleted layer 508 and the electron injection layer 522. An insulator 520 is disposed between the source structure 524 and the drain structure 518. Furthermore, the insulator 502 and the other insulator 516 may be optionally positioned adjacent to the source structure 524 and the drain structure 518, respectively. In some specific embodiments, the transistor 500 may be a BEOL or FEOL transistor.

[0060] Figure 6 shows a cross-sectional view of a thin-film transistor 600 disposed on an insulator 602 having a channel with a carrier-deficient layer 614 and an electron injection layer 618, according to one embodiment of the present disclosure. The transistor 600 may be a FEOL transistor or a BEOL transistor. In some embodiments, the transistor 600 may also be a thin-film transistor.

[0061] The transistor 600 includes an electron injection layer 618 disposed on an insulator 602 and a carrier depletion layer 614 disposed on the electron injection layer 618, thereby forming a channel. Insulators 604 and 616 are located on the opposite ends of layers 614 and 618. The source structure 606 is partially located on the carrier depletion layer 614, and so is the drain structure 614, with a dielectric 608 located between them. The gate structure 610 is located on the dielectric 608. In some specific embodiments, the transistor 600 may be a BEOL or FEOL transistor.

[0062] Figure 7 shows a cross-sectional view of a ferroelectric field-effect transistor 700 disposed on a metal 706 having a channel with a carrier-depleted layer 708 and an electron injection layer 722, according to one embodiment of the present disclosure. The gate structure 710 is disposed on the metal 706 and has insulators 704, 712 surrounding the gate structure 710. The ferroelectric material 714 is disposed on the gate structure 710. The carrier-depleted layer 708 is disposed on the ferroelectric material 714. The source structure 724 and drain structure 718 are in contact with the channel formed by the carrier-depleted layer 708 and the electron injection layer 722. An insulator 720 is disposed between the source structure 724 and the drain structure 718. In addition, an insulator 702 and another insulator 716 may be optionally disposed adjacent to the source structure 724 and the drain structure 718, respectively. In some specific embodiments, the transistor 700 may be a BEOL or FEOL transistor.

[0063] Figure 8 shows a cross-sectional view of a ferroelectric field-effect transistor 800 disposed on an insulator 802 having a channel with a carrier-depleted layer 814 and an electron injection layer 818, according to one embodiment of the present disclosure. The transistor 800 may be a FEOL transistor or a BEOL transistor. In some embodiments, the transistor 800 may also be a thin-film transistor.

[0064] The transistor 800 includes an electron injection layer 818 disposed on an insulator 802 and a carrier depletion layer 814 disposed on the electron injection layer 818, thereby forming a channel. Insulators 804 and 816 are located on the opposite ends of layers 814 and 818. A source structure 806 is partially located on the carrier depletion layer 814, and a ferroelectric material 808 is placed between them, as is the drain structure 814. A gate structure 810 is located on the dielectric 808. In some specific embodiments, the transistor 800 may be a BEOL or FEOL transistor.

[0065] Figure 9 shows a cross-sectional view of a thin-film transistor 900 having a channel with alternating carrier depletion layers 908, 912, 918 and electron injection layers 910, 914, 920, according to one embodiment of the present disclosure. In some specific embodiments, the transistor 900 may be a BEOL or FEOL transistor. The transistor 900 in Figure 9 may be similar to the transistor 200 in Figure 2, but the transistor 900 has an alternating channel in which alternating carrier depletion layers 908, 912, 918 and electron injection layers 910, 914, 920 are present.

[0066] The transistor 900 includes an insulator 922 on which a source structure 902 and a drain structure 916 are partially disposed. An alternating channel, which has alternating carrier depletion layers 908, 912, 918 and electron injection layers 910, 914, 920, is located on the insulator 922 and between the source structure 902 and the drain structure 916. A dielectric 906 is then partially disposed on the channel structure, the source structure 902, and the drain structure 916. The gate structure 904 is located on the dielectric layer 906. In some specific embodiments, the transistor 900 may be a BEOL or FEOL transistor. In further additional embodiments, the insulator 922 may be a metal to which sufficient or optional insulating layers are added, as is known to those skilled in the art.

[0067] Figure 10 shows a cross-sectional view of a ferroelectric field-effect transistor 1000 having a channel comprising alternating carrier-depletion layers 1016, 1012, 1006 and electron injection layers 1014, 1010, 1004, according to one embodiment of the present disclosure. In some specific embodiments, the transistor 1000 may be a BEOL or FEOL transistor. The transistor 1000 includes an insulator 1002 on which a source structure 1008 and a drain structure 1020 are disposed. The channel is located between the source structure 1008 and the drain structure 1020 and includes alternating carrier-depletion layers 1016, 1012, 1006 with electron injection layers 1014, 1010, 1004. A ferroelectric layer 1021 is located on top of the channel structure, the source structure 1008, and the drain structure 1020. A gate structure 1018 is located on the ferroelectric layer 1021. In some specific embodiments, the transistor 1000 may be a BEOL or FEOL transistor. In further embodiments, the insulator 1002 may be a metal to which sufficient or optional insulating layers have been added, as is known to those skilled in the art.

[0068] Figure 11 shows a cross-sectional view of a thin-film transistor 1100 having a channel with alternatingly arranged carrier-deficient layers 1110, 1116, 1122 and electron injection layers 1114, 1120, 1124, according to one embodiment of the present disclosure. Transistor 1100 may be a BEOL or FEOL transistor in some specific embodiments. Transistor 1100 in Figure 11 may be similar to transistor 900 in Figure 9, but transistor 1100 has insulating layers 1102, 1118.

[0069] The transistor 1100 includes an insulator 1126 and insulators 1102 and 1118, with a source structure 1104 and a drain structure 1112 partially located on them, respectively. An alternating channel, with alternating carrier depletion layers 1110, 1116, and 1122 and electron injection layers 1114, 1120, and 1124, is located on the insulator 1126 and between the source structure 1104 / insulator 1102 and the drain structure 1112 / insulator 1118. A dielectric 1108 is then partially located on the channel structure, source structure 1104, and drain structure 1112. The gate structure 1106 is located on the dielectric layer 1108. In some specific embodiments, the transistor 1100 may be a BEOL or FEOL transistor. In further additional embodiments, the insulator 1126 may be a metal to which sufficient or optional insulating layers have been added, as is known to those skilled in the art.

[0070] Figure 12 shows a cross-sectional view of a ferroelectric field-effect transistor 1200 having a channel with alternating carrier-depletion layers 1212, 1208, 1204 and electron injection layers 1210, 1206, 1202, according to one embodiment of the present disclosure. In some specific embodiments, the transistor 1200 may be a BEOL or FEOL transistor. The transistor 1200 includes an insulator 1226 on which a source structure 1216 and a drain structure 1222 are disposed. The channel is located between the source structure 1216 / insulator 1214 and the drain structure 1222 / insulator 1224 and includes alternating carrier-depletion layers 1212, 1208, 1204 with electron injection layers 1210, 1206, 1202. A ferroelectric layer 1220 is located on top of the channel structure, the source structure 1216, and the drain structure 1222. The gate structure 1218 is located on the ferroelectric layer 1220. The transistor 1200 may be a BEOL or FEOL transistor in some specific embodiments. In further embodiments, the insulator 1226 may be a metal to which sufficient or optional insulating layers have been added, as is known to those skilled in the art.

[0071] Figure 13 shows graph 1300 illustrating predictive results expected from having channel layers with various types of materials according to one embodiment of the present disclosure. Graph 1300 shows Vgs versus carrier mobility for different material configurations as described herein. Plot 1306 shows a plot where the channel is fabricated with carrier-deficient channel material only. Plot 1302 shows a predictive plot from a device having multilayer channel material, e.g., alternating materials as described above, while plot 1304 shows a predictive result from a device having carrier-injection channel material only. As can be seen, different layers may be used to control the characteristics of the transistor.

[0072] Figure 14 is a flowchart of an exemplary method 1400 for forming a device. Method 1400 may include forming a gate structure (block 1402). Method 1400 may also include forming a first electrode (block 1404) and forming a second electrode (block 1406). Method 1400 may include operation 1408 for forming a multilayer channel structure positioned between the first and second electrodes. Method 1400 may include operation 1410 for forming a carrier-depleted layer of the multilayer channel structure and operation 1412 for forming an electron injection layer positioned in contact with the carrier-depleted layer (block 1408). Method 1400 may include operation 1414 for forming a ferroelectric layer positioned between the gate structure and the multilayer channel structure.

[0073] Figure 14 shows an exemplary block of method 1400, and in some implementations, method 1400 may include additional blocks, fewer blocks, different blocks, or blocks arranged differently from those shown in Figure 14. Additionally or alternatively, two or more blocks of process 1400 may be executed in parallel.

[0074] A person skilled in the art can devise various alternative and modified forms without departing from this disclosure. Therefore, this disclosure is intended to encompass all such alternative, modified, and variant forms. In addition, while some embodiments of this disclosure have been shown in the drawings and / or discussed herein, this disclosure is intended to be as broad as the art allows, and this specification is intended to be interpreted similarly; therefore, this disclosure is not intended to be limited to these embodiments. Accordingly, the above description should not be construed as limiting, but merely as an example of a particular embodiment. A person skilled in the art will also anticipate other modifications within the scope and spirit of the claims appended herein. Other elements, steps, methods, and techniques substantially different from those described above and / or in the appended claims are also intended to be within the scope of this disclosure.

[0075] For example, the channels described herein may include n-type layers such as ITO, IGZO, IZO, AZO, a-Si, ZnO, a-Ge, polysilicon or poly-III-V such as polySi, polyGe, or InAs, and / or additional layers such as p-type layers such as a-Si, ZnO, a-Ge, polysilicon, polygermanium, poly-III-V such as InAs, CuO, or SnO. The channel length may include, but is not limited to, 5 nm to 100 nm, and may be any suitable length known to those skilled in the art. The layers may be formed using atomic layer deposition and may include, but is not limited to, 2 nm to 10 nm, and may be any suitable thickness known to those skilled in the art. In some embodiments, there may be an odd number of carrier-deficient layers (e.g., 1, 3, 5, 7, 9, etc.) and an even number of electron-injection layers (2, 4, 6, 8, 10, etc.). In yet another embodiment, there are even-numbered carrier-deficient layers (2, 4, 6, 8, 10, etc.) and odd-numbered electron-injection layers (e.g., 1, 3, 5, 7, 9, etc.). In yet another embodiment, there are even-numbered carrier-deficient layers (2, 4, 6, 8, 10, etc.) and even-numbered electron-injection layers (2, 4, 6, 8, 10, etc.).

[0076] The embodiments shown in the drawings are presented solely to illustrate specific examples of the present disclosure. Furthermore, the drawings are illustrative and not limiting. For illustrative purposes, the sizes of some elements in the drawings may be exaggerated and may not be drawn to a specific scale. Additionally, elements with the same number shown in the drawings may be identical or similar elements, depending on the context.

[0077] Where the term “including” is used in this specification and in the claims, it does not preclude other elements or steps. Where an indefinite or definite article, e.g., “a,” “an,” or “the,” is used when referring to a singular noun, it includes the plural form of that noun unless otherwise specified. Therefore, the term “including” should not be interpreted as being limited to the items listed thereafter, and it does not preclude other elements or steps, so the expression “device including items A and B” should not be limited to a device consisting only of components A and B. This expression means that, with respect to this disclosure, the relevant components of a device are only A and B.

[0078] Furthermore, terms such as “first,” “second,” and “third,” whether used in the specification or claims, are provided to distinguish similar elements and are not necessarily provided to describe a sequential or chronological order. Terms used in this manner are (unless otherwise expressly disclosed) interchangeable under appropriate circumstances, and it should be understood that embodiments of the disclosures described herein may operate in an order and / or arrangement other than those described or illustrated herein.

[0079] Each of the features and embodiments described herein, as well as any combination thereof, may be referred to as being encompassed by this disclosure. Numerous variations and configurations will become apparent in light of this disclosure and the following embodiments.

[0080] Example 1: A semiconductor device comprising a gate structure, a first electrode, a second electrode, and a multilayer channel structure electrically connected to the first electrode and the second electrode, wherein the multilayer channel structure comprises a carrier-depleted layer and an electron injection layer disposed on the carrier-depleted layer.

[0081] Example 2: The device according to Example 1, further comprising a dielectric layer disposed between the gate structure and the multilayer channel structure.

[0082] Example 3: The device according to Example 2, wherein the dielectric layer is formed from a ferroelectric material.

[0083] Example 4: The device according to Example 1, wherein the multilayer channel structure includes a plurality of carrier-deficient layers including a carrier-deficient layer and a plurality of electron injection layers including an electron injection layer, and the plurality of carrier-deficient layers and the plurality of electron injection layers are arranged alternately together, thereby forming an alternating arrangement multilayer channel structure.

[0084] Example 5: The device according to Example 4, further comprising a ferroelectric layer disposed between the gate structure and the alternating multilayer channel structure.

[0085] Example 6: The device according to Example 1, further comprising an insulator.

[0086] Example 7: The device according to Example 6, wherein a multilayer channel structure is arranged on an insulator, a first side insulator is arranged on the first side surface of the multilayer channel structure, and a second side insulator is arranged on the second side surface of the multilayer channel structure.

[0087] Example 8: The device according to Example 7, wherein the first side insulator is in contact with the insulator, and the second side insulator is in contact with the insulator.

[0088] Example 9: The device according to Example 6, wherein the gate structure is located on an insulator.

[0089] Example 10: The device according to Example 9, wherein the gate structure forms a trapezoidal cross-sectional shape.

[0090] Example 11: The device according to Example 9, wherein the dielectric layer is arranged on the gate structure and the insulator.

[0091] Example 12: The device according to Example 11, wherein the multilayer channel structure is arranged on a dielectric layer.

[0092] Example 13: The device according to Example 12, wherein the first electrode and the second electrode are electrically connected to each other via a multilayer channel structure.

[0093] Example 14: The device according to Example 6, wherein the multilayer channel structure is arranged on an insulator.

[0094] Example 15: The device according to Example 14, wherein the dielectric layer is arranged on a multilayer channel structure.

[0095] Example 16: The device according to Example 15, wherein the gate structure is located on a dielectric layer.

[0096] Example 17: The device according to Example 15, wherein the dielectric layer is made of a ferroelectric material.

[0097] Example 18: The device according to Example 15, wherein the first electrode is electrically connected to a multilayer channel structure.

[0098] Example 19: The device according to Example 15, wherein the first electrode is in physical contact with a multilayer channel structure.

[0099] Example 20: The device according to Example 19, wherein the first electrode is in physical contact with the dielectric layer.

[0100] Example 21: The device according to Example 19 or 20, wherein the first electrode is in physical contact with an insulator.

[0101] Example 22: The device according to Example 19 or 20, further comprising another insulator positioned adjacent to the first electrode on the side opposite to the multilayer channel structure.

[0102] Example 23: The device according to any one of Examples 1 to 5, further comprising a metal, wherein the gate structure is disposed on the metal.

[0103] Example 24: The device according to Example 23, further comprising a dielectric layer disposed on the gate structure.

[0104] Example 25: The device according to Example 24, wherein the first electrode is arranged on a multilayer channel structure and a dielectric layer, and the second electrode is arranged on a multilayer channel structure and a dielectric layer.

[0105] Example 26: The device according to Example 25, further comprising an intervening insulator disposed between the first electrode and the second electrode.

[0106] Example 27: The device according to Example 24, wherein the multilayer channel structure is arranged on a dielectric layer.

[0107] Example 28: The device according to Example 23, further comprising a ferroelectric material disposed on a gate structure.

[0108] Example 29: The device according to Example 28, wherein the multilayer channel structure is arranged on a ferroelectric material.

[0109] Example 30: The device according to any one of Examples 1 to 29, further comprising a first insulator disposed adjacent to the gate structure on a first side surface and a second insulator disposed adjacent to the gate structure on a second side surface.

[0110] Example 31: The device according to any one of Examples 1 to 30, wherein the first electrode is a source structure.

[0111] Example 32: The device according to any one of Examples 1 to 31, wherein the second electrode is a drain structure.

[0112] Example 33: The device according to any one of Examples 1 to 32, wherein the carrier-deficient layer is an indium(III) oxide layer doped with a dopant having a high bond dissociation energy.

[0113] Example 34: The device according to Example 33, wherein the added dopant is selected from the group consisting of tungsten(VI) oxide, silicon dioxide, and antimony tetroxide.

[0114] Example 35: The device according to any one of Examples 1 to 34, wherein the electron injection layer is pure indium(III) oxide.

[0115] Example 36: The device according to any one of Examples 1 to 35, wherein the electron injection layer is indium(III) oxide annealed in air.

[0116] Example 37: The device according to any one of Examples 1 to 36, wherein the electron injection layer is indium(III) oxide annealed with a dopant having a low bond dissociation energy.

[0117] Example 38: The device according to Example 37, wherein the added dopant is titanium dioxide.

[0118] Example 39: The device according to any one of Examples 1 to 38, wherein the device is a thin-film transistor.

[0119] Example 40: The device according to any one of Examples 1 to 39, wherein the device is located on the back-end obline portion of an integrated circuit.

[0120] Example 41: The device according to any one of Examples 1 to 39, wherein the device is located on the front end of the integrated circuit.

[0121] Example 42: The device according to any one of Examples 1 to 41, wherein the multilayer channel structure has a thickness of less than 10 nanometers.

[0122] Example 43: The device according to any one of Examples 1 to 42, wherein the carrier depletion layer has a first thickness, the electron injection layer has a second thickness, and the ratio between the first thickness and the second thickness is predetermined.

[0123] Example 44: An integrated circuit system comprising at least one integrated circuit having a plurality of devices, wherein at least one of the plurality of devices is a device according to any of Examples 1 to 43.

[0124] Example 45: The device according to any one of Examples 2, 11-12, 15-16, 20, 24-25, or 27, wherein the dielectric layer is a ferroelectric layer.

[0125] Example 46: A method for fabricating an integrated circuit, comprising: forming a gate structure; forming a first electrode; forming a second electrode; forming a multilayer channel structure disposed between the first electrode and the second electrode; forming a carrier-depleted layer of the multilayer channel structure; and forming an electron injection layer disposed in contact with the carrier-depleted layer.

[0126] Example 47: The method according to Example 46, wherein the carrier-deficient layer is an indium(III) oxide layer, and the method further comprises adding a dopant having a high bond dissociation energy to the indium(III) oxide layer.

[0127] Example 48: The method according to Example 47, wherein the dopant is selected from the group consisting of tungsten(VI) oxide, silicon dioxide, and antimony tetroxide.

[0128] Example 49: The method according to Example 46, wherein the electron injection layer is pure indium(III) oxide.

[0129] Example 50: The method according to Example 46, wherein the electron injection layer is indium(III) oxide, and the method further comprises annealing the electron injection layer in air.

[0130] Example 51: The method according to Example 46, wherein the electron injection layer is indium(III) oxide, and the method further comprises annealing the electron injection layer to which a dopant having a low bond dissociation energy is added.

[0131] Example 52: The method according to Example 51, wherein the added dopant is titanium dioxide.

[0132] Example 53: The method according to Example 46, wherein the method is to form a thin-film transistor.

[0133] Example 54: The method according to Example 46, further comprising forming a dielectric layer disposed between the gate structure and the multilayer channel structure.

[0134] Example 55: The method according to Example 54, further comprising forming a dielectric layer from a ferroelectric material.

[0135] Example 56: The method according to Example 46, wherein each forming operation is performed on the back-end obline portion of the integrated circuit.

[0136] Example 57: The method according to Example 46, further comprising forming a multilayer channel structure with a thickness of less than 10 nanometers.

[0137] Example 58: The method according to Example 46, wherein the carrier depletion layer has a first thickness and the electron injection layer has a second thickness, and the method further comprises predetermining the ratio between the first thickness and the second thickness.

[0138] Example 59: The method according to Example 46, further comprising forming a plurality of carrier-deficient layers including a carrier-deficient layer, forming a plurality of electron injection layers including an electron injection layer, and arranging the plurality of carrier-deficient layers and the plurality of electron injection layers alternately to form an alternating multilayer channel structure.

[0139] Example 60: The method according to Example 59, wherein a ferroelectric layer is formed between the gate structure and the alternating multilayer channel structure.

[0140] Example 61: The method according to Example 46, further comprising forming an insulator.

[0141] Example 62: The method according to Example 61, further comprising forming a gate structure on an insulator.

[0142] Example 63: The method according to Example 62, further comprising forming a trapezoidal cross-sectional shape of the gate structure.

[0143] Example 64: The method according to Example 62, further comprising forming a dielectric layer on a gate structure and an insulator.

[0144] Example 65: The method according to Example 64, further comprising forming a multilayer channel structure on a dielectric layer.

[0145] Example 66: The method according to Example 65, further comprising electrically connecting a first electrode and a second electrode via a multilayer channel structure.

[0146] Example 67: The method according to Example 61, further comprising forming a multilayer channel structure on an insulator.

[0147] Example 68: The method according to Example 67, further comprising forming a dielectric layer on an insulator.

[0148] Example 69: The method according to Example 68, further comprising forming a gate structure on an insulator.

[0149] Example 70: The method according to Example 68, further comprising forming a dielectric layer from a ferroelectric material.

[0150] Example 71: The method according to Example 68, further comprising electrically communicating the first electrode with a multilayer channel structure.

[0151] Example 72: The method according to Example 68, wherein the first electrode is in physical contact with the multilayer channel structure.

[0152] Example 73: The method according to Example 68, wherein the first electrode is in physical contact with the dielectric layer.

Claims

1. Gate structure and The first electrode and The second electrode and A multilayer channel structure electrically coupled to the first electrode and the second electrode, A semiconductor device comprising, wherein the multilayer channel structure is Career-deprived group, An electron injection layer disposed on the carrier-deficient layer, Equipped with, Semiconductor devices.

2. The device according to claim 1, further comprising a dielectric layer disposed between the gate structure and the multilayer channel structure.

3. The device according to claim 2, wherein the dielectric layer is formed from a ferroelectric material.

4. The aforementioned multilayer channel structure, Multiple carrier-deficient layers, including the aforementioned carrier-deficient layer, A plurality of electron injection layers including the aforementioned electron injection layer, The plurality of carrier-deficient layers and the plurality of electron injection layers are arranged alternately, thereby forming an alternating multilayer channel structure. The device according to claim 1.

5. The device according to claim 4, further comprising a ferroelectric layer disposed between the gate structure and the alternating multilayer channel structure.

6. The device according to claim 1, further comprising an insulator.

7. The device according to claim 6, wherein the multilayer channel structure is disposed on the insulator, the first side insulator is disposed on the first side surface of the multilayer channel structure, and the second side insulator is disposed on the second side surface of the multilayer channel structure.

8. The device according to claim 7, wherein the first side insulator is in contact with the insulator, and the second side insulator is in contact with the insulator.

9. The device according to claim 6, wherein the gate structure is arranged on the insulator.

10. The device according to claim 9, wherein the gate structure has a trapezoidal cross-sectional shape.

11. The device according to claim 9, wherein the dielectric layer is disposed on the gate structure and the insulator.

12. The device according to claim 11, wherein the multilayer channel structure is arranged on the dielectric layer.

13. The device according to claim 12, wherein the first electrode and the second electrode are electrically in communication with each other via the multilayer channel structure.

14. The device according to claim 6, wherein the multilayer channel structure is arranged on the insulator.

15. The device according to claim 14, wherein the dielectric layer is arranged on the multilayer channel structure.

16. The device according to claim 15, wherein the gate structure is disposed on the dielectric layer.

17. The device according to claim 15, wherein the dielectric layer is made of a ferroelectric material.

18. The device according to claim 15, wherein the first electrode is electrically in communication with the multilayer channel structure.

19. The device according to claim 15, wherein the first electrode is in physical contact with the multilayer channel structure.

20. The device according to claim 19, wherein the first electrode is in physical contact with the dielectric layer.

21. The device according to claim 19 or 20, wherein the first electrode is in physical contact with the insulator.

22. The device according to claim 19 or 20, further comprising another insulator disposed adjacent to the first electrode on the side opposite to the multilayer channel structure.

23. The device according to any one of claims 1 to 5, further comprising a metal, wherein the gate structure is disposed on the metal.

24. The device according to claim 23, further comprising a dielectric layer disposed on the gate structure.

25. The device according to claim 24, wherein the first electrode is disposed on the multilayer channel structure and the dielectric layer, and the second electrode is disposed on the multilayer channel structure and the dielectric layer.

26. The device according to claim 25, further comprising an intervening insulator disposed between the first electrode and the second electrode.

27. The device according to claim 24, wherein the multilayer channel structure is arranged on the dielectric layer.

28. The device according to claim 23, further comprising a ferroelectric material disposed on the gate structure.

29. The device according to claim 28, wherein the multilayer channel structure is arranged on the ferroelectric material.

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