Interposer for rear-side power supply network

Abstract

In some embodiments, the structure comprises an active element having a front surface and a back surface opposite to the front surface, the active element having an active circuit closer to the front surface than to the back surface, and a power redistributing element having a front surface hybridized to the back surface of the active element, the power redistributing element comprising a first plurality of contact pads on the front surface of the power redistributing element and a second plurality of contact pads on the back surface of the power redistributing element opposite to the front surface of the power redistributing element, wherein the pitch of the first plurality of contact pads is smaller than the pitch of the second plurality of contact pads, and the power redistributing element is configured to supply at least one of power and ground to the active element.

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims priority to U.S. Provisional Patent Application No. 63 / 493,627, filed on March 31, 2023, entitled "INTERPOSER FOR BACKSIDE POWER DELIVERY NETWORK", the entire disclosure of which is incorporated herein by reference for all purposes.

[0002] This disclosure relates to semiconductor device structures and methods. In particular, some embodiments are directed to methods and structures for backside power delivery.

Background Art

[0003] Although the techniques described in this section could have been pursued, they were not necessarily envisioned or pursued in the past. Therefore, unless otherwise indicated, none of the techniques described in this section should be regarded as being in the prior art merely for the reason that they are included in this section.

[0004] As the features of semiconductor devices continue to shrink, concerns about power supply issues are increasing. Issues such as electrical insulation problems, feature size limitations due to high density of circuit elements and interconnections, and losses due to crossing multiple metal layers make efficient power supply to semiconductor devices difficult.

Summary of the Invention

[0005] Referring to the drawings of certain embodiments, the above and other features, aspects, and advantages of the present disclosure will be described. These drawings are illustrative and not intended to limit the present disclosure. It is understood that the accompanying drawings, which are incorporated herein and form a part of this specification, are for the purpose of illustrating the concepts disclosed herein and may not be to scale.

Brief Description of the Drawings

[0006] [Figure 1A] This figure shows an exemplary embodiment of a device structure that can supply power to the back surface of an integrated device die. [Figure 1B] This figure shows an exemplary embodiment of a power supply die having a redistribution layer. [Figure 2] This figure shows an exemplary embodiment of a power supply die having a redistribution layer and contact pads. [Figure 3] This figure shows an exemplary embodiment of a stacked structure in which a power supply die interacts with elements via an interposer. [Figure 4] This is a top view of one exemplary embodiment of the interposer contact pad layout. [Figure 5A] This figure shows an exemplary pattern of an interposer contact pad according to several embodiments. [Figure 5B] This figure shows an exemplary pattern of an interposer contact pad according to several embodiments. [Figure 5C] This figure shows an exemplary pattern of an interposer contact pad according to several embodiments. [Figure 6] This figure shows an exemplary embodiment of a portion of a power supply die having a separate voltage plane. [Figure 7A] This figure shows an exemplary embodiment of a power supply die having two or more power or ground lines in the same plane. [Figure 7B] This figure shows an exemplary embodiment of a power supply die having two or more power or ground lines in the same plane. [Figure 8A] This figure shows an exemplary embodiment of a stacked structure including passive elements. [Figure 8B] This figure shows an exemplary embodiment of a stacked structure including passive elements. [Figure 9A] This figure shows an exemplary embodiment of a power supply die. [Figure 9B] This figure shows an exemplary embodiment of a power supply die. [Figure 10A] This diagram schematically illustrates a direct bonding process according to several embodiments. [Figure 10B] This diagram schematically illustrates a direct bonding process according to several embodiments.

[0007] Each of the systems, methods, and devices described herein has multiple embodiments, but none of them alone possess the desired attributes. Several non-limiting features are briefly described below without limiting the scope of this disclosure.

[0008] In one embodiment, the technology described herein relates to a structure comprising: an active element having a front surface and a back surface opposite to the front surface, a plurality of vias extending perpendicularly from the back surface through a portion of the active element, and an active region closer to the front surface than to the back surface; and a power redistribution element disposed on the back surface of the active element, wherein the power redistribution element comprises a front surface and a back surface opposite to the front surface, a first plurality of contact pads disposed on the front surface, and a second plurality of contact pads disposed on the back surface, the pitch of the first plurality of contact pads being smaller than the pitch of the second plurality of contact pads, and the first plurality of contact pads being electrically coupled to a plurality of vias.

[0009] In some embodiments, the technology described herein relates to a power supply die having a front surface and a back surface opposite to the front surface, wherein the front surface is in electrical contact with a second plurality of contact pads of a power redistribution element.

[0010] In some embodiments, the technology described herein relates to a structure in which a power redistribution element is configured to carry power and ground, but not to carry logic signals.

[0011] In some embodiments, the technology described herein relates to a structure in which the power redistribution element comprises an interposer.

[0012] In some embodiments, the technology described herein relates to a structure in which the power redistribution element further includes a hybrid bonding layer disposed on the surface of the power redistribution element.

[0013] In some embodiments, the technology described herein relates to a structure in which the power redistribution element further includes a hybrid bonding layer disposed on the back surface of the power redistribution element.

[0014] In some embodiments, the technology described herein relates to a structure in which at least a part of the power redistribution element is deposited on the back surface of the active element.

[0015] In some embodiments, the technology described herein relates to a structure in which at least a part of the power redistribution element is deposited on the back surface of the active element after the active element is thinned.

[0016] In some embodiments, the technology described herein relates to a structure in which the surface of the power supply die is hybrid bonded to the back surface of the power redistribution element.

[0017] In some embodiments, the technology described herein relates to a structure in which the surface of the power supply die is hybrid bonded to the back surface of the power redistribution element, and the surface of the power redistribution element is hybrid bonded to the back surface of the active element.

[0018] In some embodiments, the technology described herein relates to a structure further including a passive element disposed between the power supply die and the power redistribution element.

[0019] In some embodiments, the technology described herein relates to a structure in which power is supplied to the back surface of the active element through the power redistribution element.

[0020] In one embodiment, the technology described herein relates to a structure comprising an active element having a front surface and a back surface opposite to the front surface, wherein the active element has an active circuit closer to the front surface than to the back surface, and a power redistributing element having a front surface hybridized to the back surface of the active element, wherein the power redistributing element comprises a first plurality of contact pads on the front surface of the power redistributing element and a second plurality of contact pads on the back surface of the power redistributing element opposite to the front surface of the power redistributing element, wherein the pitch of the first plurality of contact pads is smaller than the pitch of the second plurality of contact pads, and the power redistributing element is configured to supply at least one of power and ground to the active element.

[0021] In some embodiments, the technology described herein relates to a structure in which an active element comprises vias extending from the back surface of the active element to an active circuit.

[0022] In some embodiments, the technology described herein further comprises a power supply die having a front surface and a back surface opposite to the front surface, wherein the front surface of the power supply die is hybrid-bonded to the back surface of a power redistribution element.

[0023] In some embodiments, the technology described herein relates to a structure in which at least one of power and ground is carried through a power redistribution element and supplied to the back surface of an active element.

[0024] In one embodiment, the technology described herein relates to an interposer comprising a front surface, a back surface opposite to the front surface, a redistribution layer, a first plurality of contact pads disposed on the front surface of the interposer, and a second plurality of contact pads disposed on the back surface of the interposer, wherein the first pitch of the first plurality of contact pads is smaller than the second pitch of the second plurality of contact pads, the first plurality of contact pads are configured to be electrically connected to vias on the back surface of an active element, and the second plurality of contact pads are configured to be electrically connected to contact pads on a power supply die, and at least one of the front surface and the back surface comprises a hybrid bonding layer.

[0025] In some embodiments, the technology described herein relates to an interposer having a first pitch of about 50 nm to about 1000 nm and a second pitch of about 1 μm to about 500 μm.

[0026] In some embodiments, the technology described herein relates to an interposer having a thickness of about 1 μm to about 50 μm.

[0027] In some embodiments, the technology described herein relates to an interposer in which a plurality of second contact pads are arranged in a periodic pattern.

[0028] In some embodiments, the technology described herein relates to an interposer whose surface comprises a hybrid bonding layer.

[0029] In some embodiments, the technology described herein relates to an interposer whose back surface comprises a hybrid bonding layer.

[0030] In some embodiments, the technology described herein relates to an interposer comprising a plurality of layers, each layer configured to carry a single voltage or ground, and each layer being isolated from the other layers by a dielectric material.

[0031] In some embodiments, the technology described herein relates to an interposer configured to transport power from a power supply die on the back surface of the interposer to the front surface of the interposer, which is electrically connected to vias on the back surface of an active element.

[0032] In another embodiment, the technology described herein comprises forming a first interposer comprising: a first surface; a first back surface opposite to the first surface; a first surface contact disposed on the first surface, the first surface contact being arranged in a first frontside arrangement and configured to be electrically connected to vias on the back surface of a first active element; and a first back contact disposed on the first back surface, the first back contact being arranged in a first back pattern and configured to be electrically connected to a first power supply die; and a second surface; a second back surface opposite to the second surface; and a second surface contact disposed on the second surface, the second surface contact being arranged in a second frontside arrangement. The present invention relates to a method for forming a second interposer comprising: a second surface contact arranged in a (first surface arrangement) and configured to be electrically connected to vias on the back surface of a second active element; and a second back surface contact disposed on the back surface of the second interposer, the second back surface contact arranged in a second back surface pattern and configured to be electrically connected to a second power supply die, wherein the first surface arrangement is different from the second surface arrangement, and the first back surface pattern is the same as the second back surface pattern.

[0033] In some embodiments, the technology described herein relates to a method wherein the first interposer further comprises a first surface hybrid bonding surface disposed on the first surface.

[0034] In some embodiments, the technology described herein relates to a method wherein the first interposer further comprises a first back surface hybrid bonding surface disposed on the first back surface.

[0035] In some embodiments, the techniques described herein relate to a method in which the pitches of the first back surface pattern and the second back surface pattern are greater than the pitches of the first surface arrangement and the second surface arrangement.

[0036] In some embodiments, the techniques described herein relate to a method in which the pitch of a first surface array is about 100 nm to about 500 nm, the pitch of a second surface array is about 100 nm to about 500 nm, and the pitch of the first back surface pattern and the second back surface pattern is about 20 μm to about 500 μm.

[0037] In some embodiments, the technology described herein relates to a method in which a first interposer is configured to supply first power from a first power supply die to the first back surface of a first active element, and a second interposer is configured to supply second power from a second power supply die to the second back surface of a second active element.

[0038] In another embodiment, the technique described herein includes a method for forming a first interposer comprising: a first surface; a first back surface opposite to the first surface; a first surface contact disposed on the first surface, the first surface contact being arranged in a first frontside arrangement and configured to electrically connect to vias on the back surface of a first active element; and a first back surface contact disposed on the first back surface, the first back surface contact being arranged in a first back surface pattern and configured to electrically connect to a first power supply die.

[0039] In some embodiments, the technology described herein relates to a method wherein the first interposer further comprises a first surface hybrid bonding surface disposed on the first surface.

[0040] In some embodiments, the technology described herein relates to a method wherein the first interposer further comprises a first back surface hybrid bonding surface disposed on the first back surface.

[0041] In some embodiments, the technology described herein relates to a method in which a first interposer is configured to supply first power from a first power supply to the first back surface of a first active element.

[0042] In some embodiments, the technology described herein further includes a method for forming a second interposer comprising: a second surface; a second back surface opposite to the second surface; a second surface contact disposed on the second surface, the second surface contact being arranged in a second frontside arrangement and configured to electrically connect to vias on the back surface of a second active element; and a second back contact disposed on the second back surface, the second back contact being arranged in a second back pattern and configured to electrically connect to a second power supply die.

[0043] In some embodiments, the techniques described herein relate to a method in which a first surface arrangement differs from a second surface arrangement.

[0044] In some embodiments, the technology described herein relates to a method in which a first back surface pattern is the same as a second back surface pattern.

[0045] In some embodiments, the techniques described herein relate to a method in which the pitches of the first back surface pattern and the second back surface pattern are greater than the pitches of the first surface arrangement and the second surface arrangement.

[0046] In some embodiments, the techniques described herein relate to a method in which the pitch of a first surface array is about 100 nm to about 500 nm, the pitch of a second surface array is about 100 nm to about 500 nm, and the pitch of the first back surface pattern and the second back surface pattern is about 20 μm to about 500 μm.

[0047] Various combinations of the features, embodiments, and aspects listed above and below are also disclosed and intended in this disclosure.

[0048] Additional embodiments of this disclosure will be described below with reference to the attached claims, which may serve as an additional overview of this disclosure. [Modes for carrying out the invention]

[0049] Several embodiments, examples, and demonstrations are disclosed below, but those skilled in the art will understand that the disclosures described herein extend beyond the specific embodiments, examples, and demonstrations disclosed herein, including other uses of the disclosure and their obvious improvements and equivalents. Embodiments are described with reference to the accompanying drawings, where the same numbers throughout represent the same elements. The technical terms used in the descriptions presented herein are not intended to be restrictive or limiting, merely because they are used in conjunction with the detailed descriptions of some specific embodiments of the disclosure. Furthermore, embodiments may include several novel features. No single feature alone is responsible for its desired attributes, nor is it essential for carrying out the disclosures described herein.

[0050] Backside power supply can mitigate the problems associated with high density and feature size reduction by separating power supply from signal routing. However, backside power supply can be difficult to implement. Some embodiments of this specification may enable easier and / or lower-cost deployment of backside power supply.

[0051] In conventional semiconductor devices, both signal transmission and power supply occur through the device surface. However, as device features continue to shrink, it is becoming increasingly difficult to supply both power and signals through the device surface without affecting device performance. For example, as semiconductor devices become denser and more complex, the number of transistors or computing cells per unit area increases with each new advanced process node, and consequently, the number of metal layers containing signal and power (or ground) lines supplying these transistors also tends to increase, substantially increasing the path length of power-carrying wires. As the density of transistors in the active device region increases, the density of power and signal circuits may also increase accordingly. To cope with this increased density, one might consider reducing the cross-sectional area of ​​vias and other circuits. However, this can increase impedance and power loss. For example, reducing the cross-sectional area and increasing the length of power lines can result in significant power loss due to the high resistance of the thin copper typically used for surface power supply. For example, a device can be designed to cope with approximately 10% power supply loss (e.g., voltage drop) from the power source during transmission to the active device region through the metal layers. However, significant drops are observed, especially in micro- or more advanced manufacturing nodes, when a large number of metal layers are present (e.g., around 10, 15, 20, or more). In some processes, metal interconnects can include alternative materials such as cobalt, for example at lower back-end-of-life (BEOL) levels, which can reduce power loss. However, the advantages of using other conductive materials are limited, and given the continued shrinking of semiconductor device features, different approaches are likely to be needed to address power and signal transmission failures. Furthermore, power lines occupy a large area on the device surface. This could mean that the mounting area of ​​the semiconductor device may be significantly larger to allow sufficient area for power and signal transmission lines to coexist on the device surface.

[0052] Backside power supply can mitigate some of the problems associated with scaling semiconductor devices to smaller process nodes. For example, backside power supply can alleviate surface congestion by eliminating or reducing the need to route power across the surface. Backside power supply can enable wider and thicker power supply and / or signal transmission lines. Backside power supply can shorten the electrical path length between the power supply and the active device area. Such lines may have lower impedance, thus enabling reduced power loss and / or improved signal integrity. Also, even without increasing the cross-sectional area of ​​the lines, backside power supply can improve signal integrity because, for example, power supplies can be placed relatively far away from signal transmission lines, reducing the possibility of power transmission electromagnetic interference with signal transmission.

[0053] In addition to reducing losses and improving signal integrity, back-side power supply can be used as a tool to enable designers to create more compact devices. As briefly mentioned above, semiconductor devices can become unnecessarily large relative to the active device area when both power and signal reside on the same side of the device. Such design decisions can play an increasingly important role in scaling, as the benefits of moving to smaller, more advanced technology nodes exhibit diminishing returns.

[0054] Figure 1A schematically shows an example of supplying power to the back surface of an active element, such as an integrated device die. In Figure 1A, the active element 101 may include a logic / signal stack 102 disposed near the front surface 152 of the active element 101. The logic / signal stack may include transistors, signal routing circuits, and other components, including active devices, device cells and circuits, or electronic components that process, store, or transmit signals. The active element 101 may include a back bulk portion 103 that includes vias 104 for supplying power to the active components of the logic / signal stack 102 via the back surface 150 of the active element 101. The vias 104 are electrically contactable with the logic / signal stack 102. In some embodiments, the vias 104 can be embedded power rails, nanoTSVs, power TSVs, back surface contacts to sources and drains, etc. A power supply structure 170 having a power supply die 105 can be joined to the back surface 150 of the active element 101 via a junction interface 106 (for example, it can be hybrid-jointed as will be discussed in more detail herein). An active circuit (for example, a transistor) may be located closer to the front surface 152 than to the back surface 150.

[0055] As via 104, blind vias (e.g., vias that do not completely penetrate the active element 101) are possible. In some embodiments, via 104 may include nanovias that connect directly to transistors in the logic / signal stack 102 located on the surface side of the device, but in some embodiments, vias do not have to connect directly to transistors. In some embodiments, via 104 can be electrically connected to one or more metal layers (or signal layers) on the surface of the device to effectively supply power from the surface to the transistors. In some embodiments, via 104 can supply power to the side or back of the logic / signal stack 102 (e.g., transistors in the logic / signal stack 102). In some embodiments, the power supply structure or via 104 can supply power to the transistor or device cell from the surface of the transistor or device (e.g., contacts from the surface to the drain and source via embedded power rails, plugs, etc.), from the side of the transistor cell or device (e.g., electrical contacts to the source and drain regions via embedded power rails, power vias, nanoTSVs, etc.), or from the back side (e.g., back side contacts, i.e., BSC) by direct contact to the source / drain regions. Vias may comprise one or more conductive materials, such as polysilicon (which may have similar mechanical properties to silicon substrates), cobalt, ruthenium, and / or tungsten. In some embodiments, vias may be formed relatively early in the semiconductor device manufacturing process prior to the completion of the front-end process. For this reason, in some embodiments, it is considered preferable to avoid the use of copper and / or nickel, which may diffuse into the surrounding material and cause malfunction or failure. Also, the relatively low melting point of copper may pose problems when performing high-temperature annealing and other high-temperature processing steps to construct high-quality advanced node transistors. In some embodiments, vias may be formed after the completion of the front-end process. In some embodiments, thinning of the active element may expose vias formed before the completion of the front-end process.In some embodiments, a "drilling and filling" technique may be used. For example, holes may be formed after thinning of the active element, and these holes may be filled with a conductive material (e.g., by deposition) after the completion of the front-end process.

[0056] As shown in Figure 1B, the power supply die 105 may include a redistribution layer 107. The redistribution layer 107 may be configured to distribute power and ground from the power supply die 105 to the active element 101 via 104. However, realizing such a power supply die can be difficult. For example, the pitch between the vias 104 can be less than about 1 μm (e.g., about 20 nm to about 1000 nm (e.g., in the range of about 20 nm to about 100 nm, about 50 nm to about 1000 nm, about 100 nm to about 1000 nm, or about 100 nm to about 500 nm)). And although direct bonding (e.g., hybrid bonding) can be used, alignment challenges can be significant. Furthermore, such methods present design, manufacturing, and storage complexities for power supply die manufacturers. Different elements typically do not share a common layout of power vias. For example, the via layout can vary depending on the number of voltages required, the layout of transistors in the logic and signal stack, the functional block layout, etc. Therefore, if the redistribution layer is integrated into the power supply die and interacts directly with the element (for example, directly with the element's power supply vias), it becomes necessary to design, manufacture, and store a different power supply die for each different via layout of different elements, which increases design costs and creates logistical obstacles.

[0057] Therefore, it is beneficial to have a general-purpose interposer between the active element 101 and the power supply die 105. The general-purpose interposer may have a standardized layout on one side for working with the power supply die 105, while the other side may be customized for each different type of active element 101. Since the power supply die manufacturer can design a die that works with the standardized layout of the interposer, the need to customize the power supply die for each type of element can be avoided. However, naturally, some limited customization may still be possible. For example, depending on the size of the element, the power supply die can be configured to be larger or smaller (for example, with more or fewer contacts). Such customization may be relatively easy because the standardized layout may, in some embodiments, include repeating patterns that can be easily scaled up or down to accommodate elements of a particular size or to handle a particular number of electrical connections.

[0058] In some embodiments, the interposer may include a deposited redistribution layer, a reconfiguration layer, etc. In some embodiments, the interposer may include an active circuit, a semiconductor device, or a transistor. In some embodiments, the interposer may not include an active circuit, a semiconductor device, or a transistor. The interposer can have a smaller or larger mounting area, or it can be the same size as a logic die or another element. In some embodiments, the interposer can extend beyond the edge of a logic die or another element. In some embodiments, the interposer can be a single layer. In some embodiments, the interposer may comprise multiple layers. For example, in some embodiments, the interposer may include one or more deposited redistribution layers and one or more junction (e.g., hybrid junction) layers. For example, it may be desirable to junction one or more first layers to the back surface of an element where a relatively small pitch makes direct junction difficult. Since the interposer carries only a limited number of signals (e.g., power, ground, and possibly some slow signaling), redistribution is very simple and it can be made thin. For example, the interposer may have a thickness of about 0.5 μm to about 5 μm (e.g., about 1 μm to about 2 μm). In some embodiments, the interposer may have a thickness of less than about 700 μm. In another embodiment, the interposer may be one or more routing layers deposited on the back of a thinned logic die on exposed nanovias, which expand the pitch of nanovias on one side of the deposited routing layer stack to an expanded standard pitch on the other side.

[0059] In some embodiments, the power supply die may be bonded to the interposer (e.g., by hybrid bonding). In some embodiments, the power supply die may be surface-mounted or soldered to the interposer (e.g., by a flip-chip process). In some embodiments, the power supply die may be bonded to the interposer by thermocompression bonding. In some embodiments, external power may be supplied to the power die by wire bonding or a pin grid array.

[0060] An example of a power supply die 105 having a standardized contact pad layout is shown in Figure 2. As shown in Figure 2, the power supply die 105 may include a redistribution layer 108 and contact pads 109a to 109c. Unlike the redistribution layer 107 in Figure 1B, which is designed to be electrically connected to vias 104 of the active element 101, the redistribution layer 108 may be used to route power and ground signals to contact pads 109a to 109c, which have known patterns for electrical connection to the interposer. For example, in the exemplary embodiment of Figure 2, the contact pads 109a to 109c include several (e.g., three) different types of pads. For example, the first pad 109a may provide ground, the second pad 109b may provide a first supply voltage, and the third pad 109c may provide a second supply voltage different from the first supply voltage. Of course, such a layout is just an example, and different layouts may be used depending on, for example, the number of voltages to be supplied, the layout of the active element 101, etc.

[0061] Figure 3 shows an exemplary embodiment of a laminated structure in which a power supply structure 170 interacts with an active element 101 via an interposer 110. In some embodiments, power can be transferred to the power supply structure 170 from outside the laminated structure (e.g., via wire bonds, etc.) and traverse the circuitry of the power supply structure 170. In some embodiments, the power supply structure 170 can modify voltage amplitude, frequency, clock signal, power supply timing, etc. In some embodiments, the power supply structure 170 may include a power supply die 105. In some embodiments, the power supply structure 170 may include other structures, such as an integrated voltage regulator and / or any other suitable active, passive, or dummy device, as an addition or alternative.

[0062] The power supply die 105 may have a circuit (e.g., a transistor) that controls the distribution of power and ground to the active element 101. In some embodiments, the power supply die 105 may include passive elements such as resistors, capacitors, and inductors. The contact pads 109a to 109c of the power supply die 105 are in electrical contact with the contact pads 111a to 111c of the interposer 110 at the junction interface 113. At the junction interface 114, the contact pads 142a to 142c are in electrical contact with the logic / signal stack 102. The contact pads 142a to 142c may have a first pitch p1 (for example, the contact pads 142a to 142c of the interposer 110 may have a minimum first pitch corresponding to the minimum pitch of the pads in the interposer 110), and the contact pads 111a to 111c may have a second pitch p2. Pitch p1 may be smaller than pitch p2. In some embodiments, contact pads 142a to 142c may have a first width w1, and contact pads 111a to 111c may have a second width w2. Since the ground pad does not carry current, in some embodiments it may be smaller in size (e.g., width, diameter, etc.) than the other pads. On the other hand, the voltage or power supply pads may be larger (e.g., width, diameter, etc.). The via 104 may have a pitch of about 50 nm to about 1000 nm (e.g., about 100 nm to about 500 nm). The pitch p1 may be the same as or identical to the pitch of the via 104 (e.g., about 50 nm to about 1000 nm), or it may be about 10 nm to about 5000 nm. The pitch p2 can be approximately 0.2 μm to 50 μm, approximately 1 μm to 500 μm, or approximately 20 μm to 500 μm (for example, approximately 20 μm to 100 μm). The interposer 110 can be a thin structure that allows for expansion from fine vias to coarser pads (for example, contact pads 111a to 111c). The contact pads 142a to 142c are shown in a regular repeating arrangement in Figure 3, but of course, such an arrangement is not mandatory.The contact pads 142a to 142c may be arranged according to the layout of the vias 104 of the active element 101, which may or may not be arranged in a regular pattern.

[0063] In some embodiments, the interposer 110 (e.g., a power redistribution element) redistributes power. In some embodiments, the interposer 110 can redistribute signals (e.g., logic signals) in addition to power signals and / or ground signals. Signals received by the interposer 110 from the power supply die 105 via contact pads 111a-111c can then be redistributed in the redistribution layer 112 of the interposer 110. The redistribution layer 112 may be configured to supply power and ground signals to vias 104 of the active element 101. The interposer 110 can be electrically connected (e.g., electrically coupled) to the vias 104 on the back surface 103 of the active element 101 at the junction interface 114. The power supply die 105 can be bonded (e.g., hybrid bonded) to the interposer 110 via the junction interface 113. In some embodiments, the interposer layer can be formed by depositing the redistribution layer 112 onto the vias 104.

[0064] In some embodiments, the interposer 110 may be bonded (e.g., directly bonded or hybrid bonded) to the back surface of the active element 101. The interposer 110 can be any power distribution element (e.g., a power redistribution element), and may be a separate element (e.g., a separate interposer that can be bonded to the active element 101), or it may be partially or entirely deposited on the back surface of the active element 101. For example, in other embodiments, the interposer 110 may be formed on the back surface of the active element 101 by processes such as lithography, deposition, etching, polishing, and other processes known to those skilled in the art. Briefly as described above, the interposer 110 is shown as a single unit in Figure 3, but in some embodiments it may comprise multiple layers or multiple subunits, some of which may be deposited (e.g., one or more layers closest to the back surface of the active element 101), and the others may be directly bonded (e.g., hybrid bonded) (e.g., one or more layers closest to the power supply die 105).

[0065] Figure 4 is a top view of the interposer's pad layout. As shown in Figure 4, the contact pads 111a to 111c can be distributed in a regular pattern with respect to the interposer. For example, as described above, contact pad 111a can provide a first voltage (or ground), contact pad 111b can provide a second voltage (or ground), and contact pad 111c can provide a third voltage (or ground). In some embodiments, it is possible to increase or decrease the number of contact pad types. For example, some embodiments may include two types of contact pads (e.g., one set of pads for providing ground and another set of pads for providing power supply voltage). In some embodiments, larger contact pads 115a to 115c may be distributed around contact pads 111a to 111c, but in some embodiments, larger contact pads 115a to 115c may not be present. Naturally, Figure 4 is for illustrative purposes only. Actual devices may have more pads than those shown in Figure 4.

[0066] Figures 5A to 5C show exemplary patterns of contact pads in an interposer according to several embodiments. In the example in Figure 5A, the contact pads 111a to 111c are arranged in a repeating pattern horizontally and vertically, with each row starting one position offset from the previous row. For example, in the second row from the top, the first contact pad from the left corresponds to the second contact pad in the first row from the top. Such an arrangement can help ensure that the distance between the contact pads and the vias that access the specific power supply voltage (or ground) provided by the pads is relatively short, regardless of the via's position on the element. For example, in Figure 5A showing three voltages (or ground), each pad has multiple nearest adjacent vias containing the other voltages (or ground). Such a design is considered desirable for general interposers used with elements having arbitrary via layouts. However, such a design may be suboptimal for a particular element layout. For example, in devices using fin-type field-effect transistors (FINFETs) or gate-all-around field-effect transistors (GAAFETs) (e.g., nanosheet GAA FETs and / or nanowire GAA FETs), the components of the device (e.g., FINFETs) are often arranged in rows. Therefore, a structure like the one shown in Figure 5B may be advantageous. For example, contact pads 111a to 111c may be arranged in rows that roughly coincide with the positions of the FINFETs of the device. In some embodiments, each row may be supplied with a specific power supply voltage (or ground). Such an arrangement allows for, for example, simplification of the redistribution layer, reduction of the path length that power (or a specific voltage) must travel to reach the transistors of the device (and thus reduction of power loss), etc.

[0067] Figure 5C shows another exemplary pattern of contact pads according to several embodiments. In Figure 5C, the contact pads are clustered. For example, a first region may include a first type of contact pad (e.g., supplying a first voltage or ground), and a second region may provide a second type of contact pad (e.g., supplying a second voltage or ground). Alternatively, two or more types of contact pads may be present within a given region. For example, one region may include contact pads for supplying a power voltage and contact pads for ground. Such an arrangement is considered desirable, for example, when the element is arranged as regions (e.g., regions for general arithmetic tasks that the CPU typically performs, regions for graphical tasks, regions for communication, etc.) and the regions have different power demands (e.g., require different supply voltages). In some embodiments, the element may be a reconfigurable element comprising multiple sub-elements that may be configured according to different processes and / or have different power requirements. The layout shown in Figure 5C is considered particularly beneficial in such an element.

[0068] Power supply dies having periodic or other standardized patterns for interaction with an interposer can have a variety of structures. In some embodiments, the power supply die may have separate power surfaces (also referred to herein as voltage surfaces). For example, in some embodiments, the power supply die may have a separate power surface for each voltage supplied to an element. The power supply die may also have one or more surfaces for providing ground. In some embodiments, each voltage may be on its own voltage surface. In some embodiments, one or more combinations of voltages may be provided on the same surface, which may include ground. In some embodiments, a ground surface may be provided between two voltage surfaces to separate and shield the two voltage surfaces. The power supply die may have a standardized interface (e.g., a standardized arrangement of contact pads) that can electrically contact an element such as a semiconductor die in interaction with a thin interposer, which may have contacts with a remarkably small pitch, but may not have a standardized layout.

[0069] Figure 6 shows an exemplary embodiment of a portion of the power supply die 105 in which separate voltage planes are used to provide contact pads of a desired pattern. As shown in Figure 6, the power supply die 105 may have a first voltage / ground line 116a, a second voltage / ground line 116b, and a third voltage / ground line 116c, each voltage line being primarily located within its own horizontal plane. The first voltage / ground line 116a, the second voltage / ground line 116b, and the third voltage / ground line 116c may be embedded in dielectric layers 160a, 160b, 160c, and 160d that can electrically insulate the planes from each other, with vertical lines extending toward the planes of the power supply die. The vertical lines extend toward the planes of the power supply die 105 to form a pattern of contact pads that can be joined (e.g., directly joined or hybrid joined) to an interposer. For example, in some embodiments, the vertical extensions can form patterns as shown in Figures 5A to 5C. As mentioned above, it can be advantageous to have a ground layer between voltage layers. For example, in some embodiments, a first voltage / ground line 116a may carry a power supply voltage, a third voltage / ground line 116c may carry a second power supply voltage, while a second voltage / ground line 116b may provide ground.

[0070] While the design in Figure 6 may have many advantages, forming multiple layers can be expensive and difficult, especially when many different voltages are provided. Therefore, as mentioned above, in some embodiments, one or more voltage and / or ground lines may be provided in the same plane. Figures 7A and 7B show an exemplary embodiment in which multiple power / ground lines are present in the same plane. Figure 7A is a top view of such a power / ground line distribution, and Figure 7B is a cross-sectional view of such an embodiment.

[0071] Figure 7A is a top view of a power supply die 105 according to several embodiments. The power supply die 105 may include power supply (or ground) lines 118a, 118b, and 118c. All power supply lines 118a to 118c may be located in a common plane. As shown in Figure 7B, contact pads 119a, 119b, and 119c may be exposed on the main surface of the power supply die. The contact pads 119a to 119c may be arranged periodically or in other patterns, for example, as shown in Figures 5A to 5C. Power can also be routed from the power supply lines 118a to 118c to the contact pads 119a to 119c by using a redistribution layer 120. The power supply lines 118a to 118c and the contact pads 119a to 119c may be disposed in a dielectric material 162 that can provide electrical insulation.

[0072] In some embodiments, the power supply die can be a passive device. For example, the power supply die can redistribute power without additional functionality. In some embodiments, the power supply die may include additional circuitry, such as devices and transistors, including buffer circuits, to improve voltage uniformity across the die. In some embodiments, a separate passive element may provide a buffer circuit that enables more uniform power supply. The passive element may include, for example, a resistor, capacitor, inductor, etc.

[0073] Figure 8A shows an exemplary embodiment including a separate passive element 121. In Figure 8A, the power supply die 105 may be bonded (e.g., directly bonded or hybrid bonded) to the passive element 121 at the bonding interface 122. The passive element 121 may include first contact pads 123a to 123c that are in electrical contact with the contact pads 109a to 109c of the power supply die 105. The passive element 121 may be bonded (e.g., directly bonded or hybrid bonded) to the interposer 110 at the bonding interface 124. The passive element may include second contact pads 127a to 127c that are in electrical contact with the contact pads 111a to 111c of the interposer 110. The interposer may have contact pads 142a to 142c having a smaller pitch than the contact pads 111a to 111c, as described above with reference to Figure 3, for example. Passive elements may include, for example, a buffer circuit that can enable a more uniform power supply. Passive elements may include one or more capacitors, resistors, inductors, integrated voltage regulators (IVRs), etc. In some embodiments, the pitch between the first contact pads 123a to 123c may differ from (e.g., larger than) the pitch between the second contact pads 127a to 127c. In some embodiments, the size (e.g., width or diameter) of the first contact pads 123a to 123c may differ from (e.g., larger than) the size (e.g., width or diameter) of the second contact pads 127a to 127c.

[0074] Figure 8B shows another exemplary embodiment including a separate passive element 125. In Figure 8B, the power supply die 105 may be bonded (e.g., directly bonded or hybrid bonded) to the interposer 110 at the bonding interface 113. The interposer 110 may be bonded (e.g., directly bonded or hybrid bonded) to the passive element 125 at the bonding interface 128. The passive element 125 may be bonded (e.g., directly bonded or hybrid bonded) to the active element 101 at the bonding interface 130. The interposer shown in Figure 8B may have contact pads 111a-111c and contact pads 144a-144c. The contact pads 111a-111c may be electrically connected to the contact pads 109a-109c of the power supply die 105. The interposer 110 may have a second set of contacts 144a-144c that can be electrically connected to the passive element 125 via contact pads 146a-146c. The pitch of the contact pads 144a-144c can be smaller than, larger than, or approximately the same as the pitch of the contact pads 111a-111c. The passive element 125 may include contacts 148a-148c that are electrically connected to vias 104 of the active element 101. The contacts 148a-148c may have a pitch that matches the pitch of vias 104. The pitch of the contacts 148a-148c can be the same as the pitch p1 of the contact pads 142a-142c shown in Figure 3. As shown in Figures 8A and 8B, the position of the passive element can vary within the stack and may be located on both sides of the interposer depending on the particular embodiment. For example, in Figure 8A, the passive element 121 is disposed between the power supply die 105 and the interposer 110, while Figure 8B shows the passive element 125 disposed between the interposer 110 and the active element 101 (for example, a semiconductor die).

[0075] Figures 9A and 9B illustrate an exemplary embodiment of a power supply die. In Figures 9A and 9B, different voltages may flow orthogonally to each other in different planes. In Figures 9A and 9B, a first voltage (or ground) may be carried by power rail 132 and distributed via power line 134. In another plane, a second voltage (or ground) may be supplied by power rail 136 and power line 138. Power rails 132, 134, 136, and 138 may be arranged in a dielectric 164 that can provide electrical insulation. Power lines 134 and 138 may be electrically connected to contact pads 140. Since power lines 134 and 138 can be oriented perpendicularly to each other, a more uniform power distribution may be possible by suppressing capacitive coupling between lines with different voltages. In some embodiments, there may be only one power rail to which the power lines connect (as shown by power line 134). However, other embodiments are also possible. For example, a power line may be connected to one power rail at a first end (as shown in power line 138) and to another power rail at the opposite end of the power line. Such a configuration can improve the uniformity of the power distribution across the entire element. In some embodiments, a separate ground plane may be located between two power (or voltage) planes. In some embodiments, both power planes may be located on the same side of the junction interface. In some embodiments, the power planes can be distributed across a reconfigured logic wafer, a reconfigured power wafer, etc. Figures 9A and 9B show two layers, but additional layers are also possible. For example, in some embodiments, each plane may have wires containing power or ground lines extending perpendicular to the nearest adjacent plane, but the number of planes is not necessarily limited. In some embodiments, the width or thickness of the power and ground lines may be the same or different.

[0076] While the above example illustrates a power die interacting with an element via an interposer, this disclosure is not limited to power supply alone. In some embodiments, the power die may also include other components such as power control circuits, memory (e.g., static random access memory, dynamic random access memory, etc.), additional logic, capacitor components (or integrated passive devices), and integrated voltage regulators (IVRs). In some embodiments, the power supply die may include analog circuitry, which is considered more suitable for older and larger technology nodes due to the tendency for poorer scaling.

[0077] direct bonding Various embodiments disclosed herein relate to direct bonding structures in which two or more elements can be directly joined to each other without the interposition of an adhesive. In this specification, such processes and structures are referred to as “direct bonding” processes or “direct bonding” structures. Direct bonding may include joining a material on one element to a material on another element (also referred to herein as “uniform” direct bonding), but without conventional adhesive materials, and the materials on the different elements do not need to be the same. Direct bonding may also include joining multiple materials on one element to multiple materials on the other element (e.g., hybrid bonding).

[0078] In some embodiments (not shown), each bonding layer has one material. In these uniform direct bonding processes, only one material on each element is directly bonded. An example of a uniform direct bonding process is the ZIBOND® technology, commercially available from Adeia in San Jose, California. The materials of opposing bonding layers on different elements can be identical or different, and may include elemental or compound materials. For example, in some embodiments, a non-conductive bonding layer can be blanket-deposited on a base substrate portion without patterning with conductive features (e.g., without pads). In other embodiments, the bonding layers can be patterned on one or both elements and can be identical or different, but one material on each element is directly bonded across the entire surface of both elements (or across the entire surface of the smaller element if the elements are of different sizes) without adhesive. In another embodiment of uniform direct bonding, one or both of the non-conductive bonding layers may contain one or more conductive features, but the conductive features do not participate in the bonding. For example, in some embodiments, opposing nonconductive bonding layers can be uniformly and directly bonded to each other, after which through-substrate vias (TSVs) can be formed on one of the bonded elements to provide electrical communication to the other element.

[0079] In various embodiments, the bonding layers 1008a and / or 1008b (see Figures 10A and 10B) may include nonconductive materials such as dielectric materials or undoped semiconductor materials such as undoped silicon, which may contain native oxides. Suitable dielectric bonding surfaces or materials for direct bonding include, but are not limited to, inorganic dielectrics such as silicon oxide, silicon nitride, or silicon oxynitride, silicon carbide, silicon oxycarbonitride, low-K dielectric materials, SiCOH dielectrics, silicon carbonitride, or materials containing carbon or diamond surfaces such as diamond-like carbon. Such carbon-containing ceramic materials are considered inorganic despite containing carbon. In some embodiments, the dielectric material of the bonding surface does not include polymer materials such as epoxy (e.g., epoxy adhesives, cured epoxy, or epoxy composites such as FR-4 materials), resins, or molding materials.

[0080] In other embodiments, the bonding layer may include a conductive material such as a deposited conductive oxide material (e.g., indium tin oxide (ITO)) as disclosed in U.S. Provisional Patent Application No. 63 / 524,564 filed June 30, 2023, but all of its contents are incorporated herein by reference to provide an example of a conductive bonding layer without short-circuit contacts through the interface.

[0081] In direct bonding, the first and second elements can be directly bonded to each other without adhesive, which, unlike the deposition process, results in a structurally different interface compared to the interface produced by deposition. In some applications, the width of the first element in the bonded structure is similar to the width of the second element. In some other embodiments, the width of the first element in the bonded structure is different from the width of the second element. The width or area of ​​a larger element in the bonded structure may be at least 10% greater than the width or area of ​​a smaller element. Furthermore, the interface between direct bonded structures, unlike the interface directly beneath the deposited layer, may contain defect regions where nanometer-scale voids (nanovoids) exist. Nanovoids may be formed by activation of one or both of the bonding surfaces (e.g., exposure to the plasma described below).

[0082] The bonding interface between non-conductive bonding surfaces may contain higher concentrations of material due to activation and / or final chemical treatment processes compared to the bulk of the bonding layer. For example, in embodiments utilizing nitrogen plasma for activation, a nitrogen concentration peak may be formed at the bonding interface. In some embodiments, the nitrogen concentration peak is considered detectable by using secondary ion mass spectrometry (SIMS) techniques. In various embodiments, for example, nitrogen termination (e.g., exposure of the bonding surface to a nitrogen-containing plasma) can result in a nitrogen-terminated surface by substituting OH groups in the hydrolysis (OH termination) surface with NH2 molecules. In embodiments utilizing oxygen plasma for activation, an oxygen concentration peak may be formed at the bonding interface between non-conductive bonding surfaces. In some embodiments, the bonding interface may contain silicon oxynitride, silicon oxycarbonite, or silicon carbonite. Direct bonding may involve covalent bonds stronger than van der Waals bonds. The bonding layer may also include polished surfaces planarized to a high degree of smoothness.

[0083] In direct bonding processes such as uniform direct bonding and hybrid bonding, two elements are joined integrally without the interposition of an adhesive. In non-direct bonding processes that utilize adhesives, an intervening material is usually applied to one or both elements to create a physical connection between them. For example, in some adhesive-based processes, a fluid adhesive (e.g., an organic adhesive such as epoxy) that may contain a conductive filler material is applied to one or both elements, and when it hardens, a physical connection (neither chemical nor covalent) can be formed between the elements. With typical organic adhesives, neither chemical nor covalent bonds with either element are strong. In such processes, the connection between elements is fragile and / or easily reversible due to reheating or detachment.

[0084] In contrast, direct bonding processes join two elements by forming a strong chemical bond (e.g., a covalent bond) between opposing nonconductive materials. For example, in direct bonding processes between nonconductive materials, one or both nonconductive surfaces of the two elements are planarized and chemically prepared (e.g., activated and / or terminated) so that when the elements come into contact, a chemical bond (e.g., a covalent bond) stronger than van der Waals bonds or hydrogen bonds is formed. In some embodiments (e.g., between opposing dielectric surfaces such as opposing silicon oxide surfaces), the chemical bond may spontaneously form at room temperature upon contact. In some embodiments, the chemical bond between opposing nonconductive materials may be strengthened after annealing of the elements.

[0085] As described above, hybrid bonding is a type of direct bonding in which non-conductive features are directly bonded to other non-conductive features, and conductive features are directly bonded to the conductive features of the elements being bonded. While the non-conductive bonding material and interface can be as described above, conductive bonding can be formed, for example, as a direct intermetallic bond. In conventional metal bonding processes, fused metal (e.g., solder) is placed between the conductors of two elements, the alloy is melted by heating, and a bond can be formed between the two elements by cooling. In the resulting bond, the interface with the conductors of both elements is often clearly defined and is subject to reversal upon reheating. In contrast, direct metal bonding, such as that employed in hybrid bonding, does not require melting or intermediate fused metal, and a strong mechanical and electrical connection can be obtained without the much higher temperatures and pressures of thermocompression bonding, often exhibiting interdiffusion of bonded conductive features with grain growth across the bonding interface between elements.

[0086] Figures 10A and 10B are schematic side cross-sectional views of first and second elements 1002 and 1004 before and after a process for forming a direct bond structure, more specifically, a hybrid bond structure, according to several embodiments. In Figure 10B, the bond structure 1000 includes first and second elements 1002 and 1004 directly bonded to each other at a bond interface 1018 without the interposition of an adhesive. A conductive feature 1006a of the first element 1002 may be electrically connected to the corresponding conductive feature 1006b of the second element 1004. In the illustrated hybrid bond structure 1000, the conductive feature 1006a is directly bonded to the corresponding conductive feature 1006b without the interposition of solder or conductive adhesive.

[0087] The conductive features 1006a and 1006b in the illustrated embodiment are embedded in the first bonding layer 1008a of the first element 1002 and the second bonding layer 1008b of the second element 1004, respectively, and are considered to be parts of each. The field regions of the bonding layers 1008a and 1008b extend between the conductive features 1006a and 1006b, enclosing part or all of them. As described above, the bonding layers 1008a and 1008b may include layers of non-conductive material suitable for direct bonding, and the field regions are directly bonded to each other without adhesive. The non-conductive bonding layers 1008a and 1008b may be disposed on the surfaces 1014a and 1014b of the base substrate portions 1010a and 1010b, respectively.

[0088] The first and second elements 1002 and 1004 may include microelectronic elements such as semiconductor elements including, for example, integrated device dies, wafers, passive devices, discrete active devices such as power switches, and MEMS. In some embodiments, the base substrate portion may comprise a device portion such as a bulk semiconductor (e.g., silicon) portion of the elements 1002 and 1004, and a back-end (BEOL) interconnection layer on such a semiconductor portion. The junction layers 1008a and 1008b may be provided as part of such a BEOL layer during device fabrication, part of a redistribution layer (RDL), or as a specific junction layer added to an existing device, with junction pads extending from the contacts of the underlying layer. Active devices and / or circuits may be patterned and / or disposed in or on the base substrate portions 1010a and 1010b and may be electrically in communication with at least some of the conductive features 1006a and 1006b. Active devices and / or circuits may be disposed on the front surfaces 1014a, 1014b or their vicinity of the base substrate portions 1010a, 1010b, and / or on the back surfaces 1016a, 1016b or their vicinity on the opposite side of the base substrate portions 1010a, 1010b. In other embodiments, the base substrate portions 1010a, 1010b may not include active circuits and instead may comprise dummy substrates, passive interposers, passive optical elements (e.g., glass substrates, grids, lenses), etc. Although the bonding layers 1008a, 1008b are shown as being provided on the surface of the element, similar bonding layers may be provided on the back surface of the element as an addition or alternative.

[0089] In some embodiments, the base substrate portions 1010a and 1010b may have significantly different coefficients of thermal expansion (CTE), but by joining elements including such different base substrate portions, a non-uniform joint structure can be formed. The CTE difference between the base substrate portions 1010a and 1010b, and especially between the bulk semiconductor (usually single crystal) portions of the base substrate portions 1010a and 1010b, can be greater than 5 ppm / °C or greater than 10 ppm / °C. For example, the CTE difference between the base substrate portions 110a and 110b can be in the range of 5 ppm / °C to 100 ppm / °C, 5 ppm / °C to 40 ppm / °C, 10 ppm / °C to 100 ppm / °C, or 10 ppm / °C to 40 ppm / °C.

[0090] In some embodiments, one of the base substrate portions 1010a, 1010b may include an optoelectronic single crystal material, including a perovskite material useful for photoelectric or pyroelectric applications, while the other base substrate portion 1010a, 1010b may include a more conventional substrate material. For example, one of the base substrate portions 1010a, 1010b may include lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), while the other base substrate portion 1010a, 1010b may include silicon (Si), quartz, fused silica glass, sapphire, or glass. In other embodiments, one of the base substrate portions 1010a and 1010b comprises a III-V single semiconductor material such as gallium arsenide (GaAs) or gallium nitride (GaN), and the other of the base substrate portions 1010a and 1010b may comprise a non-III-V semiconductor material such as silicon (Si), or other materials having a similar CTE, such as quartz, fused silica glass, sapphire, or glass. In yet another embodiment, one of the base substrate portions 1010a and 1010b comprises a semiconductor material, and the other of the base substrate portions 1010a and 1010b comprises a packaging material such as a glass, organic, or ceramic substrate.

[0091] In some configurations, the first element 1002 may include isolated elements, such as isolated integrated device dies. In other configurations, the first element 1002 may comprise a carrier or substrate (e.g., a semiconductor wafer) containing multiple (e.g., tens, hundreds, or more) device regions that, when isolated, constitute multiple integrated device dies. In other embodiments, such a carrier can be a package substrate or a passive or active interposer. Similarly, the second element 1004 may include isolated elements, such as isolated integrated device dies. In other configurations, the second element 1004 may comprise a carrier or substrate (e.g., a semiconductor wafer). Accordingly, the embodiments disclosed herein are applicable to wafer-to-wafer (W2W), die-to-die (D2D), or die-to-wafer (D2W) bonding processes. In a W2W process, two or more wafers may be directly bonded to each other (e.g., direct hybrid bonding) and separated by a suitable separation process. After separation, the side edges of the separated structures (e.g., the side edges of two joined elements) can be made substantially coplanar (substantially aligned x and y dimensions), and / or the edges of the joint interface of elements that have been both joined and separated can be extended, and the edges may include markings indicating a common separation process for the joint structures (e.g., cutting markings if a cutting process is used).

[0092] Although only two elements 1002 and 1004 are shown above, any number of elements can be stacked in the junction structure 1000. For example, a third element (not shown) can be stacked on the second element 1004, a fourth element (not shown) can be stacked on the third element, and so on. In such embodiments, electrical communication between the vertically stacked elements can be provided by forming through-substrate vias (TSVs). As an addition or alternative, one or more additional elements (not shown) can be stacked along the first element 1002, laterally adjacent to one another. In some embodiments, the laterally stacked additional elements may be smaller than the second element. In some embodiments, the junction structure can be sealed with an insulating material such as an inorganic dielectric (e.g., silicon oxide, silicon nitride, silicon carbonitride). Alternatively, one or more insulating layers can be provided on the junction structure. For example, in some embodiments, a first insulating layer may be conformally deposited on a joint structure, and a second insulating layer (which may contain the same material as the first insulating layer or a different material) may be provided on the first insulating layer.

[0093] To create a direct bond between bonding layers 1008a and 1008b, bonding layers 1008a and 1008b can be prepared for direct bonding. For example, the non-conductive bonding surfaces 1012a and 1012b on the top or outer surfaces of bonding layers 1008a and 1008b can be prepared for direct bonding by chemical mechanical polishing (CMP). The roughness of the polished bonding surfaces 1012a and 1012b can be less than 30 Årms. For example, the roughness of the bonding surfaces 1012a and 1012b can be in the range of approximately 0.1 Årms to 15 Årms, 0.5 Årms to 10 Årms, or 1 Årms to 5 Årms. The polishing can also be adjusted to leave recessed conductive features 1006a and 1006b relative to the field region of bonding layers 1008a and 1008b.

[0094] Furthermore, preparation for direct bonding may include cleaning one or both of the bonding surfaces 1012a and 1012b and exposing them to plasma and / or etchant to activate at least one of the surfaces 1012a and 1012b. In some embodiments, one or both of the surfaces 1012a and 1012b may be terminated with chemical species after or during activation (e.g., during the plasma and / or etching process). Without theoretical limitations, in some embodiments, the activation process may break the chemical bonds at the bonding surfaces 1012a and 1012b, and the termination process may provide additional chemical species to the bonding surfaces 1012a and 1012b that result in changes to the chemical bonds and / or improvements in the bond energy in direct bonding. In some embodiments, activation and termination occur in the same step (e.g., the plasma that activates and terminates the surfaces 1012a and 1012b). In other embodiments, additional chemical species for direct bonding can be provided by the termination of one or both of the bonding surfaces 1012a, 1012b in a separate treatment. In various embodiments, the termination species may include nitrogen. For example, in some embodiments, the bonding surfaces 1012a, 1012b may be exposed to a nitrogen-containing plasma. Depending on the material of the bonding surfaces 1012a, 1012b, other termination species may be suitable for improving the bonding energy. Furthermore, in some embodiments, the bonding surfaces 1012a, 1012b may be exposed to fluorine. For example, one or more fluorine concentration peaks may be present at or near the bonding interface 1018 between the first and second elements 1002, 1004. Typically, fluorine concentration peaks occur at the interface between material layers.For additional examples of activation and / or termination processes, see U.S. Patent No. 9,391,143, lines 55-3 of column 5 to 3 of column 7, line 52 of column 8 to 45 of column 9, lines 24-36 of column 10, lines 24-32 of column 11, lines 42-47, lines 52-55, and lines 60-64 of column 11, lines 3-14 of column 12, lines 31-33, and lines 55-67. The teachings relating to activation and termination found in columns 14, lines 38-40 and 44-50, and in U.S. Patent No. 10,434,749, columns 4, lines 41-50, columns 5, lines 7-22, 39, 55-61, columns 8, lines 25-31, 35-40, and 49-56, and columns 12, lines 46-61, are incorporated herein by reference.

[0095] Thus, in the direct bonding structure 1000, the bonding interface 1018 between the two nonconductive materials (e.g., bonding layers 1008a, 1008b) may constitute a very smooth interface, but at this bonding interface 1018, the nitrogen (or other terminal chemical species) content and / or fluorine concentration peaks are higher. In some embodiments, the nitrogen and / or fluorine concentration peaks may be detected using various types of inspection techniques, such as SIMS technology. The polished bonding surfaces 1012a and 1012b may become slightly rough after the activation process (e.g., about 1 Årms to 30 Årms, 3 Årms to 20 Årms, or possibly rougher). In some embodiments, activation and / or termination may cause the surface to become slightly smooth prior to bonding, such as when plasma treatment preferentially corrodes higher points on the bonding surface.

[0096] The nonconductive bonding layers 1008a and 1008b can be directly bonded to each other without adhesive. In some embodiments, elements 1002 and 1004 are integrated at room temperature without the need for voltage application and without the need for external pressure or force application beyond what is used to initiate contact between the two elements 1002 and 1004. Direct bonding between the nonconductive surfaces of bonding layers 1008a and 1008b can be achieved by contact alone (e.g., dielectric covalent bonding). By subsequent annealing of the bonding structure 1000, conductive features 1006a and 1006b can be directly bonded.

[0097] In some embodiments, prior to direct bonding, the conductive features 1006a and 1006b are recessed relative to the surrounding field region such that the total gap between opposing contacts after dielectric bonding and before annealing is less than 15 nm or less than 10 nm. Since the recess depth of the conductive features 1006a and 1006b may vary across each element due to process variations, the gap may represent the maximum or average gap between the corresponding conductive features 1006a and 1006b of the two bonded elements (before annealing). During annealing, the conductive features 1006a and 1006b may expand and come into contact with each other, thereby forming a direct metal-to-metal bond.

[0098] During annealing, the conductive features 1006a and 1006b (e.g., metallic material) may expand, while the direct bonding between the non-conductive materials surrounding the bonding layers 1008a and 1008b resists separation of the elements. As a result, thermal expansion increases the internal contact pressure between the opposing conductive features. Furthermore, annealing causes metal grain growth across the bonding interface, so particles from one element migrate across the bonding interface to the other element, at least partially, and vice versa. Therefore, in some embodiments of hybrid bonding, the opposing conductive materials are joined without heating above the melting temperature of the conductive material, allowing the bond to be formed at a lower annealing temperature than soldering or thermocompression bonding.

[0099] In various embodiments, the conductive features 1006a, 1006b may include discrete pads, contacts, electrodes, or traces that are at least partially embedded in the non-conductive field regions of the bonding layers 1008a, 1008b. In some embodiments, the conductive features 1006a, 1006b may include exposed contact surfaces of TSVs (e.g., through-silicon vias).

[0100] As described above, in some embodiments, in elements 1002 and 1004 of Figure 1A before direct bonding, portions of each conductive feature 1006a and 1006b may be recessed below the nonconductive bonding surfaces 1012a and 1012b by, for example, less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm (for example, in the range of 2 nm to 20 nm or 4 nm to 10 nm). Due to process variations, both the dielectric thickness and the recess depth of the conductor may vary across the entire element. Therefore, the above range of recess depth may apply to the average depth of the recess for individual conductive features 1006a and 1006b or local nonconductive field regions. For individual conductive features 1006a and 1006b, the vertical recess may also vary across the entire feature, and can therefore be measured at the lateral center or near the center of the cavity in which a given conductive feature 1006a or 1006b is formed, or on the side of the cavity.

[0101] Beneficially, the use of hybrid bonding technologies (such as DBI (Direct Bond Interconnect)® technology, commercially available from Adeia in San Jose, California) can enable high-density (e.g., small-pitch or fine-pitch in the case of a regular array) connections between conductive features 1006a, 1006b across the direct bonding interface 1018.

[0102] In some embodiments, the pitch p of conductive features 1006a, 1006b, such as conductive traces embedded in one bonding surface of a bonding element, may be less than 40 μm, less than 20 μm, less than 10 μm, less than 5 μm, less than 2 μm, or even less than 1 μm. In some applications, the ratio of the pitch of conductive features 1006a and 1006b to one of the lateral dimensions of the bonding pad (e.g., diameter) may be less than 20, less than 10, less than 5, or less than 3, and may be less than 2. In various embodiments, the conductive features 1006a and 1006b and / or traces may include copper or copper alloys, but other metals such as nickel, aluminum, or alloys thereof may also be preferred. Conductive features disclosed herein, such as conductive features 1006a and 1006b, may include fine-grained metals (e.g., fine-grained copper). Furthermore, the main lateral dimensions (e.g., pad diameter) can also be reduced to a range such as approximately 0.25 μm to 30 μm, approximately 0.25 μm to 5 μm, or approximately 0.5 μm to 5 μm.

[0103] In the case of hybrid junction elements 1002, 1004, as shown in the figure, the orientation of one or more conductive features 1006a, 1006b of opposing elements can be opposite to each other. As is known in the art, conductive features can generally be formed near vertical sidewalls, in particular in this case the conductive sidewall is defined directly by etching of the conductive material by directional reactive ion etching (RIE) or indirectly by etching of the surrounding insulator in a damascene process. However, a slight taper may exist in the conductive sidewall, and the conductor narrows as it moves away from the first etched surface. The taper may be more pronounced if the conductive sidewall is defined directly or indirectly by isotropic wet etching or dry etching. In the illustrated embodiment, at least one conductive feature 1006b (and / or at least one internal conductive feature such as a BEOL feature) in the junction layer 1008b of the upper element 1004 may taper upward toward the junction surface 1012b. In contrast, at least one conductive feature 1006a (and / or at least one internal conductive feature such as a BEOL feature) in the bonding layer 1008a of the lower element 1002 may be tapered downwards toward the bonding surface 1012a. Similarly, any bonding layer (not shown) on the back surfaces 1016a and 1016b of elements 1002 and 1004 may be tapered toward the back surface toward the same element, with a tapered orientation opposite to that of the surface conductive features 1006a and 1006b.

[0104] As described above, during the annealing stage of the hybrid bond, the conductive features 1006a and 1006b may expand and come into contact with each other, thereby forming a direct intermetallic bond. In some embodiments, the materials of the conductive features 1006a and 1006b of the opposing elements 1002 and 1004 may interdiffuse during the annealing process. In some embodiments, metal particles grow toward each other across the bonding interface 1018. In some embodiments, the metal is copper or contains copper, which can improve copper diffusion across the bonding interface 1018 by having particles oriented along the 111 crystal plane. In some embodiments, the conductive features 1006a and 1006b may include a nanotwin copper particle structure that can assist in the fusion of the conductive features during annealing. In or near the bonded conductive features 1006a and 1006b, there is no substantial gap between the non-conductive bonding layers 1008a and 1008b. In some embodiments, a barrier layer may be provided to surround the underside and / or sides of the conductive features 1006a and 1006b (for example, it may contain copper). However, in other embodiments, a barrier layer may not be present on the underside of the conductive features 1006a and 1006b.

[0105] Additional embodiments In the above specification, systems and processes have been described with reference to specific embodiments. However, it will be apparent that various improvements and modifications are possible without departing from the broader idea and scope of the embodiments disclosed herein. Accordingly, this specification and the drawings should be taken as illustrative rather than restrictive.

[0106] In practice, while the systems and processes have been disclosed in the context of specific embodiments and examples, those skilled in the art will understand that various embodiments of the systems and processes extend beyond the specifically disclosed embodiments to other alternative embodiments and / or uses relating to the systems and processes and their respective obvious improvements and equivalents. Furthermore, while several variations of the embodiments of the systems and processes have been illustrated and described in detail, those skilled in the art will readily recognize, based on this disclosure, other improvements included in the scope of this disclosure. Various combinations or partial combinations of specific features and embodiments of the embodiments are also conceivable and are still included in the scope of this disclosure. It will also be understood that various combinations or substitutions of different features and embodiments of the disclosed embodiments can constitute diverse forms of the disclosed systems and processes. No method disclosed herein needs to be performed in the order listed. Thus, the scope of the systems and processes disclosed herein is not intended to be limited by the specific embodiments described above.

[0107] Naturally, each of the systems and methods disclosed herein has multiple innovative embodiments, but none of them alone can or do not represent the desired attributes disclosed herein. The various features and processes described above may be used independently of each other or in various combinations. All conceivable combinations and partial combinations are intended to be included within the scope of this disclosure.

[0108] Furthermore, certain features described herein may be realized in combination in a single embodiment within the context of a separate embodiment. Conversely, various features described herein may be realized separately in multiple embodiments within the context of a single embodiment, or in any preferred partial combination. Moreover, features may be described above as acting in a particular combination and claimed from the outset in this manner, although one or more features of the claimed combination may be excluded from the combination, and the claimed combination may cover a partial combination or a variation thereof. No single feature or set of features is required or essential in every embodiment.

[0109] Furthermore, naturally, conditional expressions used herein, particularly "can, could," "might, may," and "for example," are generally intended to convey that certain embodiments include certain features, elements, and / or steps, while other embodiments do not, unless otherwise specified or understood within the context of use. Therefore, such conditional expressions are not generally intended to imply that features, elements, and / or steps are required in some way in one or more embodiments, or that one or more embodiments necessarily include logic for determining whether these features, elements, and / or steps should be included or performed in any particular embodiment, with or without input or instruction from the author. The terms "comprising," "including," and "having" are synonyms and are used comprehensively in an open-ended manner, without excluding additional elements, features, functions, actions, etc. Furthermore, the term "or" is used in an inclusive (not exclusive) sense, for example, when used to connect a list of elements, to mean one, some, or all of the elements in the list. Also, as used in this application and the appended claims, the articles "a," "an," and "the" are interpreted as meaning "one or more" or "at least one" unless otherwise specified. Similarly, while drawings may show operations in a specific order, it should be recognized that such operations do not need to be performed in a specific order shown, nor in a sequential order, nor do they need to be performed in all shown operations for a desired result. In addition, drawings may schematically illustrate one or more exemplary processes in the form of flowcharts. However, the schematicly shown exemplary methods and processes may incorporate other operations that are not illustrated. For example, one or more additional operations may be performed before, during, or between any of the illustrated operations. In other embodiments, these operations may be rearranged or reordered.Other embodiments are also included in the following claims. In some cases, the operations enumerated in the claims may be performed in a different order, and the desired results can still be achieved.

[0110] Furthermore, the methods and devices described herein are likely to be susceptible to various improvements and alternative forms, specific examples of which are shown in the drawings and described in detail herein. However, it should be understood that embodiments are not limited to any particular form or method of disclosure, but rather should encompass the ideas and scope of the various embodiments described and all improvements, equivalents, and alternatives included in the appended claims. Furthermore, any specific features, aspects, methods, characteristics, properties, qualities, attributes, elements, etc., disclosed herein relating to one embodiment or embodiment may be used in all other embodiments or embodiments described herein. No method disclosed herein does not need to be performed in the order listed. A method disclosed herein may include specific actions by the practitioner, and may also include any third-party instructions regarding such actions, either explicitly or implicitly. The scope of disclosure herein also includes all overlaps, sub-scopes, and combinations thereof. Expressions such as "up to," "at least," "greater than," "less than," and "between" include the listed numbers. Numbers preceded by terms such as "about" or "approximately" include the listed numbers and should be interpreted in context (for example, as reasonably accurate as possible under those circumstances (e.g., ±5%, ±10%, ±15%)). For example, "about 3.5 mm" includes "3.5 mm". Expressions preceded by terms such as "substantially" include the listed expressions and should be interpreted in context (for example, as reasonably accurate as possible under those circumstances). For example, "substantially constant" includes "constant". Unless otherwise stated, all measurement results are under standard conditions, including temperature and pressure.

[0111] In use herein, the expression “at least one” in a list of items refers to any combination of these items (including a single component). For example, “at least one of A, B, or C” is intended to encompass “A,” “B,” “C,” “A and B,” “A and C,” “B and C,” and “A, B, and C.” Conjunctions such as “at least one of X, Y, and Z” are understood, unless otherwise specified, to be used in the context of general usage to indicate that an item, term, etc., may be at least one of X, Y, or Z. Thus, such conjunctions are generally not intended to imply that a particular embodiment requires at least one of X, at least one of Y, and at least one of Z for its existence. Where there are headings herein, they are for convenience only and do not necessarily affect the scope or meaning of the devices and methods disclosed herein.

[0112] Therefore, the claims are not limited to the embodiments described herein, but rather are given the broadest scope consistent with the disclosures, principles, and novel features described herein.

Claims

1. It is a structure, It is an active element, The front surface and the back surface opposite to the front surface, Multiple vias extending vertically from the back surface through a portion of the active element, An active region closer to the surface than the back surface, The active element comprises, This is a power redistribution element disposed on the back surface of the active element, The front surface and the back surface opposite to the front surface, A plurality of first contact pads arranged on the surface, The second set of contact pads arranged on the back surface, The power redistribution element comprises the first plurality of contact pads having a pitch smaller than the pitch of the second plurality of contact pads, Equipped with, A structure in which the first plurality of contact pads are electrically coupled to the plurality of vias.

2. The structure according to claim 1, further comprising a power supply die having a surface and a back surface opposite to the surface, wherein the surface is in electrical contact with the second plurality of contact pads of the power redistribution element.

3. The structure according to claim 1, wherein the power redistribution element is configured to transmit power and ground, and is not configured to transmit logic signals.

4. The power redistribution element comprises an interposer, as described in claim 1.

5. The structure according to claim 4, wherein the power redistribution element further comprises a hybrid junction layer disposed on the surface of the power redistribution element.

6. The structure according to claim 4, wherein the power redistribution element further comprises a hybrid junction layer disposed on the back surface of the power redistribution element.

7. The structure according to claim 1, wherein at least a portion of the power redistribution element is deposited on the back surface of the active element.

8. The structure according to claim 7, wherein at least a portion of the power redistribution element is deposited on the back surface of the active element after the active element has been thinned.

9. The structure according to claim 7, wherein the surface of the power supply die is hybrid-bonded to the back surface of the power redistribution element.

10. The structure according to claim 2, wherein the surface of the power supply die is hybrid-bonded to the back surface of the power redistribution element, and the surface of the power redistribution element is hybrid-bonded to the back surface of the active element.

11. The structure according to claim 2, further comprising a passive element disposed between the power supply die and the power redistribution element.

12. The structure according to claim 1, wherein power is supplied to the back surface of the active element through the power redistribution element.

13. It is a structure, An active element having a front surface and a back surface opposite to the front surface, wherein the active element has an active circuit closer to the front surface than to the back surface, A power redistribution element having a surface hybridized and bonded to the back surface of the active element, wherein the power redistribution element comprises a first plurality of contact pads on the surface of the power redistribution element and a second plurality of contact pads on the back surface of the power redistribution element opposite to the surface of the power redistribution element, Equipped with, The pitch of the first plurality of contact pads is smaller than the pitch of the second plurality of contact pads. A structure wherein the power redistribution element is configured to supply at least one of power and ground to the active element.

14. The structure according to claim 13, wherein the active element comprises vias extending from the back surface of the active element to the active circuit.

15. The power supply die further comprises a front surface and a back surface opposite to the front surface, The structure according to claim 13, wherein the surface of the power supply die is hybrid-bonded to the back surface of the power redistribution element.

16. The structure according to claim 13, wherein at least one of power and ground is transmitted through the power redistribution element and supplied to the back surface of the active element.

17. It is an interposer, The front side and, The opposite side of the table, The redistribution layer, A plurality of first contact pads arranged on the front surface of the interposer, A second set of contact pads arranged on the back surface of the interposer, Equipped with, The first pitch of the first plurality of contact pads is smaller than the second pitch of the second plurality of contact pads. The first plurality of contact pads are configured to be electrically connected to vias on the back surface of the active element. The second plurality of contact pads are configured to be electrically connected to the contact pads on the power supply die. An interposer having a hybrid bonding layer on at least one of the front surface and the back surface.

18. The first pitch is approximately 50 nm to approximately 1000 nm. The interposer according to claim 17, wherein the second pitch is approximately 1 μm to approximately 500 μm.

19. The interposer according to claim 17, wherein the interposer has a thickness of about 1 μm to about 50 μm.

20. The interposer according to claim 17, wherein the second plurality of contact pads are arranged in a periodic pattern.

21. The interposer according to claim 17, wherein the surface of the table above comprises a hybrid bonding layer.

22. The interposer according to claim 17, wherein the aforementioned back surface comprises a hybrid bonding layer.

23. The interposer according to claim 17, comprising a plurality of layers, each layer configured to transmit a single voltage or ground, and each layer being isolated from the other layers by a dielectric material.

24. The interposer according to claim 17, wherein the interposer is configured to transport power from the power supply die on the back surface of the interposer to the front surface of the interposer which is electrically connected to the via on the back surface of the active element.

25. To form a first interposer, wherein the first interposer is The first surface and The first back surface opposite to the first front surface, A first surface contact disposed on the first surface, wherein the first surface contact is arranged in a first surface arrangement and is configured to be electrically connected to a via on the back surface of the first active element, A first back surface contact disposed on the first back surface, wherein the first back surface contact is arranged in a first back surface pattern and is configured to be electrically connected to the first power supply die, To form the first interposer comprising, To form a second interposer, wherein the second interposer is The second surface and The second back surface opposite to the second front surface, A second surface contact disposed on the second surface, wherein the second surface contact is arranged in a second surface arrangement and is configured to be electrically connected to a via on the back surface of the second active element, A second back surface contact disposed on the second back surface, wherein the second back surface contact is arranged in a second back surface pattern and is configured to be electrically connected to a second power supply die, To form the aforementioned second interposer, Includes, The first surface arrangement differs from the second surface arrangement, A method wherein the first back surface pattern is the same as the second back surface pattern.

26. The method according to claim 25, wherein the first interposer further comprises a first surface hybrid bonding surface disposed on the first surface.

27. The method according to claim 25, wherein the first interposer further comprises a first back surface hybrid bonding surface disposed on the first back surface.

28. The method according to claim 25, wherein the pitch of the first back surface pattern and the second back surface pattern is greater than the pitch of the first surface arrangement and the pitch of the second surface arrangement.

29. The pitch of the first surface arrangement is approximately 100 nm to approximately 500 nm. The pitch of the second surface arrangement is approximately 100 nm to approximately 500 nm. The method according to claim 28, wherein the pitch of the first back surface pattern and the second back surface pattern is approximately 20 μm to approximately 500 μm.

30. The method according to claim 25, wherein the first interposer is configured to supply first power from the first power supply die to the first back surface of the first active element, and the second interposer is configured to supply second power from the second power supply die to the second back surface of the second active element.

31. To form a first interposer, wherein the first interposer is The first surface and The first back surface opposite to the first front surface, A first surface contact disposed on the first surface, wherein the first surface contact is arranged in a first surface arrangement and is configured to be electrically connected to a via on the back surface of the first active element, A first back surface contact disposed on the first back surface, wherein the first back surface contact is arranged in a first back surface pattern and is configured to be electrically connected to the first power supply die, A method comprising forming the first interposer comprising the following:

32. The method according to claim 31, wherein the first interposer further comprises a first surface hybrid bonding surface disposed on the first surface.

33. The method according to claim 31, wherein the first interposer further comprises a first back surface hybrid bonding surface disposed on the first back surface.

34. The method according to claim 31, wherein the first interposer is configured to supply first power from the first power supply die to the first back surface of the first active element.

35. To form a second interposer, wherein the second interposer is The second surface and The second back surface opposite to the second front surface, A second surface contact disposed on the second surface, wherein the second surface contact is arranged in a second surface arrangement and is configured to be electrically connected to a via on the back surface of the second active element, A second back surface contact disposed on the second back surface, wherein the second back surface contact is arranged in a second back surface pattern and is configured to be electrically connected to a second power supply die, The method according to claim 31, further comprising forming the second interposer comprising the above.

36. The method according to claim 35, wherein the first surface arrangement is different from the second surface arrangement.

37. The method according to claim 36, wherein the first back surface pattern is the same as the second back surface pattern.

38. The method according to claim 35, wherein the pitch of the first back surface pattern and the second back surface pattern is greater than the pitch of the first surface arrangement and the pitch of the second surface arrangement.

39. The pitch of the first surface arrangement is approximately 100 nm to approximately 500 nm. The pitch of the second surface arrangement is approximately 100 nm to approximately 500 nm. The method according to claim 38, wherein the pitch of the first back surface pattern and the second back surface pattern is about 20 μm to about 500 μm.

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