Multiple threshold voltage integration scheme for complementary field-effect transistors

Abstract

Methods for manufacturing electronic devices are described. Embodiments of this disclosure are advantageous in that they reduce thickness, reduce leakage, reduce heat balance, and (multi-V t (including) V t The present invention provides a method for manufacturing electronic devices, such as complementary field-effect transistors (CFETs), that meet requirements and offer improved device performance and reliability. Some embodiments of the method include conventional dipole engineering techniques, such as a first dipole process and / or a final dipole process, which do not require the repair of the interface layer after processing (in the first dipole process) or the repair of the high dielectric constant dielectric layer after the annealing process (in the final dipole process).

Description

[Technical Field]

[0001]

[0001] Embodiments of the present disclosure relate to the field of electronic device manufacturing, and more particularly to transistors. More specifically, embodiments of the present disclosure relate to complementary field-effect transistors (CFETs) and methods for manufacturing CFETs. [Background technology]

[0002]

[0002] Integrated circuits have evolved into complex devices that can house millions of transistors, capacitors, and resistors on a single chip. In the course of integrated circuit evolution, the functional density (i.e., the number of interconnected devices per chip area) has increased overall, while the shape dimensions (i.e., the smallest component (or line) that can be manufactured using the manufacturing process) have decreased.

[0003]

[0003] A transistor is a circuit component or circuit element that is often formed on a semiconductor device. Depending on the circuit design, many transistors can be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements. Integrated circuits incorporate a planar field-effect transistor (FET) through which current flows in response to a voltage applied to a control gate, through a semiconductor channel between the source and drain.

[0004]

[0004] Since the drive current of a transistor, and therefore its speed, is proportional to the gate width of the transistor, faster transistors generally require larger gate widths. Therefore, there is a trade-off between transistor size and speed, and "fin" field-effect transistors (finFETs) have been developed to address the conflicting goals of maximum drive current and minimum size. FinFETs feature a fin-shaped channel region that allows for a significant increase in transistor size without significantly increasing the transistor's mounting area, and are now applied to many integrated circuits. However, FinFETs also have drawbacks.

[0005]

[0005] In order to improve circuit density and performance, the characteristic size of transistor devices continues to shrink, and improvements in transistor device structure are needed to improve electrostatic coupling and reduce adverse effects such as parasitic capacitance and leakage current in the off state. Examples of transistor device structures include planar structures, FinFET structures, and gate-all-around (GAA) structures. GAA device structures include multiple lattice-matched channels suspended in a stacked configuration and connected by source / drain regions. GAA structures provide good electrostatic control and can be widely used in complementary metal-oxide-semiconductor (CMOS) wafer manufacturing.

[0006]

[0006] An example of GAA technology is a complementary field-effect transistor (CFET), in which "N-type metal-oxide-semiconductor (NMOS) FETs" and "P-type metal-oxide-semiconductor (PMOS) FETs" are stacked vertically on top of each other. Compared to GAA transistors, CFETs increase on-chip device density and reduce area consumption. When NMOS FETs and PMOS FETs are monolithically stacked, n and p superlattices (e.g., NMOS FETs or PMOS FETs, respectively) are continuously deposited with intermediate dielectric insulating (MDI) layers and intermediate sacrificial layers that are selectively removed and replaced during processing. The MDI layers serve to electrically isolate the lower level GAA from the upper level GAA.

[0007]

[0007] Each n or p superlattice of the CFET includes alternating layers of channel layers and release layers. The channel layers typically contain silicon (Si). The release layers typically contain silicon germanium (SiGe) with a low concentration of germanium (Ge). For etching contrast between the intermediate sacrificial layer and the channel layer, the intermediate sacrificial layer contains SiGe with a high concentration of Ge.

[0008]

[0008] Currently, the reduction of materials used as NMOS FETs and PMOS FETs is due to the threshold voltage (V t Changes in fundamental characteristics such as these have become a challenge.t The tuning range is limited by the variation in the thickness of the film, and the device size is further reduced.

[0009]

[0009] There are also issues related to conventional dipole engineering techniques. To achieve the desired dipole effect, the desired element is driven from a film deposited using spike annealing and removed after the driving in. Spike annealing can cause a penalty in the equivalent oxide thickness (EOT) and a high thermal budget because free oxygen atoms in the gate dielectric layer and the overlapping dipole stack diffuse downward to oxidize the underlying silicon layer.

[0010]

[0010] In addition, to achieve the desired threshold voltage V t (or multiple threshold voltages (multi-V t )), precise control of the amount of dipole species is extremely important. Conventional dipole engineering techniques include "dipole first" processes and "dipole last" processes. Typically, the first process of the dipole is to deposit metal atoms on the interface layer (to form a processed interface layer) to achieve the desired dipole effect, and then flow metal-containing precursors and reactants to deposit a high-k dielectric layer on the processed interface layer. The first process of the conventional dipole also includes repairing the interface layer after processing.

[0011]

[0011] The final process of the dipole typically involves forming an interface layer on a substrate, forming a high-k dielectric layer on the interface layer, flowing a metal-containing precursor and reactants over the high-k dielectric layer to deposit metal atoms thereon, and annealing the substrate to drive metal atoms into the interface between the interface layer and the high-k dielectric layer to achieve the desired dipole effect. In the final process of the dipole, instead of forming an ultrathin surface adsorption layer, an atomic layer deposition (ALD) process is performed, and a dipole layer containing metal atoms with a thickness ranging from 3 Å to 20 Å and typically in the form of an oxide or nitride is deposited. A capping material is typically required on top of the diode oxide / nitride layer to avoid regrowth of silicon oxide during the annealing process. The conventional final process of the dipole also includes repairing the high-k dielectric layer after the annealing process.

[0012]

[0012] In the conventional final process of the dipole, multiple annealing steps are required to reach an increased V t For example, the V t achieved by the first process of the conventional dipole is required. Also, particularly in the first process of the dipole, there are issues related to V t shift and leakage. Due to the increased on-chip device density and reduced area consumption of CFETs, it is even more difficult to adjust V t in CFETs compared to GAA transistors.

[0013]

[0013] Therefore, there is a need for an improved method of manufacturing CFETs that meets the requirements of thickness reduction, leakage reduction, heat budget reduction, and V t (including multi-V t ) and has a minimum EOT penalty.

Summary of the Invention

[0014]

[0014] One or more embodiments of the present disclosure relate to a method for forming a complementary field-effect transistor (CFET). The method involves depositing interface layers on a vertically stacked superlattice structure on a substrate, the substrate comprising a first portion, a second portion, and a third portion. The vertically stacked superlattice structure comprises a first horizontal gate-all-around (hGAA) structure on the upper surface of the substrate, an intermediate dielectric insulating layer on the upper surface of the first hGAA structure, and a second hGAA structure on the upper surface of the intermediate dielectric insulating layer. The interface layers are formed on the first hGAA structure, on the intermediate dielectric insulating layer, and on the second hGAA structure. Next, the method includes depositing a high dielectric constant dielectric layer on an interface layer, depositing a first p-type dipole layer on the high dielectric constant dielectric layer, depositing a first p-type capping layer on the first p-type dipole layer, depositing a first protective layer on a first portion of the substrate, and etching the vertical stacked superlattice structure to remove the first protective layer, a portion of the first p-type capping layer, and a portion of the first p-type dipole layer from a second portion of the substrate. The first portion has a first threshold voltage (V t ) has, and the second part is the second V tThe method comprises: etching a vertical stacked superlattice structure to remove a first protective layer, a portion of the first p-type capping layer, and a portion of the first p-type dipole layer from a second portion of the substrate; depositing a second p-type dipole layer on a first portion, a second portion, and a third portion of the substrate, wherein the second p-type dipole layer is formed on a first hGAA structure, an intermediate dielectric insulating layer, and a second hGAA structure; and depositing a second p-type capping layer on the second p-type dipole layer, wherein the second p-type capping layer is formed vertically stacked The process involves depositing a second p-type capping layer to fill trenches within a layered superlattice structure, etching the vertical stacked superlattice structure to remove a portion of the first p-type capping layer, a portion of the first p-type dipole layer, a portion of the second p-type capping layer, and a portion of the second p-type dipole layer to expose a high-dielectric-constant dielectric layer on a second hGAA structure, depositing a first n-type dipole layer on the exposed high-dielectric-constant dielectric layer on the second hGAA structure, depositing a first n-type capping layer on the first n-type dipole layer, and depositing a second retaining layer on a first portion of the substrate. The method involves depositing a protective layer, etching the vertical stacked superlattice structure to remove the second protective layer, exposing the first portion of the first n-type capping layer, removing a portion of the first n-type capping layer and a portion of the first n-type dipole layer from the second and third portions of the substrate, and depositing a second n-type dipole layer on the first, second, and third portions of the substrate, wherein the second n-type dipole layer is formed on the second hGAA structure, and depositing a second n-type capping layer on the second n-type dipole layer. This involves depositing a second n-type capping layer that fills trenches within a vertically stacked superlattice structure, etching the vertically stacked superlattice structure to remove a portion of the second n-type capping layer and a portion of the second n-type dipole layer from the first, second, and third portions of the substrate, depositing a third protective layer on the first and second portions of the substrate, etching the vertically stacked superlattice structure to remove the third protective layer, a portion of the first n-type capping layer, and a portion of the first n-type dipole layer from the second portion of the substrate,The method includes exposing the high-dielectric-constant dielectric layer on each of the first and second hGAA structures, annealing the substrate at a temperature of 1000°C or less to drive atoms from each of the first p-type dipole layer, the second p-type dipole layer, the first n-type dipole layer, and the second n-type dipole layer into the high-dielectric-constant dielectric layer to form an annealed high-dielectric-constant dielectric layer, and etching the vertical stacked superlattice structure to remove each of the first p-type dipole layer, the first p-type capping layer, the second p-type dipole layer, the second p-type capping layer, the first n-type dipole layer, the first n-type capping layer, the second n-type dipole layer, and the second p-type capping layer.

[0015]

[0015] To enable a detailed understanding of the features of the Disclosure listed above, a more detailed description of the Disclosure, which has been briefly summarized above, can be obtained by referring to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only typical embodiments of the Disclosure, as the Disclosure may also allow for other equally effective embodiments, and therefore should not be considered to limit the scope of the Disclosure. Embodiments described herein are illustrated in the accompanying drawings as examples, not limitations, and similar reference numerals in the drawings indicate similar elements. [Brief explanation of the drawing]

[0016] [Figure 1A] The following are process flow diagrams illustrating methods for manufacturing complementary field-effect transistors (CFETs) according to one or more embodiments. [Figure 1B] A schematic cross-sectional view is shown of a vertically stacked superlattice structure on a substrate having a first part, a second part, and a third part, according to one or more embodiments. [Figure 2A] The images show two-directional cross-sectional views of a vertically stacked superlattice structure on a substrate, showing a first cross-sectional view through the gate (across the fins) and a second cross-sectional view through the fins (across the gates), according to one or more embodiments. [Figure 2B]Figure 2A shows bidirectional cross-sectional views of the substrate after the deposition of an interface layer on a vertically stacked superlattice structure and the deposition of a high dielectric constant layer on the interface layer, according to one or more embodiments. [Figure 2C] Figure 2B shows a bidirectional cross-sectional view of the substrate after a first p-type dipole layer has been deposited on a high dielectric constant dielectric layer according to one or more embodiments. [Figure 2D] Figure 2C shows a bidirectional cross-sectional view of the substrate after a first p-type capping layer has been deposited on a first p-type dipole layer according to one or more embodiments. [Figure 2E] Figure 2D shows a bidirectional cross-sectional view of the substrate after a first protective layer has been deposited on a first portion of the substrate, according to one or more embodiments. [Figure 2F] Figure 2E shows bidirectional cross-sectional views of the substrate after etching the vertical stacked superlattice structure to remove the first protective layer from a first portion of the substrate, according to one or more embodiments. [Figure 2G] Figure 2F shows bidirectional cross-sectional views of the substrate after a second p-type dipole layer has been deposited on a first portion, a second portion, and a third portion of the substrate according to one or more embodiments. [Figure 2H] Figure 2G shows a bidirectional cross-sectional view of the substrate after a second p-type capping layer, which fills trenches in a vertically stacked superlattice structure, has been deposited on a second p-type dipole layer according to one or more embodiments. [Figure 2I] Figure 2H shows a bidirectional cross-sectional view of the substrate after etching the vertical stacked superlattice structure to remove a portion of the first p-type capping layer, a portion of the first p-type dipole layer, a portion of the second p-type capping layer, and a portion of the second p-type dipole layer in order to expose a high dielectric constant dielectric layer according to one or more embodiments. [Figure 2J] Figure 2I shows a bidirectional cross-sectional view of the semiconductor substrate after a first n-type dipole layer has been deposited on an exposed high-dielectric-constant dielectric layer, according to one or more embodiments. [Figure 2K] Figure 2J shows a bidirectional cross-sectional view of the semiconductor substrate after a first n-type capping layer has been deposited on a first n-type dipole layer according to one or more embodiments. [Figure 2L] Figure 2K shows a bidirectional cross-sectional view of the semiconductor substrate after a second protective layer has been deposited on a first portion of the substrate, according to one or more embodiments. [Figure 2M] Figure 2L shows a two-directional cross-sectional view of a semiconductor substrate after etching a vertical stacked superlattice structure according to one or more embodiments, removing the second protective layer to expose the first portion of the first n-type capping layer, and removing a portion of the first n-type capping layer and a portion of the first n-type dipole layer from the second and third portions of the substrate. [Figure 2N] Figure 2M shows bidirectional cross-sectional views of the semiconductor substrate after a second n-type dipole layer has been deposited on a first portion, a second portion, and a third portion of the substrate according to one or more embodiments. [Figure 2O] Figure 2N shows a bidirectional cross-sectional view of the semiconductor substrate after a second n-type capping layer, which fills trenches in a vertically stacked superlattice structure, has been deposited on a second n-type dipole layer according to one or more embodiments. [Figure 2P] Figure 2O shows bidirectional cross-sectional views of a semiconductor substrate after etching the vertical stacked superlattice structure to remove a portion of the second n-type capping layer and a portion of the second n-type dipole layer from a first portion, a second portion, and a third portion of the substrate, according to one or more embodiments. [Figure 2Q] Figure 2P shows a bidirectional cross-sectional view of the semiconductor substrate after a third protective layer has been deposited on the first and second portions of the substrate according to one or more embodiments. [Figure 2R] Figure 2Q shows a bidirectional cross-sectional view of a semiconductor substrate after etching a vertical stacked superlattice structure according to one or more embodiments to remove a third protective layer, a portion of the first n-type capping layer, and a portion of the first n-type dipole layer from a second portion of the substrate, thereby exposing a high dielectric constant dielectric layer. [Figure 2S]Figure 2R shows a bidirectional cross-sectional view of a semiconductor substrate after annealing the substrate at a temperature of 1000°C or less to drive atoms from each of the first p-type dipole layer, the second p-type dipole layer, the first n-type dipole layer, and the second n-type dipole layer to the high dielectric layer in order to form an annealed high dielectric layer according to one or more embodiments. [Figure 2T] Figure 2S shows a bidirectional cross-sectional view of the semiconductor substrate after etching the vertical stacked superlattice structure to remove the first p-type dipole layer, the first p-type capping layer, the second p-type dipole layer, the second p-type capping layer, the first n-type dipole layer, the second n-type dipole layer, and the second p-type capping layer, respectively, according to one or more embodiments. [Modes for carrying out the invention]

[0017]

[0038] Before describing several exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the configuration or process step details described below. Other embodiments of this disclosure are also possible and can be practiced or performed in a variety of ways.

[0018]

[0039] As used herein, the term “approximately” means roughly or nearly, and means a variation of no more than ±15% of the given number or range. For example, values ​​differing by ±14%, ±10%, ±5%, ±2%, or ±1% satisfy the definition of “approximately.”

[0019]

[0040] Spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used here to describe the relationship between one element or feature shown in a drawing and another, for the sake of clarity. It will be understood that spatially relative terms are intended to encompass different orientations of a device in use or operation, in addition to the orientation shown in the drawing. Therefore, for example, if a device in a drawing is upside down, an element described as “below” or “beneath” another element or feature will be located “above” that other element or feature. Thus, the exemplary term “below” may encompass both above and below directions. Devices may be oriented in other ways (rotated 90 degrees or in other directions), and the spatially relative descriptions used in this document should be interpreted accordingly.

[0020]

[0041] In the context of describing the materials and methods discussed herein (particularly in the context of the following claims), the terms “a,” “an,” and “the,” and similar references, should be interpreted as covering both singular and plural forms, unless otherwise stated herein or unless the context clearly contradicts this. The enumeration of numerical ranges herein is merely intended as abbreviations to refer individually to each distinct value falling within that range, unless otherwise noted herein, and each distinct value is incorporated into the specification as if it were individually enumerated herein. All methods described herein may be performed in any appropriate order, unless otherwise indicated herein or unless the context clearly contradicts this. The use of any and all examples or exemplary language provided herein (e.g., “such as”) is merely intended to better describe the materials and methods and does not limit their scope unless otherwise specified in the claims. Nothing in this document should be interpreted as indicating that any element not specified in the claims is essential for carrying out the disclosed materials and methods.

[0021]

[0042] Throughout this Specified Publication, any reference to “one embodiment,” “a particular embodiment,” “one or more embodiments,” or “embodiment” means that a particular feature, structure, material, or property described in relation to an embodiment is included in at least one embodiment of this Disclosure. Therefore, phrases such as “in one or more embodiments,” “in a particular embodiment,” “in one embodiment,” or “in an embodiment” appearing in various places throughout this Specified Publication do not necessarily refer to the same embodiment of this Disclosure. In one or more embodiments, particular features, structures, materials, or properties are combined in any and appropriate manner.

[0022]

[0043] As used herein and in the appended claims, the terms “substrate” or “wafer” refer to the surface or portion of a surface on which the process is performed. Furthermore, unless otherwise indicated in the context, a reference to a substrate may refer only to a portion of the substrate. In addition, when a deposition on a substrate is referred to, it may mean both a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0023]

[0044] As used in this document, “substrate” refers to any substrate or material surface formed on a substrate on which a film treatment is performed during the manufacturing process. For example, substrate surfaces on which treatment may be performed include, depending on the application, silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. A substrate includes, but is not limited to, a semiconductor wafer. A substrate may be exposed to pretreatment processes for polishing, etching, reducing, oxidizing, hydroxylating, annealing, and / or baking the substrate surface. In addition to direct film treatment on the surface of the substrate itself, any of the disclosed film treatment steps may be performed on underlying layers formed on the substrate, as will be disclosed in more detail below, and the term “substrate surface” is intended to include such underlying layers as the context indicates. Therefore, for example, if a film / layer or partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0024]

[0045] The term "on" indicates direct contact between elements. The term "directly on" indicates direct contact between elements without any intervening elements.

[0025]

[0046] As used in this document and the attached claims, terms such as “precursor,” “reactant,” and “reactive gas” are interchangeable and refer to any gas species that can react with the substrate surface.

[0026]

[0047] As used in this document, “atomic layer deposition” or “periodic deposition” refers to the sequential exposure of two or more reactive compounds to a substrate surface in order to deposit a layer of material onto the substrate surface. The substrate or a portion of the substrate is exposed separately to two or more reactive compounds introduced into the reaction zone of a processing chamber. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay to allow each compound to adhere to and / or react on the substrate surface and then be purged from the processing chamber. These reactive compounds are said to be sequentially exposed to the substrate. In a spatial ALD process, different portions of the substrate surface, or material on the substrate surface, are exposed to two or more reactive compounds simultaneously such that no given point on the substrate is substantially exposed to multiple reactive compounds at the same time. As used in this document and in the appended claims, the term “substantially” as used in this context means, as understood by those skilled in the art, that a small portion of the substrate may be simultaneously exposed to multiple reactive gases by diffusion, and that this simultaneous exposure is unintentional.

[0027]

[0048] In one aspect of time-domain ALD processing, a first reactive gas (i.e., a first precursor or compound A) is pulsed into the reaction zone, followed by a first time delay. Next, a second precursor or compound B is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas (such as argon) is introduced into the processing chamber to purge the reaction zone or to remove any residual reactive compounds or reaction byproducts from the reaction zone. Alternatively, the purge gas may flow continuously throughout the entire deposition process so that only the purge gas flows during the time delays between pulsed deliveries of the reactive compounds. The reactive compounds are pulsed alternately until a desired film or film thickness is formed on the substrate surface. In either scenario, one cycle consists of the ALD process of pulsed delivery of compound A, purge gas, compound B, and purge gas. A cycle can begin with either compound A or compound B and continue each sequence of the cycle until a film of a predetermined thickness is obtained.

[0028]

[0049] One or more of the layers deposited on the substrate or the substrate surface are continuous. In this document, the term "continuous" refers to a layer that covers the entire exposed surface without gaps or bare spots that expose the material beneath the deposited layer. A continuous layer may have gaps or bare spots with a surface area of ​​less than approximately 15% or less than approximately 10% of the total surface area of ​​the layer.

[0029]

[0050] In an embodiment of the spatial ALD process, a first reactive gas and a second reactive gas (e.g., nitrogen gas) are supplied simultaneously to the reaction zone but separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas supply device so that any given point on the substrate is exposed to the first and second reactive gases.

[0030]

[0051] A transistor is a circuit component or element that is often formed on a semiconductor device. Depending on the circuit design, transistors may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive wires, or other elements. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doped regions of a substrate, such as a semiconductor substrate, exhibiting a doping profile suitable for a particular application. The gate is located above the channel region and includes a gate dielectric interposed between the gate electrode in the semiconductor substrate and the channel region.

[0031]

[0052] As used herein, the term “field-effect transistor” or “FET” refers to a transistor that uses an electric field to control the electrical behavior of a device. A field-effect transistor is a voltage-controlled device whose current-transmitting ability changes when an electric field is applied. Field-effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field within the device, which is generated by the voltage difference between the body and the gate of the device. The three terminals of an FET are the source (S) through which carriers enter the channel, the drain (D) through which carriers exit the channel, and the gate (G), which is the terminal that regulates the conductivity of the channel. Conventionally, the current entering the channel from the source (S) is I S The current entering the channel from the drain (D) is I D This is what is displayed. The voltage between the drain and source is V DS It is called a gate (G). By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., I) is increased. D ) can be controlled.

[0032]

[0053] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are a type of field-effect transistor (FET) used in integrated circuits and high-speed switching applications. MOSFETs have an insulated gate, and the voltage applied to it determines the device's conductivity. This ability to change conductivity in response to the applied voltage is used to amplify or switch electronic signals. MOSFETs are based on the modulation of charge concentration by metal-oxide-semiconductor (MOS) capacitance between the body electrodes and the gate electrode, which is located above the body and insulated from all other device regions by the gate dielectric layer. Compared to MOS capacitors, MOSFETs include two additional terminals (source and drain), each connected to a separate, highly doped region separated by the body region. These regions can be p-type or n-type, but both are the same type and are the opposite type to the body region. The source and drain (unlike the body) are highly doped, and the doping type is followed by a "+" symbol.

[0033]

[0054] If the MOSFET is an n-channel or NMOS FET, the source and drain are n+ regions, and the body is a p-type substrate region. If the MOSFET is a p-channel or PMOS FET, the source and drain are p+ regions, and the body is an n-type substrate region. The source is so named because it is the source of charge carriers (electrons in the case of n-channels, and holes in the case of p-channels) flowing through the channel. Similarly, the drain is where charge carriers exit the channel.

[0034]

[0055] An NMOS FET consists of an n-type source / drain and a p-type substrate. When a voltage is applied to the gate, holes in the body (p-type substrate) are driven away from the gate. This allows for the formation of an n-type channel between the source and drain, and current is carried by electrons from the source to the drain through the induced n-type channel. Logic gates and other digital devices implemented using NMOS are said to have NMOS logic. NMOS has three operating modes called cutoff, triode, and saturation. Circuits with NMOS logic gates dissipate electrostatic force when the circuit is idling because DC current flows through the logic gate when the output is low.

[0035]

[0056] A PMOS FET consists of a p-type source / drain and an n-type substrate. When a positive voltage is applied between the source and gate (or a negative voltage between the gate and source), a p-type channel is formed between the source and drain with opposite polarity. Current is carried from the source to the drain by holes through the induced p-type channel. When the gate voltage is high, the PMOS does not conduct, and when the gate voltage is low, the PMOS conducts. Logic gates and other digital devices implemented using PMOS are said to have PMOS logic. PMOS technology is low-cost and has good noise immunity.

[0036]

[0057] In NMOS, the carriers are electrons, while in PMOS, the carriers are holes. When a high voltage is applied to the gate, NMOS conducts, but PMOS does not. Furthermore, when a low voltage is applied to the gate, NMOS does not conduct, but PMOS does. Because the electron carriers in NMOS move twice as fast as the hole carriers in PMOS, NMOS is considered faster than PMOS. However, PMOS devices are more resistant to noise than NMOS devices. In addition, NMOS integrated circuits will be smaller than PMOS integrated circuits (providing the same functionality) because NMOS can provide half the impedance offered by PMOS (with the same shape dimensions and operating conditions).

[0037]

[0058] As used herein, the term “Fin-field-effect transistor (FinFET)” refers to a substrate-built MOSFET transistor in which the gate is located on two, three, or four sides of the channel, or wrapped around the channel, forming a double-gate structure. FinFET devices are given the common name FinFET because the source / drain regions form “fins” on the substrate. FinFET devices have fast switching times and high current density.

[0038]

[0059] As used herein, the term “gate all around (GAA)” is used to refer to electronic devices such as transistors in which the gate material completely surrounds the channel region. The channel region of a GAA transistor may include nanowires or nanoslabs or nanosheets, rod-shaped channels, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device has a plurality of vertically spaced horizontal nanowires or horizontal bars, making the GAA transistor a stacked horizontal gate all around (hGAA) transistor.

[0039]

[0060] As used herein, the term "complementary field-effect transistor (CFET)" refers to a transistor comprising NMOS FET devices and PMOS FET devices stacked together. Each of the NMOS FET devices and PMOS FET devices forming the CFET is a GAA transistor or an hGAA transistor.

[0040]

[0061] As used herein, the term "nanowire" refers to a nanometer (10⁻¹⁰) -9 This refers to nanostructures having a diameter in units of meters. Nanowires can also be defined as structures with a length-to-width ratio greater than 1000. Alternatively, nanowires can be defined as structures whose thickness or diameter is limited to tens of nanometers or less, but whose length is not limited. Nanowires are used in transistors and some laser applications, and in one or more embodiments, they are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in logic CPUs, GPUs, MPUs, and transistors for volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term “nanosheet” refers to two-dimensional nanostructures having a thickness in the range of about 0.1 nm to about 1000 nm, or 0.5 nm to 500 nm, or 0.5 nm to 100 nm, or 1 nm to 500 nm, or 1 nm to 100 nm, or 1 nm to 50 nm.

[0041]

[0062] While not intended to be theoretically binding, relaxation in vertically stacked superlattice structures containing one or more hGAAs is thought to induce defects in the nanosheet channel layers within the structure. Embodiments of this disclosure advantageously provide transistors comprising a fully distorted vertically stacked superlattice structure having defect-free or substantially defect-free nanosheet channel layers. In some embodiments, the presence of defects in the nanosheet channel layers is determined by reciprocal space mapping (RSM) spectroscopy. Without intending to be theoretically binding, RSM is an X-ray diffraction method that collects diffraction data of vertically stacked superlattice structures in which the presence of defects may be observed. As used herein, the term “substantially defect-free” means that the nanosheet channel layers substantially do not contain defects as determined by RSM.

[0042]

[0063] Embodiments of the present disclosure are illustrated by diagrams showing devices (e.g., transistors) and processes for forming transistors according to one or more embodiments of the present disclosure. The illustrated processes are merely illustrative examples of possible uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the illustrated uses.

[0043]

[0064] Embodiments of this disclosure generally relate to the field of electronic device manufacturing, and more particularly to transistors. More specifically, embodiments of this disclosure relate to CFETs and methods for manufacturing CFETs. While devices and processes are described using this context, those skilled in the art will recognize that the disclosed devices and processes are not limited to the illustrated applications.

[0044]

[0065] Figure 1A shows a process flow diagram of method 100 for manufacturing a CFET. Figures 2A to 2T show bidirectional cross-sectional views of an electronic device (e.g., a transistor such as a CFET 200) according to one or more embodiments. The CFET 200 shown in Figures 2A to 2T can be manufactured by method 100 shown in Figure 1A.

[0045]

[0066] Figure 1B shows a schematic cross-sectional view of a CFET 200 having a vertically stacked superlattice structure 260 on a substrate 202. The substrate 202 has a top surface 203. The substrate 202 can be any suitable substrate material. In one or more embodiments, the substrate 202 includes semiconductor materials (e.g., silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphide (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), germanium (Ge), silicon germanium (SiGe)), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 202 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), indium (In), phosphorus (P), or selenium (Se). While some examples of materials on which the substrate 202 may be formed are described herein, the essence and scope of this disclosure includes any material that can serve as a basis on which passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) may be built.

[0046]

[0067] In one or more embodiments, the substrate 202 is a p-type or n-type substrate. In this specification, the term “n-type” refers to a semiconductor produced by doping an intrinsic semiconductor with an electron donor element during manufacturing. The term “n-type” derives from the negative charge of electrons. In n-type semiconductors, electrons are majority carriers and holes are minority carriers. In this specification, the term “p-type” refers to the positive charge of wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a hole concentration greater than the electron concentration. In p-type semiconductors, holes are majority carriers and electrons are minority carriers.

[0047]

[0068] In one or more embodiments, the vertically stacked superlattice structure 260 includes one or more horizontal gate-all-around (hGAA) structures 215, 255 on the substrate 202. In some embodiments, the vertically stacked superlattice structure 260 includes a first or lower horizontal gate-all-around (hGAA) structure 215 on the substrate 202. In some embodiments, the vertically stacked superlattice structure 260 includes a first or lower horizontal gate-all-around (hGAA) structure 215 on the upper surface 203 of the substrate 202. In some embodiments, the vertically stacked superlattice structure includes a second or upper horizontal gate-all-around (hGAA) structure 255. Although not intended to be bound to any particular operating theory, the first hGAA 215 or second hGAA 215 and the second hGAA 255 or second hGAA 255 may independently comprise the same structure having the same layers. In one or more illustrated embodiments, the vertically stacked superlattice structure 260 includes a first hGAA structure 215 on the upper surface 203 of the substrate 202, an intermediate dielectric insulating (MDI) layer 240 on the upper surface 225 of the first hGAA structure 215, and a second hGAA structure 255 on the upper surface 245 of the MDI layer 240.

[0048]

[0069] In some embodiments, each of the first hGAA215 and the second hGAA255 includes alternating layers of nanosheet channel layers 230 and nanosheet release layers 220. In some embodiments, the multiple nanosheet release layers 220 and the multiple nanosheet channel layers 230 may include any number of lattice-matched material pairs suitable for forming a vertically stacked superlattice structure 260. In some embodiments, each of the first hGAA215 and the second hGAA255 has alternating layers of nanosheet channel layers 230 and nanosheet release layers 220, between one and five pairs.

[0049]

[0070] The nanosheet release layer 220 may have any suitable thickness. In one or more embodiments, each nanosheet release layer 220 has a thickness in the range of 5 nm to 15 nm. The nanosheet channel layer 230 may have any suitable thickness. In one or more embodiments, each nanosheet channel layer 230 has a thickness in the range of 5 nm to 15 nm.

[0050]

[0071] In some embodiments, each of the nanosheet channel layers 230 independently contains silicon (Si). In some embodiments, each of the nanosheet release layers 220 independently contains silicon germanium (SiGe).

[0051]

[0072] In one or more embodiments, a sacrificial layer (not shown) is formed between a first or lower hGAA215 and a second or upper hGAA255. In one or more embodiments, the sacrificial layer is selectively removed and replaced with an intermediate dielectric insulating (MDI) layer 240 during processing. The MDI layer 240 serves to electrically insulate the source / drain region of the first or lower GAA215 from the source / drain region of the second or upper GAA255. The MDI layer 240 may contain any suitable material. In one or more embodiments, the MDI layer 240 contains silicon germanium (SiGe). In one or more embodiments, the MDI layer 240 contains silicon germanium (SiGe) having a higher concentration of germanium (Ge) than the SiGe in the nanosheet release layer 220.

[0052]

[0073] In one or more embodiments, the MDI layer 240 may have any suitable thickness. In some embodiments, the MDI layer 240 has a thickness in the range of 15 nm to 90 nm (including the ranges of 15 nm to 80 nm, 20 nm to 75 nm, 15 nm to 60 nm, 15 nm to 50 nm, 15 nm to 75 nm, and 20 nm to 50 nm). In some embodiments, increasing the thickness of the MDI layer 240 to more than 40 nm increases the etching selectivity between the MDI layer 240 and the nanosheet release layer 220.

[0053]

[0074] As will be recognized by those skilled in the art, during subsequent processing, the sacrificial layer can be removed and replaced with the MDI layer 240. In one or more embodiments, the sacrificial layer (not shown) is selectively removed. Selective removal of the sacrificial layer can be performed by any suitable means known to those skilled in the art. In some embodiments, selective removal of the sacrificial layer includes an etching process that removes the sacrificial layer but not the nanosheet release layer 220. In some embodiments, the etching process includes one or more of a wet etching process or a dry etching process. In some embodiments, the etching process is directional etching.

[0054]

[0075] In one or more embodiments not shown, the vertically stacked superlattice structure 260 includes a plurality of vertically extending trenches and a plurality of horizontally extending trenches. In one or more embodiments, the plurality of vertically extending trenches extend vertically from the upper surface of the second hGAA or upper hGAA 255, through the MDI layer 240, through the first or lower hGAA 215, to the upper surface 203 of the substrate 202. In one or more embodiments, the plurality of horizontally extending trenches extend horizontally through a plurality of nanosheets within the second hGAA 255 or upper hGAA 255, and through a plurality of nanosheets within the first hGAA 215 or lower hGAA 215.

[0055]

[0076] Embodiments of this disclosure are advantageous in that they reduce thickness, reduce leakage, reduce heat balance, and (multi-V tを (including) V t The present invention provides a method for manufacturing electronic devices (e.g., CFETs) that meet requirements and have improved device performance and reliability. The embodiments of this disclosure are advantageously V t Increase and multi-V t This provides an improved integration scheme that enables enhanced tuning capabilities. Embodiments of this disclosure provide V without EOT penalty. t This will significantly improve the situation.

[0056]

[0077] Embodiments of this disclosure advantageously provide integration schemes that reduce the number of lithography patterning steps. Several embodiments advantageously provide integration schemes that eliminate the need to deposit a liner on top of the CFET (e.g., on top of one or more NMOS FETs or PMOS FETs), reduce the number of etching steps, and eliminate the requirement for a carbon packing step. By reducing the number of etching steps using the processes described herein, the V of the CFET is advantageously reduced. t It is known that fluctuations are eliminated. Advantageously, embodiments of this disclosure provide an improved process that reduces the number of annealing steps for incorporating metal atoms from the p-type and n-type dipole layers.

[0057]

[0078] Embodiments of the present disclosure advantageously provide improved integration schemes that include conventional dipole engineering techniques, such as a first dipole process and / or a final dipole process. Advantageously, the integration schemes described herein may include conventional dipole engineering techniques without requiring the repair of interface layers after processing (in the first dipole process) or the repair of high-dielectric constant dielectric layers after the annealing process (in the final dipole process).

[0058]

[0079] Figure 1A shows a process flow diagram of method 100 for manufacturing a complementary field-effect transistor (CFET). Method 100 includes, in step 10, depositing an interface layer on the upper surface of a vertical stacked superlattice structure on a substrate. In step 12, method 100 includes depositing a high dielectric constant layer on the interface layer. In step 14, method 100 includes depositing a first p-type dipole layer on the high dielectric constant layer. In step 16, method 100 includes depositing a first p-type capping layer on the first p-type dipole layer. In step 18, the method includes depositing a first protective layer on a first portion of the substrate. In step 20, method 100 includes etching the vertical stacked superlattice structure to remove the first protective layer, as well as a portion of the first p-type capping layer and a portion of the first p-type dipole layer from a second portion of the substrate. In step 22, method 100 includes depositing a second p-type dipole layer on a first portion, a second portion, and a third portion of the substrate. In step 24, method 100 includes depositing a second p-type capping layer on the second p-type dipole layer. In step 26, method 100 includes etching the vertical stacked superlattice structure to remove a portion of the first p-type capping layer, a portion of the first p-type dipole layer, a portion of the second p-type capping layer, and a portion of the second p-type dipole layer to expose a high-dielectric-constant dielectric layer on the second hGAA structure. In step 28, method 100 includes depositing a first n-type dipole layer on the exposed high-dielectric-constant dielectric layer on the second hGAA structure. In step 30, method 100 includes depositing a first n-type capping layer on the first n-type dipole layer. In step 32, method 100 includes depositing a second protective layer on a first portion of the substrate. In step 34, method 100 includes etching the vertical stacked superlattice structure to remove the second protective layer to expose a first portion of the first n-type capping layer and to remove portions of the first n-type capping layer and the first n-type dipole layer from the second and third portions of the substrate. In step 36, method 100 includes depositing a second n-type dipole layer on the first, second, and third portions of the substrate.In step 38, method 100 includes depositing a second n-type capping layer on a second n-type dipole layer. In step 40, method 100 includes etching the vertical stacked superlattice structure to remove portions of the second n-type capping layer and the second n-type dipole layer from the first, second, and third portions of the substrate. In step 42, method 100 includes depositing a third protective layer on the first and second portions of the substrate. In step 44, method 100 includes etching the vertical stacked superlattice structure to remove the third protective layer, as well as portions of the first n-type capping layer and the first n-type dipole layer from the second portion of the substrate, exposing the high dielectric constant dielectric layers on the first and second hGAA structures, respectively. In step 46, method 100 includes annealing the substrate at a temperature of 1000°C or less to drive atoms from each of the first p-type dipole layer, the second p-type dipole layer, the first n-type dipole layer, and the second n-type dipole layer to the high-dielectric-constant dielectric layer, thereby forming the annealed high-dielectric-constant dielectric layer. In step 48, method 100 includes etching the vertical stacked superlattice structure to remove each of the first p-type dipole layer, the first p-type capping layer, the second p-type dipole layer, the second p-type capping layer, the first n-type dipole layer, the first n-type capping layer, the second n-type dipole layer, and the second p-type capping layer.

[0059]

[0080] In one or more embodiments, Method 100 essentially consists of steps 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, and 48.

[0060]

[0081] For example, if, after dipole engineering, the work function is shifted to either a P-type dipole or N-type dipole band edge, the method herein can be used to shift the band edge in the opposite direction. For example, the method herein shifts the band edge to the most P-type dipole and / or N-type dipole band edge, respectively, at the very low V t (ULV t ) from low V t (LV t ) or standard V t (SV t ), or intermediate gap: high V t (HV t It can be shifted to ).

[0061]

[0082] While not intended to be theoretically binding, selectively etching one or more dipole layers (e.g., a first p-type dipole layer, a second p-type dipole layer, a first n-type dipole layer, and / or a second n-type dipole layer) and increasing the thickness of one or more dipole layers results in multiple threshold voltages (multiple V). t It is thought that a CFET having ) is formed. In other words, if one dipole layer has a first thickness (e.g., a first p-type dipole layer) and another dipole layer has a second thickness (e.g., a second p-type dipole layer), and the first and second thicknesses are different, then multiple threshold voltages (multiple V) are formed. t ) is formed.

[0062]

[0083] Figures 2A to 2T show bidirectional cross-sectional views of an electronic device (e.g., a transistor such as a complementary field-effect transistor (CFET) 200) according to one or more embodiments. Specifically, Figures 2A to 2T show a first cross-sectional view through the gate across the fins and a second cross-sectional view through the fins (across the gate). The substrate 202 includes a first portion 202-1, a second portion 202-2, and a third portion 202-3.

[0063]

[0084] The CFET 200 shown in Figures 2A to 2T can be manufactured by the method 100 shown in Figure 1A.

[0064]

[0085] Referring to Figures 1A and 2B, in some embodiments, in step 10, the interface layer 270 is deposited on the upper surface of the vertically stacked superlattice structure 260 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In some embodiments, in step 10, the interface layer 270 is deposited on a first hGAA structure 215, an MDI layer 240, and a second hGAA structure 255. In one or more embodiments, the interface layer 270 comprises silicon oxide (SiOx). In one or more embodiments, the interface layer 270 may be formed by etching and oxide formation on a surface (e.g., the upper surface of the vertically stacked superlattice structure 260).

[0065]

[0086] In some embodiments, a wet chemical technique is performed in step 10 to form the interface layer 270. The wet chemical technique may be any suitable technique known to those skilled in the art. In some embodiments, the wet chemical technique includes a pre-cleaning process. In some embodiments, the pre-cleaning process includes using an SC-1 solution containing one or more of ozone, ammonium hydroxide, or hydrogen peroxide. In some embodiments, the pre-cleaning process includes using an SC-1 solution that does not contain ozone, ammonium hydroxide, or hydrogen peroxide. In some embodiments, after using the SC-1 solution, the pre-cleaning process includes etching off native oxides on the substrate using dilute hydrofluoric acid (dilute HF, e.g., dilute HF of 130:1) in a ratio greater than 100:1 to form a hydrophobic surface (i.e., the interface layer 270).

[0066]

[0087] In some embodiments, in step 10, rapid heat treatment (RTP) is used to form the interface layer 270. RTP may be any suitable process known to those skilled in the art. In some embodiments, in step 10, RTP is a thermal oxidation process in which a silicon oxide (SiOx) layer (e.g., the interface layer 270) grows on the upper surface of the vertically stacked superlattice structure.

[0067]

[0088] In one or more embodiments, step 10 further includes depositing an etching stop layer 205 on the interface layer 270. In one or more embodiments, the CFET 200 includes the etching stop layer 205 on at least a portion of the interface layer 270. In one or more embodiments, the CFET 200 includes the etching stop layer 205 over the entire interface layer 270. In some embodiments, the etching stop layer 205 is deposited on the upper surface of the interface layer 270 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art.

[0068]

[0089] The etching stop layer 205 may contain any suitable material known to those skilled in the art. In some embodiments, the etching stop layer 205 contains, but is not limited to, one or more of silicon nitride (SiN), silicon carbonitride (SiCN), or silicon carbonate (SiCON).

[0069]

[0090] Referring again to Figures 1A and 2B, in some embodiments, in step 12, the high dielectric constant dielectric layer 272 is deposited on the interface layer 270 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In some embodiments, in step 12, the high dielectric constant dielectric layer 272 is conformally deposited on the interface layer 270 by ALD.

[0070]

[0091] In some embodiments, the high dielectric constant dielectric layer 272 is conformally deposited on the etching stop layer 205 on the interface layer 270 by ALD.

[0071]

[0092] In some embodiments, the high dielectric constant dielectric layer 272 includes one or more of hafnium oxide (HfOx), hafnium zirconium oxide (HfZrOx), zirconium oxide (ZrOx), nitrogen-doped hafnium oxide (HfOx), nitrogen-doped hafnium zirconium oxide (HfZrOx), and nitrogen-doped zirconium oxide (ZrOx). In some embodiments, the high dielectric constant dielectric layer 272 includes hafnium oxide (HfOx).

[0072]

[0093] Referring to Figures 1A and 2C, in some embodiments, in step 14, the first p-type dipole layer 274 is deposited on the high-dielectric-constant dielectric layer 272 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In some embodiments, the first p-type dipole layer 274 comprises one or more of aluminum oxide (AlOx), aluminum nitride (AlNx), or alloys thereof.

[0073]

[0094] In some embodiments, in step 14, depositing the first p-type dipole layer 274 includes exposing the substrate 202 (e.g., the upper surface of the high dielectric layer 272) to pulses of an aluminum-containing precursor and pulses of an oxygen-containing reactant by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. In some embodiments, in step 14, depositing the first p-type dipole layer 274 includes exposing the upper surface of the high dielectric layer 272 to pulses of an aluminum-containing precursor and pulses of a nitrogen-containing reactant by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. In some embodiments, the substrate 202 is purged after each pulse.

[0074]

[0095] In some embodiments, the oxygen-containing reactant is oxygen (O2), ozone (O3), or water. ( Contains one or more of the following (H2O): 。

[0075]

[0096] In some embodiments, the nitrogen-containing reactant is nitrogen (N2), ammonia (NH3), hydrazine (N2H4), nitrogen radical (N2 * ) and hydrogen radical (H * Co-flow of ), co-flow of nitrogen radicals (N2*) and hydrogen (H2) gas, or nitrogen radicals (N2 * and deuterium ( 2 Includes one or more of the confluences of H) gases.

[0076]

[0097] In some embodiments, the nitrogen-containing reactant comprises substituted or unsubstituted alkylhydrazines. In some embodiments, the alkylhydrazine comprises atoms ranging from 1 to 6 carbon atoms. In one or more embodiments, the alkylhydrazine is t-butylhydrazine. In some embodiments, the nitrogen-containing reactant comprises plasma. In some embodiments, the nitrogen-containing reactant comprises ammonia (NH3).

[0077]

[0098] The first p-type dipole layer 274 may be deposited as a single layer or a multilayer. The first p-type dipole layer 274 may be deposited to a predetermined thickness. In some embodiments, the first p-type dipole layer 274 has a thickness ranging from 3 angstroms to 25 angstroms.

[0078]

[0099] Referring to Figures 1A and 2D, in some embodiments, in step 16, a first p-type capping layer 276 is deposited on the first p-type dipole layer 274 using a deposition technique, but not limited to ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In some embodiments, in step 16, the first p-type capping layer 276 is conformally deposited on the first p-type dipole layer 274 by ALD. In some embodiments, the first p-type capping layer 276 comprises one or more of silicon (Si), silicon oxide (SiOx), aluminum oxide (AlOx), titanium nitride (TiN), or tantalum nitride (TaN). In some embodiments, the first p-type capping layer 276 has a thickness ranging from 10 angstroms to 30 angstroms.

[0079]

[0100] Referring to Figures 1A and 2E, in some embodiments, in step 18, the first protective layer 278 is deposited on the first portion 202-1 of the substrate 202 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In some embodiments, the first protective layer 278 protects a portion of the first p-type capping layer 276 on the first portion 202-1 of the substrate 202. The first protective layer 278 may contain any suitable material known to those skilled in the art. In some embodiments, the first protective layer 278 contains a hard mask material. In some embodiments, the first protective layer 278 contains carbon (C). In some embodiments, the first protective layer 278 contains spin-on carbon (C).

[0080]

[0101] Method 100 includes selective etching of the vertical stacked superlattice structure 260 in step 20 to remove the first protective layer 278 from a first portion 202-1 of the substrate 202, and a portion of the first p-type capping layer 276 and a portion of the first p-type dipole layer 274 from a second portion 202-2 of the substrate 202. In one or more embodiments, Method 100 includes multiple threshold voltages (multi-V) within the CFET 200. t Step 20 includes selective etching to form the ). Figure 2F shows a bidirectional cross-sectional view of the substrate 202 of Figure 2E after etching the vertical stacked superlattice structure 260 in step 20.

[0081]

[0102] The etching process in step 20 may be any suitable etching process known to those skilled in the art. In some embodiments, the etching process includes a wet etching process or a dry etching process. In some embodiments, the etching process includes a wet etching process. In some embodiments, the wet etching process includes a pre-washing process. In some embodiments, the pre-washing process includes using one or more ammonium hydroxide (NH4OH) or water (H2O). In some embodiments, water (H2O) is deionized water (DI). In some embodiments, the pre-washing process includes using a DI:NH4OH ratio ranging from 100:1 DI:NH4OH to 5:1 DI:NH4OH. 。

[0082]

[0103] In some embodiments, the pre-washing process includes using either the SC-1 solution or the SC-2 solution. In one or more embodiments, the SC-1 solution includes one or more of ozone, ammonium hydroxide, or hydrogen peroxide. In one or more embodiments, the SC-2 solution includes one or more of hydrochloric acid additives or hydrogen peroxide. Advantageously, it has been found that using either the SC-1 solution or the SC-2 solution in step 22 selectively etches the first p-type dipole layer 274 (and other layers above it) without etching any portion of the interface layer 270.

[0083]

[0104] The first protective layer 278 is removed from the first portion 202-1 of the substrate 202, as well as from a portion of the first p-type capping layer 276 and a portion of the first p-type dipole layer 274 of the substrate 202, and the thickness of the dipole layer is selectively etched (for example, by depositing a second p-type dipole layer 28 in step 28). 。 22) To have an advantage, MultiV t The present invention provides a CFET200 having the following characteristics.

[0084]

[0105] Referring to Figures 1A and 2G, in some embodiments, in step 22, a second p-type dipole layer 280 is deposited on the first p-type capping layer 276 of the first portion 202-1, the second portion 202-2, and the third portion 202-3 of the substrate 202 and on the high dielectric constant dielectric layer 272 using a deposition technique such as ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In some embodiments, in step 22, the second p-type dipole layer 280 is formed on the first hGAA structure 215, the MDI layer 240, and the second hGAA structure 255. In one or more embodiments, depositing the second p-type dipole layer 280 in step 22 involves the same process as depositing the first p-type dipole layer 274 in step 14.

[0085]

[0106] In some embodiments, the second p-type dipole layer 280 comprises one or more of aluminum oxide (AlOx), aluminum nitride (AlNx), or alloys thereof. The second p-type dipole layer 280 may be deposited as a single layer or a multilayer film. The second p-type dipole layer 280 may be deposited to a predetermined thickness. In some embodiments, the second p-type dipole layer 280 has a thickness ranging from 3 angstroms to 25 angstroms.

[0086]

[0107] Referring to Figures 1A and 2H, in some embodiments, in step 24, the second p-type capping layer 282 is deposited on the second p-type dipole layer 280 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In some embodiments, in step 24, the second p-type capping layer 282 is conformally deposited on the second p-type dipole layer 280 by ALD. In some embodiments, the second p-type capping layer 282 comprises one or more of silicon (Si), silicon oxide (SiOx), aluminum oxide (AlOx), titanium nitride (TiN), or tantalum nitride (TaN). In some embodiments, the second p-type capping layer 282 has a thickness ranging from 30 angstroms to 70 angstroms.

[0087]

[0108] In one or more embodiments, in step 24, the second p-type capping layer 282 fills one or more trenches in the vertical stacked superlattice structure 260. In one or more embodiments, in step 24, the second p-type capping layer 282 fills each of the multiple vertically extending trenches and each of the multiple horizontally extending trenches in the vertical stacked superlattice structure 260.

[0088]

[0109] Referring to Figures 1A and 2I, in some embodiments, step 26 of Method 100 includes etching the vertical stacked superlattice structure 260 to remove a portion of the first p-type capping layer 276, a portion of the first p-type dipole layer 274, a portion of the second p-type capping layer 282, and a portion of the second p-type dipole layer 280 to expose the high dielectric constant dielectric layer 277 on the underlying structure GAh22. In some embodiments, step 26 includes the same process as step 20, and / or steps 30, 34, 40, 44, or 48 (further described below). In one or more embodiments, Method 100 applies multiple threshold voltages (multi-V) to the CFET. t The process includes selective etching in step 26 to form the above-ground hGAA 255. Advantageously, in one or more embodiments, step 26 selectively etches the vertical stacked superlattice structure 260 to remove the first p-type capping layer 276, the first p-type dipole layer 274, the second p-type capping layer 282, and the second p-type dipole layer 280 from the above-ground hGAA 255. Thus, step 26 is a selective etching process for the high-dielectric constant dielectric layer 272.

[0089]

[0110] In one or more embodiments, the portion of the second p-type capping layer 282 to be removed is the portion deposited on top of the second p-type dipole layer 280 and located within a plurality of vertically extending trenches extending from the upper surface of the second or upper hGAA 255 to the MDI layer 240. In other words, the material of the second p-type capping layer 282 filling the plurality of vertically extending trenches and the plurality of horizontally extending trenches in the first or lower hGAA 215 remains after etching in step 26.

[0090]

[0111] Referring to Figures 1A and 2J, in some embodiments, in step 28, the first n-type dipole layer 290 on the exposed high-dielectric-constant dielectric layer 272 on the second hGAA structure 255 is deposited by, but is not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In some embodiments, the first n-type dipole layer 290 comprises one or more of lanthanum oxide (LaOx), lanthanum nitride (LaNx), or alloys thereof.

[0091]

[0112] In some embodiments, in step 28, depositing the first n-type dipole layer 290 includes exposing the substrate 202 (e.g., the upper surface of the exposed high-dielectric-constant dielectric layer 272) to pulses of lanthanum-containing precursor and oxygen-containing reactant by an atomic layer deposition (ALD) process or chemical vapor deposition (CVD) process. In some embodiments, in step 34, depositing the first n-type dipole layer 290 includes exposing the upper surface of the exposed high-dielectric-constant dielectric layer 272 to pulses of lanthanum-containing precursor and nitrogen-containing reactant by an atomic layer deposition (ALD) process or chemical vapor deposition (CVD) process. In some embodiments, the substrate 202 is purged after each pulse.

[0092]

[0113] In some embodiments, the oxygen-containing reactant includes one or more of oxygen (O2), ozone (O3), or water (H2O). 。

[0093]

[0114] In some embodiments, the nitrogen-containing reactant is nitrogen (N2), ammonia (NH3), hydrazine (N2H4), nitrogen radical (N2 * ) and hydrogen radical (H * ) co-flow, nitrogen radicals (N2 * ) and co-flow of hydrogen (H2) gas, or nitrogen radicals (N2 * ) and deuterium ( 2 H) Includes one or more of the gas confluences.

[0094]

[0115] In some embodiments, the nitrogen-containing reactant comprises substituted or unsubstituted alkylhydrazines. In some embodiments, the alkylhydrazine comprises atoms ranging from 1 to 6 carbon atoms. In one or more embodiments, the alkylhydrazine is t-butylhydrazine. In some embodiments, the nitrogen-containing reactant comprises plasma. In some embodiments, the nitrogen-containing reactant comprises ammonia (NH3).

[0095]

[0116] The first n-type dipole layer 290 may be deposited as a single layer or a multilayer. The first n-type dipole layer 290 may be deposited to a predetermined thickness. In some embodiments, the first n-type dipole layer 290 has a thickness ranging from 3 angstroms to 25 angstroms.

[0096]

[0117] Referring to Figures 1A and 2K, in some embodiments, in step 30, the first n-type capping layer 292 is deposited on the first n-type dipole layer 290 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In some embodiments, in step 30, the first n-type capping layer 292 is conformally deposited on the first n-type dipole layer 290 (on the second hGAA structure 255) by ALD. In some embodiments, the first n-type capping layer 292 comprises one or more of silicon (Si), silicon oxide (SiOx), aluminum oxide (AlOx), titanium nitride (TiN), or tantalum nitride (TaN). In some embodiments, the first n-type capping layer 292 has a thickness ranging from 10 angstroms to 30 angstroms.

[0097]

[0118] Referring to Figures 1A and 2L, in some embodiments, in step 32, a second protective layer 284 is deposited on the first portion 202-1 of the substrate 202 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In some embodiments, the second protective layer 284 protects the first n-type capping layer 292, the first n-type dipole layer 290, and the layer beneath the first n-type dipole layer 290. The second protective layer 284 may include any suitable material known to those skilled in the art. In some embodiments, the second protective layer 284 includes a hard mask material. In some embodiments, the second protective layer 284 includes carbon (C). In some embodiments, the second protective layer 284 includes spin-on carbon (C).

[0098]

[0119] Referring to Figures 1A and 2M, in some embodiments, step 34 of Method 100 includes selectively etching the vertical stacked superlattice structure 260 to remove the second protective layer 284 and expose the first portion 202-1, and removing a portion of the first n-type capping layer 292 and a portion of the first n-dipole layer 290 from the second portion 202-2 and the third portion 202-3 of the substrate 202. In some embodiments, step 30 includes the same process as steps 20, 26, and / or 40, 44, or 48 (described further below). In one or more embodiments, Method 100 includes multiple threshold voltages (multi-V) within the CFET 200. t To form ), step 34 includes selective etching.

[0099]

[0120] Referring to Figures 1A and 2N, in some embodiments, in step 36, the second n-type dipole layer 296 is deposited on the first portion 202-1, the second portion 202-2, and the third portion 202-2 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In some embodiments, in step 36, the second n-type dipole layer 296 is conformally deposited on the second hGAA structure 255 by ALD. In one or more embodiments, depositing the second n-type dipole layer 296 in step 36 involves the same process as depositing the first n-type dipole layer 290 in step 28.

[0100]

[0121] In some embodiments, the second n-type dipole layer 296 comprises one or more of lanthanum oxide (LaOx), lanthanum nitride (LaNx), or alloys thereof. The second n-type dipole layer 296 may be deposited as a single layer or a multilayer film. The second n-type dipole layer 296 may be deposited to a predetermined thickness. In some embodiments, the second n-type dipole layer 296 has a thickness ranging from 3 angstroms to 25 angstroms.

[0101]

[0122] Referring to Figures 1A and 2O, in some embodiments, in step 38, a second n-type capping layer 298 is deposited on the second n-type dipole layer 296 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In some embodiments, in step 38, the second n-type capping layer 298 is conformally deposited on the second n-type dipole layer 296 by ALD. In some embodiments, the second n-type capping layer 298 comprises one or more of silicon (Si), silicon oxide (SiOx), aluminum oxide (AlOx), titanium nitride (TiN), or tantalum nitride (TaN). In some embodiments, the second n-type capping layer 298 has a thickness ranging from 30 angstroms to 70 angstroms.

[0102]

[0123] In one or more embodiments, in step 38, the second n-type capping layer 298 fills one or more trenches in the vertical stacked superlattice structure 260. In one or more embodiments, in step 38, the second n-type capping layer 298 fills each of the multiple vertically extending trenches and each of the multiple horizontally extending trenches in the vertical stacked superlattice structure 260. More specifically, in one or more embodiments, the second n-type capping layer 298 fills each of the multiple vertically extending trenches and each of the multiple horizontally extending trenches in the second or information hGAA 255 up to the MDI layer 240.

[0103]

[0124] Referring to Figures 1A and 2P, in some embodiments, step 40 of method 100 includes etching the vertical stacked superlattice structure 260 to remove a portion of the second n-type capping layer 298 and a portion of the second n-type dipole layer 296 from a first portion 202-1, a second portion 202-2, and a third portion 202-3 of the substrate 202.

[0104]

[0125] In one or more embodiments, in step 40, the vertical stacked superlattice structure 260 is etched, and the upper surface of the etching stop layer 205 is exposed.

[0105]

[0126] In one or more embodiments, the portion of the second n-type capping layer 298 that is removed is the portion deposited on top of the second n-type dipole layer 296. In other words, the material of the second n-type capping layer 298 that fills multiple vertically extending trenches and multiple horizontally extending trenches down to the bottom of the etching stop layer 205 is not removed.

[0106]

[0127] In one or more embodiments, after etching in step 40, a plurality of vertically extending trenches and a plurality of horizontally extending trenches are filled with the material of a second n-type capping layer 298 in a second or upper hGAA 255, and a plurality of vertically extending trenches and a plurality of horizontally extending trenches are filled with the material of a second p-type capping layer in a second or lower hGAA 215.

[0107]

[0128] Referring to Figures 1A and 2Q, in some embodiments, in step 42, a third protective layer 294 is deposited on the first portion 202-1 and the second portion 202-2 of the substrate 202 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In some embodiments, the upper surface of the etching stop layer 205 is left exposed at the third portion 202-3 of the substrate 202.

[0108]

[0129] In some embodiments, the third protective layer 294 protects the second n-type capping layer 298, the second n-type dipole layer 296, the first n-type capping layer 292, the first n-type dipole layer 290, and the layer beneath the first n-type dipole layer 290. The third protective layer 294 may include any suitable material known to those skilled in the art. In some embodiments, the third protective layer 294 includes a hard mask material. In some embodiments, the third protective layer 294 includes carbon (C). In some embodiments, the third protective layer 294 includes spin-on carbon (C).

[0109]

[0130] Referring to Figures 1A and 2R, in step 44, Method 100 selectively etches the vertical stacked superlattice structure 260 to remove the third protective layer 294, a portion of the first n-type capping layer 292, and a portion of the first n-type dipole layer 290 from the second portion 202-2 of the substrate 202, exposing the high dielectric constant dielectric layer 272 on the first hGAA structure 215 and the second hGAA structure 255 of the third portion 202-3. In one or more embodiments, Method 100 applies multiple threshold voltages (multi-V) within the CFET 200. t Step 44 includes selective etching to form the etching stop layer. In Figure 2R, the upper surface of the etching stop layer 205 is exposed in the first portion 202-1, the second portion 202-2, and the third portion 202-3 of the substrate 202.

[0110]

[0131] Referring to Figures 1A and 2S, in some embodiments, in step 46, Method 100 anneals the substrate 202 (indicated by arrow 302) at a temperature of 1000°C or less to form an annealed high-dielectric-constant dielectric layer 272' (shown in Figure 2T), which includes driving atoms of a first p-type dipole layer 274, a second p-type dipole layer 280, a first n-type dipole layer 290, and 6 into the high-dielectric-constant dielectric layer.

[0111]

[0132] In some embodiments, step 46 of method 100 includes annealing the substrate 202 at a temperature of 950°C or less. In some embodiments, the temperature is in the range of 500°C to 1000°C, including the range of 600°C to 1000°C, the range of 700°C to 1000°C, the range of 750°C to 950°C, or the range of 800°C to 900°C.

[0112]

[0133] Without intending to be bound by theory, it is believed that annealing the substrate 202 according to step 46 drives an increase in the number of atoms from the dipole layers (e.g., the first p-type dipole layer 274, the second p-type dipole layer 280, the first n-type dipole layer 290, and / or the second n-type dipole layer 296) to the interface compared to a method in which annealing is not performed. In one or more embodiments, annealing the substrate 202 in step 46 includes rapid heat treatment (RTP). RTP may be any suitable process known to those skilled in the art. Without intending to be bound by theory, in step 46, method 100 includes annealing the substrate 202 at a temperature of 1000°C or less to drive atoms from one or more dipole layers to the interface of the interface layer 270 and the high-dielectric-constant dielectric layer 272, thereby causing the interface of the interface layer 270 and the high-dielectric-constant dielectric layer 272 to include properties.

[0113]

[0134] Referring to Figures 1A and 2T, in some embodiments, in step 48, method 100 etches the vertical stacked superlattice structure 260 to remove the first p-type dipole layer 274, the first p-type capping layer 276, the second p-type dipole layer 280, the second p-type capping layer 282, the first n-type dipole layer 290, the first n-type capping layer 292, the second n-type dipole layer 296, and the second n-type capping layer 298. In Figure 2T, the upper surface of the etching stop layer 205 is exposed by the first portion 202-1, the second portion 202-2, and the third portion 202-3 of the substrate 202.

[0114]

[0135] After step 48, method 100 may include any post-processing steps for semiconductor manufacturing known to those skilled in the art.

[0115]

[0136] In one or more embodiments, the CFET200 has any suitable number of different dipole layer thicknesses and multiple threshold voltages (multiple V) t ) may include. In one or more embodiments, the CFET200 has two different dipole layer thicknesses and two multiple threshold voltages (multi-V). t) and. In one or more embodiments, the CFET200 includes three different dipole layer thicknesses and three multiple threshold voltages (multi-V). t ) includes. In one or more embodiments, the CFET200 has four different dipole layer thicknesses and four multiple threshold voltages (multi-V). t ) includes.

[0116]

[0137] Further embodiments of the present disclosure relate to electronic devices having a plurality of CFET regions. In one or more embodiments, the electronic device includes a CFET 200 formed by Method 100.

[0117]

[0138] In some embodiments, an electronic device (e.g., CFET200) has a first threshold voltage (V t A first complementary field-effect transistor (CFET) region having ) and a second V t A second CFET region having, and a third V t The device comprises a third CFET region having a first CFET region, a second CFET region, and a third CFET region, each formed on a vertical stacked superlattice structure 260 on a substrate 202, the vertical stacked superlattice structure 260 including a first horizontal gate-all-around (hGAA) structure 215 (e.g., a P-type metal-oxide-semiconductor (PMOS) transistor) on the upper surface 203 of the substrate 202, an MDI layer 240 on the upper surface 225 of the first hGAA structure 215, and a second hGAA structure 255 (e.g., an N-type metal-oxide-semiconductor (NMOS) transistor) on the upper surface 245 of the MDI layer 240, and interface layers 270 on each of the first hGAA structure 215, the MDI layer 240, and the second hGAA structure 255.

[0118]

[0139] In some embodiments, the first CFET region includes a hafnium oxide (HfOx) layer 272 on the interface layer 270, a first p-type dipole layer 274 on the hafnium oxide (HfOx) layer 272, and a first p-type capping layer 276 on the first p-type dipole layer 274.

[0119]

[0140] In some embodiments, the second CFET region includes a hafnium oxide (HfOx) layer 272 on the interface layer 270, a first p-type dipole layer 274 on the hafnium oxide (HfOx) layer 272, a first p-type dipole layer 280 on the first p-type dipole layer 274, and a second p-type capping layer 282 on the second p-type dipole layer 280.

[0120]

[0141] In some embodiments, the third CFET region comprises a hafnium oxide (HfOx) layer 272 on the interface layer 270, a first p-type dipole layer 274 on the hafnium oxide (HfOx) layer 272, a first p-type capping layer 276 on the first p-type dipole layer 274, a second p-type dipole layer 280 on the first exposed portion of the hafnium oxide (HfOx) layer 272, and a second p-type The structure includes a second p-type capping layer 282 on the dipole layer 280, a first n-type dipole layer 290 on an exposed high-dielectric-constant dielectric layer 272 on the second hGAA structure 255, a first n-type capping layer 292 on the first n-type dipole layer 290, a second n-type dipole layer 296 on the second hGAA structure 255, and a second n-type capping layer 298 on the second n-type dipole layer 296.

[0121]

[0142] In one or more embodiments, each of the first p-type dipole layer 274 and the second p-type dipole layer 280 independently comprises one or more of aluminum oxide (AlOx), aluminum nitride (AlNx), or alloys thereof. In some embodiments, each of the first n-type dipole layer 290 and the second n-type dipole layer 296 independently comprises one or more of lanthanum oxide (LaOx), lanthanum nitride (LaNx), or alloys thereof.

[0122]

[0143] In some embodiments, each of the first p-type capping layer 276, the second p-type capping layer 282, the first n-type capping layer 292, and the second n-type capping layer 298 independently comprises one or more of silicon (Si), silicon oxide (SiOx), aluminum oxide (AlOx), titanium nitride (TiN), or tantalum nitride (TaN).

[0123]

[0144] Further embodiments of this disclosure relate to the described method and processing tools (i.e., cluster tools) for performing the CFET. In one or more embodiments, the cluster tool comprises an integrated processing system such that the steps of Method 100 are performed without vacuum breaking. In one or more embodiments, there is a vacuum breaking during at least one of the steps of Method 100.

[0124]

[0145] The specific arrangement of the processing chamber and its components can be modified depending on the cluster tool and should not be considered to limit the scope of this disclosure.

[0125]

[0146] Embodiments of this disclosure relate to non-temporary computer-readable media. In one or more embodiments, the non-temporary computer-readable media includes instructions, when executed by a controller of a processing chamber, that cause the processing chamber to perform any of the steps of the methods described herein. In one or more embodiments, the controller causes the processing chamber to perform the steps of Method 100.

[0126]

[0147] While the disclosures in this book are described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and uses of the disclosure. It will be apparent to those skilled in the art that various modifications and changes can be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Therefore, the disclosure is intended to include modifications and variations that fall within the scope of the appended claims and their equivalents.

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21. A method for forming a complementary field-effect transistor (CFET), First threshold voltage (V ｔ To form a first complementary field-effect transistor (CFET) region having ) The second V ｔ A second CFET region having the above, which forms a second CFET region adjacent to the first CFET region, The third V ｔ A third CFET region having the above, which forms a third CFET region adjacent to the second CFET region, A method wherein each of the first CFET region, the second CFET region, and the third CFET region is formed on a high dielectric constant dielectric layer on an interface layer on a vertical stacked superlattice structure on a substrate, and the vertical stacked superlattice structure includes a second horizontal gate all-around (hGAA) structure on an intermediate dielectric insulating (MDI) layer on a first horizontal gate all-around (hGAA) structure.

22. Forming the first CFET region described above is A first p-type dipole layer is deposited on the high dielectric constant dielectric layer, Depositing a first p-type capping layer on the first p-type dipole layer, A first protective layer is deposited on the first portion of the substrate, Etching the vertical stacked superlattice structure to remove the first protective layer, a portion of the first p-type capping layer, and a portion of the first p-type dipole layer from the second portion of the substrate. The method according to claim 21, including the method described in claim 21.

23. Forming the aforementioned second CFET region The method involves depositing a second p-type dipole layer on the first portion, the second portion, and the third portion of the substrate, wherein the second p-type dipole layer is formed on the first hGAA structure, the MDI layer, and the second hGAA structure. The method involves depositing a second p-type capping layer on the second p-type dipole layer, wherein the second p-type capping layer fills trenches within the vertical stacked superlattice structure. The vertical stacked superlattice structure is etched to remove a portion of the first p-type capping layer, a portion of the first p-type dipole layer, a portion of the second p-type capping layer, and a portion of the second p-type dipole layer, thereby exposing the high dielectric constant dielectric layer on the second hGAA structure. The method according to claim 22, including the method described in claim 22.

24. Forming the above-mentioned third CFET region is The first n-type dipole layer is deposited on the exposed high dielectric layer on the second hGAA structure, Depositing a first n-type capping layer on the first n-type dipole layer, A second protective layer is deposited on the first portion of the substrate, The vertical stacked superlattice structure is etched to expose a portion of the first n-type capping layer, and a portion of the first n-type capping layer and a portion of the first n-type dipole layer are removed from the second and third portions of the substrate. The method according to claim 23, including the method described in claim 23.

25. Forming the above-mentioned third CFET region is A second n-type dipole layer is deposited on the first portion, the second portion, and the third portion of the substrate, wherein the second n-type dipole layer is formed on the second hGAA structure. The method involves depositing a second n-type capping layer on the second n-type dipole layer, wherein the second n-type capping layer fills the trenches within the vertically stacked superlattice structure. The vertical stacked superlattice structure is etched to remove a portion of the second n-type capping layer and a portion of the second n-type dipole layer from the first portion, the second portion, and the third portion of the substrate. The method according to claim 24, further comprising:

26. The method according to claim 25, further comprising depositing a third protective layer on the first and second portions of the substrate.

27. The method according to claim 26, further comprising etching the vertical stacked superlattice structure to remove the third protective layer, a portion of the first n-type capping layer, and a portion of the first n-type dipole layer from the second portion of the substrate, thereby exposing the high dielectric constant dielectric layer on each of the first hGAA structure and the second hGAA structure.

28. The method according to claim 27, further comprising annealing the substrate to form an annealed high dielectric constant dielectric layer.

29. The method according to claim 28, further comprising etching the vertical stacked superlattice structure after annealing.

30. The method according to claim 29, wherein etching of the vertical stacked superlattice structure after annealing is configured to remove each of the first p-type dipole layer, the first p-type capping layer, the second p-type dipole layer, the second p-type capping layer, the first n-type dipole layer, the first n-type capping layer, the second n-type dipole layer, and the second p-type capping layer.

31. The method according to claim 21, wherein the first hGAA structure is a P-type metal-oxide-semiconductor (PMOS) transistor and the second hGAA structure is an N-type metal-oxide-semiconductor (NMOS) transistor.

32. The method according to claim 23, wherein each of the first p-type dipole layer and the second p-type dipole layer independently comprises one or more of aluminum oxide (AlOx), aluminum nitride (AlNx), or alloys thereof, and each of the first p-type capping layer and the second p-type capping layer independently comprises one or more of silicon (Si), silicon oxide (SiOx), aluminum oxide (AlOx), titanium nitride (TiN), or tantalum nitride (TaN).

33. The method according to claim 25, wherein each of the first n-type dipole layer and the second n-type dipole layer independently comprises one or more of lanthanum oxide (LaOx), lanthanum nitride (LaNx), or alloys thereof, and each of the first n-type capping layer and the second n-type capping layer independently comprises one or more of silicon (Si), silicon oxide (SiOx), aluminum oxide (AlOx), titanium nitride (TiN), or tantalum nitride (TaN).

34. The method according to claim 26, wherein each of the first protective layer, the second protective layer, and the third protective layer independently comprises a hard mask material.

35. It is an electronic device, First threshold voltage (V ｔ A first complementary field-effect transistor (CFET) region having ) The second V ｔ A second CFET region having, The third V ｔ A third CFET region having Equipped with, An electronic device in which each of the first CFET region, the second CFET region, and the third CFET region is formed on an interface layer on a vertical stacked superlattice structure on a substrate, and the vertical stacked superlattice structure includes a second horizontal gate all-around (hGAA) structure on an intermediate dielectric insulating (MDI) layer on a first horizontal gate all-around (hGAA) structure.

36. The electronic device according to claim 35, wherein the first CFET region includes a high dielectric constant dielectric layer on the interface layer, a first p-type dipole layer on the high dielectric constant dielectric layer, and a first p-type capping layer on the first p-type dipole layer.

37. The electronic device according to claim 36, wherein the second CFET region includes the high dielectric constant dielectric layer on the interface layer, the first p-type dipole layer on the high induction dielectric layer, the first p-type capping layer on the first p-type dipole layer, the second p-type dipole layer, and the second p-type capping layer on the second p-type dipole layer.

38. The electronic device according to claim 37, wherein the third CFET region includes the high dielectric constant dielectric layer on the interface layer, the first p-type dipole layer on the high induction dielectric layer, the first p-type capping layer on the first p-type dipole layer, the second p-type dipole layer, the second p-type capping layer on the second p-type dipole layer, the first n-type dipole layer on the exposed portion of the high dielectric constant dielectric layer on the second hGAA structure, the first n-type capping layer on the first n-type dipole layer, the second n-type dipole layer on the second hGAA structure, and the second n-type capping layer on the second n-type dipole layer.

39. The electronic device according to claim 38, wherein each of the first p-type dipole layer and the second p-type dipole layer independently comprises one or more of aluminum oxide (AlOx), aluminum nitride (AlNx), or alloys thereof, and each of the first n-type dipole layer and the second n-type dipole layer independently comprises one or more of lanthanum oxide (LaOx), lanthanum nitride (LaNx), or alloys thereof.

40. The electronic device according to claim 39, wherein each of the first p-type capping layer, the second p-type capping layer, the first n-type capping layer, and the second n-type capping layer independently comprises one or more of silicon (Si), silicon oxide (SiOx), aluminum oxide (AlOx), titanium nitride (TiN), or tantalum nitride (TaN).

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