Chiplet packaging for digitized interconnection and redistribution

Abstract

A method for forming a multi-chip module includes the steps of: molding a chipset in a medium to fix each chip relative to each other; mapping the positions and orientations of the chips inside the molded chipset based on alignment marks provided on each chip inside the molded chipset; forming an interconnection substrate, which includes forming a first interconnection layer on a base substrate and patterning the first interconnection layer to include a first plurality of patterned vias patterned at least partially based on the mapping; and joining the interconnection substrate to a multi-chip module, which includes positioning and aligning the interconnection substrate to the molded chipset so that the interconnection portions of each chip inside the molded chipset are aligned with the first plurality of patterned vias formed on the interconnection substrate.

Claims

1. A method for forming a multi-chip module, The steps include: molding the chipset in a medium to secure each chip to the others; A step of mapping the position and orientation of the chips inside the molded chipset based on alignment marks provided on each chip inside the molded chipset, A step of forming an interconnection substrate, Forming a first interconnection layer on the base substrate, The first interconnection layer is patterned to include a first plurality of patterned vias that are patterned at least partially based on the mapping. Steps including, A step of coupling the interconnection board to the multichip module, wherein the interconnection board is positioned and aligned with the molded chipset, and the interconnection portions of each chip inside the molded chipset are aligned with the first plurality of patterned vias formed on the interconnection board. A method that includes this.

2. The method according to claim 1, further comprising the step of forming metal interconnects within a first plurality of patterned vias.

3. The method according to claim 1, further comprising the step of forming a second interconnection layer on the first interconnection layer.

4. The method according to claim 1, further comprising the step of adhering the chipset to a temporary carrier before molding the chipset in the medium.

5. The method according to claim 1, wherein the chipset is attached to a temporary carrier by tape.

6. The method according to claim 1, wherein the step of mapping the position and orientation of the chips inside the molded chipset includes scanning and analyzing each alignment mark of each chip to determine the orientation and chip shift of each chip and storing the orientation and chip shift of each chip.

7. The method according to claim 3, wherein the first interconnection layer is a first redistribution layer (RDL), and the second interconnection layer is a second redistribution layer (RDL).

8. The method according to claim 1, wherein the first plurality of patterned vias are formed penetrating the first interconnection layer and the base substrate.

9. A method for forming a multi-chip module, A step of forming an alignment mark set on a die set to be integrated into a multichip module, wherein the die set comprises a first die unit having a first die and a second die unit having a second die, and each die having at least one alignment mark, The steps include: molding the die set in a medium in order to fix each die relative to each other; The steps include mapping the alignment marks of each die in the die set molded within the medium, A step of forming an interconnection substrate, Forming a first interconnection layer on the base substrate, The first interconnection layer is patterned to include a first plurality of patterned vias that are at least partially patterned based on the mapping. Steps including, The steps include dicing the interconnection board into individual interconnection board units, each including a first interconnection board unit corresponding to the first die unit and a second interconnection board unit corresponding to the second die unit, The steps of coupling the first interconnection board unit to the first die unit and coupling the second interconnection board unit to the second die unit A method that includes this.

10. The method according to claim 9, further comprising the step of forming metal interconnects within a first plurality of patterned vias.

11. The method according to claim 9, further comprising the step of forming a second interconnection layer on the first interconnection layer.

12. The method according to claim 11, wherein the first interconnection layer is a first redistribution layer (RDL), and the second interconnection layer is a second RDL.

13. The method according to claim 9, further comprising the step of adhering the chipset to a temporary carrier before molding the chipset in the medium.

14. The method according to claim 9, wherein the chipset is attached to a temporary carrier by tape.

15. The method according to claim 9, wherein the step of mapping each alignment mark of each die in the die set includes scanning and analyzing each alignment mark of each die to determine the orientation and die shift of each die and storing the orientation and die shift of each die.

16. The method according to claim 9, wherein the first plurality of patterned vias are formed penetrating the first interconnection layer and the base substrate.

17. A packaged multi-chip module, A chipset molded within a medium, wherein each chip has at least one alignment mark, An interconnection substrate coupled to the chipset, comprising: a first interconnection layer formed on a base substrate; and a first plurality of patterned vias formed through the base substrate and the first interconnection layer, patterned based on the position and orientation of the chip determined at least partially based on the mapping of each alignment mark; A packaged multi-chip module equipped with the following features.

18. The packaged multichip module according to claim 17, further comprising forming a second interconnection layer formed on the first interconnection layer.

19. The packaged multichip module according to claim 18, wherein the first interconnection layer is a first redistribution layer (RDL), and the second interconnection layer is a second RDL.

20. The packaged multichip module according to claim 17, wherein the medium includes a tape.

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