Formation of an insulating module for back-side power supply applications

Abstract

This document describes a semiconductor device and a method for manufacturing the same. The method includes combining selective recessing of a sacrificial layer and isotropic etching of a silicon layer to form a protective cap that can etch the silicon layer of a substrate without affecting the sacrificial layer.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to semiconductor devices. More particularly, embodiments of the present disclosure are directed to gate-all-around (GAA) devices, FinFET devices, and CFET devices that include a dielectric material instead of a silicon substrate to form an insulating module for backside power supply applications.

Background Art

[0002] Transistors are an important component of most integrated circuits. Since the drive current of a transistor, and thus its speed, is proportional to the gate width of the transistor, high-speed transistors generally require a large gate width. Thus, there is a trade-off between the size and speed of a transistor, and "fin" field-effect transistors (finFETs) have been developed to address the conflicting goals of a transistor having maximum drive current and minimum size. FinFETs are characterized by a fin-shaped channel region that significantly increases the transistor size without significantly increasing the mounting area of the transistor, and are currently applied to many integrated circuits. However, finFETs have their own drawbacks.

[0003] Since the feature size of transistor devices continues to shrink to achieve improvements in circuit density and performance, it is necessary to improve the transistor device structure to improve electrostatic coupling and reduce adverse effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field-effect transistor (FinFET) structures, gate-all-around (GAA) structures, and the like. The GAA device structure includes several lattice-matched channels suspended in a stack configuration and connected at the source / drain regions. The GAA structure provides good electrostatic control and is widely adopted in complementary metal-oxide-semiconductor (CMOS) wafer manufacturing.

[0004] In back-side power delivery (BSPDN) architectures, silicon (Si) substrates must be replaced with dielectric materials to prevent short-circuit mechanisms between adjacent contacts. Since silicon-germanium (SiGe) is required as a placeholder for direct contacts on the back surface, selectively removing silicon (Si) from silicon-germanium (SiGe) is extremely difficult. Therefore, improved semiconductor devices and manufacturing methods are needed. [Overview of the Initiative]

[0005] One or more embodiments of the present disclosure relate to methods for forming semiconductor devices. In one or more embodiments, the method for forming a semiconductor device includes forming a recessed region by recessing a sacrificial layer in a silicon layer of a substrate, wherein the substrate is formed on a channel including a superlattice structure, the superlattice structure is on a shallow trench isolation on the substrate, and the channel is on a gate, forming a recessed region by recessing a sacrificial layer in a silicon layer of a substrate, forming a first opening by isotropically etching the silicon layer, depositing a cap layer in the first opening, removing the silicon layer to form a second opening, depositing a fluidized layer in the second opening, removing the cap layer and the sacrificial layer to form a third opening, and forming a back surface contact metallization in the third opening.

[0006] Additional embodiments of the present disclosure relate to methods for forming semiconductor devices. In one or more embodiments, a method for forming a semiconductor device includes forming a recessed region by recessing a sacrificial layer in a silicon layer of a substrate, wherein the substrate is formed on a channel including a superlattice structure, the superlattice structure is on a shallow trench isolation on the substrate, and the channel is on a gate, forming a recessed region by recessing a sacrificial layer in a silicon layer of a substrate, forming a first opening by isotropically etching the silicon layer, depositing a cap layer in the first opening, partially removing the silicon layer to form a second opening, oxidizing the remaining silicon layer to form an oxidized silicon layer, optionally depositing a conformal liner in the second opening, depositing a fluidized layer in the second opening on the oxidized silicon layer or the optionally conformal liner, removing the cap layer and the sacrificial layer to form a third opening, and forming a back-surface contact metallization in the third opening.

[0007] Further embodiments of the present disclosure relate to semiconductor devices. In one or more embodiments, the semiconductor device includes a recessed sacrificial layer of a substrate, wherein the substrate is formed on channels including a superlattice structure, the superlattice structure is on shallow trench isolations on the substrate, and the channels are on gates; a capping layer on the recessed sacrificial layer; and a fluidized layer adjacent to the recessed sacrificial layer.

[0008] A more detailed description of the Disclosure, which is briefly summarized above, can be obtained by referring to embodiments, some of which are shown in the accompanying drawings, so that the above features of the Disclosure may be understood in more detail. However, it should be noted that the accompanying drawings show only typical embodiments of the Disclosure and should not be considered limiting in scope, as the Disclosure may permit other equally effective embodiments. [Brief explanation of the drawing]

[0009] [Figure 1] Process flow diagram of a method according to one or more embodiments [Figure 2] Cross-sectional view of a semiconductor device according to one or more embodiments. [Figure 3] Cross-sectional view of a semiconductor device according to one or more embodiments. [Figure 4] Cross-sectional view of a semiconductor device according to one or more embodiments. [Figure 5] Cross-sectional view of a semiconductor device according to one or more embodiments. [Figure 6] Cross-sectional view of a semiconductor device according to one or more embodiments. [Figure 7] Cross-sectional view of a semiconductor device according to one or more embodiments. [Figure 8] Cross-sectional view of a semiconductor device according to one or more embodiments. [Figure 9] Cross-sectional view of a semiconductor device according to one or more embodiments. [Figure 10] Cross-sectional view of a semiconductor device according to one or more embodiments. [Figure 11] Cross-sectional view of a semiconductor device according to one or more embodiments. [Figure 12] Diagram showing a cluster tool in one or more embodiments. [Modes for carrying out the invention]

[0010] For ease of understanding, the same reference numeral is used to indicate identical elements common to multiple drawings, where possible. The drawings are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment can be usefully incorporated into other embodiments without further description.

[0011] Before describing some exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the configuration or process details described below. Other embodiments of this disclosure are possible and can be implemented or performed in a variety of ways.

[0012] As used herein and in the appended claims, the term “substrate” is used to refer to a surface or portion of a surface on which processing is performed. It will also be understood by those skilled in the art that a reference to a substrate may refer to only a portion of the substrate unless otherwise explicitly stated in the context. Furthermore, a reference to deposition on a substrate may mean both a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0013] As used herein, “substrate” means any substrate or material surface formed on such substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatment can be performed include, depending on the application, materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. Substrates may be subjected to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate (or otherwise generate or graft a target chemical portion to impart chemical functionality), anneal, and / or bake the substrate surface. In addition to film treatment directly on the surface of the substrate itself, any film treatment process disclosed herein may also be performed on underlayment formed on the substrate, as disclosed in more detail below, and the term “substrate surface” is intended to include such underlayment, as the context indicates. Therefore, for example, when a film / layer or partial film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface. What constitutes a given substrate surface depends on which film is deposited and the specific chemicals used.

[0014] As used herein and in the appended claims, terms such as “precursor,” “reactant,” and “reactive gas” are interchangeable to refer to any gaseous species capable of reacting with the substrate surface.

[0015] Epitaxy is a process that highly crystallographically matches a deposited film to a substrate. In a broad sense, epitaxial growth is defined as forming a film on a substrate by condensing a gaseous precursor. Liquid precursors can also be used. Vapor precursors can be obtained by chemical vapor deposition (CVD) and laser ablation. Several epitaxy techniques are currently available, including molecular beam epitaxy (MBE), epitaxial CVD, or atomic layer epitaxy (ALE).

[0016] A transistor is a circuit component or element that is often formed on a semiconductor device. Depending on the circuit design, a transistor is formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive wires, or other elements. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doped regions of the substrate and exhibit a doping profile suitable for a particular application. The gate is located above the channel region and includes a gate dielectric interposed between the gate electrode and the channel region of the substrate.

[0017] As used herein, the term “field-effect transistor” or “FET” refers to a transistor that uses an electric field to control the electrical behavior of a device. Enhancement-mode field-effect transistors generally exhibit very high input impedance at low temperatures. Conductivity between the drain and source terminals is controlled by the electric field within the device, which is generated by the voltage difference between the body and gate of the device. The three terminals of an FET are the source (S) where carriers enter the channel, the drain (D) where carriers exit the channel, and the gate (G), which is the terminal that adjusts the conductivity of the channel. Typically, the current entering the channel at the source (S) is I S It is specified that the current entering the channel at the drain (D) is I D It is specified as follows. The voltage from drain to source is V DSis specified. By applying a voltage to the gate (G), the current flowing into the channel at the drain (i.e., I D ) can be controlled.

[0018] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate, and its conductivity is determined by the voltage. This function of changing conductivity according to the amount of applied voltage is used for amplifying or switching electronic signals. The MOSFET is based on the modulation of the charge concentration by the metal-oxide-semiconductor (MOS) capacitance between the body electrode and the gate electrode located on the body and insulated from all other device regions by the gate dielectric layer. Compared with the MOS capacitor, the MOSFET has two additional terminals (source and drain), each connected to an individual highly doped region separated by the body region. These regions are either p-type or n-type, but both are of the same type and of the opposite type to the body region. The source and drain are (unlike the body) highly doped, and a "+" symbol is appended after the type of doping.

[0019] When the MOSFET is an n-type channel or an nMOS FET, the source and drain are n+ regions, and the body is a p region. When the MOSFET is a p-type channel or a pMOS FET, the source and drain are p+ regions, and the body is an n region. The source is so called because it is the source of the charge carriers flowing through the channel (electrons in the case of an n-type channel and holes in the case of a p-type channel); similarly, the drain is the place where the charge carriers exit the channel.

[0020] As used herein, the term "Fin-field-effect transistor (FinFET)" refers to a MOSFET transistor built on a substrate in which the gate is located on two or three sides of the channel, forming a double-gate or triple-gate structure. FinFET devices are given the common name FinFET because the channel region forms "fins" on the substrate. FinFET devices have fast switching times and high current densities.

[0021] As used herein, the term “gate all around (GAA)” is used to refer to an electronic device, such as a transistor, in which the gate material surrounds the channel region on all sides. The channel region of a GAA transistor may include nanowires, or nanoslabs, or nanosheets, bar-shaped channels, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device has a plurality of vertically spaced horizontal nanowires or horizontal bars, and the GAA transistor becomes a stacked horizontal gate all around (hGAA) transistor.

[0022] An example of gate-all-around (GAA) technology is the complementary field-effect transistor (CFET). As used herein, the term "complementary field-effect transistor (CFET)" refers to a transistor comprising NMOS FET devices and PMOS FET devices stacked together. The NMOS FET devices and PMOS FET devices constituting the CFET are, respectively, GAA transistors or hGAA transistors. Compared to GAA transistors, CFET transistors have increased on-chip device density and reduced area consumption.

[0023] As used herein, the term "nanowire" refers to a wire with a diameter of nanometers (10⁻¹⁰ -9This refers to nanostructures approximately 1000 nanometers in size. Nanowires can also be defined as structures with a length-to-width ratio greater than 1000. Alternatively, nanowires can be defined as structures whose thickness or diameter is limited to tens of nanometers or less, and whose length is not limited. Nanowires are used in transistors and certain laser applications, and in one or more embodiments, they are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in logic CPUs, GPUs, MPUs, and transistors for volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term “nanosheet” refers to two-dimensional nanostructures having a thickness on a scale ranging from about 0.1 nm to about 1000 nm.

[0024] Embodiments of the present disclosure are illustrated by drawings, which show devices (e.g., transistors) and processes for forming transistors according to one or more embodiments of the present disclosure. The processes shown are merely illustrative possible uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the illustrated uses.

[0025] One or more embodiments of this disclosure will be described with reference to the drawings. Methods of one or more embodiments are used to manufacture transistors such as gate-all-around transistors, FinFETs, and CFETs. One or more embodiments advantageously combine selective recessing of the sacrificial layer with isotropic etching of the silicon layer to form a protective cap that can etch the silicon layer of the substrate without affecting the sacrificial layer. Formation of the protective cap is essential in one or more embodiments.

[0026] Figure 1 shows a process flow diagram of method 10 for forming a semiconductor device according to some embodiments of the present disclosure. Figures 2 to 11 show the steps for manufacturing a semiconductor structure according to the process flow of Figure 1.

[0027] Method 10 for forming a semiconductor device will be described with reference to Figures 2 to 11, which are cross-sectional views of a semiconductor device (e.g., GAA) according to one or more embodiments. Method 10 in Figure 1 may be part of a multi-step manufacturing process for a semiconductor device. Thus, Method 10 in Figure 1 can be carried out in any suitable processing chamber connected to a cluster tool. The cluster tool may comprise processing chambers for manufacturing a semiconductor device, such as chambers configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, and epitaxy, or any other suitable chambers used in the manufacture of a semiconductor device.

[0028] Referring to Figure 1, the method 10 for forming the semiconductor device 100 begins with step 12, which involves planarizing the silicon layer of the substrate against shallow trench isolation (STI). In step 14, the sacrificial layer is recessed against the silicon layer of the substrate and the STI. In step 16, the silicon substrate is isotropically etched. In step 18, a cap is formed. In step 20, the silicon layer of the substrate is etched to form an opening. In step 22, the remaining silicon layer is optionally oxidized. In step 24, a liner layer is optionally deposited in the opening. In step 26, a fluid material is filled into the opening. In step 28, the fluid material is compacted using high-density plasma (HDP) treatment. In step 30, the cap and sacrificial layer are removed to form a cavity. In step 32, the cavity is filled with back-surface contact metallization.

[0029] Referring to Figures 2 to 11, in one or more embodiments, at least one superlattice structure 101 is formed on the substrate 102. The superlattice structure 101 includes a plurality of semiconductor material layers and a plurality of corresponding horizontal channel layers, which are alternately arranged in a plurality of stacked pairs 116. In some embodiments, the plurality of stacked layer groups include silicon (Si) groups and silicon germanium (SiGe) groups. In some embodiments, the plurality of semiconductor material layers include silicon germanium (SiGe) and the plurality of horizontal channel layers include silicon (Si). In other embodiments, the plurality of horizontal channel layers include silicon germanium (SiGe) and the plurality of semiconductor material layers include silicon (Si).

[0030] In some embodiments, the plurality of semiconductor material layers and the corresponding plurality of horizontal channel layers may include any number of pairs of lattice-matched materials suitable for forming the superlattice structure 101. In some embodiments, the plurality of semiconductor material layers and the corresponding plurality of horizontal channel layers include about 2 pairs to about 50 pairs of lattice-matched materials.

[0031] In one or more embodiments, the thicknesses of the multiple semiconductor material layers and the multiple horizontal channel layers are in the range of approximately 2 nm to approximately 50 nm, approximately 3 nm to approximately 20 nm, or approximately 2 nm to approximately 15 nm.

[0032] Referring to Figures 1 and 2, the shallow trench isolation (STI) 104 is formed adjacent to the substrate containing the silicon layer 102 and the sacrificial layer 106. As used herein, the term “shallow trench isolation (STI)” refers to an integrated circuit function that prevents current leakage. In one or more embodiments, the STI is produced by depositing one or more dielectric materials (such as silicon dioxide) to fill a trench or opening and removing the excess dielectric using a technique such as chemomechanical planarization.

[0033] Referring to Figures 2 to 11, in some embodiments, a dummy gate structure 113 is formed adjacent to the superlattice structure 101. The dummy gate structure 113 defines the channel region of the transistor device. The dummy gate structure 113 can be formed using any suitable conventional deposition and patterning process known in the art.

[0034] In one or more embodiments, the dummy gate structure 113 comprises one or more of the gate material 114 and the polysilicon layer 112. In one or more embodiments, the gate material 114 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the gate material 114 comprises one or more of tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum (TiAl), and n-type doped polysilicon. In some embodiments, the dummy gate structure 113 may also comprise a dielectric layer between the superlattice structure and the polysilicon layer 112.

[0035] Referring to Figures 2 to 11, in one or more embodiments, the source / drain 110 is formed adjacent to (i.e., on either side of) the superlattice structure 101. In some embodiments, the source 110 region is formed adjacent to a first end of the superlattice structure 101, and the drain 110 is formed adjacent to a second opposing end of the superlattice structure 101. In some embodiments, the source / drain 110 region is formed from any suitable semiconductor material, including but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon phosphorus (SiP), and silicon arsenic (SiAs). In some embodiments, the source / drain 110 region can be formed using any suitable deposition process, such as an epitaxial deposition process. In some embodiments, the source / drain 110 region is independently doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga).

[0036] Referring to Figures 1 and 2, in step 12, the substrate 102 is planarized to the shallow trench isolation 104. Planarization may be any suitable planarization process known to those skilled in the art, including but not limited to chemical mechanical planarization (CMP).

[0037] In some embodiments, the substrate 102 may be a bulk semiconductor substrate. As used herein, the term “bulk semiconductor substrate” refers to a substrate in which the entire substrate is composed of semiconductor material. A bulk semiconductor substrate can be composed of any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> The materials may include one or more materials, such as strained silicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). While some examples of materials that can form substrates are described herein, any material that can serve as a basis on which passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) can be constructed is within the spirit and scope of this disclosure.

[0038] In some embodiments, the material of the semiconductor substrate 102 may be a doped material such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In some embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. As used herein, the term “n-type” refers to a semiconductor produced by doping an intrinsic semiconductor with an electron donor element during manufacturing. The term n-type derives from the negative charge of electrons. In n-type semiconductors, electrons are majority carriers and holes are minority carriers. As used herein, the term “p-type” refers to the positive charge of wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a hole concentration greater than the electron concentration. In p-type semiconductors, holes are majority carriers and electrons are minority carriers. In one or more embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or combinations thereof.

[0039] In one or more embodiments, the sacrificial layer 106 is adjacent to the semiconductor substrate 102 material. The sacrificial layer 106 may include any suitable material known to those skilled in the art. In some embodiments, the sacrificial layer includes one or more of the following: silicon germanium (SiGe), metal, amorphous carbon, etc. In certain embodiments, the sacrificial layer includes silicon germanium (SiGe).

[0040] Referring to Figures 1 and 3, in step 14, the sacrificial layer 106 is recessed relative to the silicon layer 102 of the substrate to form a recessed region 122. In one or more embodiments, the recessed region 122 has a depth in the range of 2 nm to 50 nm, or 2 nm to 40 nm, or 2 nm to 30 nm, or 2 nm to 20 nm, or 2 nm to 15 nm, or 2 nm to 10 nm, or 2 nm to 7 nm, or 2 nm to 5 nm.

[0041] Referring to Figures 1 and 4, in step 16, the silicon layer 102 is isotropically etched to form an opening 124 including a recessed region 122 and the etched portion of the silicon layer 102. In one or more embodiments, the opening 124 has a critical dimension (CD) in the range of 2 nm to 60 nm, including the range of 2 nm to 50 nm, the range of 2 nm to 40 nm, the range of 2 nm to 30 nm, the range of 2 nm to 25 nm, the range of 2 nm to 20 nm, the range of 2 nm to 15 nm, the range of 2 nm to 10 nm, and the range of 2 nm to 5 nm.

[0042] Referring to Figures 1 and 5, in step 18, the cap layer 126 is deposited on the opening 124. The cap layer may contain any suitable material known to those skilled in the art. In one or more embodiments, the cap layer contains one or more of the following: silicon nitride (SiN), amorphous carbon, silicon oxynitride (SiON), aluminum oxide (AlOx), etc.

[0043] Referring to Figures 1 and 6, in step 20, the silicon layer 102 is etched to form the opening 128. In some embodiments, the silicon layer 102 is completely removed by SRP etching to form the opening 128. In other embodiments, as shown in Figure 6, the silicon layer 102 is anisotropically etched so that a portion of the silicon layer 102 remains. A silicon oxide layer 102 of any suitable thickness can be left behind. In one or more embodiments, the remaining portion of the silicon oxide layer 102 has a thickness ranging from 3 nm to 5 nm.

[0044] The opening 128 can be formed by any suitable means known to those skilled in the art. In some embodiments, the etching process of step 20 includes one or more wet etching processes or dry etching processes. The etching process may be directional etching.

[0045] In some embodiments, the dry etching process may include conventional plasma etching or a remote plasma-assisted dry etching process. In one or more embodiments of the remote plasma-assisted dry etching process, the device is exposed to H2, NF3, and / or NH3 plasma species, e.g., plasma-excited hydrogen and fluorine species. For example, in some embodiments, the device may be exposed to H2, NF3, and NH3 plasmas simultaneously. The remote plasma-assisted dry etching process can be carried out in a pre-cleaning chamber, which can be integrated into one of various multi-processing platforms known to those skilled in the art. The wet etching process may include a hydrofluoric acid (HF) rust process, i.e., a so-called "HF rust" process, in which the surface is HF-etched and the surface becomes hydrogen-terminated. Alternatively, any other liquid-based epitaxial pre-cleaning process may be employed. In some embodiments, the process includes sublimation etching to remove native oxides. The etching process may be plasma-based or thermal-based. The plasma process may be any suitable plasma (e.g., conduction-coupled plasma, inductively coupled plasma, microwave plasma).

[0046] Referring to Figures 1 and 7, in step 22, the remaining portion of the silicon layer 102 is oxidized to form the oxide layer 130. The remaining portion of the silicon layer 102 can be oxidized by any suitable method known to those skilled in the art. In one or more embodiments, the remaining silicon layer 102 can be oxidized at a temperature above 400°C using a rapid thermal oxidation (RTO) process.

[0047] Referring to Figure 1, in step 24, a conformal liner (not shown) is optionally deposited on the opening 128 on the oxide layer 130. The conformal liner may include any suitable material known to those skilled in the art. In one or more embodiments, the conformal liner includes one or more of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), etc. The conformal liner may have any suitable thickness. In one or more embodiments, the conformal liner has a thickness in the range of 1 nm to 20 nm.

[0048] Referring to Figures 1 and 8, in step 26, the fluid material 132 is deposited in the opening 128. In embodiments in which the conformal liner is first deposited in step 24, the fluid material 132 is deposited in the opening 128 on the conformal liner. The fluid material 132 may include any suitable material known to those skilled in the art. In one or more embodiments, the fluid material 132 includes one or more of silicon oxide (SiOx), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxycarbonitride (SiOCN), etc. In one or more specific embodiments, the fluid material 132 includes silicon oxide (SiOx).

[0049] In one or more embodiments not shown, in step 28 of Figure 1, the fluid material 132 is compacted using high-density plasma (HDP) treatment and then planarized, for example by chemical mechanical polishing (CMP) to form a top surface equivalent to the STI layer 104.

[0050] Referring to Figures 1 and 9, in step 30, the cap layer 126 is removed to form an opening 134. The opening 134 exposes the upper surface of the sacrificial layer 106.

[0051] As shown in Figures 1 and 10, in step 30, the sacrificial layer 106 is removed to form a cavity 136. The cavity 136 can be molded and processed as needed.

[0052] Referring to Figures 1 and 11, in step 32, a back-contact metallization is performed in which one or more of the metal layer 138 and the metal fill 140 are deposited. The back-contact metallization may include any suitable material known to those skilled in the art. In one or more embodiments, the back-contact metallization, for example, the metal layer 138 and the metal fill 140 may include one or more of tungsten (W), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), ruthenium (Ru), and copper (Cu).

[0053] In one or more embodiments, the method 10 shown in Figure 1 manufactures a gate-all-around (GAA device). The intermediate device includes a recessed sacrificial layer 106 of the substrate. The substrate is formed on a channel 101 which includes a superlattice structure, the superlattice structure 101 which is on shallow trench isolation 104 on the substrate, and the channel which is on a gate 113. In one or more embodiments, a capping layer 126 is on the recessed sacrificial layer 106. A fluidized layer 132 is adjacent to the recessed sacrificial layer 106. After the capping layer 126 and the recessed sacrificial layer 106 are removed, back-surface contact metallizations 138, 140 are formed.

[0054] Additional embodiments of this disclosure, as shown in Figure 12, relate to a processing tool 300 for forming the GAA device and method described. Various multiprocessing platforms known to those skilled in the art can be utilized. The cluster tool 300 includes at least one central transfer station 314 having multiple sides. A robot 316 is positioned within the central transfer station 314 and configured to move robotic blades and wafers to each of the multiple sides.

[0055] The cluster tool 300 includes a number of processing chambers 308, 310, and 312, also called processing stations, connected to a central transfer station. The various processing chambers provide separate processing areas isolated from adjacent processing stations. The processing chambers may include, but are not limited to, pre-washing chambers, deposition chambers, annealing chambers, etching chambers, and any other suitable chamber. The specific arrangement of processing chambers and components may be modified depending on the cluster tool and should not be construed as limiting the scope of this disclosure.

[0056] In the embodiment shown in Figure 12, the factory interface 318 is connected to the front of the cluster tool 300. The factory interface 318 includes a loading and unloading chamber 302 on the front 319 of the factory interface 318.

[0057] The size and shape of the loading and unloading chambers 302 may vary, for example, depending on the substrates being processed in the cluster tool 300. In the shown embodiment, the loading and unloading chambers 302 are sized to hold a wafer cassette in which multiple wafers are positioned within the cassette.

[0058] Robot 304 is located within the factory interface 318 and can move between the loading chamber and the unloading chamber 302. Robot 304 can transfer wafers from the cassette in the loading chamber 302 to the load lock chamber 320 via the factory interface 318. Robot 304 can also transfer wafers from the load lock chamber 320 to the cassette in the unloading chamber 302 via the factory interface 318.

[0059] In some embodiments, the robot 316 is a multi-arm robot capable of independently moving multiple wafers at once. The robot 316 is configured to move wafers between chambers around a transfer chamber 314. Each wafer is carried on a wafer transport blade located at the distal end of the first robot mechanism.

[0060] The system controller 357 communicates with the robot 316 and the multiple processing chambers 308, 310, and 312. The system controller 357 can be any suitable component capable of controlling the processing chambers and the robot. For example, the system controller 357 may be a computer including a central processing unit (CPU) 392, memory 394, input / output 396, suitable circuitry 398, and storage.

[0061] The process, when executed by a processor, can generally be stored in the memory of the system controller 357 as a software routine that causes a processing chamber to execute the process of the present disclosure. The software routine can also be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure can also be executed in hardware. Thus, the processing may be implemented in software, and the processing may be executed, for example, by using a computer system in hardware as an application-specific integrated circuit or other kind of hardware implementation or a combination of software and hardware. When executed by a processor, the software routine transforms a general-purpose computer into an application-specific computer (controller) that controls the process of the chamber so that the process can be executed.

[0062] In some embodiments, the system controller 357 is configured to control the rapid heat treatment chamber to crystallize the template material.

[0063] In one or more embodiments, the processing tool includes a central transfer station including a robot configured to move wafers, a plurality of processing stations, each processing station connected to the central transfer station and providing a processing area separated from the processing areas of adjacent processing stations, the plurality of processing stations including recessed chambers, etching chambers, and deposition chambers, and controllers connected to the central transfer station and the plurality of processing stations, the controllers configured to activate the robot to move wafers between processing stations and to control the processing performed at each of the processing stations.

[0064] The terms “a,” “an,” and “the,” and similar references in the context describing the materials and methods discussed herein (in particular, in the context of the following claims), should be interpreted as encompassing both singular and plural forms unless otherwise stated herein or unless clearly contradicted by the context. The enumeration of value ranges herein is intended merely as a simple way to refer individually to each individual value falling within the range, unless otherwise stated herein, and each individual value is incorporated herein as if it were individually stated herein. All methods described herein may be carried out in any suitable order unless otherwise stated herein or unless clearly contradicted by the context. Any and all examples or illustrative language provided herein (e.g., “etc.”) are intended merely to further clarify the materials and methods and do not impose limitations on the claims unless specifically stated otherwise. Nothing in the specification should be interpreted as indicating that non-claimed elements are essential to the carrying out of the disclosed materials and methods.

[0065] Throughout this specification, any reference to “one embodiment,” “a particular embodiment,” “one or more embodiments,” or “embodiments” means that any particular feature, structure, material, or property described in relation to an embodiment is included in at least one embodiment of this disclosure. Therefore, any other expression such as “in one or more embodiments,” “in one embodiment,” “in one embodiment,” or “in an embodiment” found elsewhere in this specification does not necessarily refer to the same embodiment of this disclosure. Furthermore, any particular feature, structure, material, or property may be combined in any suitable manner in one or more embodiments.

[0066] While the disclosures herein are described with reference to specific embodiments, it will be understood that the embodiments described are merely illustrative of the principles and uses of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Accordingly, the disclosure may include modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

1. A method for forming a semiconductor device, A method for forming a recessed region by recessing a sacrificial layer in the silicon layer of a substrate, wherein the substrate is formed on a channel including a superlattice structure, the superlattice structure is on a shallow trench isolation on the substrate, and the channel is on a gate, wherein a sacrificial layer is recessed in the silicon layer of a substrate to form a recessed region. The silicon layer is etched isotropically to form a first opening. A cap layer is deposited in the first opening. To remove at least a portion of the silicon layer to form a second opening, A fluidized bed is deposited in the second opening. To remove the cap layer and the sacrificial layer to form a third opening, and Forming back surface contact metallization in the third opening. A method for forming a semiconductor device, including [a specific component].

2. The method according to claim 1, wherein the silicon layer is completely removed.

3. The method according to claim 1, further comprising depositing a conformal liner before depositing the fluidized bed, wherein the conformal liner comprises one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon oxycarbonitride, and has a thickness in the range of 1 nm to 20 nm.

4. The method according to claim 1, wherein the silicon layer is partially removed and a portion of the silicon layer remains.

5. The method according to claim 4, further comprising oxidizing the remaining silicon layer.

6. The method according to claim 1, wherein the superlattice structure includes a plurality of horizontal channel layers and a plurality of corresponding semiconductor material layers arranged alternately in a plurality of stacked pairs.

7. The method according to claim 1, wherein the sacrificial layer comprises one or more of the following: silicon germanium (SiGe), metal, amorphous carbon, etc.

8. The method according to claim 1, wherein the cap layer comprises one or more of silicon nitride (SiN), amorphous carbon, silicon oxynitride (SiON), aluminum oxide (AlOx), and the like.

9. The method according to claim 1, wherein the recessed region has a depth in the range of 2 nm to 30 nm, and the first opening has a critical dimension in the range of 2 nm to 60 nm.

10. The method according to claim 1, wherein the gate comprises one or more of tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum (TiAl), and n-type doped polysilicon, and the fluidized bed comprises one or more of silicon oxide (SiOx), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxycarbonitride (SiOCN), and the like.

11. The method according to claim 1, wherein the method is carried out in a processing chamber without disrupting the vacuum.

12. The method according to claim 1, wherein the back surface contact metallization includes one or more of tungsten (W), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), ruthenium (Ru), and copper (Cu).

13. The method according to claim 1, wherein the semiconductor device includes one or more of gate-all-around, FinFET, and CFET.

14. A method for forming a semiconductor device, A method for forming a recessed region by recessing a sacrificial layer in the silicon layer of a substrate, wherein the substrate is formed on a channel including a superlattice structure, the superlattice structure is on a shallow trench isolation on the substrate, and the channel is on a gate, wherein a sacrificial layer is recessed in the silicon layer of a substrate to form a recessed region. The silicon layer is etched isotropically to form a first opening. A cap layer is deposited in the first opening. The silicon layer is partially removed to form a second opening. The remaining silicon layer is oxidized to form an oxidized silicon layer. Optionally depositing a conformal liner in the second opening, A fluidized bed is deposited in the second opening on the oxidized silicon layer. To remove the cap layer and the sacrificial layer to form a third opening, and Forming back surface contact metallization in the third opening. A method for forming a semiconductor device, including [a specific component].

15. The method according to claim 14, wherein the recessed region has a depth in the range of 2 nm to 30 nm.

16. The method according to claim 15, wherein the first aperture has a critical dimension in the range of 2 nm to 60 nm.

17. The method according to claim 14, wherein the sacrificial layer comprises one or more of silicon germanium (SiGe), metal, amorphous carbon, etc., the cap layer comprises one or more of silicon nitride (SiN), amorphous carbon, silicon oxynitride (SiON), aluminum oxide (AlOx), etc., the fluidized bed comprises one or more of silicon oxide (SiOx), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxycarbonitride (SiOCN), etc., and the back surface contact metallization comprises one or more of tungsten (W), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), ruthenium (Ru), and copper (Cu).

18. It is a semiconductor device, A recessed sacrificial layer for a substrate, wherein the substrate is formed on a channel including a superlattice structure, the superlattice structure is on a shallow trench isolation on the substrate, the channel is on a gate, and the sacrificial layer contains one or more of silicon germanium (SiGe), metal, amorphous carbon, etc. A cap layer on the recessed sacrificial layer, comprising one or more of silicon nitride (SiN), amorphous carbon, silicon oxynitride (SiON), aluminum oxide (AlOx), and A fluidized bed adjacent to the recessed sacrificial layer, comprising one or more of the following: silicon oxide (SiOx), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxycarbonitride (SiOCN), etc. A semiconductor device equipped with these features.

19. The device according to claim 18, further comprising a conformal liner adjacent to the fluidized bed, wherein the conformal liner comprises one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon oxycarbonitride (SiOCN), and has a thickness in the range of 1 nm to 20 nm.

20. The device according to claim 18, wherein the semiconductor device includes one or more of gate-all-around, FinFET, and CFET.

Images