Integrated cooling assembly including signal rewiring and method for manufacturing the same
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC
- Filing Date
- 2024-05-16
- Publication Date
- 2026-06-09
AI Technical Summary
【0032】 以下の詳細な説明を添付図面と共に検討することにより、本開示の上記の及びその他の目的及び利点が明らかになるであろう。
Smart Images
Figure 2026518689000001_ABST
Abstract
Claims
1. It is a device package, A semiconductor device having an active side and a back surface opposite to the active side, Multiple stacked and joined layers, The plurality of stacked and joined layers are provided, A first side having a base surface, a support feature extending downward from the base surface, and a side wall extending downward from the base surface and surrounding the base surface and the support feature, and a second side opposite to the first side, A first interconnection portion is arranged vertically through the aforementioned support feature, The first interconnection portion is electrically coupled to the semiconductor device through a direct hybrid junction formed between the first side of the plurality of stacked bonded layers and the semiconductor device. Device package.
2. The aforementioned multiple stacked and joined layers collectively form a cold plate. The device package according to claim 1.
3. The first side of the cold plate and the back surface of the semiconductor device define a coolant channel between them. The device package according to claim 2.
4. The semiconductor device and the plurality of stacked and bonded layers are part of an integrated cooling assembly. The device package according to claim 1.
5. One or more first layers of the plurality of stacked and joined layers include the side walls and support features, The second layer of the plurality of stacked and joined layers is positioned between the base surface and the second side. The second layer includes a second interconnection portion that is perpendicularly positioned through the second layer, The first and second interconnection portions are electrically coupled through a direct hybrid junction formed between the one or more first layers and the second layer. The device package according to claim 1.
6. The aforementioned multiple stacked and joined layers include a power surface and / or a ground surface. The device package according to claim 1.
7. The first interconnection unit connects the semiconductor device to at least one of the power plane or the ground plane. The device package according to claim 6.
8. The support feature has a width that decreases from the base surface to the interface between the first side of the plurality of stacked and bonded layers and the semiconductor device. The device package according to claim 1.
9. The side walls of the aforementioned multiple stacked and joined layers are inclined. The device package according to claim 1.
10. The plurality of stacked and joined layers include a stack of the first layer, Each of the first layers includes a segment of the first interconnection, Each segment of the first interconnect is connected to another vertically adjacent segment of the first interconnect through a direct hybrid joint formed between the first layers. The device package according to claim 1.
11. Microelectronic package, A first side having a base surface, a side wall surrounding the base surface and extending downward from the base surface to define a cavity, and a support feature disposed within the cavity, and a second side opposite to the first side, A first interconnection portion is arranged vertically through the aforementioned support feature, It comprises multiple stacked and joined layers, The first interconnection portion is electrically coupled to the device through a direct hybrid bond formed between the first side and the back surface of the device. The first side of the plurality of stacked and joined layers and the back surface of the device define a coolant channel between them. Micro electronic package.
12. The aforementioned multiple stacked and joined layers collectively form a cold plate. The microelectronic package according to claim 11.
13. The device and the plurality of stacked and bonded layers are part of an integrated cooling assembly. The microelectronic package according to claim 11.
14. One or more first layers of the plurality of stacked and joined layers include the side walls and support features, The second layer of the plurality of stacked and joined layers is positioned between the base surface and the second side. The second layer includes a second interconnection portion that is perpendicularly positioned through the second layer, The first and second interconnection portions are electrically coupled through a direct hybrid junction formed between the one or more first layers and the second layer. The microelectronic package according to claim 11.
15. The first side of the plurality of stacked and bonded layers is directly bonded to the device through a direct hybrid bond. The microelectronic package according to claim 11.
16. The device is a first device, and the first interconnection unit communicates with the first device and one or more second devices through a direct hybrid connection. The microelectronic package according to claim 11.
17. The one or more second devices include a memory stack, and the first device is a logic device. The microelectronic package according to claim 16.
18. The first side has peripheral support features arranged in the peripheral portion of the first side, and the peripheral support features include a plurality of interconnection parts arranged vertically through the peripheral support features, and the plurality of interconnection parts communicately connect the memory stack and the logic device. The microelectronic package according to claim 17.
19. The support feature has a width that decreases from the base surface to the bonding interface between the first side of the plurality of stacked and bonded layers and the device. The microelectronic package according to claim 11.
20. The plurality of stacked and joined layers include a stack of the first layer, Each of the first layers includes a segment of the first interconnection, Each segment of the first interconnect is connected to another vertically adjacent segment of the first interconnect through a direct hybrid joint formed between the first layers. The microelectronic package according to claim 11.
21. It is a device package, A semiconductor device having an active side and a back surface opposite to the active side, Multiple stacked and joined layers, The plurality of stacked and joined layers are provided, The present invention comprises a first layer and a second layer, the first layer having a base surface, a support feature extending downward from the base surface to the second layer, and a side wall extending downward from the base surface to the second layer and surrounding the base surface and the support feature, and the plurality of stacked and joined layers are The present invention further includes a first interconnection portion arranged vertically through the support feature, the first interconnection portion being electrically coupled to the semiconductor device through a direct hybrid junction formed between the second layer and the semiconductor device. Device package.
22. The semiconductor device and the plurality of stacked and bonded layers are part of an integrated cooling assembly. The device package according to claim 21.
23. The aforementioned multiple stacked and joined layers collectively form a cold plate, and the first and second layers of the cold plate define a coolant channel between them. The device package according to claim 21.
24. The cold plate is an interposer, and the device package further includes a plurality of semiconductor devices coupled to each other in a manner that allows them to communicate through the interposer. The device package according to claim 23.
25. Two or more of the aforementioned semiconductor devices are directly bonded to the opposite side of the cold plate by a hybrid junction. The device package according to claim 24.
26. At least two of the aforementioned plurality of semiconductor devices are bonded to the interposer in a side-by-side arrangement. The device package according to claim 24.
27. The aforementioned multiple stacked and joined layers include a power surface and / or a ground surface. The device package according to claim 21.
28. The first interconnection unit connects the semiconductor device to at least one of the power plane or the ground plane. The device package according to claim 27.
29. The aforementioned support feature has a width that decreases from the base surface to the second layer. The device package according to claim 21.
30. The plurality of stacked and bonded layers include a plurality of interconnections that form a signal rewiring network that is communicably coupled to the input / output (I / O) features of the semiconductor device through direct hybrid bonding. The device package according to claim 21.
31. The system further comprises a conductive layer disposed on the base surface and the support feature. The device package according to claim 21.
32. The conductive layer further comprises a dielectric layer disposed on the conductive layer, The device package according to claim 31.
33. Microelectronic package, It comprises multiple stacked and joined layers, and the multiple stacked and joined layers are The first layer comprises a base surface, a side wall surrounding the base surface and extending downward from the base surface to define a cavity between the first layer and the second layer, and a support feature disposed within the cavity, wherein the plurality of stacked and joined layers are It further includes a first interconnection portion that is vertically positioned through the aforementioned support feature, The first interconnection portion is electrically coupled to the device through a direct hybrid bond formed between the second layer and the back surface of the device. The first and second layers of the plurality of stacked and joined layers define a coolant channel between them. Micro electronic package.
34. The aforementioned multiple stacked and joined layers collectively form a cold plate. The microelectronic package according to claim 33.
35. The device and the plurality of stacked and bonded layers are part of an integrated cooling assembly. The microelectronic package according to claim 33.
36. The third layer of the plurality of stacked and joined layers includes a second interconnection portion that is vertically positioned through the third layer, The first and second interconnection portions are electrically coupled through a direct hybrid junction formed between the first layer and the third layer. The microelectronic package according to claim 33.
37. The second layer is directly bonded to the device through the direct hybrid bonding. The microelectronic package according to claim 33.
38. The support feature has a width that decreases from the base surface to the bonding interface between the first layer and the second layer. The microelectronic package according to claim 33.
39. The aforementioned multiple stacked and joined layers include a stack of layers. Each of the layers in the stack includes a segment of the first interconnection section. Each segment of the first interconnect is connected to another vertically adjacent segment of the first interconnect through a direct hybrid joint formed between the stacks of the layers. The electronic package according to claim 33.
40. The plurality of stacked and joined layers include an interposer having interconnection portions between the device and one or more other devices. The microelectronic package according to claim 33.
41. An integrated cooling assembly, A semiconductor device having an active side and a back surface opposite to the active side, Multiple stacked and joined layers collectively form a cold plate, The cold plate is equipped with, A first side having a base surface, a support feature extending downward from the base surface, and a side wall extending downward from the base surface and surrounding the base surface and the support feature, and a second side opposite to the first side, A first interconnection portion is arranged vertically through the aforementioned support feature, The first interconnection portion is electrically coupled to the semiconductor device through a direct hybrid junction formed between the cold plate and the semiconductor device. Device package.
42. The first side of the cold plate and the back surface of the semiconductor device define a coolant channel between them. The integrated cooling assembly according to claim 41.
43. One or more first layers of the plurality of stacked and joined layers include the side walls and support features, The second layer of the plurality of stacked and joined layers is positioned between the base surface and the second side. The second layer includes a second interconnection portion that is perpendicularly positioned through the second layer, The first and second interconnection portions are electrically coupled through a direct hybrid junction formed between the one or more first layers and the second layer. The integrated cooling assembly according to claim 41 or 42.
44. The cold plate includes a power surface and / or a ground surface. An integrated cooling assembly according to any one of claims 41 to 43.
45. The first interconnection unit connects the semiconductor device to at least one of the power plane or the ground plane. An integrated cooling assembly according to any of claim 44.
46. The aforementioned support feature has a width that decreases from the base surface to the junction interface between the cold plate and the semiconductor device. An integrated cooling assembly according to any one of claims 41 to 45.
47. The side wall of the cold plate is inclined. An integrated cooling assembly according to any one of claims 41 to 46.
48. The side wall is inclined at an angle of less than 90 degrees away from the back surface of the semiconductor device. An integrated cooling assembly according to any one of claims 41 to 47.
49. The side wall is inclined at an angle greater than 90 degrees away from the semiconductor device. An integrated cooling assembly according to any one of claims 41 to 48.
50. The side wall is inclined at an angle greater than 115 degrees away from the semiconductor device. An integrated cooling assembly according to any one of claims 41 to 49.
51. The plurality of stacked and joined layers include a stack of the first layer, Each of the first layers includes a segment of the first interconnection, Each segment of the first interconnect is connected to another vertically adjacent segment of the first interconnect through a direct hybrid joint formed between the first layers. An integrated cooling assembly according to any one of claims 41 to 50.
52. The plurality of stacked and joined layers further include one or more second layers including a second interconnection portion, the second interconnection portion being electrically coupled to the first interconnection portion through a direct hybrid bond formed between the stack of the first layers and the second layers. The integrated cooling assembly according to claim 51.
53. The first interconnection portion has a height of approximately 10 μm or more. The integrated cooling assembly according to claim 51.
54. Each segment of the first interconnection section has an aspect ratio of approximately 20 or less. An integrated cooling assembly according to any one of claims 51 to 53.
55. Each first layer contains crystalline silicon or polycrystalline silicon. An integrated cooling assembly according to any one of claims 41 to 54.
56. One or more segments of the first interconnection are horizontally offset from one or more of the other segments of the first interconnection. An integrated cooling assembly according to any one of claims 41 to 55.
57. The support feature includes a plurality of first interconnection parts, The plurality of first interconnectors form a signal rewiring network that is communicatively coupled to the input / output (I / O) features of the semiconductor device through a direct hybrid junction formed between the semiconductor device and the semiconductor device. An integrated cooling assembly according to any one of claims 41 to 56.
58. The I / O features of the semiconductor device include through-substrate vias. The integrated cooling assembly according to claim 57.
59. The cold plate includes a plurality of support features, An integrated cooling assembly according to any one of claims 41 to 58.
60. The system further comprises a conductive layer disposed on the base surface and the support feature. An integrated cooling assembly according to any one of claims 41 to 59.
61. The conductive layer is electrically insulated from the coolant channel by a dielectric layer disposed on the conductive layer. An integrated cooling assembly according to any one of claims 42 to 60.
62. The conductive layer connects the semiconductor device to at least one of the power surface or the ground surface. An integrated cooling assembly according to any one of claims 44 to 61.
63. The first side further includes a third layer directly bonded to the support feature and the side wall, The plurality of first layers, second layers and third layers collectively define a coolant channel. An integrated cooling assembly according to any one of claims 41 to 62.
64. The third layer includes a third interconnection portion that is perpendicularly positioned through the third layer, The direct hybrid junction is formed between the semiconductor device and the third layer. An integrated cooling assembly according to any one of claims 41 to 63.
65. The cold plate is an interposer, and the integrated cooling assembly includes a plurality of semiconductor devices coupled to each other so as to be able to communicate through the interposer. An integrated cooling assembly according to any one of claims 41 to 64.
66. The plurality of semiconductor devices are bonded to both sides of the cold plate by direct hybrid junctions. The integrated cooling assembly according to claim 65.
67. One or more of the semiconductor devices include a logic device, and one or more of the semiconductor devices include a memory device stack. The integrated cooling assembly according to claim 65 or 66.
68. At least two of the aforementioned semiconductor devices are bonded to the interposer in a side-by-side arrangement. An integrated cooling assembly according to any one of claims 65 to 67.
69. A method for forming an integrated cooling assembly according to any one of claims 41 to 68, comprising forming one or more segments of the first interconnection before directly hybrid bonding the first layer.
70. This includes directly hybrid bonding the first layer, and then patterning the first side to form the base surface, side wall, and support features. The method according to claim 69.
71. The process includes, before directly hybrid bonding the first layers, patterning each of the first layers to form the respective portions of the sidewalls and support features, The method according to claim 69.
72. An integrated cooling assembly, A first side having a base surface, a side wall surrounding the base surface and extending downward from the base surface to define a cavity, and a support feature disposed within the cavity, and a second side opposite to the first side, A first interconnection portion is arranged vertically through the aforementioned support feature, It comprises multiple stacked and joined layers that collectively form a cold plate containing, The first interconnection portion is electrically coupled to the device through a direct hybrid bond formed between the first side and the back surface of the device. The first side of the cold plate and the back surface of the device define a coolant channel between them. Integrated cooling assembly.
73. The cold plate is an interposer that includes an interconnection section between the device and one or more other devices. The integrated cooling assembly according to claim 72.
74. The first interconnection unit communicates with the device and one or more other devices through the direct hybrid connection. The integrated cooling assembly according to claim 72.
75. The one or more devices include a memory stack, and the devices are logic devices. The integrated cooling assembly according to claim 74.
76. The first side has peripheral support features arranged in the peripheral portion of the first side, and the peripheral support features include a high-speed interconnection channel between the memory stack and the logic device. The integrated cooling assembly according to claim 75.
77. The cold plate is attached to the device by the direct hybrid bonding. The integrated cooling assembly according to claim 72.
78. The cold plate includes a conductive surface, and the device is electrically coupled to the conductive surface through the direct hybrid junction. The integrated cooling assembly according to claim 77.
79. The support feature has a width that decreases from the base surface to the bonding interface between the cold plate and the device. The integrated cooling assembly according to claim 72.
80. The side wall of the cold plate is inclined. The integrated cooling assembly according to claim 72.
81. The side wall is inclined at an angle greater than 90 degrees away from the back surface of the device. The integrated cooling assembly according to claim 80.
82. The cold plate comprises a first material, and the support feature comprises the first material. The integrated cooling assembly according to claim 72.
83. The first material contains Si, The integrated cooling assembly according to claim 82.
84. The cold plate comprises a first material, and the support feature comprises a second material different from the first material. The integrated cooling assembly according to claim 72.
85. The support feature comprises (i) a first portion including a first material and (ii) a second portion including a second material different from the first material. The integrated cooling assembly according to claim 72.
86. The integrated cooling assembly is located within the device package, and the device package is A package substrate with a device positioned at the top, A package cover is placed on the package substrate and extends to cover the cold plate and the device, A material layer disposed between the package cover and the cold plate, The package cover includes an inlet opening and an outlet opening that are positioned through the package cover, and the coolant channel is in fluid communication with the inlet opening and the outlet opening. The integrated cooling assembly according to claim 72.
87. The first interconnection portion is such that the first end of the first interconnection portion is wider than the second end of the first interconnection portion. The integrated cooling assembly according to claim 72.
88. The back surface of the device includes a rewiring layer, and the rewiring layer includes an interconnection between the first interconnection and the active side circuit of the device. The integrated cooling assembly according to claim 72.
89. The first interconnection section is part of the signal rewiring network of the cold plate, and a plurality of conductive elements are arranged within the back surface of the device, on the back surface, and / or through the back surface. The integrated cooling assembly according to claim 88.
90. The cold plate is directly bonded to the device without the use of an intervening adhesive. The integrated cooling assembly according to claim 88.
91. The cold plate further comprises one or more passive device components arranged on the first side, The integrated cooling assembly according to claim 72.
92. The cold plate further comprises one or more passive device components arranged on the second side, The integrated cooling assembly according to claim 72.
93. An integrated cooling assembly, The cold plate comprises a base surface and a first side having a side wall surrounding the base surface and extending downward from the base surface to define a cavity, and a second side opposite to the first side, wherein the cold plate is A first substrate comprising a first conductive layer and a second conductive layer disposed on the opposite side of the first conductive layer, wherein the first conductive layer is bonded to the second conductive layer via the first substrate, A second substrate comprising a third conductive layer and a fourth conductive layer disposed on the opposite side of the third conductive layer, wherein the third conductive layer is bonded to the fourth conductive layer via the second substrate, A plurality of support features are provided within the cavity and positioned between the first substrate and the second substrate, thereby defining a coolant channel between the first substrate and the second substrate. The plurality of support features include an interconnection between the conductive layer of the first substrate and the conductive layer of the second substrate, Integrated cooling assembly.
94. The device further comprises an active side and a back surface opposite to the active side, wherein the back surface of the device is attached to the second substrate and electrically coupled to the fourth conductive layer. The integrated cooling assembly according to claim 93.