Method for generating distributed computing system, PCIe device, and interconnection topology information

Abstract

This disclosure provides a distributed computing system, PCIe devices, and a method for generating interconnection topology information. The distributed computing system includes a plurality of PCIe devices and a master control device. Each of the plurality of PCIe devices includes a plurality of ports. The master control device establishes point-to-point links between the plurality of ports of the plurality of PCIe devices. A first portion of the plurality of ports operates in root port mode, and a second portion of the plurality of ports operates in terminal mode. The first portion and the second portion of the plurality of ports are located on different PCIe devices. The master control device inputs the corresponding root port device identification code and the corresponding root port identification code to the first portion of the plurality of ports, and the first portion of the plurality of ports outputs the corresponding root port device identification code and the corresponding root port identification code to the second portion of the plurality of ports. The master control device generates interconnection topology information by reading the second portion of the plurality of ports and obtaining a plurality of link pair information.

Description

Technical Field

[0001] This application claims the priority of Chinese Patent Application No. 202410383242.7 filed on April 1, 2024, and the disclosure content thereof is incorporated herein by reference in its entirety.

[0002] This disclosure relates to a distributed computing system, a PCIe device, and a method for generating interconnection topology information.

Background Art

[0003] In a distributed computing system, usually, a plurality of computing devices are interconnected using an interconnection board or a Universal Base Board (UBB). Since different boards or UBBs correspond to different interconnection topologies, it should be noted that the master control unit needs to adapt the interconnection based on the actual physical connection method and generate information on the multi-card interconnection topology structure. However, due to the existence of various types of boards or UBBs, in a conventional distributed computing system, often a lot of manual adaptation work is required.

[0004] Also, when temporarily changing interconnection settings such as link speed and link bandwidth between a plurality of computing devices, in a conventional distributed computing system, due to the complex adaptation method used to generate the multi-card interconnection topology structure, it often takes a considerable amount of time to implement the interconnection settings.

Summary of the Invention

[0005] This disclosure relates to a distributed computing system, a PCIe device, and a method for efficiently generating interconnection topology information for generating interconnection topology information.

[0006] According to embodiments of the present disclosure, the distributed computing system of the present disclosure includes a plurality of PCIe devices and a master control device. Each of the plurality of PCIe devices includes a plurality of ports. The master control device is connected to the plurality of PCIe devices and is used to establish point-to-point links between the plurality of ports of the plurality of PCIe devices. A first portion of the plurality of ports operates in root port mode, and a second portion of the plurality of ports operates in terminal mode. The master control device inputs a corresponding root port device identification code and a corresponding root port identification code to the first portion of the plurality of ports, and the first portion of the plurality of ports outputs the corresponding root port device identification code and the corresponding root port identification code to the second portion of the plurality of ports. The first portion and the second portion of the plurality of ports are located on different PCIe devices. The master control device generates interconnection topology information by reading the second portion of the plurality of ports and obtaining a plurality of link pair information. Each of the plurality of link pair information includes the corresponding root port device identification code, the corresponding root port identification code, the corresponding terminal device identification code, and the corresponding terminal port identification code.

[0007] In the above embodiment, the plurality of PCIe devices each include a plurality of root port circuits and a plurality of terminal port circuits corresponding to the plurality of ports. At least one of the plurality of root port circuits is used to store the corresponding root port device identification code and the corresponding root port identification code, and at least one of the plurality of terminal port circuits is used to store the corresponding terminal device identification code and the corresponding terminal port identification code.

[0008] In the above embodiment, each of the multiple root port circuits includes a first register and a flip-flop. The first register is used to store the corresponding root port device identification code and the corresponding root port identification code, and the flip-flop is used to determine whether or not to output the corresponding root port device identification code and the corresponding root port identification code.

[0009] In the above embodiment, each of the plurality of terminal port circuits includes a second register. The second register is used to store the corresponding root port device identification code and the corresponding root port identification code.

[0010] In the above embodiment, in response to the master control device determining that the first portion of the plurality of ports is operating in root port mode, the master control device writes the corresponding root port device identification code and the corresponding root port identification code to the first register of the corresponding port, triggers the corresponding port, and writes the corresponding root port device identification code and the corresponding root port identification code to the second register of the peer port.

[0011] In the above embodiment, in response to the master control device determining that the second portion of the plurality of ports is operating in terminal mode, the master control device stores the current terminal device identification code and the current terminal port identification code in an initial list.

[0012] In the above embodiment, the master control device sequentially reads the second registers of the plurality of corresponding ports according to the initial list, obtains a plurality of link pair information, and generates interconnection topology information.

[0013] In the above embodiment, the master control device updates the values ​​of the first registers of each of the multiple ports of the multiple PCIe devices to the corresponding device identification code and the corresponding port identification code. The master control device initializes the point-to-point link configuration between the multiple PCIe devices and performs link training.

[0014] In the above embodiment, the master control device enumerates the plurality of PCIe devices and obtains a plurality of addresses for the plurality of PCIe devices, and the master control device uses the data of the plurality of addresses as the lower bit data of the device identification code.

[0015] In the above embodiment, the data of the upper bits of the device identification code includes the data of the master control device address of the master control device.

[0016] According to embodiments of the present disclosure, the PCIe device of the present disclosure includes a plurality of ports, a plurality of root port circuits, and a plurality of terminal port circuits. The root port circuits are connected to the plurality of ports. The terminal port circuits are connected to the plurality of ports. In response to at least one of the plurality of ports operating in root port mode, at least one of the plurality of ports receives a root port device identification code and a root port identification code corresponding to the PCIe device provided by a master control device, and stores the root port device identification code and the corresponding root port identification code corresponding to the PCIe device in at least one of the plurality of root port circuits. In response to at least one of the plurality of ports operating in terminal port mode, at least one of the plurality of ports receives a root port device identification code and a root port identification code corresponding to another PCIe device, and stores the root port device identification code and the root port identification code corresponding to the other PCIe device in at least one of the plurality of terminal port circuits.

[0017] According to embodiments of the present disclosure, the method for generating interconnection topology information of the present disclosure includes: establishing point-to-point links between multiple ports of multiple PCIe devices; inputting a corresponding root port device identification code and a corresponding root port identification code to a first portion of the multiple ports, wherein the first portion of the multiple ports operates in root port mode; outputting the corresponding root port device identification code and the corresponding root port identification code to a second portion of the multiple ports via the first portion of the multiple ports, wherein the second portion of the multiple ports operates in terminal mode, and the first portion of the multiple ports and the second portion of the multiple ports are located on different PCIe devices; and generating the interconnection topology information by reading the second portion of the multiple ports to obtain a plurality of link pair information, each of which includes the corresponding root port device identification code, the corresponding root port identification code, the corresponding terminal device identification code, and the corresponding terminal port identification code.

[0018] In the above embodiment, each of the plurality of PCIe devices includes a plurality of root port circuits and a plurality of terminal port circuits corresponding to the plurality of ports.

[0019] In the above embodiment, at least one of the plurality of root port circuits is used to store the corresponding root port device identification code and the corresponding root port identification code, and at least one of the plurality of terminal port circuits is used to store the corresponding terminal device identification code and the corresponding terminal port identification code.

[0020] In the above embodiment, each of the multiple root port circuits includes a first register and a flip-flop. The first register is used to store the corresponding root port device identification code and the corresponding root port identification code, and the flip-flop is used to determine whether or not to output the corresponding root port device identification code and the corresponding root port identification code.

[0021] In the above embodiment, each of the plurality of terminal port circuits includes a second register. The second register is used to store the corresponding root port device identification code and the corresponding root port identification code.

[0022] In the above embodiment, inputting the corresponding root port device identification code and the corresponding root port identification code to the first portion of the plurality of ports includes writing the corresponding root port device identification code and the corresponding root port identification code to the first register of the corresponding port in response to the first portion of the plurality of ports operating in root port mode. Outputting the corresponding root port device identification code and the corresponding root port identification code to the second portion of the plurality of ports via the first portion of the plurality of ports includes triggering the corresponding port to write the corresponding root port device identification code and the corresponding root port identification code to the second register of the peer port.

[0023] In the above embodiment, the method for generating interconnection topology information further includes storing the current terminal device identification code and the current terminal port identification code in an initial list in response to the master control device determining that the second portion of the plurality of ports is operating in terminal mode.

[0024] In the above embodiment, generating the interconnection topology information includes sequentially reading the second registers of a plurality of corresponding ports according to the initial list, obtaining a plurality of link pair information, and generating interconnection topology information.

[0025] In the above embodiment, the master control device is connected to the plurality of PCIe devices and is used to establish point-to-point links between the plurality of ports of the plurality of PCIe devices.

[0026] In the above embodiment, the method for generating interconnection topology information further includes updating the numerical values of the first registers of each of the plurality of ports of the plurality of PCIe devices to corresponding device identification codes and corresponding port identification codes, and initializing the point-to-point link settings between the plurality of PCIe devices and executing link training.

[0027] In the above embodiment, the method for generating interconnection topology information further includes enumerating the plurality of PCIe devices to obtain the plurality of addresses of the plurality of PCIe devices, and the master control device uses the data of the plurality of addresses as the data of the lower bits of the device identification code. The master control device is connected to the plurality of PCIe devices and is used to establish point-to-point links between the plurality of ports of the plurality of PCIe devices.

[0028] Based on the above, the distributed computing system, PCIe device, and method for generating interconnection topology information of the present disclosure can efficiently generate interconnection topology information between a plurality of ports of a plurality of PCIe devices.

[0029] This disclosure can be understood by referring to the following detailed description and the accompanying drawings. For the sake of easy understanding and brevity, many of the drawings in this disclosure show only a part of the device, and some components in the drawings are not drawn to actual scale. Furthermore, the number and dimensions of the components in the drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure.

Brief Description of the Drawings

[0030] [Figure 1] It is a schematic diagram of a distributed computing system according to an embodiment of this disclosure. [Figure 2] It is a flowchart of generating interconnection topology information according to an embodiment of this disclosure. [Figure 3] It is a schematic diagram of a distributed computing system according to an embodiment of this disclosure. [Figure 4] It is a flowchart of generating interconnection topology information according to an embodiment of this disclosure. [Figure 5] It is a flowchart of generating interconnection topology information according to an embodiment of this disclosure. [Figure 6] It is a schematic diagram of a distributed computing system according to an embodiment of this disclosure.

Modes for Carrying Out the Invention

[0031] Hereinafter, exemplary embodiments of this disclosure will be described in detail. Examples of these embodiments are shown in the accompanying drawings. As much as possible, the same reference numerals are used in the drawings and the description to indicate the same or similar components.

[0032] Throughout the specification and the accompanying claims of this disclosure, specific terms are used to refer to specific components. Those skilled in the art will understand that electronic equipment manufacturers may use different names to refer to the same component. This specification is not intended to distinguish between components that are functionally identical but have different names. In the following description and claims, terms such as “includes” and “equipment” are not limiting and should be interpreted as “includes, but not limited to…”.

[0033] Figure 1 is a schematic diagram of a distributed computing system according to an embodiment of the present disclosure. The distributed computing system 100 includes a master control device 110, a PCIe (Peripheral Component Interconnect Express) switch 121, a PCIe switch 122, and a plurality of PCIe devices 131 to 138. In this embodiment, each PCIe device 131 to 138 includes a terminal port EP and a plurality of ports P1 to P7. Each PCIe device 131 to 138 may be connected to PCIe switch 121 or PCIe switch 122 via terminal port EP. Each PCIe device 131 to 138 may be connected to other PCIe devices via ports P1 to P7. In this embodiment, PCIe devices 131 to 134 share one PCIe switch 121, and PCIe devices 135 to 138 share one PCIe switch 122.

[0034] In one embodiment, the master control device 110 may be, for example, a Central Processing Unit (CPU) and may be mounted on a motherboard. PCIe devices 131-138 may be, for example, display chip cards or AI accelerator cards and may be mounted on PCIe switches 121 and 122 on a motherboard. PCIe devices 131-138 may include, but are not limited to, graphics processing units (GPUs), general-purpose graphics processing units (GPGPUs), field programmable gate arrays (FPGAs), neural processing units (NPUs), or application-specific integrated circuit (ASIC) chips.

[0035] In this embodiment, the master control device 110 can acquire interconnection topology information of the point-to-point links between PCIe devices 131 to 138 and realize data transport operations between PCIe devices 131 to 138 according to the interconnection topology information.

[0036] Figure 2 is a flowchart of interconnection topology information generation according to the embodiment of this disclosure. Referring to Figures 1 and 2, in this embodiment, each port (P1 to P7) of PCIe devices 131 to 138 can operate in root port mode or terminal mode. Note that a port operating in root port mode can write data to and read data from a port operating in terminal mode. In this embodiment, the distributed computing system 100 can perform the following steps S210 to S240. In step S210, the master control device 110 can establish point-to-point links between multiple ports (P1 to P7) of PCIe devices 131 to 138. In step S220, the master control device 110 can input the corresponding root port device identification code (i.e., the current address of the PCIe device) and the corresponding root port identification code (i.e., the current port identification code of this port) to the first part of the multiple ports, where the first part of the multiple ports operates in root port mode.

[0037] In this embodiment, the master control device 110 can enumerate PCIe devices 131 to 138 and obtain multiple addresses of PCIe devices 131 to 138. These addresses may be data for the bus (8 bits), device (5 bits), and function (3 bits) identification codes. The master control device 110 can use the data of these multiple addresses as the lower bits (e.g., [15:0]) of the individual device identification codes of PCIe devices 131 to 138. In a multi-machine interconnection application, the data for the upper bits (e.g., [23:16]) of the device identification code may include the master control device address data of the master control device 110. In this embodiment, the master control device 110 can input the above device identification codes and port identification codes to the first portion of the multiple ports operating in root port mode and use them as the corresponding root port device identification codes and corresponding root port identification codes.

[0038] In step S230, the first portion of the plurality of ports outputs the corresponding root port device identification code and the corresponding root port identification code to the second portion of the plurality of ports, where the second portion of the plurality of ports operates in terminal mode. In this embodiment, the master control device 110 can enable the first portion of the plurality of ports operating in root port mode to start a write operation (meaning writing data to a peer) and output the corresponding root port device identification code and the corresponding root port identification code to the peer port. Here, the peer port is the second portion of the plurality of ports operating in terminal mode. The first portion of the plurality of ports and the second portion of the plurality of ports are located on different PCIe devices.

[0039] In step S240, the master control device 110 can generate the interconnection topology information by reading the second portion of the plurality of ports and obtaining a plurality of link pair information. In this embodiment, each of the plurality of link pair information includes the corresponding root port device identification code, the corresponding root port identification code, the corresponding terminal device identification code (i.e., the current address of the PCIe device of the port operating in terminal mode), and the corresponding terminal port identification code (i.e., the port identification code of the port operating in terminal mode). Therefore, the master control device 110 can effectively generate interconnection topology information according to the plurality of link pair information.

[0040] Figure 3 is a schematic diagram of a distributed computing system according to an embodiment of the present disclosure. Referring to Figure 3, two PCIe devices are shown as examples. In this embodiment, the master control device 300 The first PCIe device 331 and the second PCIe device 332 are connected via a PCIe switch (not shown). The first PCIe device 331 may include a port, a root port circuit 310, and a terminal port circuit 320. The second PCIe device 332 may include a port, a root port circuit 331, and a terminal port circuit 340. The port of the first PCIe device 331 is connected to the port of the second PCIe device 332. In this embodiment, the root port circuit 310 includes a first register 311 and a flip-flop 312. The first register 311 is connected to the flip-flop 312. The terminal port circuit 320 includes a second register 321. The root port circuit 330 includes a first register 331 and a flip-flop 332. The first register 331 is connected to the flip-flop 332. The terminal port circuit 340 includes a second register 341.

[0041] In this embodiment, the first registers 311 and 331 may be used to store the corresponding root port device identification code and the corresponding root port identification code, and the flip-flops 312 and 332 may be used to determine whether or not to output the corresponding root port device identification code and the corresponding root port identification code. In this embodiment, the second registers 321 and 341 may be used to store the corresponding root port device identification code and the corresponding root port identification code.

[0042] Specifically, the master control device 300 The address of the first PCIe device 331 can be used as the device identification code for the first PCIe device 331, and the address of the second PCIe device 332 can be used as the device identification code for the second PCIe device 332. Master control device 300 The device identification code and port identification code of the first PCIe device 331 can be written to the first register 311 (as the root port device identification code and root port identification code of the first PCIe device 331), and the device identification code and port identification code of the second PCIe device 332 can be written to the first register 331 (as the terminal device identification code and terminal port identification code of the second PCIe device 332). When the port of the first PCIe device 331 operates in root port mode and the port of the second PCIe device 332 operates in terminal mode, the first PCIe device 331 can output the device identification code and port identification code of the first PCIe device 331 stored in the first register 311 to the port of the second PCIe device 332 via the flip-flop 312 and store it in the second register 341. In this way, the master control device 300The device can read the port of the second PCIe device 332 operating in terminal mode, read the second register 341 of the second PCIe device 332, and obtain link pair information. Here, the link pair information includes the terminal device identification code and terminal port identification code of the second PCIe device 332, and the root port device identification code and root port identification code of the first PCIe device 331. Master control device 300 This can generate interconnection topology information according to this link pair information.

[0043] Therefore, referring further to Figure 1, the PCIe devices 131 to 138 in Figure 1 may have multiple ports, each of which includes a plurality of root port circuits and a plurality of terminal port circuits corresponding to the plurality of ports. Furthermore, at least one of the plurality of root port circuits may be used to store the corresponding root port device identification code and the corresponding root port identification code, and at least one of the plurality of terminal port circuits may be used to store the corresponding terminal device identification code and the corresponding terminal port identification code.

[0044] Figure 4 is a flowchart of interconnection topology information generation according to the embodiment of this disclosure. Referring to Figures 1 and 4, the distributed computing system 100 can perform the following operations S401 to S412. In step S401, the master control device 110 can enumerate a plurality of PCIe devices 131 to 138 and obtain a plurality of addresses for PCIe devices 131 to 138. The master control device 110 can use each of the plurality of addresses as an individual device identification code for PCIe devices 131 to 138.

[0045] In step S402, the master control device 110 can initialize the point-to-point link settings between PCIe devices 131 to 138. In step S403, the master control device 110 can sequentially check the status of each point-to-point link between PCIe devices 131 to 138. In step S404, the master control device 110 can determine whether a link has already been established on the current port. If not, in step S405, the master control device 110 can check the status of other point-to-point links or check the port of the next PCIe device. If so, in step S406, the master control device 110 determines whether this port operates in root port mode. If not, in step S407, in response to the master control device 110 determining that the current port operates in terminal mode, the master control device 110 can store the current terminal device identification code and the current terminal port identification code in the initial list and execute step S409. If so, in step S408, in response to the master control device 110 determining that the current port is operating in root port mode, the master control device 110 can write the current root port device identification code and the current root port identification code to the first register of the corresponding port, and trigger the corresponding port to write the current root port device identification code and the current root port identification code to the second register of the peer port.

[0046] In step S409, the master control device 110 determines whether the inspection of all point-to-point links has been completed. If not, it repeats step S403. If it has been completed, in step S410, the system can wait for a preset time, for example, 200 nanoseconds (ns). In step S411, the master control device 110 can sequentially read the second registers of multiple corresponding ports according to an initial list. The initial list can store the corresponding root port device identification code and the corresponding root port identification code stored in the second register of all ports operating in terminal mode. Therefore, in step S412, the master control device 110 can effectively generate interconnection topology information by acquiring information on multiple link pairs.

[0047] Figure 5 is a flowchart of interconnection topology information generation according to the embodiment of this disclosure. Referring to Figures 1 and 5, the distributed computing system 100 can also perform the following steps S501 to S506. In step S501, the master control device 110 can enumerate a plurality of PCIe devices 131 to 138 and obtain a plurality of addresses for PCIe devices 131 to 138. The master control device 110 can use each of the plurality of addresses as an individual device identification code for PCIe devices 131 to 138.

[0048] In step S502, the master control device 110 can update the values ​​in the first registers of multiple ports of all PCIe devices 131-138 to the corresponding device identification codes and port identification codes. In step S503, the master control device 110 can initialize the point-to-point link configuration between PCIe devices 131-138 and perform link training. In step S504, the master control device 110 determines whether training of all end-to-end links is complete. If not, after a certain delay, it repeats the determination result from step S504. If it is, in step S505, the master control device 110 can trigger the corresponding port and write the current root port device identification code and the current root port identification code to the second register of the peer port. In step S506, the master control device 110 can read the values ​​in the second register of all ports, obtain multiple link pair information, and generate interconnection topology information. It should be noted that if the master control device 110 reads the data in the second register as the reset default value (0), the master control device 110 discards the link pair information.

[0049] Figure 6 is a schematic diagram of a distributed computing system according to an embodiment of the present disclosure. Referring to Figure 6, the distributed computing system 600 according to this embodiment is used to realize a multi-machine, multi-card interconnection system. The distributed computing system 600 includes a master control device 611, a master control device 612, a PCIe switch 621, a PCIe switch 622, and a plurality of PCIe devices 631 to 638. In this embodiment, each PCIe device 631 to 638 includes a terminal port EP and a plurality of ports P1 to P4. Each PCIe device 631 to 634 is connected to the PCIe switch 621 via the terminal port EP. Each PCIe device 635 to 638 is connected to the PCIe switch 622 via the terminal port EP. Each PCIe device 631 to 638 is connected to other PCIe devices via ports P1 to P3. In this embodiment, PCIe devices 631-634 share one PCIe switch 621, and PCIe devices 635-638 share one PCIe switch 622. PCIe switch 621 is connected to master control device 611. Switch 622 is connected to master control device 612. Master control devices 611 and 612 can communicate with each other.

[0050] In this embodiment, PCIe devices 631 to 634 can perform point-to-point data transmission via multiple point-to-point links, and PCIe devices 635 to 638 can also perform point-to-point data transmission via another set of point-to-point links. Master control devices 611 and 612 can each generate interconnection topology information between PCIe devices 631 to 634 and between PCIe devices 635 to 638, respectively, by applying the interconnection topology information generation method described in the embodiments of Figures 1 to 5.

[0051] In summary, the distributed computing system, PCIe devices, and method for generating interconnect topology information of this disclosure are designed to operate in root port mode and terminal mode at both ends of a point-to-point link. A port operating in root port mode can access a port operating in terminal mode via read / write operations to read and write data from the configuration space or memory space of the corresponding PCIe device. This disclosure allows adding registers and flip-flops to a port operating in root port mode to write the location information of the port operating in root port mode to the peer's configuration space or memory space. A register for storing location information can also be added to a port operating in terminal mode. In this way, the master control device can read the registers corresponding to the ports operating in terminal mode for all PCIe devices to obtain information for each PCIe link pair and further generate interconnect topology information quickly and efficiently.

[0052] Finally, it should be noted that the embodiments described above are for illustrative purposes only and do not limit the disclosure. Although the disclosure is described in detail with reference to the embodiments described above, those skilled in the art should understand that modifications can still be made to the technical solutions described in the embodiments, or that some or all of their technical features can be replaced with equivalent substitutions. Such modifications or substitutions do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the disclosure. [Explanation of Symbols]

[0053] 100, 600: Distributed computing systems 110, 300 , 611, 612: Master control device 121, 122, 621, 622: PCIe switches 131-138, 331, 332, 631-638: PCIe devices 310, 330: Root port circuits 320, 340: Terminal port circuit 311, 331: First register 312, 332: Flip-flops 321, 341: Second register P1~P7: Ports EP: Terminal Port S210~S240, S401~S412, S501~S506: Process

Claims

1. Multiple PCIe devices, each containing multiple ports, A master control device connected to the plurality of PCIe devices and used to establish point-to-point links between the plurality of ports of the plurality of PCIe devices, The plurality of ports include, the first portion of the plurality of ports operates in root port mode, the second portion of the plurality of ports operates in terminal mode, and the first portion of the plurality of ports and the second portion of the plurality of ports are located on different PCIe devices. The master control device inputs the corresponding root port device identification code and the corresponding root port identification code to the first portion of the plurality of ports, and the first portion of the plurality of ports outputs the corresponding root port device identification code and the corresponding root port identification code to the second portion of the plurality of ports. The master control device generates interconnection topology information by reading the second portion of the plurality of ports and obtaining a plurality of link pair information. Each of the plurality of link pair information includes the corresponding root port device identification code, the corresponding root port identification code, the corresponding terminal device identification code, and the corresponding terminal port identification code. Distributed computing system.

2. Each of the plurality of PCIe devices includes a plurality of root port circuits and a plurality of terminal port circuits corresponding to the plurality of ports, At least one of the plurality of root port circuits is used to store the corresponding root port device identification code and the corresponding root port identification code, and at least one of the plurality of terminal port circuits is used to store the corresponding terminal device identification code and the corresponding terminal port identification code. The distributed computing system according to claim 1.

3. Each of the aforementioned multiple root port circuits includes a first register and a flip-flop. The first register is used to store the corresponding root port device identification code and the corresponding root port identification code, and the flip-flop is used to determine whether or not to output the corresponding root port device identification code and the corresponding root port identification code. The distributed computing system according to claim 2.

4. Each of the aforementioned multiple terminal port circuits includes a second register. The second register is used to store the corresponding root port device identification code and the corresponding root port identification code. The distributed computing system according to claim 3.

5. In response to the master control device determining that the first portion of the plurality of ports is operating in root port mode, the master control device writes the corresponding root port device identification code and the corresponding root port identification code to the first register of the corresponding port, triggers the corresponding port, and writes the corresponding root port device identification code and the corresponding root port identification code to the second register of the peer port. The distributed computing system according to claim 4.

6. In response to the master control device determining that the second portion of the plurality of ports is operating in terminal mode, the master control device stores the current terminal device identification code and the current terminal port identification code in an initial list. The distributed computing system according to claim 4.

7. The master control device sequentially reads the second registers of a plurality of corresponding ports according to the initial list, obtains a plurality of link pair information, and generates interconnection topology information. The distributed computing system according to claim 6.

8. The master control device updates the numerical values ​​of the first registers of each of the multiple ports of the multiple PCIe devices to the corresponding device identification code and the corresponding port identification code. The master control device initializes the point-to-point link configuration between the plurality of PCIe devices and performs link training. A distributed computing system according to any one of claims 4 to 7.

9. The master control device enumerates the plurality of PCIe devices and obtains the plurality of addresses of the plurality of PCIe devices, and the master control device uses the data of the plurality of addresses as the lower bit data of the device identification code. A distributed computing system according to any one of claims 1 to 8.

10. The data of the upper bits of the device identification code includes the data of the master control device address of the master control device. The distributed computing system according to claim 9.

11. Multiple ports, Multiple root port circuits connected to the aforementioned multiple ports, Multiple terminal port circuits connected to the aforementioned multiple ports, Includes, In response to at least one of the plurality of ports operating in root port mode, at least one of the plurality of ports receives a root port device identification code and a root port identification code corresponding to the PCIe device provided by the master control device, and stores the root port device identification code and the root port identification code corresponding to the other PCIe device in at least one of the corresponding root port circuits. In response to at least one of the plurality of ports operating in terminal mode, at least one of the plurality of ports receives a root port device identification code and a root port identification code corresponding to another PCIe device, and stores the root port device identification code and the root port identification code corresponding to the other PCIe device in at least one of the plurality of terminal port circuits. PCIe device.

12. Establishing point-to-point links between multiple ports of multiple PCIe devices, The input of the corresponding root port device identification code and the corresponding root port identification code to the first portion of the plurality of ports, wherein the first portion of the plurality of ports operates in root port mode, Outputting the corresponding root port device identification code and the corresponding root port identification code to the second part of the plurality of ports via the first part of the plurality of ports, wherein the second part of the plurality of ports operates in terminal mode, and the first part of the plurality of ports and the second part of the plurality of ports are located on different PCIe devices, The interconnection topology information is generated by reading the second portion of the plurality of ports and obtaining information on a plurality of link pairs. Includes, Each of the plurality of link pair information includes the corresponding root port device identification code, the corresponding root port identification code, the corresponding terminal device identification code, and the corresponding terminal port identification code. A method for generating interconnection topology information.

13. Each of the plurality of PCIe devices includes a plurality of root port circuits and a plurality of terminal port circuits corresponding to the plurality of ports, At least one of the plurality of root port circuits is used to store the corresponding root port device identification code and the corresponding root port identification code, and at least one of the plurality of terminal port circuits is used to store the corresponding terminal device identification code and the corresponding terminal port identification code. A method for generating interconnection topology information according to claim 12.

14. Each of the aforementioned multiple root port circuits includes a first register and a flip-flop. The first register is used to store the corresponding root port device identification code and the corresponding root port identification code, and the flip-flop is used to determine whether or not to output the corresponding root port device identification code and the corresponding root port identification code. A method for generating interconnection topology information according to claim 13.

15. Each of the aforementioned multiple terminal port circuits includes a second register. The second register is used to store the corresponding root port device identification code and the corresponding root port identification code. A method for generating interconnection topology information according to claim 14.

16. Inputting the corresponding root port device identification code and the corresponding root port identification code into the first portion of the plurality of ports, respectively, is: In response to the first portion of the plurality of ports operating in root port mode, write the corresponding root port device identification code and the corresponding root port identification code to the first register of the corresponding port. Includes, Outputting the corresponding root port device identification code and the corresponding root port identification code to the second part of the plurality of ports via the first part of the plurality of ports is: Triggering the corresponding port and writing the corresponding root port device identification code and the corresponding root port identification code to the second register of the peer port, including, A method for generating interconnection topology information according to claim 15.

17. In response to the master control device determining that the second portion of the plurality of ports is operating in terminal mode, the current terminal device identification code and the current terminal port identification code are stored in the initial list. It further includes, The master control device is connected to the plurality of PCIe devices and is used to establish point-to-point links between the plurality of ports of the plurality of PCIe devices. A method for generating interconnection topology information according to claim 15.

18. Generating the aforementioned interconnection topology information means The process involves sequentially reading the second registers of multiple corresponding ports according to the initial list, obtaining multiple link pair information, and generating interconnection topology information. including, A method for generating interconnection topology information according to claim 17.

19. Updating the numerical values ​​of the first registers of each of the multiple ports of the multiple PCIe devices to the corresponding device identification code and the corresponding port identification code, Initialize the point-to-point link configuration between the aforementioned multiple PCIe devices and perform link training. A method for generating interconnection topology information according to any one of claims 14 to 18, further comprising:

20. The master control device enumerates the plurality of PCIe devices, obtains the plurality of addresses of the plurality of PCIe devices, and uses the data of the plurality of addresses as the lower bit data of the device identification code. It further includes, The master control device is connected to the plurality of PCIe devices and is configured to establish point-to-point links between the plurality of ports of the plurality of PCIe devices. A method for generating interconnection topology information according to claim 12.

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