Chip composite with embedded interposer

Abstract

A chip complex is provided, which includes at least a first IC die located in a first common layer, a passive interposer, and a plurality of IC dies located in a second common layer. The passive interposer includes interconnections formed in the back-end obline (BEOL) region. The first IC die located in the first common layer is hybrid-bonded to the top surface of the passive interposer. The plurality of IC dies located in the second common layer are hybrid-bonded to the bottom surface of the passive interposer.

Description

Technical Field

[0001] The embodiments described in this specification generally relate to chip packages having integrated circuit (IC) dies, specifically, stacked IC dies comprising at least two layers separated by a passive interposer, wherein the dies from both layers are hybrid bonded to the passive interposer.

Background Art

[0002] (Description of Related Art) Some chip packages having multiple layers of IC dies utilize bridge dies to provide interconnections between adjacent IC dies disposed on different layers. Since the bridge die only partially overlaps each of the adjacent IC dies, the beachhead of each adjacent IC available for interfacing with the bridge die is limited. Accordingly, the density and number of interconnections available via the beachhead are limited.

[0003] Therefore, there is a need for improved multi-layer chip packages.

Summary of the Invention

Means for Solving the Problems

[0004] A chip composite is provided that includes a plurality of IC dies present in a first common layer, a passive interposer, and a plurality of IC dies present in a second common layer. The plurality of IC dies present in the first common layer are hybrid bonded to the bottom surface of the passive interposer. The plurality of IC dies present in the second common layer are hybrid bonded to the top surface of the passive interposer.

[0005] In one example, the passive interposer covers the entirety of any one of the plurality of IC dies present in the first common layer.

[0006] In another example, a passive interposer covers the entirety of a second IC die among multiple IC dies present in a first common layer.

[0007] In one example, the passive interposer covers the entirety of one of several IC dies that exist in the second common layer.

[0008] In another example, a passive interposer covers the entirety of a second IC die among multiple IC dies present in a second common layer.

[0009] In one example, the passive interposer includes interconnects formed by a BEOL process on a thinned substrate. Alternatively, the passive interposer may consist only of a BEOL region containing interconnects formed by the BEOL process, with the substrate removed. Optionally, the passive interposer includes only passive routing, such as having no transistors.

[0010] In one example, an integrated circuit (IC) chip complex is provided. The chip complex includes a passive interposer, at least a first IC die, and at least two or more second IC dies. The passive interposer includes interconnections formed in the back end of the line (BEOL) region. The first IC die is part of a first common layer hybrid-bonded to a first face of the passive interposer. The two or more second IC dies are part of a second common layer hybrid-bonded to a second face of the passive interposer.

[0011] Another example provides an integrated circuit (IC) chip package. The chip package includes a chip complex mounted on a substrate. The chip complex includes a passive interposer, at least a first IC die of a first common tier hybrid-bonded to a first face of the passive interposer, and at least two second IC dies of a second common tier hybrid-bonded to a second face of the passive interposer. In some examples, the passive interposer includes interconnects disposed in a BEOL region, the BEOL region comprising a first face and a second face of the passive interposer.

[0012] In yet another example, an integrated circuit (IC) memory chip complex is provided, comprising a passive interposer, a plurality of memory integrated circuit (IC) dies stacked together, any of the memory IC dies hybrid-bonded to a first face of the passive interposer, and at least two or more (IC) dies of a first common hierarchy hybrid-bonded to a second face of the passive interposer.

[0013] In yet another example, an integrated circuit (IC) chip package is provided. The chip package includes a substrate, one or more logic IC dies mounted on the substrate, and a chip complex mounted on the substrate. The chip complex is communicatively coupled to one or more logic IC dies via the substrate. The chip complex includes a passive interposer and a plurality of memory IC dies stacked together. Any of the memory IC dies is hybrid-bonded to a first face of the passive interposer. At least two or more IC dies of a first common hierarchical are hybrid-bonded to a second face of the passive interposer.

[0014] To allow for a more detailed understanding of the above-described features of the present invention, a more specific description of the present invention, which has been concisely summarized above, is made by reference to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings only show typical embodiments of the present invention and should therefore not be considered limiting its scope, as the present invention may acknowledge other equally effective embodiments. [Brief explanation of the drawing]

[0015] [Figure 1] This is a schematic diagram of an electronic device having a chip package with a chip complex. [Figure 2] This is a block diagram of a method for manufacturing an expandable chip composite to form a chip package. [Figure 3A] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Figure 3B] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Figure 3C] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Figure 3D] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Figure 3E] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Figure 3F] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Figure 3G] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Figure 3H] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Figure 3I] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Figure 3J] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Figure 3K] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Figure 3L] Schematic cross-sectional views of different passive interposers that can be used within a chip complex at different stages of manufacturing. [Figure 3M] Schematic cross-sectional views of different passive interposers that can be used within a chip complex at different stages of manufacturing. [Figure 3N] Schematic cross-sectional views of different passive interposers that can be used within a chip complex at different stages of manufacturing. [Figure 3O] Schematic cross-sectional views of different passive interposers that can be used within a chip complex at different stages of manufacturing. [Figure 3P] Schematic cross-sectional views of different passive interposers that can be used within a chip complex at different stages of manufacturing. [Figure 4] Schematic diagram of an electronic device having a chip package with a chip complex. [Figure 5] Schematic diagrams of different chip complexes that can be used in the chip package shown in FIG. 4. [Figure 6] Schematic diagrams of different chip complexes that can be used in the chip package shown in FIG. 4. [Figure 7] Schematic diagrams of different chip complexes that can be used in the chip package shown in FIG. 4. [Figure 8] Block diagram of a method for manufacturing an expandable chip complex for forming a chip package. [Figure 9A] Schematic cross-sectional views of a chip complex at different stages of manufacturing. [Figure 9B] Schematic cross-sectional views of a chip complex at different stages of manufacturing. [Figure 9C] Schematic cross-sectional views of a chip complex at different stages of manufacturing. [Figure 9D] Schematic cross-sectional views of a chip complex at different stages of manufacturing. [Figure 9E] Schematic cross-sectional views of a chip complex at different stages of manufacturing. [Figure 9F] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Figure 9G] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Figure 10] This is a block diagram of a method for manufacturing an expandable chip composite to form a chip package. [Figure 11A] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Figure 11B] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Figure 11C] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Figure 11D] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Figure 11E] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Figure 11F] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Figure 12] This is a block diagram of a method for manufacturing an expandable chip composite to form a chip package. [Figure 13A] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Figure 13B] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Figure 13C] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Figure 13D] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Figure 13F] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Figure 13G] This is a schematic cross-sectional view of the chip composite at different stages of manufacturing. [Modes for carrying out the invention]

[0016] For ease of understanding, the same reference numerals are used to indicate identical elements common to the drawings, where possible. Elements of one embodiment are intended to be usefully incorporated into other embodiments.

[0017] A chip complex comprising at least a first IC die located in a first common layer, a passive interposer, and a plurality of IC dies located in a second common layer is described herein. The chip complex may be used in chip packages and electronic devices. The passive interposer of the chip complex includes routing formed in the wiring process (BEOL) area. By forming the routing within the passive interposer using a BEOL process coupled by a hybrid junction between the routing of the passive interposer and the first die located in the first common layer, the communication interface between the interposer and the IC dies is much denser compared to conventional interposers that have a build-up layer or rely on conventional bridging dies as described above. To further increase the density of interconnection between the passive interposer and the IC dies in the second common layer, the plurality of IC dies located in the second common layer are hybrid-junctioned on the opposite side of the passive interposer.

[0018] A passive interposer is manufactured from a substrate such as a silicon wafer or other suitable substrate, including interconnects formed on the surface of the substrate. The interconnects are prefabricated on the substrate, for example, using a BEOL process that forms patterned metal routings within multiple dielectric layers. The interconnects formed in the BEOL layer consist only of passive routings, such as having no transistors. Thus, a passive interposer is a passive routing structure that does not have active circuit elements. In some examples, the substrate is thinned and vias are formed through the substrate to connect the patterned metal routings of the interconnects to routings formed in a hybrid junction layer. In other examples, the substrate is completely removed from the BEOL region, leaving the BEOL region and defining both sides of the passive interposer. Hybrid junction layers are formed on both sides of the BEOL region, enabling the passive interposer to be packaged using wafer-on-wafer bonding technology. Wafer-on-wafer bonding provides improved alignment between bond pads while also allowing for reduced pitch between bond pads. By using a passive interposer as an intermediate layer between layers, the chip composite can be extended beyond the reticle limit, making large-scale packaging more reliable and cost-effective.

[0019] Several examples described herein provide chip packages that leverage a chip complex having memory dies such as DRAM and logic die integration using 3D hybrid junctions. The memory-based chip complex enables high-bandwidth and low-energy interconnects between the logic dies and memory dies. By enabling high-bandwidth connectivity, the overall computational performance of the chip package is improved. Since many AI applications are memory-rebound, the memory-based chip complex alleviates this bottleneck for large-scale language model AI chips (training and inference). By reducing the energy consumed when transferring data between the compute engine of the compute die and the memory die, the memory-based chip complex improves the performance of chip packages running AI applications. This energy-efficient implementation helps reduce the power requirements of large data centers and improves performance / watt by allocating more of the available power to improve computation instead of wasting power for data transfer between the compute die and memory die. Chip packages with a memory-based chip complex can be manufactured with reduced processing time by leveraging parallel manufacturing flows, by generating partial stacks and combining them to generate a multilayer die stack as a chip complex.

[0020] Some of the advantages of memory-based chip complexes include increased memory bandwidth between memory dies and logic dies, increased energy efficiency of the chip package due to reduced interconnect power consumption, avoidance of the need for very large 2.5D chip modules that would be required to achieve similar performance, shortened manufacturing process time, and avoidance of costly process steps for chip-on-wafer assembly by leveraging wafer-on-wafer assembly technology.

[0021] In addition, the passive interposer of the chip composite improves alignment between interconnects and avoids the need to design and manufacture TSVs to match the precise interface shape between the logic die and memory die. The use of wafer-on-wafer processes for die stacking reduces the number of expensive process steps involved in the chip-on-wafer process, such as gap-filling oxide deposition. Furthermore, the use of reconfigured wafers with known good IC dies increases product yield. The widespread use of hybrid junctions improves energy efficiency and provides higher bandwidth than conventional 2.5D connections.

[0022] Referring to Figure 1, a schematic cross-sectional view of an example of a chip package 100 is provided. The chip package 100 includes at least one integrated circuit (IC) chip complex 150 mounted on one or more substrates. The substrate may be a package substrate 104 or an interposer 102 mounted on the package substrate 104. The interposer 102 may have a silicon core with through silicon vias (TSVs), an elevated fan-out bridge (EFB), etc., if present, or another suitable interposer. In the example shown in Figure 1, the chip package 100 includes a chip complex 150 mounted on the interposer 102 and an interposer 102 mounted on the package substrate 104. The chip package 100 may optionally include one or more additional chip complexes 170 also mounted on the package substrate 104 and / or the interposer 102. One additional chip complex 170 is shown in Figure 1. The additional chip complex 170 includes one or more IC dies 116.

[0023] Any or all of the IC dies 116 may be memory IC dies, compute IC dies, phonics IC dies, or other desired IC dies. When configured as a compute die, the IC die 116 includes a central processing unit (CPU) core and / or a graphics processing unit (GPU) core. The functional circuitry of the compute die may also include a System Management Unit (SMU) circuit. The SMU circuit is configured to monitor thermal and power conditions and adjust power and cooling to keep the IC die 116 functioning within specifications. The functional circuitry of the compute die may also include a Dynamic Function eXchange (DFX) controller IP circuit. The DFX circuit provides management of hardware or software trigger events. For example, the DFX circuit may extract partial bitstreams from memory and deliver them to an internal configuration access port (ICAP). The DFX circuit also supports customizable logic decoupling and startup events for each reconfigurable partition. When the GPU core is included in the functional circuitry of the IC die 116, it generally includes a mathematical engine circuit. The mathematical engine circuit is typically designed for task-specific computing applications such as data center computing, high-performance computing, and AI / ML computing. Along with the accelerated computing core, the functional circuitry of the IC die 116 may also include SMU and DFX circuits.

[0024] The chip complex 150 includes a first surface 132 and a second surface 134 on the opposite side. The first surface 132 faces away from the interposer 102. The first surface 132 may optionally interface with a thermal management device (not shown in Figure 1). Examples of thermal management devices are heat sinks or liquid heat exchangers. The second surface 134 of the chip complex 150 is coupled to the top surface 136 of the interposer 102 by a solder interconnect 106. The solder interconnect 106 may be a solder microbump or other suitable electrical connection suitable for transferring ground, signal, and power transmission between the routing circuit of the interposer 102 and the functional circuit of the IC die in the chip complex 150.

[0025] The bottom surface 138 of the interposer 102 may be coupled to the top surface 140 of the package substrate 104. The bottom surface 138 of the interposer 102 is coupled to the top surface 140 of the package substrate 104 by a solder interconnect 108 or other suitable interconnect. The bottom surface 146 of the package substrate 104 may also be coupled to the top surface 128 of the printed circuit board (PCB) 130, thus forming an electronic device 160. The bottom surface 146 of the package substrate 104 is coupled to the top surface 128 of the PCB 130 by a solder interconnect 148 such as a ball grid array or other suitable interconnect. The electronic device 160 may, among other things, be a tablet, computer, server, data center, call center, automotive electronic system, copier, digital camera, smartphone, control system, ATM, call center, computing system, game system, artificial intelligence system, or machine learning system.

[0026] The chip composite 150 includes at least one IC die 112 disposed in a first common layer 152 and a plurality of IC dies 114 disposed in a second common layer 154. Layers 152 and 154 are disposed on both sides of the passive interposer 110. The chip composite 150 may optionally include an additional layer of one or more IC dies disposed on one or both sides of the passive interposer 110. The chip composite 150 may also optionally include one or more additional passive interposers 110 disposed between layers, as needed. A dielectric material 118 may be disposed between the IC dies in the common layers to add structural rigidity and reduce the possibility of warping of the chip composite 150. The dielectric material 118 may be a molding compound, a gap-filling oxide, or other suitable dielectric material. In one example, the dielectric material 118 is a silicon-based dielectric film such as SiO or SiN.

[0027] The passive interposer 110 is generally at least the same width as or wider than the IC die 112, which advantageously increases the area (i.e., beachhead) available for signal, ground, and power interconnects between the passive interposer 110 and the IC die 112 of the first common tier 152. For example, as shown in Figure 1, the first surface 124 of the passive interposer 110 covers the entire adjacent surface 142 of the first IC die 112. In some other examples where there are multiple IC dies 112 in the first common tier 152, the first surface 124 of the passive interposer 110 covers the entire adjacent surfaces 142 of at least two or more, or even all, of the IC dies 112 of the first common tier 152.

[0028] Similarly, the passive interposer 110 is at least the same width as, or wider than, at least two of the IC dies 114 of the second common layer 154. For example, as shown in Figure 1, the second surface 126 of the passive interposer 110 covers the entirety of at least two adjacent surfaces 144 of the IC die 114. In some other examples, the second surface 126 of the passive interposer 110 covers the entirety of all adjacent surfaces 142 of the IC die 114 of the second common layer 152.

[0029] The passive interposer 110, further described below with respect to Figures 3L to 3P, generally includes at least a back-end-of-line (BEOL) region fabricated within the substrate. The BEOL region may include 3 to 15 layers of complex wiring that form metal interconnect routing that carries power, ground, and signal transmission across the passive interposer. The metal interconnect routing (i.e., the circuitry of the passive interposer 110) is generally formed by alternately laminating oxide layers (for insulation purposes) and metal layers (for interconnect routing). Vias are formed between the layers to connect patterned metal wires and complete the routing. The metal interconnect routing is formed from copper or other good conductors. The interconnect routing terminates on a first surface 124 of the passive interposer 110, on which a hybrid junction layer 122 is formed for connection with the mating hybrid junction layer 122 of the first common layer 152. Once the substrate is completely removed and the BEOL region is left as a complete passive interposer 110, the opposite end of the interconnect routing terminates on a second surface 126 of the passive interposer 110, on which a hybrid bonding layer 122 is formed for connection with the mating hybrid bonding layer 122 of the second common layer 154. In the example where the substrate is completely removed after the fabrication of the BEOL region, the BEOL region itself defines both opposing surfaces 124 and 126 of the passive interposer 110 on which the hybrid bonding layer 122 is formed.

[0030] As described above, the hybrid junction layer 122 physically and electrically couples adjacent dies 112, 114 of the first and second common layers 152, 154 to the first and second surfaces 124, 126 of the passive interposer 110. Each hybrid junction layer 122 includes exposed metal and exposed dielectric material. The exposed metal is connected to the circuits of the connected structure, such as the functional circuits and BEOL region routing of the IC die. The hybrid junction includes forming nonmetal-nonmetallic bonds and metal-metallic bonds. Nonmetal-nonmetallic bonds may form fusion bonds. Metal-metallic bonds may be formed using pressure and heat to form eutectic metallic bonds. In one example, a hybrid bond is formed by bonding dielectric materials surrounding a bond pad to first fix the passive interposer 110 and IC dies 112 and 114, and then fusing the metallic materials of the bond pad together to create an electrical interconnection between the functional circuits of the IC dies 112 and 114 and the circuits (i.e., interconnect routing) of the passive interposer 110. The dielectric material surrounding the bond pad is selected from materials suitable for hybrid bonding to another dielectric material. Suitable materials for hybrid bonding include polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), and combinations thereof.

[0031] The first common layer 152 includes at least one IC die 112, but the first common layer 152 may optionally include multiple IC dies 112. In the example shown in Figure 1, three IC dies 112 are shown. Each IC die 112 in the first common layer 152 may include circuitry that has the same or different functionality as at least one other IC die 112 in the first common layer 152. If one or more additional layers are stacked on top of the first common layer 152, the IC dies of the additional layers may include circuitry that has the same or different functionality as at least one other IC die 112 in the first common layer 152.

[0032] The IC die 112 may be configured as a memory IC die, a compute IC die, a phonics IC die, or any other desired IC die. When configured as a memory die, the IC die 112 includes memory circuits such as static random-access memory (SRAM), dynamic random-access memory (DRAM), or other suitable volatile memory types. Optionally, the memory circuits of the IC die 112 may be non-volatile memory such as ferroelectric random-access memory (FeRAM) and magnetoresistive random-access memory (MRAM), or other suitable non-volatile memory types. When configured as a compute die, the IC die 112 includes a CPU core and / or a GPU core. The functional circuits of the compute die may include an SMU circuit. The SMU circuit is configured to monitor thermal and power conditions and adjust power and cooling to maintain the IC die 112 functioning within specifications. The functional circuits of the compute die may also include a DFX controller IP circuit. The DFX circuit provides management of hardware or software trigger events. For example, the DFX circuit may extract partial bitstreams from memory and deliver them to the ICAP. The DFX circuit also supports customizable logic decoupling and startup events for each reconfigurable partition. When the GPU core is included in the functional circuitry of the IC die 112, it generally includes a mathematical engine circuit. The mathematical engine circuit is generally designed for task-specific computing such as data center computing, high-performance computing, and AI / ML computing in which it is used. Along with the accelerated computing core, the functional circuitry of the IC die 112 may also include an SMU circuit and a DFX circuit.

[0033] One or more of the IC dies 112 may be configured as an active interposer die. An IC die 112 configured as an active interposer die may include a memory controller circuit and a cache memory circuit. The active interposer die may further include a network on a chip (NOC) circuit, a peripheral component interconnect express (PCIe) circuit, a memory physical layer (PHY) circuit configured to communicate with the memory stack, a die-to-die PHY configured to communicate with other IC dies, and an I / O PHY configured to communicate with electronic devices located away from the chip package 100.

[0034] IC die 114 may be configured as described above with reference to IC die 112. Each IC die 114 in the second common hierarchy 154 may include circuitry having the same or different functions as at least one other IC die 114 in the second common hierarchy 154. IC die 114 may further have circuitry having the same or different functions as at least one other IC die 112 in the first common hierarchy 152. Any of all of IC dies 112, 114 may optionally be configured as a chiplet.

[0035] In one example, any of the IC dies 114 that include the second common layer 154 of the IC die may be a logic die. Any of the IC dies 112 that have the first common layer 152 of the IC die may optionally be configured as memory.

[0036] The chip complex 150 may optionally include a silicon block 120 mounted on the top surface of the IC die of the chip complex 150 furthest from the package substrate 104 (indicated as the IC die 112 of the first common layer 152). The silicon block 120 has no functional or routing circuits and is used so that the total height of the assembled chip complex may be similar to the total height of the monolithic die, for example, about 800 μm. The silicon block 120 may also be used, either alternatively or additionally, to match the height of any adjacent chip complex 170 within the chip package 100, to provide structural rigidity, and / or to facilitate good heat transfer from the chip complex 150.

[0037] Figure 2 is a block diagram of a method 200 for manufacturing a chip composite such as the chip composite 150 described above, or other suitable chip composites. Method 200 may be extended to include forming a chip package such as the chip package 100 described above, or other suitable chip packages. Figures 3A to 3K show the chip composite 150 at different stages of manufacturing, and Figures 3L to 3P show alternative versions of the passive interposer 110 at different stages of manufacturing, which may be used as the passive interposer 110 in Method 200.

[0038] Method 200 begins with operation 202 by mounting the IC die 114 on the first carrier substrate 302 to form a second common layer 154, as shown in Figures 3A and 3B. The IC die 114 may be mounted on the first carrier substrate 302 using die mounting tape, diffusion bonding, or other preferred mounting techniques. In one example, the carrier substrate 302 is bonded to the back surface of the IC die 114 such that the active surface of the IC die 114 faces away from the carrier substrate 302 to form the second common layer 154. The second common layer 154 of the IC die 114 bonded to the carrier substrate 302 generally forms a reconfigured wafer.

[0039] Operation 202 may include depositing dielectric material 118 in the gap space between IC dies 114, as shown in Figure 3C. The dielectric material 118 may be a gap-filling oxide or other suitable dielectric material. In one example, the dielectric material 118 is a silicon-based dielectric material such as SiO or SiN. The carrier substrate 302 may extend beyond the outermost IC die 114 in the second common layer 154 so that the dielectric material 118 is also disposed laterally outside the outermost IC die 114 of layer 154.

[0040] In operation 204, as shown in Figure 3D, a hybrid junction layer 122 is formed on the exposed surface of the IC die 114 of the second common layer 154. As described above, the hybrid junction layer 122 includes exposed metal pads and exposed dielectric material. The exposed metal pads are connected to exposed bond pads on the adjacent surface 144 of the IC die 114 by vias and lines that form routing within the hybrid junction layer 122. The bond pads are connected to the functional circuits of the IC die 114.

[0041] In operation 206, as shown in Figures 3E and 3F, the passive interposer 110 is mounted on the IC die 114 of the second common tier 154. The passive interposer 110 may be mounted on the IC die 114 of the second common tier 154 using wafer-to-wafer mounting or other techniques. In one example, the IC die 114 of the second common tier 154 is hybrid-bonded to the passive interposer 110. The passive interposer 110 includes a BEOL region 304 fabricated on a substrate 306. The substrate 306 may be a silicon or other type of wafer on which routing interconnects can be formed using BEOL technology. The BEOL technology used to form the routing interconnects results in a routing density of 20 nm pitch or less.

[0042] In operation 208, as shown in Figure 3G, the substrate 306 of the passive interposer 110 is thinned to form a thinned interposer 308. The substrate 306 may be thinned to less than 50% of the original thickness of the substrate 308 before thinning, or even less than 10%. The substrate 306 may be thinned by grinding, etching, milling, or other preferred techniques. The substrate 306 may optionally be completely removed, leaving only the BEOL region 304 as the thinned interposer 308.

[0043] Referring to Figures 3L to 3P, additional details of the thinning of the substrate 306 performed in operation 208 are provided. As shown in Figure 3L, the passive interposer 110 includes a BEOL region 304 formed on the substrate 306. The BEOL region 304 includes interconnect routing 310 formed from a patterned metal layer that forms lines 316 and vias 318 within the dielectric layer 320. No transistors or other active circuits are present in the BEOL region 304. The routing 310 connects to bond pads 312, 314 formed on either side of the BEOL region 304. Bond pad 312 is later connected to a bond pad formed in the hybrid junction layer 122, while bond pad 314 is later connected to a bond pad formed in the hybrid junction layer 122 located on the opposite side of the passive interposer 110, or to a via 322 formed through the substrate 306.

[0044] After forming the BEOL region 304, the substrate 306 is thinned or completely removed. Figure 3M shows a version of the passive interposer 110 with the substrate 306 completely removed. As shown in Figure 3M, the substrate 306 is thinned by removing a portion 324 of the substrate 306, indicated by dashed lines, to form a thinned substrate 308. The thinned substrate 308 includes through-silicon vias (TSVs) that connect to bond pads 312 formed in the BEOL region 304. The exposed surface of the BEOL region 304 forms the first surface 124 of the completed passive interposer 110, and the exposed surface of the thinned substrate 308 forms the second surface 126 of the completed passive interposer 110.

[0045] Subsequently, as shown in Figure 3N, a hybrid bonding layer 122 is formed on the first surface 124 and the second surface 126 of the passive interposer 110. Note that one of the hybrid bonding layers 122 may be formed on the passive interposer 110 after it has been hybrid-bonded to an adjacent structure using the other hybrid bonding layer 122.

[0046] Each of the hybrid bonding layers 122 shown in Figure 3N includes routing 332 formed from patterned lines and vias. The routing 332 is terminated with bond pads 330, 334, such as those formed from copper or other suitable materials. The patterned lines and vias of the routing 332 are electrically insulated from each other by a plurality of dielectric layers 336. The dielectric layers 336 are formed from materials suitable for hybrid bonding, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), or combinations thereof.

[0047] When one hybrid junction layer 122 is positioned in contact with another hybrid junction layer 122, the exposed dielectric layer 336 of one hybrid junction layer 122 fuses with the exposed dielectric layer 336 of the other hybrid junction layer 122, combining the two hybrid junction layers 122 to form a single hybrid junction layer 122 that holds the bonded structure together. Subsequently, a metal-to-metal bond is formed using pressure and heat, thereby forming a eutectic metallic bond between the bonding pads 330 that are in contact with each other within the now-bonded hybrid junction layer 122. The fusion of the metallic material of the bonding pads 330 creates an electrical interconnection between the routing of the passive interposer 110 and the functional circuitry of the IC die bonded to the passive interposer 110.

[0048] Figure 3O shows a version of the passive interposer 110 with the substrate 306 completely removed. As shown in Figure 3O, the substrate 306 is completely removed as indicated by the dashed line, leaving only the BEOL region 304 of the passive interposer 110 as a whole.

[0049] Subsequently, the hybrid bonding layer 122 is formed on the first surface 124 and the second surface 126 of the passive interposer 110, which are defined by both sides of the BEOL region 304. On the second surface 126 of the passive interposer 110, the bond pad 334 of the routing 332 is formed on the exposed bond pad 314 of the routing 310, as shown in Figure 3P. At this point, the passive interposer 110 is ready for hybrid bonding to adjacent structures (die 112, 114, etc., of adjacent common layers 152, 154).

[0050] Referring back to Figure 2, in operation 210, the hybrid junction layer 122 is formed on the passive interposer 110, as shown in Figure 3H. The passive interposer 110 shown in Figure 3H includes a thinned substrate (308 as shown in Figure 3M), but the passive interposer 110 may alternatively have a substrate 306 and comprise only the BEOL region 304 (as shown in Figure 3O).

[0051] In operation 212, as shown in Figure 3I, the IC die 112 of the first common tier 152 is hybrid-bonded to the passive interposer 110. In operation 214, the gap space between the IC dies 112 may be filled using dielectric material 118, as shown in Figure 3J. In optional operation 216, as shown in Figure 3K, an optional silicon block 120 may be placed on top of the IC die 112 of the first common tier 152. The silicon block 120 may be attached to the IC die 112 of the first common tier 152 by fusion splicing, die mounting tape, adhesive or other preferred techniques.

[0052] Method 200 continues in operation 218 by separating individual chip complexes 150 from the reconfigured wafer. Each chip complex 150 can be sold and shipped as a unit to another manufacturer that utilizes the chip complex 150 to manufacture a chip package 100. If the chip complex 150 is the desired final product, Method 200 may end after separation. If the chip package 100 is the desired final product, Method 200 continues in operation 220 by forming the chip package 100 by mounting the chip complex 150 onto the interposer 102 (or alternatively directly onto the package substrate 104) using solder connections 106 or via another preferred technique. Optionally, in operation 220, one or more additional chip complexes 170 may be mounted onto the interposer 102 (or alternatively directly onto the package substrate 104). Also optional, in operation 220, the chip package 100 may be mounted onto the PCB 130 to form an electronic device 160.

[0053] Figure 4 is a schematic cross-sectional view of another example of the chip package 400. The chip package 400 may be configured as a memory device, such as a high-bandwidth memory (HBM) device. The chip package 400 includes at least one integrated circuit (IC) chip complex 450 configured as a memory device and at least one chip complex 470 configured as a logic device, both of which are mounted on the interposer 102 (or alternatively directly on the package substrate 104). The chip complex 450 utilizes the same passive interposer 110 located between the two layers of the IC die, as described above. The chip package 400 may optionally include one or more additional chip complexes 450, 470, also mounted on the interposer 102 (or alternatively directly on the package substrate 104).

[0054] The chip complex 450 includes one or more IC dies 112 configured as compute dies. The IC dies 112 include a central processing unit (CPU) core and / or a graphics processing unit (GPU) core. The functional circuitry of the compute die may also include a system management unit (SMU) circuit. The SMU circuit is configured to monitor thermal and power conditions and adjust power and cooling to maintain the IC die 112 functioning within specifications. The functional circuitry of the compute die may also include a dynamic function exchange (DFX) controller IP circuit. The DFX circuit provides management of hardware or software trigger events. For example, the DFX circuit may extract partial bitstreams from memory and deliver them to internal configuration access ports (ICAPs). The DFX circuit also assists with customizable logic decoupling and startup events for each reconfigurable partition. If the GPU core is included in the functional circuitry of the IC die 112, it generally includes a mathematical engine circuit. The mathematical engine circuit is generally designed for task-specific computing such as data center computing, high-performance computing, and AI / ML computing. Along with the accelerated computing core, the functional circuits of the IC die 112 may also include SMU circuits and DFX circuits. The IC die 112 communicates with the memory circuits of the chip complex 450 via routing formed in or on the interposer 102.

[0055] The chip composite 450 includes a first surface 432 and a second surface 434 on the opposite side. The first surface 432 is oriented away from the package interposer 104. The first surface 432 may optionally interface with a thermal management device (not shown in Figure 4). The second surface 434 of the chip composite 450 is coupled by a solder interconnect 106 to the top surface 136 of the interposer 102 (or to the top surface 140 of the package substrate 104 if the interposer 102 is not used).

[0056] The bottom surface 138 of the interposer 102 may be coupled to the top surface 140 of the package substrate 104. The bottom surface 138 of the interposer 102 is coupled to the top surface 140 of the package substrate 104 by a solder interconnect 108 or other suitable interconnect. The bottom surface 146 of the package substrate 104 may also be coupled to the top surface 128 of the printed circuit board (PCB) 130, thus forming an electronic device 460. The bottom surface 146 of the package substrate 104 is coupled to the top surface 128 of the PCB 130 by a solder interconnect 148 such as a ball grid array or other suitable interconnect. The electronic device 460 is any of the devices described above with reference to the electronic device 160.

[0057] The chip complex 450 includes a memory stack 410, at least one IC die 112 disposed in a first common layer 152, and a plurality of IC dies 114 disposed in a second common layer 154. Layers 152 and 154 are disposed on both sides of the passive interposer 110. The chip complex 150 may optionally include an additional layer of one or more IC dies disposed on one or both sides of the passive interposer 110. The chip complex 150 may also optionally include one or more additional passive interposers 110 disposed between layers, if necessary. Dielectric material 118 may be disposed between IC dies in the common layers to add structural rigidity and reduce the possibility of warping of the chip complex 150.

[0058] The memory stack 410 includes a stack of one or more memory IC dies 412. While the memory stack 410 shown in Figure 4 shows two memory IC dies 412, the memory stack 410 may include four, five, six, seven, eight or more memory IC dies 412 stacked in a single column. Alternatively, the memory IC dies 412 may be stacked in two or more columns, and the width of the rows of memory IC dies 412 across multiple columns does not exceed the width of the passive interposer 110. The memory IC dies 412 are fixed together within the memory stack 410 by hybrid junctions, for example, by using hybrid junction layers 122 disposed between adjacent memory IC dies 412. Each memory IC die 412 includes memory circuitry such as static random access memory (SRAM), dynamic random access memory (DRAM), or other preferred volatile memory types. Optionally, the memory circuit of the memory IC die 412 may be a non-volatile memory such as a ferroelectric random access memory (FeRAM) or magnetoresistive random access memory (MRAM), or another suitable non-volatile memory type.

[0059] The memory IC die 412 communicates with the compute die 112 of the chip complex 470 via the interposer 102. The memory controller circuit may reside on either of the IC dies 114 or 112 of the chip complex 470, or within either of the compute dies 112 of the chip complex 450. In one example, the memory controller circuit resides on at least one of the IC dies 114 configured as an active interposer die, and at least one of the IC dies 112 configured as a compute die.

[0060] The passive interposer 110 is generally at least the same width as, or wider than, the memory IC die 142, which favorably increases the area available for signal, ground, and power interconnects (i.e., beachhead). For example, as shown in Figure 4, the first surface 124 of the passive interposer 110 covers the entire adjacent surface 442 of the memory IC die 412. Also, as shown in Figure 4, the second surface 126 of the passive interposer 110 covers the entirety of any of the IC dies 114 disposed in a second common tier 154 adjacent to the passive interposer 110. In some other examples where there are multiple IC dies 114 in the second common tier 154, the second surface 126 of the passive interposer 110 covers the entirety of at least two or more, or even all, of the IC dies 114 in the second common tier 154. The passive interposer 110 may consist only of routing formed in the BEOL region, or it may further include a thinned substrate having TSV.

[0061] As described above, the hybrid junction layer 122 physically and electrically couples the IC dies 112, 114, and 412 to each other and / or to the passive interposer 110 of the chip complex 450. In the example shown in Figure 4, the IC die 114 of the second common tier 154 is hybrid-bonded to the passive interposer 110 using the hybrid junction layer 122, the passive interposer 110 is hybrid-bonded to the memory stack 410 using the hybrid junction layer 122, and the memory stack 410 is hybrid-bonded to the IC die 112 of the first common tier 152 using the hybrid junction layer 122. An optional silicon block 120 may be fused to the IC die 112 of the first common tier 152 or otherwise fixed.

[0062] Figures 5 to 7 are schematic diagrams of different chip complexes 550, 650, and 750 that can be used in the chip package 400 shown in Figure 4 instead of the chip complex 450. The chip complexes 550, 650, and 750 are generally the same as the chip complex 450, except that the memory stack 410, the first common tier 152 of the IC die 114, and the second common tier 154 of the IC die 112 have different locations within the chip complex.

[0063] First, referring to the chip complex 550 shown in Figure 5, the chip complex 550 includes at least one passive interposer 110, two or more IC dies 112 of a first common layer 152, and two or more IC dies 114 of a second common layer 154. The chip complex 750 has a first face 532 and a second face 534. The second face 534 is configured to be mounted on a package substrate 104 and / or interposer 102 using solder interconnects 108 / 106. The chip complex 550 includes a memory stack 410 containing one or more memory IC dies 412. Four memory IC dies 412 are shown in Figure 5, but one to eight or more memory IC dies 412 may be used instead. The IC dies 412 are hybrid-bonded together, for example, by using a hybrid junction layer 122. Additional details of the memory stack 410 are described above with reference to Figure 4.

[0064] Continuing to refer to Figure 5, one face of the memory stack 410 defines the second face 534 of the chip composite 550. The face of the memory stack 410 is hybrid bonded to the passive interposer 110 using the hybrid junction layer 122. The passive interposer 110 is hybrid bonded to the IC die 114 of the second common tier 154 using the hybrid junction layer 122. The IC die 114 of the second common tier 154 is hybrid bonded to the IC die 112 of the first common tier 152 using the hybrid junction layer 122. An optional silicon block 120 may be fused to the IC die 112 of the first common tier 152 or otherwise fixed.

[0065] Figure 6 shows another example of the chip complex 750. The chip complex 650 has a first surface 632 and a second surface 634. The second surface 634 is configured to be mounted on a package substrate 104 or interposer 102 using solder interconnects 108 / 106. The chip complex 650 includes a memory stack 410 containing one or more memory IC dies 412. Four memory IC dies 412 are shown in Figure 6, but one to eight or more memory IC dies 412 may be used instead. The IC dies 412 are hybrid-bonded together, for example, by using a hybrid junction layer 122.

[0066] The chip complex 650 includes at least one passive interposer 110, two or more IC dies 112 of a first common layer 152, and two or more IC dies 114 of a second common layer 154. One face of the IC die 114 of the second common layer 154 defines a second face 634 of the chip complex 650. The other face of the IC die 114 of the second common layer 154 is hybrid bonded to a memory stack 410 using a hybrid junction layer 122. The memory stack 410 is hybrid bonded to the IC die 112 of the first common layer 152 using a hybrid junction layer 122. An optional silicon block 120 may be fused to the IC die 112 of the first common layer 152 or otherwise fixed.

[0067] Figure 7 shows another example of the chip complex 750. The chip complex 750 has a first surface 732 and a second surface 734. The second surface 734 is configured to be mounted on an optional interposer 102 or package substrate 104 using solder interconnects 106 / 108. The chip complex 750 includes a memory stack 410 containing one or more memory IC dies 412. Four memory IC dies 412 are shown in Figure 7, but one to eight or more memory IC dies 412 may be used instead. The IC dies 412 are hybrid-bonded together, for example, by using a hybrid junction layer 122.

[0068] The chip complex 750 includes at least one passive interposer 110, two or more IC dies 112 of a first common tier 152, and two or more IC dies 114 of a second common tier 154. One face of the IC die 114 of the second common tier 154 defines a second face 734 of the chip complex 750. The other face of the IC die 114 of the second common tier 154 is hybrid bonded to the IC die 112 of the first common tier 152 using a hybrid junction layer 122. The IC die 112 of the first common tier 152 is hybrid bonded to the memory stack 410 using a hybrid junction layer 122. An optional silicon block 120 (not shown in Figure 7) may be fused to the side of the memory stack 410 opposite to the first common tier 152, or may be otherwise fixed.

[0069] Figure 8 is a block diagram of a method 800 for manufacturing a chip composite such as chip composite 550, 750, or other similar chip composites. Method 800 can be extended to form a chip package such as chip package 400, or other suitable chip packages. Figures 9A to 9G show the chip composite 550 (750) at different stages of manufacturing.

[0070] Method 800 begins with operation 802 by mounting the memory stack 410 on a first carrier substrate 302, as shown in Figure 9A. The memory stack 410 may be mounted on the first carrier substrate 302 using die mounting tape, diffusion bonding, or other preferred mounting techniques. As described above, the memory stack 410 includes one or more memory IC dies 412. Although the memory stack 410 shown in Figure 9A shows four memory IC dies 412, the memory stack 410 may include four, five, six, seven, eight or more memory IC dies 412 stacked in a single row. Alternatively, the memory IC dies 412 may be stacked in two or more rows. The memory IC dies 412 are fixed together within the memory stack 410 by hybrid bonding, for example, by using a hybrid bonding layer 122 disposed between adjacent memory IC dies 412.

[0071] In operation 804, the passive interposer 110 is mounted on the memory stack 410, as shown in Figures 9B and 9C. The passive interposer 110 may be mounted on the memory stack 410 using wafer-to-wafer mounting or other techniques. In one example, the memory stack 410 is hybrid-bonded to the passive interposer 110, for example, by using a hybrid bonding layer 122. As described above, the passive interposer 110 includes a BEOL region 304 fabricated on a substrate 306. The substrate 306 may be a silicon or other type of wafer on which routing interconnects can be formed using BEOL technology. The BEOL technology used to form the routing interconnects results in a routing density of 80 nm pitch or less.

[0072] In operation 806, as shown in Figure 9D, the substrate 306 of the passive interposer 110 is thinned to form a thinned interposer 308. The substrate 306 may be thinned to less than 50% of the original thickness of the substrate 308 before thinning, or even less than 10%. The substrate 306 may be thinned by grinding, etching, milling, or other preferred techniques. The substrate 306 may optionally be completely removed, leaving only the BEOL region 304 as the thinned interposer 308.

[0073] In operation 808, one or more IC dies 114 are mounted on the passive interposer 110, as shown in Figure 9E. The IC dies 114 may be placed on the common layer 154 before being mounted on the passive interposer 110 by forming a reconfigured wafer using a carrier substrate 902 having dielectric material 118 disposed between adjacent IC dies 114. The IC dies 114 may be fixed to the carrier substrate 902 by fusion bonding, die mounting tape, or other preferred techniques. Although not shown in Figure 9E, the IC dies 114 may also be fixed to the passive interposer 110 using hybrid bonding, for example, by using a hybrid bonding layer 122.

[0074] In operation 810, as shown in Figure 9F, one or more IC dies 112 are mounted on a common layer 154 of IC dies 114. The IC dies 112 can be positioned on the common layer 152. The IC dies 112 on the common layer 152 can be fixed to the IC dies 114 on the common layer 154 by using a hybrid junction, for example by using a hybrid junction layer 122. Once the IC dies 112 are mounted on the common layer 154 of IC dies 112, the gaps between the IC dies 114 are filled with dielectric material 118.

[0075] The chip complex 550 can be completed by placing solder interconnects 106 on the memory IC die 412 that forms the second surface 534 of the chip complex 550. Alternatively, the chip complex 750 can be completed by placing solder interconnects 106 on the common layer 154 of the IC die 112 that forms the second surface 734 of the chip complex 750.

[0076] Method 800 continues in operation 812 by separating individual chip complexes 550(750) from the reconfigured wafer. Each chip complex 550(750) can be sold and shipped as a unit to another manufacturer that utilizes the chip complex 550(750) to manufacture a chip package 400. If the chip complex 550(750) is the desired final product, Method 800 may end after separation. If the chip package 400 is the desired final product, Method 800 continues in operation 814 by mounting the chip complexes 550(750) onto an optional interposer 102 and package substrate 104 using solder connections 106 / 108 or via another preferred technique to form the chip package 400. Optionally, in operation 816, one or more additional chip complexes 470 may be mounted onto the interposer 102 and / or package substrate 104. Additionally, optionally, in operation 816, the chip package 400 may be mounted on the PCB 130 to form an electronic device 460.

[0077] Figure 10 is a block diagram of method 1000 for manufacturing a chip composite such as chip composite 650 or other similar chip composites. Method 1000 can be extended to form a chip package such as chip package 400 or other suitable chip packages. Figures 11A to 11F show the chip composite 650 at different stages of manufacturing.

[0078] Method 1000 begins with operation 1002 by mounting a memory stack 410 on a first carrier substrate 302, as shown in Figure 11A. The memory stack 410 may be mounted on the first carrier substrate 302 using die mounting tape, diffusion bonding, or other preferred mounting techniques. As described above, the memory stack 410 includes one or more memory IC dies 412. Although the memory stack 410 shown in Figure 11A shows four memory IC dies 412, the memory stack 410 may include four, five, six, seven, or ten or more memory IC dies 412 stacked in a single row. Alternatively, the memory IC dies 412 may be stacked in two or more rows. The memory IC dies 412 are fixed together within the memory stack 410 by hybrid bonding, for example, by using a hybrid bonding layer 122 disposed between adjacent memory IC dies 412.

[0079] In operation 1004, the passive interposer 110 is mounted on the memory stack 410, as shown in Figure 11B. The passive interposer 110 may be mounted on the memory stack 410 using wafer-to-wafer mounting or other techniques. In one example, the memory stack 410 is hybrid-bonded to the passive interposer 110, for example, by using a hybrid bonding layer 122. As described above, the passive interposer 110 includes a BEOL region 304 fabricated on a substrate 306. The substrate 306 may be a silicon or other type of wafer on which routing interconnects can be formed using BEOL technology. The BEOL technology used to form the routing interconnects results in a routing density of 100 nm pitch or less.

[0080] In operation 1006, as shown in Figure 11C, the substrate 306 of the passive interposer 110 is thinned to form a thinned interposer 308. The substrate 306 may be thinned to less than 50% of the original thickness of the substrate 308 before thinning, or even less than 10%. The substrate 306 may be thinned by grinding, etching, milling, or other preferred techniques. The substrate 306 may optionally be completely removed, leaving only the BEOL region 304 as the thinned interposer 308.

[0081] In operation 1008, one or more IC dies 112 are mounted on the passive interposer 110, as shown in Figure 11D. The IC dies 112 may be placed on the common layer 152 before being mounted on the passive interposer 110 by forming a reconfigured wafer using a carrier substrate 1100 having dielectric material 118 disposed between adjacent IC dies 112. The IC dies 112 may be fixed to the carrier substrate 1100 by fusion bonding, die mounting tape, or other preferred techniques. Although not shown in Figure 11D, the IC dies 112 may also be fixed to the passive interposer 110 using hybrid bonding, for example, by using a hybrid bonding layer 122.

[0082] In operation 1010, as shown in Figure 11E, one or more IC dies 114 are mounted on the memory stack 410 on the opposite side of the memory stack 410 from the common layer 152 of the IC die 112. The IC die 114 may be located in the common layer 154. The IC die 114 in the common layer 154 may be fixed to the exposed memory IC die 412 of the memory stack 410 by using a hybrid junction, for example by using a hybrid junction layer 122 (not shown in Figure 11E). Once the IC die 114 is mounted on the memory stack 410, the gaps between the IC dies 114 are filled with dielectric material 118, as shown in Figure 11F.

[0083] Method 1000 continues in operation 1012 by framing individual chip complexes 650 from the reconfigured wafer. Each chip complex 650 can be sold and shipped as a unit to another manufacturer that utilizes the chip complex 650 to manufacture a chip package 400. If the chip complex 650 is the desired final product, Method 1000 may end after framing. If the chip package 400 is the desired final product, Method 1000 continues in operation 1014 by mounting the chip complexes 650 onto the interposer 102 and / or package substrate 104 using solder connections 106 / 108 or through another preferred technique to form the chip package 400. Optionally, in operation 1016, one or more additional chip complexes 470 may be mounted onto the interposer 102 (or alternatively, the package substrate 104). Also optionally, in operation 1016, the chip package 400 may be mounted onto the PCB 130 to form an electronic device 460.

[0084] Figure 12 is a block diagram of method 1200 for manufacturing a chip composite such as chip composite 650 or other similar chip composites. Method 1200 can be extended to form a chip package such as chip package 400 or other suitable chip packages. Figures 13A to 13G show the chip composite 650 at different stages of manufacturing.

[0085] Method 1200 begins with operation 1202 by mounting a plurality of IC dies 112 on a first carrier substrate 302, as shown in Figure 13A. The IC dies 112 can be mounted on the first carrier substrate 302 by their back surfaces by diffusion bonding or other preferred techniques. The IC dies 112 diffusely bonded to the carrier substrate 302 generally form a reconfigured wafer.

[0086] In operation 1204, as shown in Figure 13B, the passive interposer 110 is mounted on an IC die 112 diffusely bonded to a carrier substrate 302. The passive interposer 110 may be mounted on the IC die 112 defining a common layer 152 using wafer-to-wafer mounting or other techniques. In one example, the IC die 112 is hybrid-bonded to the passive interposer 110, for example, by using a hybrid bonding layer 122 (not shown in Figure 13B). As described above, the passive interposer 110 includes a BEOL region 304 fabricated on the substrate 306. The substrate 306 may be a silicon or other type of wafer on which routing interconnects can be formed using BEOL techniques. The BEOL techniques used to form the routing interconnects result in a routing density of 120 nm pitch or less.

[0087] In operation 1206, as shown in Figure 13C, the substrate 306 of the passive interposer 110 is thinned to form a thinned interposer 308. The substrate 306 may be thinned to less than 50% of its original thickness before thinning, or even less than 12%. The substrate 306 may be thinned by grinding, etching, milling, or other preferred techniques. The substrate 306 may optionally be completely removed, leaving only the BEOL region 304 as the thinned interposer 308. After the substrate 306 is thinned or removed in operation 1206, a hybrid bonding layer 122 is formed on the exposed surface of the passive interposer 110 facing away from the carrier substrate 302.

[0088] In operation 1208, the memory stack 410 is mounted on the passive interposer 110, as shown in Figure 13D. The memory stack 410 is hybrid-bonded to the passive interposer 110, for example, by using a hybrid junction layer 122. The memory stack 410 may include a temporary carrier substrate 1302. The memory IC dies 412 of the memory stack 410 are fixed together within the memory stack 410 by hybrid bonding, for example, by using a hybrid junction layer 122 disposed between adjacent memory IC dies 412 and the passive interposer 110.

[0089] In operation 1210, as shown in Figure 13F, multiple IC dies 114 are mounted on the memory stack 410 on the side opposite the passive interposer 110. In operation 1212, as shown in Figure 13G, the gaps between the IC dies 114 are filled with dielectric material 118. The temporary carrier substrate 302 may be removed in either operation 1208 or operation 1210.

[0090] Method 1200 continues in operation 1214 by framing individual chip complexes 650 from the reconfigured wafer. Each chip complex 650 can be sold and shipped as a unit to another manufacturer that utilizes the chip complex 650 to manufacture a chip package 400. If the chip complex 650 is the desired final product, Method 1200 may end after framing. If the chip package 400 is the desired final product, Method 1200 continues in operation 1216 by mounting the chip complex 650 onto an optional interposer 102 and / or package substrate 104 using solder connections 106 / 108 or through another preferred technique to form the chip package 400. Optionally, in operation 1218, one or more additional chip complexes 470 may be mounted onto the interposer 102 and / or package substrate 104. Also optionally, in operation 1218, the chip package 400 may be mounted onto PCB 130 to form an electronic device 460.

[0091] Using a hybrid chip-on-wafer hybrid bonding process, the active surface of a common tier IC die is bonded to a metal bonding pad exposed on a hybrid bonding layer formed on the opposite side of the substrate's BEOL surface. The entire surface of each common tier IC die is bonded to the hybrid bonding layer of the substrate, which significantly increases the area available for making connections between routing within the substrate and the bond pad of the second common tier IC die. [Examples]

[0092] The technologies disclosed above may be represented in the following non-limiting embodiments. Chip complexes, chip packages, and electronic devices are all examples of integrated circuit (IC) devices.

[0093] Example 1. An integrated circuit (IC) chip complex comprising a passive interposer, the passive interposer comprising an interconnection formed in a back-end obline (BEOL) region, at least a first (IC) die of a first common hierarchy hybrid-bonded to a first surface of the passive interposer, and at least two or more second (IC) dies of a second common hierarchy hybrid-bonded to a second surface of the passive interposer.

[0094] Example 2. The IC chip composite according to Example 1, wherein the passive interposer covers the entire first IC die.

[0095] Example 3. The IC chip composite according to Example 2, wherein the passive interposer covers the entirety of a second IC die among a plurality of first IC dies present in a first common hierarchical layer.

[0096] Example 4. The IC chip composite according to Example 2, wherein the passive interposer covers the entirety of the first IC die among a plurality of second IC dies present in the second common hierarchical layer.

[0097] Example 5. The IC chip composite according to Example 4, wherein the passive interposer covers the entirety of a second IC die among a plurality of first IC dies present in a second common hierarchical layer.

[0098] Example 6. The IC chip composite according to Example 1, wherein the passive interposer comprises a thinned substrate and vias formed through the thinned substrate and coupled to an interconnection.

[0099] Example 7. The IC chip complex according to Example 6, wherein the passive interposer includes passive routing without the presence of transistors.

[0100] Example 8. The IC chip composite according to Example 1, wherein the BEOL region defines the first and second surfaces of the passive interposer.

[0101] Example 9. The IC chip composite according to Example 1, further comprising a silicon block disposed on the first IC die.

[0102] Example 10. The IC chip complex according to Example 1, wherein the first IC die is a memory die.

[0103] Example 11. The IC chip complex according to Example 1, wherein the first IC die is a logic die.

[0104] Example 12. The IC chip composite according to Example 1, further comprising an active-passive interposer die stacked with a passive interposer.

[0105] Example 13. An integrated circuit (IC) chip package comprising a package substrate and a chip composite mounted on the package substrate, wherein the chip composite comprises a passive interposer, at least a first (IC) die of a first common hierarchy hybrid-bonded to a first surface of the passive interposer, and at least two or more second (IC) dies of a second common hierarchy hybrid-bonded to a second surface of the passive interposer.

[0106] Example 14. The chip package according to Example 13, wherein the passive interposer covers the entirety of the first IC die located in the first common layer and all of the second IC dies located in the second common layer.

[0107] Example 15. The chip package according to Example 14, wherein the substrate includes passive routing without the presence of transistors.

[0108] Example 16. The chip package according to Example 15, wherein the passive interposer comprises an interconnect disposed in the BEOL region of the thinned substrate and a via formed through the thinned substrate and coupled to the interconnect.

[0109] Example 17. The chip package according to Example 15, wherein the passive interposer comprises an interconnection disposed in the BEOL region, and the BEOL region comprises a first surface and a second surface of the passive interposer.

[0110] Example 18. The chip package according to Example 13, wherein the first IC die is a memory die or a logic die.

[0111] Example 19. A method for forming a chip composite, comprising: fixing a plurality of IC dies forming a first common layer to a temporary carrier substrate; hybrid bonding the IC dies of the first common layer to a first surface of a passive interposer; thinning a second surface of the passive interposer; and hybrid bonding the IC dies of a second common layer to a second surface of the passive interposer.

[0112] Example 20. The method according to Example 19, wherein hybrid bonding of a first common hierarchical IC die to a first surface of a passive interposer comprises performing a wafer-to-wafer hybrid bonding process, and hybrid bonding of a second common hierarchical IC die to a first surface of a passive interposer comprises performing a chip-to-chip hybrid bonding process.

[0113] Example 21. An integrated circuit (IC) memory chip complex comprising a passive interposer, a plurality of memory integrated circuit (IC) dies stacked together, any of the memory IC dies hybrid-bonded to a first surface of the passive interposer, and at least two or more (IC) dies of a first common hierarchy hybrid-bonded to a second surface of the passive interposer.

[0114] Example 22. The IC memory chip complex according to Example 21, wherein the passive interposer covers the entire memory IC die.

[0115] Example 23. The IC memory chip complex according to Example 22, wherein the passive interposer covers the entirety of any one of two or more IC dies present in the first common hierarchical layer.

[0116] Example 24. The IC memory chip complex according to Example 22, wherein the passive interposer covers the entirety of all IC dies present in the first common hierarchical layer.

[0117] Example 25. The IC memory chip complex according to Example 24, further comprising at least two or more (IC) dies of a second common layer, hybrid-bonded to an IC die present in a first common layer.

[0118] Example 26. The IC memory chip complex according to Example 25, wherein at least one of the IC dies in the first and second common hierarchy comprises a memory controller circuit.

[0119] Example 27. The IC memory chip complex according to Example 26, wherein at least one of the IC dies in the first and second common hierarchy comprises a logic circuit coupled to at least one IC die having a memory controller circuit.

[0120] Example 28. The IC memory chip composite according to Example 21, wherein the passive interposer comprises an interconnection disposed in the BEOL region of the thinned substrate and a via formed through the thinned substrate and coupled to the interconnection.

[0121] Example 29. The IC memory chip complex according to Example 28, wherein the substrate includes passive routing without the presence of transistors.

[0122] Example 30. The IC memory chip complex according to Example 21, wherein the passive interposer comprises interconnects disposed in the BEOL region, and the BEOL region comprises the first and second surfaces of the passive interposer.

[0123] Example 31. An integrated circuit (IC) chip package comprising a package substrate and a chip complex mounted on the package substrate and communicatively coupled to one or more logic IC dies via the package substrate, wherein the chip complex comprises a passive interposer and a plurality of memory IC dies stacked together, wherein one of the memory IC dies is hybrid-bonded to a first surface of the passive interposer, and at least two or more (IC) dies of a first common hierarchy are hybrid-bonded to a second surface of the passive interposer.

[0124] Example 32. The chip package according to Example 31, wherein the passive interposer covers the entire memory IC die.

[0125] Example 33. The chip package according to Example 32, wherein the passive interposer covers the entirety of any one of two or more IC dies present in the first common hierarchical layer.

[0126] Example 34. The chip package according to Example 32, wherein the passive interposer covers the entirety of all IC dies present in the first common layer.

[0127] Example 35. The chip package according to Example 34, further comprising at least two IC dies of a second common layer, hybrid-bonded to an IC die in a first common layer.

[0128] Example 36. The chip package according to Example 35, wherein at least one of the IC dies in the first and second common layers comprises a memory controller circuit.

[0129] Example 37. The chip package according to Example 36, wherein at least one of the IC dies in the first and second common hierarchy comprises a logic circuit coupled to at least one IC die having a memory controller circuit.

[0130] Example 38. The chip package according to Example 31, wherein the passive interposer comprises an interconnection disposed in the BEOL region of the thinned substrate and a via formed through the thinned substrate and coupled to the interconnection.

[0131] Example 39. The chip package according to Example 38, wherein the substrate includes passive routing without the presence of transistors.

[0132] Example 40. The chip package according to Example 31, wherein the passive interposer comprises an interconnection disposed in the BEOL region, and the BEOL region comprises the first and second surfaces of the passive interposer.

[0133] The above describes embodiments of the present invention, but other embodiments and further embodiments of the present invention can be devised without departing from the basic scope of the present invention, and the scope of the present invention is determined by the following "Claims".

Claims

1. An integrated circuit (IC) chip complex, A passive interposer including interconnections formed in the back-end obline (BEOL) region, A first IC die of a first common hierarchy is hybrid-bonded to the first surface of the passive interposer, The passive interposer comprises at least two second IC dies of a second common hierarchy, which are hybrid-bonded to the second surface of the passive interposer. IC chip complex.

2. The aforementioned passive interposer is, Thinned substrate and A via formed through the thinned substrate and coupled to the interconnection, The IC chip composite according to claim 1.

3. The BEOL region defines the first surface and the second surface of the passive interposer. The IC chip composite according to claim 1.

4. The IC die comprises a silicon block disposed on the first IC die, The IC chip composite according to claim 1.

5. The first IC die is a memory die. The IC chip composite according to claim 1.

6. The first IC die is a logic die. The IC chip composite according to claim 1.

7. An integrated circuit (IC) chip package, circuit board and The substrate comprises a chip composite mounted on the aforementioned substrate, The aforementioned chip composite is Passive interposer, A first IC die of a first common hierarchy is hybrid-bonded to the first surface of the passive interposer, The passive interposer comprises at least two second IC dies of a second common hierarchy, which are hybrid-bonded to the second surface of the passive interposer. IC chip package.

8. The passive interposer covers the entire first IC die. The IC chip composite according to claim 1 or 7.

9. The passive interposer covers the entirety of the second IC die located in the first common layer. The IC chip composite according to claim 8.

10. The passive interposer covers the entirety of the first of the at least two second IC dies present in the second common layer. The IC chip composite according to claim 8.

11. The passive interposer covers the entirety of the second of at least two second IC dies present in the second common layer. The IC chip composite according to claim 8.

12. The aforementioned substrate includes passive routing in which no transistors are present. The chip package according to claim 9.

13. The aforementioned passive interposer is, Interconnections arranged in the BEOL region of the thinned substrate, A via formed through the thinned substrate and coupled to the interconnection, A chip package according to claim 12.

14. The passive interposer is equipped with interconnects located in the BEOL area. The BEOL region comprises the first surface and the second surface of the passive interposer. A chip package according to claim 12.

15. The first IC die is a memory die or a logic die. The chip package according to claim 7.

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