FVBP without a Si recess on the back side

Abstract

A microelectronic structure comprising a nanosheet transistor having a source / drain. A front-side contact having a first section located on the front side of the source / drain and a via section extending to the back side of the nanosheet transistor. A shallow isolation layer located around a portion of the via section of the first front-side contact. A back-side metal line located on the back surface of the via section and on the back surface of the shallow trench isolation layer. A dielectric liner located along the sidewall of the back-side metal line and along the lowest surface of the back-side metal line.

Description

Background Art

[0001] The present invention generally relates to the field of microelectronics, and more specifically, to the formation of backside metal lines.

[0002] Nanowires are advanced device architectures in continuous CMOS scaling. However, nanowire technology has shown problems such as devices interfering with each other as they become smaller and closer together when scaled down. When multiple devices are attached in a smaller area, it becomes more difficult to form backside contacts and short circuits with adjacent components.

Summary of the Invention

[0003] Additional aspects and / or advantages will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

[0004] A microelectronic structure comprising a nanowire transistor having a source / drain. A front-side contact having a first section located on the front side of the source / drain and a via section extending to the back side of the nanowire transistor; A shallow isolation layer located around a portion of the via section of the first front-side contact; A backside metal line located on the backside surface of the via section and on the backside surface of the shallow trench isolation layer; A dielectric liner located along the sidewalls of the backside metal line and along the bottommost surface of the backside metal line.

[0005] A microelectronic structure comprising a first nanosheet transistor having a first source / drain. A first front-facing contact having a first section located on the front side of the first source / drain and a via section extending to the back side of the first nanosheet transistor. A second nanosheet transistor having a second source / drain. A second front-facing contact having a first section located on the front side of the second source / drain and a via section extending to the back side of the second nanosheet transistor. A shallow isolation layer located around a portion of the via section of the first front-facing contact and around a portion of the via section of the second front-facing contact. A first back-side metal line located on the back surface of the via section of the first front-facing contact and on the back surface of the shallow trench isolation layer. A second back-side metal line located on the back surface of the via section of the second front-facing contact and on the back surface of the shallow trench isolation layer. A first dielectric liner positioned along the sidewall of the first back metal line and along the lowest surface of the first back metal line, and a second dielectric liner positioned along the sidewall of the second back metal line and along the lowest surface of the second back metal line. A substrate layer positioned between the first dielectric liner and the second dielectric liner.

[0006] A microelectronic structure comprising a first nanosheet transistor having a first source / drain. A first front-facing contact having a first section located on the front side of the first source / drain and a via section extending to the back side of the first nanosheet transistor. A second nanosheet transistor having a second source / drain. A second front-facing contact having a first section located on the front side of the second source / drain and a via section extending to the back side of the second nanosheet transistor. A shallow isolation layer located around a portion of the via section of the first front-facing contact and around a portion of the via section of the second front-facing contact. A first back-side metal line located on the back surface of the via section of the first front-facing contact and on the back surface of the shallow trench isolation layer. A second back-side metal line located on the back surface of the via section of the second front-facing contact and on the back surface of the shallow trench isolation layer. A first dielectric liner positioned along the side wall of the first back metal line and along the lowest surface of the first back metal line, and a second dielectric liner positioned along the side wall of the second back metal line and along the lowest surface of the second back metal line. A passive device positioned between the first dielectric liner and the second dielectric liner. [Brief explanation of the drawing]

[0007] The above and other aspects, features, and advantages of certain exemplary embodiments of the present invention will become more apparent from the following description in conjunction with the accompanying drawings.

[0008] [Figure 1] This is a top view of a plurality of nanodevices according to embodiments of the present invention.

[0009] [Figure 2] This is a cross-sectional view X of a nanostack after front-side processing of a nanodevice according to an embodiment of the present invention.

[0010] [Figure 3] This is a diagram of the cross-sectional Y of the source / drain region of a nanodevice after front-side processing according to an embodiment of the present invention.

[0011] [Figure 4] This is a cross-sectional view X of the nanostack after the nanodevice has been inverted for backside processing according to an embodiment of the present invention, and the first substrate and etching stop have been removed.

[0012] [Figure 5] This is a cross-sectional view of the source / drain region Y after the nanodevice has been inverted for backside processing according to an embodiment of the present invention and the first substrate and etching stop have been removed.

[0013] [Figure 6] This is a cross-sectional view X of a nanostack after a portion of the second substrate has been removed, according to an embodiment of the present invention.

[0014] [Figure 7] This is a cross-sectional view Y of the source / drain region after a plurality of trenches have been formed in a second substrate according to an embodiment of the present invention.

[0015] [Figure 8] This is a cross-sectional view X of a nanostack after forming a dielectric liner and etch-back, according to an embodiment of the present invention.

[0016] [Figure 9] This is a cross-sectional view of the source / drain region Y after forming a dielectric liner and etch-back, according to an embodiment of the present invention.

[0017] [Figure 10] This is a cross-sectional view X of a nanostack after forming a backside metal line, a backside interlayer dielectric layer, and a backside power distribution network (BSPDN) according to an embodiment of the present invention.

[0018] [Figure 11] FIG. of cross-section Y of a source / drain region after forming a backside metal line, a backside interlayer dielectric layer, and a backside power distribution network (BSPDN) according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0019] The following description, referring to the accompanying drawings, is provided to assist in a comprehensive understanding of exemplary embodiments of the present invention defined by the claims and their equivalents. It includes various specific details for that purpose, which are regarded as merely exemplary. Thus, those skilled in the art will recognize that various changes and modifications to the embodiments described herein can be made without departing from the scope and spirit of the present invention. Further, descriptions of well-known functions and structures may be omitted for clarity and conciseness.

[0020] The terms and words used in the following description and claims are not limited to bibliographical meanings but are merely used to enable a clear and consistent understanding of the present invention. Thus, it should be clear to those skilled in the art that the following description of exemplary embodiments of the present invention is provided for purposes of illustration only and not for the purpose of limiting the present invention defined by the appended claims and their equivalents.

[0021] The singular forms "a," "an," and "the" are understood to include the plural referents unless the context clearly indicates otherwise. Thus, for example, reference to "component surface" includes reference to one or more of such surfaces unless the context clearly indicates otherwise.

[0022] Detailed embodiments of the claimed structure and method are disclosed herein, but it should be understood that the disclosed embodiments are merely illustrative of the claimed structure and method, which may be embodied in various forms. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the exemplary embodiments described herein. Rather, these exemplary embodiments are provided to make this disclosure thorough and complete and to fully convey the scope of the invention to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring these embodiments.

[0023] References in this specification to “one embodiment,” “an embodiment,” and “an example embodiment” indicate that the described embodiments may include certain features, structures, or characteristics, but not all embodiments may include such features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, if certain features, structures, or characteristics are described in relation to one embodiment, it is considered to be within the knowledge of those skilled in the art that this may affect such features, structures, or characteristics in relation to other embodiments, whether or not they are explicitly described.

[0024] For the purposes of the following explanation, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” and “bottom,” and their derivatives, shall be used in relation to the structures and methods disclosed, as oriented in the drawings. The terms “overlying,” “atop,” “on top,” “positioned on,” or “positioned atop” mean that a first element, such as a first structure, lies on a second element, such as a second structure, where an intervening element, such as an interface structure, may exist between the first and second elements. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected at the contact surface of the two elements without any intermediate conductive, insulating, or semiconductor layer.

[0025] To avoid ambiguity in the presentation of embodiments of the present invention, some processing steps or operations known in the art may be combined in the following detailed description for presentation and illustrative purposes, and in some cases may not be described in detail. In other cases, some processing steps or operations known in the art may not be described at all. It should be understood that the following description focuses rather on the distinctive features or elements of various embodiments of the present invention.

[0026] Various embodiments of the present invention are described herein with reference to the relevant drawings. Alternative embodiments can be devised without departing from the scope of the present invention. Note that various connections and positional relationships between elements (e.g., above, below, adjacent, etc.) are described in the following description and drawings. These connections and / or positional relationships may be direct or indirect unless otherwise specified, and the present invention is not intended to be limiting in this respect. Thus, the joining of entities may refer to either direct or indirect joining, and the positional relationship between entities may be direct or indirect. As an example of an indirect positional relationship, the reference herein to forming layer "A" above layer "B" includes a situation in which one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B", provided that the relevant properties and functions of layers "A" and "B" are not substantially altered by the intermediate layers.

[0027] The following definitions and abbreviations may be used for the purposes of the claims and interpretation of this specification. Where used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains,” or “containing,” or other variations thereof, are intended to encompass non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus containing a list of elements is not necessarily limited to those elements alone, but may include other elements not expressly listed, or other elements specific to such composition, mixture, process, method, article, or apparatus.

[0028] Furthermore, the term “exemplary” is used herein to mean “serving as an example, case, or illustration.” Embodiments or designs described herein as “exemplary” should not necessarily be construed as being preferable or advantageous to other embodiments or designs. The terms “at least one” and “one or more” may be understood to include any integer greater than or equal to 1, i.e., 1, 2, 3, 4, etc. The term “a plurality” may be understood to include any integer greater than or equal to 2, i.e., 2, 3, 4, 5, etc. The term “connection” may include both indirect and direct “connections.”

[0029] As used herein, the term “about” modifying the amount of a component, part of the present invention used refers to, for example, the variation in quantity that may occur through typical measurement and liquid handling procedures employed to produce a concentration or solution. Furthermore, variations may arise from careless errors in measurement procedures, differences in the manufacture, source, or purity of the components employed to produce a composition or to perform a method, and the like. The terms “about” or “substantial” are intended to include the degree of error associated with the measurement of a particular quantity, based on the equipment available at the time of filing. For example, “about” may include a range of ±8%, 5%, or 2% of a given value. In another embodiment, the term “about” means within 5% of the reported value. In another embodiment, the term “about” means within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the reported value.

[0030] Microchips that will be packaged within integrated circuits (ICs) are formed using various processes encompassing four general categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process of growing, coating, or otherwise transferring material onto a wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). Removal / etching is any process of removing material from a wafer. Examples include etching processes (wet or dry), reactive ion etching (RIE), and chemical mechanical planarization (CMP) and similar processes. Semiconductor doping is the modification of electrical properties by doping the source and drain of a transistor, for example, generally by diffusion and / or ion implantation. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing helps activate implanted dopants. Films of both conductors (e.g., aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and insulate electrical components. Selective doping of different regions of a semiconductor substrate makes it possible to change the conductivity of the substrate by applying a voltage.

[0031] Embodiments of the present invention are described in detail here, and these examples are illustrated in the accompanying drawings, where similar reference numerals refer to similar elements throughout. The present invention relates to forming a back power rail (or first level of back metal line) where a portion of the original substrate is not removed. The remaining substrate allows a passive device (e.g., a diode) to be positioned on the remaining Si having sufficient thickness. During back processing of an active device (e.g., a nanosheet transistor), the substrate is typically completely removed, exposing the back surface of the device components, and the back interlayer dielectric layer is positioned between adjacent back metal lines.

[0032] In contrast, the present invention does not remove the entire substrate, but instead leaves an inverted U-shaped / V-shaped portion. The trench is formed within the substrate so that the back surface of the contact via is exposed. The remaining thickness of the Si substrate is greater than that of shallow trench isolation (STI), allowing for the easy formation of passive devices (e.g., ESD diodes) (not shown, on other areas of the wafer). The trench is lined with a dielectric liner to create a barrier between the back power rail (or back metal line) and the remaining substrate. The back interlayer dielectric layer is not located between the back power rails, but rather on the back surface of the substrate, the back power rail, and the dielectric liner.

[0033] Figure 1 illustrates a top view of a nanodevice, which may consist of multiple electronic components such as transistors, according to an embodiment of the present invention. Cross-section X extends horizontally through one of the nanostacks of the device. Cross-section Y is perpendicular to cross-section X, and cross-section Y passes through a source / drain region that extends across multiple nanostacks.

[0034] Referring now to Figures 2 and 3, the structure in an intermediate stage of a method for manufacturing nanodevices such as nanosheet transistor structures after the completion of the front-side processing according to one embodiment of the present invention is shown.

[0035] Figures 2 and 3 illustrate the processing steps of the structure after the completion of the front-side processing of the nanodevice. Figure 2 shows the first substrate 105, etching stop 106, second substrate 110, multiple channel layers 115, internal spacer 117, gate 125, upper spacer 120, first source / drain 127, second source / drain 129, front-side interlayer dielectric layer 150, first front-side source / drain contact 142, first back-side source / drain contact 140, first front-side via contact 152, back-end-of-the-line (BEOL) layer 160, and carrier wafer 165.

[0036] The first substrate 105 and the second substrate 110 may, but are not necessarily limited, be materials containing, for example, silicon (Si), silicon germanium (SiGe), Si:C (carbon-doped silicon), carbon-doped silicon germanium (SiGe:C), III-V group, II-V group compound semiconductors, or other similar semiconductors. Furthermore, multiple layers of semiconductor material may be used as semiconductor material for the first substrate 105 and the second substrate 110. In some embodiments, the first substrate 105 and the second substrate 110 include both semiconductor material and dielectric material. The semiconductor first substrate 105 and the second substrate 110 may include an organic semiconductor or multilayer semiconductor, such as Si / SiGe, or a silicon-on-insulator or SiGe-on-insulator. Parts or all of the semiconductor first substrate 105 and the second substrate 110 may be composed of amorphous, polycrystalline, or single crystal materials. The first semiconductor substrate 105 and the second substrate 110 can be doped, undoped, or contain doped and undoped regions.

[0037] Figure 2 illustrates multiple nanosheet columns, each of which consists of multiple channel layers 115, internal spacers 117 located at each end of the channel layers 115, an upper spacer 120 located on the uppermost channel layer 115, and gates 125 located between the upper spacer segments 120 and around the channel layers 115. The gates 125 are made of, for example, a gate dielectric liner, such as HfO2, ZrO2, or HfL a O xIt may consist of a high-k dielectric such as, a work function layer such as TiN, TiAlC, TiC, and a conductive metal fill such as W. Sources / drains 127 and 129 are located between each of the nanosheet columns. The first front-side source / drain contact 142 is located on the second source / drain 129. The first back-side source / drain contact 140 is located on the first source / drain 127. The first back-side source / drain contact 140 includes a via section that extends to the back side of the nanodevice shown in Figure 3. The front-side interlayer dielectric layer 150 is located on the gate 125, the upper spacer 120, the first back-side source / drain contact 140, and the first front-side source / drain contact 142. The first front-side via contact 152 is in the front-side interlayer dielectric layer 150 and on the first front-side source / drain contact 142. The BEOL layer 160 is located on the front-side interlayer dielectric layer 150 and the first front-side via contact 152. The carrier wafer 165 is located on the BEOL layer 160.

[0038] Figure 3 illustrates a cross-section of the source / drain region of the nanodevice after the completion of the front-side processing. Figure 3 shows the shallow trench isolation layer 112, the first source / drain 127, the third source / drain 132, the fourth source / drain 134, the fifth source / drain 136, the second front-side source / drain contact 146, the third front-side source / drain contact 148, the first back-side source / drain contact 140, the second back-side source / drain contact 144, the front-side interlayer dielectric layer 150, the second front-side via contact 154, the third front-side via contact 156, the BEOL layer 160, and the carrier wafer 165. The second front-side source / drain contact 146 is located on the fifth source / drain 136, and the third front-side source / drain contact 148 is located on the third source / drain 132. The second back-side source / drain contact 144 is located on the third source / drain 134. The first back-side source / drain contact 140 and the second back-side source / drain contact 144 each include a via section that extends to the back side of the nanodevice, where the via section extends within the shallow trench isolation layer 112.

[0039] The first source / drain 127, the second source / drain 129, the third source / drain 132, the fourth source / drain 134, and the fifth source / drain 136 may be, for example, n-type epitaxy or p-type epitaxy. For n-type epitaxy, an n-type dopant selected from the group consisting of phosphorus (P), arsenic (As), and / or antimony (Sb) may be used. For p-type epitaxy, a p-type dopant selected from the group consisting of boron (B), gallium (Ga), indium (In), and / or thallium (Tl) may be used. Other doping techniques, such as ion implantation, gas-phase doping, plasma doping, plasma permeation ion implantation, cluster doping, implantation doping, liquid-phase doping, solid-phase doping, and / or any suitable combination of these techniques may be used. In some embodiments, the dopant may be realized by thermal annealing, such as laser annealing, flash annealing, rapid thermal annealing (RTA), or any preferred combination of these techniques.

[0040] Figures 4 and 5 illustrate the processing steps of the structure after the nanodevice has been inverted for backside processing and the first substrate and etching stop have been removed. The nanodevice is inverted so that the back side of the nanodevice is exposed for processing. The first substrate 105 and etching stop 106 are removed, and the back surface of the second substrate 110 is exposed.

[0041] At this stage of manufacturing, the second substrate 110 is removed in its entirety; however, the present invention does not remove the second substrate 110 entirely, as will be described in more detail below.

[0042] Figures 6 and 7 illustrate the processing steps of the structure after multiple portions of the second substrate 110 have been removed. Figure 6 illustrates that a portion of the second substrate 110 has been removed. As shown in section X, the remaining portion of the second substrate 110 is a horizontal bar of the second substrate 110 located on the back surface of the nanosheet column and the back surfaces of the source / drain 127, 129. Figure 7 illustrates multiple trenches 170 formed within the second substrate 110, where each trench 170 exposes a portion of the shallow trench isolation layer 112 and the back surface of one of the first or second back source / drain contacts 140, 144 vias. Continuous sections of the second substrate 110 remain after the formation of the multiple trenches 170, resulting in inverted U-shaped or V-shaped sections of the second substrate 110 remaining between the trenches 170, as highlighted by the dashed box 110U. The remaining second substrate 110 located in the dashed box 110U leaves sufficient material of the second substrate 110, allowing a passive device (e.g., a doped second substrate 110) to be located at various positions on the wafer, but within the U-shaped / V-shaped sections of the second substrate 110. After the formation of the second substrate 110, it can be doped for the formation of one or more passive devices during the front-side fabrication process, before the formation of the nanosheet layer. The inverted U-shape or V-shape of the second substrate 110, as highlighted in the dashed box 110U, allows for the presence of passive devices after the back-side processing is complete. Each of the multiple trenches 170 exposes the back surface of the shallow trench isolation layer 112, the lateral section of the shallow trench isolation layer 112, and the back surface of one of the first or second back-side source / drain contacts 140, 144.

[0043] Figures 8 and 9 illustrate the processing steps of the structure after the dielectric liner 175 has been formed and etched back. The dielectric liner 175 is formed on the exposed second substrate 110 as shown in Figure 8 and within a plurality of trenches 170 as shown in Figure 9. The dielectric liner 175 is etched back to remove any dielectric liner 175 located on the shallow trench isolation layer 112 and on the back surface of the first or second back source / drain contacts 140, 144. The dielectric liner 175 may be made of, for example, SiN, SiBCN, SiOCN, SiC, SiOC, etc. The plurality of second trenches 172 are formed from the plurality of trenches 170. The dielectric liner 175 is located along the side walls of each of the plurality of second trenches 172 and is in contact with the sides of the shallow trench isolation layer 112. The dielectric liner 175 does not form a continuous layer along the side / bottom boundary of the second trench 172. The dielectric liner 175 is separated into multiple segments by the shallow trench isolation layer 112 and one of the first or second backside source / drain contacts 140, 144 vias. The segments of the dielectric liner 175 have an L-shape, where vertical / inclined sections and horizontal sections are present. The dielectric liner 175, the back surface of the shallow trench isolation layer 112, and the back surface of the first or second backside source / drain contacts 140, 144 form the respective side and bottom boundaries of the second trench 172. The segments of the dielectric liner 175 are located on the side of the shallow trench isolation layer 112 exposed by the formation of the trench 170. Etching back of the dielectric liner 175 separates the dielectric liner 175 into multiple segments. The dielectric liner 175 is in contact with the side of the shallow trench isolation layer 112, but not with the back surface of the shallow trench isolation layer 112. The inverted U-shape or V-shape of the second substrate 110, as highlighted by the dashed box 110U, is located between sections / segments of the dielectric liner 175 that are situated within adjacent second trenches 173.Furthermore, the inverted U-shape or V-shape of the second substrate 110, as highlighted by the dashed box 110U, is in contact with a section of the shallow trench isolation layer 112 located below the dielectric liner 175. The section of the shallow trench isolation layer 112 is located at the center of the inverted U-shape or V-shape of the second substrate 110, as highlighted by the dashed box 110U. The section of the shallow trench isolation layer 112 is located between the two vertical inverted U-shapes or V-shapes of the second substrate 110.

[0044] Figures 10 and 11 illustrate the structural processing steps after the formation of the first back metal lines (or back power rails) 180, 185, the back interlayer dielectric layer 190, the connecting via contacts 195, and the back distribution network (BSPDN) 200. Figure 10 shows the back interlayer dielectric layer 190 located on the dielectric liner 175, and the BSPDN 200 located on the back interlayer dielectric layer 190. The second trench 172 is filled with conductive metal to form the first back power rail 180 and the second back power rail 185. The sidewall of the first back power rail 180 is in contact with the dielectric liner 175, and the bottom surface of the first back power rail 180 is in contact with the back surface of the dielectric liner 175, the back surface of the shallow trench isolation layer 112, and the back surface of the vias of the first back source / drain contact 140. The dielectric liner 175 acts as a barrier between the first back power rail 180 and the inverted U-shape or V-shape of the second substrate 110, as highlighted by the dashed box 110U. The sidewalls of the second back power rail 185 are in contact with the dielectric liner 175, and the bottom surface of the second back power rail 185 is in contact with the back surface of the dielectric liner 175, the back surface of the shallow trench isolation layer 112, and the back surface of the second back source / drain contact 144. The dielectric liner 175 acts as a barrier between the second back power rail 185 and the inverted U-shape or V-shape of the second substrate 110, as highlighted by the dashed box 110U.

[0045] The dimensions of the dielectric liner 175 vary based on its location. Figure 11 highlights, for example, a first dimension A, a second dimension B, and a third dimension C. Dimension A represents the thickness / width of the dielectric liner 175 located between one sidewall of the back power rails 180, 185 and the second substrate 110. Dimension B represents the thickness / width of the dielectric liner 175 located between the sidewall of the shallow trench isolation layer 112 and the second substrate 110, where the value of dimension B is less than twice the value of dimension A. Dimension C represents the depth / thickness of the dielectric liner 175 located between the bottom surface of the back power rails 180, 185 and the second substrate 110. The value of dimension C is greater than or equal to 6 nanometers.

[0046] The back-side interlayer dielectric layer 190 is located on the second substrate 110, the dielectric liner 175, the first back-side power rail 180, and the second back-side power rail 185. A connecting contact 195 is formed within the back-side interlayer dielectric layer 190, where it is connected to the first back-side power rail 180. A connecting contact 195 located within the back-side interlayer dielectric layer 190 and connected to the second back-side power rail 185 is not shown. The BSPDN 200 is located on the back-side interlayer dielectric layer 190 and on the connecting contact 195. As shown in Figure 11, the inverted U-shape or V-shape of the second substrate 110, as highlighted by the dashed box 110U, allows a considerable amount of the second substrate 110 to remain after the back-side processing of the nanosheet device / transistor is complete. As highlighted by the dashed box 110U, this inverted U-shape or V-shape of the second substrate 110 allows the passive device to be positioned in this section of the second substrate 110 after the backside processing of the nanosheet device / transistor is completed.

[0047] Although the present invention has been shown and described with reference to certain exemplary embodiments, it will be understood by those skilled in the art that various modifications in form and detail can be made to the invention without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.

[0048] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or limitful to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to best describe the principles, practical applications, or technical improvements to the technology available on the market of one or more embodiments, or to enable other those skilled in the art to understand the embodiments disclosed herein.

[0049] The concept of the invention can be summarized by the following points.

[0050] 1. Nanosheet transistor with source / drain; A back-side source / drain contact having a first section located on the front side of the source / drain and a via section extending to the back side of the nanosheet transistor; A shallow trench isolation layer located around a portion of the via section of the rear source / drain contact; A back metal line located on the back surface of the via section and on the back surface of the shallow trench isolation layer; and A dielectric liner located along the side wall of the aforementioned back metal line and along the lowest surface of the aforementioned back metal line A microelectronic structure comprising the above features.

[0051] 2. The microelectronic structure according to item 1, wherein the dielectric liner is composed of at least two distinct segments.

[0052] 3. The microelectronic structure according to item 2, wherein each of the at least two distinct segments of the dielectric liner has an L-shape, the vertical section of the L-shaped dielectric liner is located adjacent to the side wall of the back metal line, and the horizontal section of the L-shaped dielectric liner is located below the lowest surface of the back metal line.

[0053] 4. The microelectronic structure according to item 3, wherein the horizontal section of the L-shaped dielectric liner is located adjacent to the sidewall of the shallow trench isolation layer.

[0054] 5. The microelectronic structure according to item 4, wherein the vertical section of the L-shaped dielectric liner has a first width measured horizontally from the side wall of the back metal line across the vertical section of the L-shaped dielectric liner to the adjacent layer.

[0055] 6. The microelectronic structure according to item 5, wherein the horizontal section of the L-shaped dielectric liner has a second width measured horizontally from the side wall of the shallow trench isolation layer across the horizontal section of the L-shaped dielectric liner to the adjacent layer, the adjacent layer being composed of substrate material or doped substrate material.

[0056] 7. The microelectronic structure described in item 6, wherein the second width value is twice the size of the first width value.

[0057] 8. A first nanosheet transistor having a first source / drain; A first back-side source / drain contact having a first section located on the front side of the first source / drain and a via section extending to the back side of the first nanosheet transistor; A second nanosheet transistor having a second source / drain; A second back-side source / drain contact having a first section located on the front side of the second source / drain and a via section extending to the back side of the second nanosheet transistor; A shallow trench isolation layer located around a portion of the via section of the first backside source / drain contact, and the shallow trench isolation layer (112) located around a portion of the via section of the second backside contact; A first back metal line located on the back surface of the via section of the first back source / drain contact and on the back surface of the shallow trench isolation layer; A second back metal line located on the back surface of the via section of the second back source / drain contact and on the back surface of the shallow trench isolation layer; A first dielectric liner positioned along the side wall of the first back metal line and along the lowest surface of the first back metal line, and a second dielectric liner positioned along the side wall of the second back metal line and along the lowest surface of the second back metal line; and A substrate layer located between the first dielectric liner and the second dielectric liner, wherein the substrate layer is a passive device located between the first dielectric liner and the second dielectric liner. A microelectronic structure comprising the above features.

[0058] 9. The first dielectric liner is composed of at least two distinct segments, and the second dielectric liner is composed of at least two distinct segments. Each of the at least two distinct segments of the first dielectric liner has an L-shape, and each of the at least two distinct segments of the second dielectric liner has an L-shape, The vertical section of the L-shaped first dielectric liner is located adjacent to the side wall of the first back metal line, and the horizontal section of the L-shaped first dielectric liner is located below the lowest surface of the first back metal line. The vertical section of the L-shaped second dielectric liner is located adjacent to the side wall of the second back metal line, and the horizontal section of the L-shaped second dielectric liner is located below the lowest surface of the second back metal line. The microelectronic structure described in item 8.

[0059] 10. The microelectronic structure according to item 9, wherein the horizontal section of the L-shaped first dielectric liner and the horizontal section of the L-shaped second dielectric liner are located adjacent to the sidewall of the shallow trench isolation layer.

[0060] 11. The microelectronic structure according to item 10, wherein the vertical section of the L-shaped first dielectric liner has a first width measured horizontally from the side wall of the first back metal line across the vertical section of the L-shaped first dielectric liner to the adjacent substrate layer.

[0061] 12. The microelectronic structure according to item 11, wherein the horizontal section of the L-shaped dielectric liner has a second width measured horizontally from the sidewall of the shallow trench isolation layer across the horizontal section of the L-shaped first dielectric liner to the adjacent substrate layer.

[0062] 13. The microelectronic structure described in item 12, wherein the second width value is twice the size of the first width value.

[0063] 14. The microelectronic structure according to item 8, wherein the substrate layer has an inverted U / V shape; and the section of the shallow trench isolation layer is located between the vertical sections of the inverted U / V shaped substrate layer.

[0064] 15. The microelectronic structure according to item 8, wherein the substrate layer is in contact with the sidewall of the first dielectric liner, the sidewall of the second dielectric liner, and the sidewall of the shallow trench isolation layer.

Claims

1. Nanosheet transistor with source / drain; A front-side contact having a first section located on the front side of the source / drain and a via section extending to the back side of the nanosheet transistor; A shallow isolation layer located around a portion of the via section of the first front contact; A back metal line located on the back surface of the via section and on the back surface of the shallow trench isolation layer; and A dielectric liner located along the side wall of the aforementioned back metal line and along the lowest surface of the aforementioned back metal line A microelectronic structure comprising the above features.

2. The microelectronic structure according to claim 1, wherein the dielectric liner is composed of at least two distinct segments.

3. The microelectronic structure according to claim 2, wherein each of the at least two distinct segments of the dielectric liner has an L-shape, the vertical section of the L-shaped dielectric liner is located adjacent to the side wall of the back metal line, and the horizontal section of the L-shaped dielectric liner is located below the lowest surface of the back metal line.

4. The microelectronic structure according to claim 3, wherein the horizontal section of the L-shaped dielectric liner is located adjacent to the side wall of the shallow trench isolation layer.

5. The microelectronic structure according to claim 4, wherein the vertical section of the L-shaped dielectric liner has a first width that is measured horizontally from the side wall of the back metal line across the vertical section of the L-shaped dielectric liner to the adjacent layer.

6. The microelectronic structure according to claim 5, wherein the horizontal section of the L-shaped dielectric liner has a second width that is measured horizontally from the side wall of the shallow trench isolation layer across the horizontal section of the L-shaped dielectric liner to the adjacent layer.

7. The microelectronic structure according to claim 6, wherein the second width value is twice the size of the first width value.

8. The microelectronic structure according to claim 6, wherein the adjacent layers are made of a substrate material.

9. The microelectronic structure according to claim 6, wherein the adjacent layers are composed of a doped substrate material.

10. A first nanosheet transistor having a first source / drain; A first front-facing contact having a first section located on the front side of the first source / drain and a via section extending to the back side of the first nanosheet transistor; A second nanosheet transistor having a second source / drain; A second front-facing contact having a first section located on the front side of the second source / drain and a via section extending to the back side of the second nanosheet transistor; A shallow isolation layer located around a portion of the via section of the first front contact and around a portion of the via section of the second front contact; A first back metal line located on the back surface of the via section of the first front contact and on the back surface of the shallow trench isolation layer; A second back metal line located on the back surface of the via section of the second front contact and on the back surface of the shallow trench isolation layer; A first dielectric liner positioned along the side wall of the first back metal line and along the lowest surface of the first back metal line, and a second dielectric liner positioned along the side wall of the second back metal line and along the lowest surface of the second back metal line; and A substrate layer located between the first dielectric liner and the second dielectric liner. A microelectronic structure comprising the above features.

11. The first dielectric liner is composed of at least two distinct segments, and the second dielectric liner is composed of at least two distinct segments. Each of the at least two distinct segments of the first dielectric liner has an L-shape, and each of the at least two distinct segments of the second dielectric liner has an L-shape, The vertical section of the L-shaped first dielectric liner is located adjacent to the side wall of the first back metal line, and the horizontal section of the L-shaped first dielectric liner is located below the lowest surface of the first back metal line. The vertical section of the L-shaped second dielectric liner is located adjacent to the side wall of the second back metal line, and the horizontal section of the L-shaped second dielectric liner is located below the lowest surface of the second back metal line. The microelectronic structure according to claim 10.

12. The microelectronic structure according to claim 11, wherein the horizontal section of the L-shaped first dielectric liner and the horizontal section of the L-shaped second dielectric liner are located adjacent to the sidewall of the shallow trench isolation layer.

13. The microelectronic structure according to claim 12, wherein the vertical section of the L-shaped first dielectric liner has a first width that is measured horizontally from the side wall of the first back metal line across the vertical section of the L-shaped first dielectric liner to the adjacent substrate layer.

14. The microelectronic structure according to claim 13, wherein the horizontal section of the L-shaped dielectric liner has a second width that is measured horizontally from the side wall of the shallow trench isolation layer across the horizontal section of the L-shaped first dielectric liner to the adjacent substrate layer.

15. The microelectronic structure according to claim 14, wherein the second width value is twice the size of the first width value.

16. The microelectronic structure according to claim 10, wherein the substrate layer has an inverted U-shape / V-shape.

17. The microelectronic structure according to claim 16, wherein the section of the shallow trench isolation layer is located between the vertical sections of the inverted U-shaped / V-shaped substrate layer.

18. The microelectronic structure according to claim 10, wherein the substrate layer is in contact with the sidewall of the first dielectric liner, the sidewall of the second dielectric liner, and the sidewall of the shallow trench isolation layer.

19. The microelectronic structure according to claim 10, wherein the substrate layer is composed of a doped substrate material.

20. A first nanosheet transistor having a first source / drain; A first front-side contact having a first section located on the front side of the first source / drain and a via section extending to the back side of the first nanosheet transistor; A second nanosheet transistor having a second source / drain; A second front-facing contact having a first section located on the front side of the second source / drain and a via section extending to the back side of the second nanosheet transistor; A shallow isolation layer located around a portion of the via section of the first front contact and around a portion of the via section of the second front contact; A first back metal line located on the back surface of the via section of the first front contact and on the back surface of the shallow trench isolation layer; A second back metal line located on the back surface of the via section of the second front contact and on the back surface of the shallow trench isolation layer; A first dielectric liner positioned along the side wall of the first back metal line and along the lowest surface of the first back metal line, and a second dielectric liner positioned along the side wall of the second back metal line and along the lowest surface of the second back metal line; and A passive device located between the first dielectric liner and the second dielectric liner. A microelectronic structure comprising the above features.

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