Oxide semiconductor channel stack

Abstract

An oxide semiconductor channel stack for a semiconductor device comprises an oxide semiconductor channel layer, an optional intervening material layer formed on the oxide semiconductor channel layer, and a conditioning layer formed on the intervening material layer (when present) or on the oxide semiconductor channel layer. The conditioning layer increases the current capacity through the channel formed in the oxide semiconductor channel layer by drawing excess oxygen atoms from adjacent oxide semiconductor regions to reduce defects. The conditioning layer may also serve as a contact, such as a gate contact, or another metal layer may be formed on the conditioning layer and serve as a contact.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. More specifically, the present invention relates to an oxide semiconductor channel stack for a semiconductor device that provides enhanced conductivity, and a method of producing such a stack in the semiconductor device.

Background Art

[0002] Semiconductor devices having an oxide semiconductor channel, such as CMOS transistors, thin film transistors (TFTs), etc., are well known. Since these devices are widely used in various use cases with different needs, various oxide semiconductor channel stacks are used in these devices, and various manufacturing processes for producing them are known.

[0003] For at least some of these semiconductor devices, the conductivity of the oxide semiconductor channel stack is a factor that limits the performance of the circuit using the semiconductor device.

[0004] It is desirable to have an oxide semiconductor channel stack that provides improved conductivity for semiconductor devices having an oxide semiconductor channel, and a method of manufacturing such a channel stack.

Summary of the Invention

Means for Solving the Problems

[0005] An object of the present invention is to provide a novel oxide semiconductor channel stack that eliminates or reduces at least one disadvantage of the prior art, and a method of manufacturing such a stack.

[0006] According to a first aspect of the present invention, the present invention comprises an oxide semiconductor channel layer; a conditioning layer formed on the oxide semiconductor channel layer, the conditioning layer drawing out undesirable atoms from regions of the oxide semiconductor channel layer adjacent to the conditioning layer to reduce defects. Preferably, the conditioning layer is selected from the group including titanium, hafnium, zirconium, and / or tantalum, and an oxide semiconductor channel stack is provided. In addition, preferably, the oxide semiconductor channel layer is selected from the group including zinc oxide, tin oxide, and / or indium gallium zinc oxide.

[0007] According to another aspect of the present invention, a method for forming an oxide semiconductor stack is provided, comprising the steps of: forming an oxide semiconductor channel layer on a substrate; and forming a conditioning material on the oxide semiconductor channel layer to extract undesirable atoms from a region of an oxide semiconductor metal member adjacent to the conditioning material.

[0008] According to yet another aspect of the present invention, a thin-film transistor is provided comprising: a substrate; a source formed on the substrate; a drain formed on the substrate and spaced apart from the source; a source channel interface member formed on the source; an oxide semiconductor channel layer formed on the substrate and extending between the source channel interface member and the drain to connect them; an intervening layer including a gate dielectric formed on the oxide semiconductor channel layer; and a regulating material including a metal gate contact formed on the intervening layer, wherein the regulating material draws out undesirable atoms from regions of the oxide semiconductor channel layer adjacent to the regulating material, thereby reducing defects. [Brief explanation of the drawing]

[0009] With reference to the attached drawings, preferred embodiments of the present invention will now be described as merely examples. [Figure 1] This figure shows a cross-section of a prior art oxide semiconductor channel stack. [Figure 2] This figure shows a cross-section of an oxide semiconductor channel stack including a conditioning layer according to an embodiment of the present invention. [Figure 3] This figure shows a cross-section of Figure 2, representing the region of the oxide semiconductor channel stack affected by the adjustment layer. [Figure 4] This figure shows a cross-section of a thin-film transistor using an oxide semiconductor stack according to an embodiment of the present invention. [Figure 5] This figure shows a cross-section of an oxide semiconductor channel stack similar to the one in Figure 2, but with the intervening layer omitted. [Figure 6] This is a flowchart illustrating a process for manufacturing an oxide semiconductor stack according to an aspect of the present invention. [Modes for carrying out the invention]

[0010] As an example of prior art oxide semiconductor channel stacks, a field-effect transistor (FET) has an oxide semiconductor channel stack schematically shown as 40 in Figure 1. As shown, the stack 40 is formed on a substrate 44, which may be any of various insulating or dielectric materials such as silicon dioxide.

[0011] The stack 40 includes an oxide semiconductor channel layer 48, such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), or tin oxide (SnO2), in this example, where the oxide semiconductor channel layer 48 is formed on a substrate 44. A dielectric material layer is formed on the oxide semiconductor channel layer 48 to act as a gate dielectric 52, and a metal layer is formed on the gate dielectric 52 to act as a gate 56.

[0012] Not shown in Figure 1 are the source and drain (or emitter and base) electrodes, which are connected by a stack 40 and, together with the gate 56, form a transistor, such as a thin-film transistor (TFT). As is well known, the gate 56 is supplied with a predetermined level (e.g., -V). onWhen a voltage higher than ) is applied, conduction channels may be formed within the oxide semiconductor channel layer 48, and current may flow from the source to the drain through the resulting channels. The selection of appropriate channel material, dielectric, gate metal, etc., in the stack 40 is all within the usual range for those skilled in the art.

[0013] Semiconductor devices using oxide semiconductor channel stacks, such as stack 40, are well known and widely used, but their current-carrying capacity may be less than desired. In particular, defects in the oxide semiconductor channel layer 48, such as the presence of excess oxygen or various contaminants, hinder carrier mobility, i.e., the current flow through the channel formed in the channel layer 48, and thus limit the current-carrying capacity of the channel.

[0014] Figure 2 shows a novel oxide semiconductor channel stack 100 according to an embodiment of the present invention. The stack 100 includes an oxide semiconductor channel layer 104 formed on a dielectric layer 108, the dielectric layer 108 of which may be a substrate such as silicon dioxide, plastic, or glass, or (in the case of a 3D "stack" layer of transistors) a dielectric layer on another semiconductor device.

[0015] Non-limiting examples of the oxide semiconductor channel layer 104 in stack 100 include zinc oxide (ZnO), indium gallium zinc oxide (IGZO), tin oxide (SnO2), and nitrogen-fixed oxide semiconductors, such as SnON, ZnON, or doped oxide semiconductors, such as Al-ZnO, Ta-doped SnO2, etc.

[0016] An intervening material 112, such as a low-k dielectric, high-k dielectric, or semiconductor layer, is formed on the oxide semiconductor channel layer 104, and the intervening material 112 may optionally be a gate dielectric, a sacrificial dielectric (which is removed in subsequent processing), or another semiconductor device element. This is because the stack 100 is expected to be used in a variety of semiconductor devices, including but not limited to CMOS transistors, TFTs, bipolar junction transistors (BJTs), and heterojunction bipolar transistors (HBTs).

[0017] The inventors have determined that the key factors leading to current flow limitation in the oxide semiconductor channel layer 104, resulting in a reduction in carrier mobility / current flow through channels formed within the oxide semiconductor channel layer 104, are the presence of excess oxygen atoms, undesirable materials, and / or contaminants in the oxide semiconductor channel layer 104, such as nitrogen, carbon, chlorine, and fluorine. These undesirable materials may be common contaminants and / or may be introduced unintentionally during various manufacturing processes.

[0018] For example, when the oxide semiconductor channel layer 104 is tin oxide (SnO2), such as when the channel stack 100 forms part of a TFT, the default stoichiometry for a desired crystal structure of the oxide semiconductor material is 1:2 (one tin atom to two oxygen atoms).

[0019] When an excess of oxygen atoms is present, increasing the stoichiometric ratio to 1:2.1, 1:2.2, etc., defects occur in the oxide semiconductor channel layer 104, and these defects suppress the carrier mobility / current flow. Similarly, when undesirable atoms such as nitrogen, carbon, chlorine, fluorine, and / or other impurities are introduced into the semiconductor channel layer 104 during manufacturing, or otherwise present, defects occur in the semiconductor channel layer 104.

[0020] Thus, in stack 100, a setting layer 116 is formed on the intervening material 112. In some implementations, the setting layer 116 is a metal that also serves as a gate contact, whereas in other implementations, such as those shown in FIG. 2, a gate contact 120 is formed on the setting layer 166. In both implementations, the setting layer 116 is selected to attract oxygen and / or contaminant atoms and functions to attract such undesirable atoms from at least the region of the oxide semiconductor channel layer 104 adjacent to the intervening material 112 and the setting layer 116 through the intervening material 112. Thus, the setting layer 116 acts to “set” the stoichiometry of this region of the material of the oxide semiconductor channel layer 104.

[0021] FIG. 3 shows a (not-to-scale) representation of the result of forming the setting layer 116 between the metal contact layer 120 and the intervening material 112, namely, the formation of a region 104a where excess oxygen and / or other undesirable atoms have been drawn out within the oxide semiconductor channel layer 104. Since the number of defects in region 104a is reduced, the carrier mobility / current flow through the channel therein is improved.

[0022] The setting layer 116 is a metal having a negative reduction potential, i.e., a metal to which oxygen and / or other undesirable atoms have a strong affinity / attraction. Ideally, the metal contact layer 120 is selected to suppress the entry of oxygen and / or other atoms from above into the setting layer 116 in addition to serving as a contact.

[0023] As described above, depending on the intended use and requirements of the stack 100, it is also expected that the intervening material 112 may be sacrificial. In such cases, the intervening material 112 and the adjustment layer 116 are selected by having the ability to remove unwanted atoms from the region 104a, and after the adjustment process, the intervening material 112 and the adjustment layer 116 are removed, and a replacement mediating layer 112 selected by having desired characteristics (such as serving as a gate dielectric, etc.) and a metal adjustment layer 116 selected by having desired characteristics (such as serving as a gate contact, etc.) are reformed over the region 104a of the oxide semiconductor channel layer 104.

[0024] An example of a particular stack 100 for a TFT is shown in FIG. 4. In FIG. 4, a TFT 150 such as that described in published PCT patent application No. WO2023 / 285936, assigned to the assignee of the present invention and incorporated herein by reference, by Barlage et al., is shown. The TFT 150 includes a source 154, which may each be a suitable metal such as ruthenium, a drain 158, and a source-channel interface member 162 such as ruthenium oxide. The stack 100 includes an oxide semiconductor channel layer 104, which may be tin oxide (SnO2), and an intervening material 112, which may be hafnium oxide acting as a gate dielectric. The metal contact layer 120 may be tungsten, tantalum nitride, or titanium nitride acting as a gate contact. In this example, the adjustment layer 116 may be titanium.

[0025] Each layer of the stack 100 may be formed in any suitable manner that would occur to those skilled in the art, such as by atomic layer deposition (ALD), sputtering, CVD, PECVD, etc.

[0026] In the above example of Barlage et al.'s TFT, the oxide semiconductor channel layer 104 may be formed as a layer with a thickness of about 3 nm to about 15 nm, more preferably a layer with a thickness of about 5 nm to about 10 nm. The adjustment layer 116 may be formed as a layer with a thickness of about 1 nm to about 10 nm by any preferred method, for example, sputtering or chemical deposition.

[0027] In some situations, as shown in Figure 5 (where components similar to those in Figure 2 are indicated by similar reference numerals), the adjustment layer 116 may be in direct contact with the oxide semiconductor channel layer 104 and the intervening material 112 may be omitted. However, in most cases, the intervening material 112 is preferably present, and it may be about 1 nm to about 20 nm thick.

[0028] It is expected that the adjustment layer 116 should not be excessively thick. This is because, otherwise, the adjustment layer 116 may draw too many oxygen atoms from the oxide semiconductor channel layer 104, potentially reducing its stoichiometry from 1:2 to 1:1.6 or 1:1.5, and changing it from a semiconductor to a conductor.

[0029] In the examples described herein, the adjustment layer 116 may have a thickness of about 0.2 nm to about 3 nm, thereby reducing defects in region 104a by extracting excess oxygen atoms from region 104a of the oxide semiconductor channel layer 104. Region 104a may range from about 2 nm to the entire thickness of the semiconductor channel layer 104.

[0030] In testing of TFTs manufactured with the new stack 100, carrier mobility measurements showed a tenfold improvement compared to similar TFTs manufactured without the modulating layer 116.

[0031] As shown in Figure 6, a method 200 for manufacturing an oxide semiconductor channel stack according to an embodiment of the present invention includes: step 204 forming an oxide semiconductor channel layer on a substrate; step 208 optionally forming an intervening material on the oxide semiconductor channel layer; step 212 forming a conditioning material on the intervening material if the intervening material is present, or on the oxide semiconductor channel layer if the intervening material is absent, wherein the conditioning material removes undesirable atoms from at least the region of the oxide semiconductor channel layer adjacent to the conditioning material; and step 216 optionally forming a metal contact on the conditioning material.

[0032] Non-limiting examples of suitable modifying materials include titanium, hafnium, zirconium, and / or tantalum.

[0033] Non-limiting examples of suitable intervening materials when present include low-k dielectrics, high-k dielectrics, semiconductors, and the like.

[0034] The embodiments described above are intended to be illustrative examples of the present invention, and modifications and changes to these embodiments may be made by those skilled in the art without departing from the scope of the present invention as defined solely by the claims appended herein.

Claims

1. Oxide semiconductor channel layer, An oxide semiconductor channel stack comprising: a conditioning layer formed on the oxide semiconductor channel layer, wherein the conditioning layer draws out undesirable atoms from the region of the oxide semiconductor channel layer adjacent to the conditioning layer, thereby reducing defects.

2. The oxide semiconductor channel stack according to claim 1, wherein the adjustment layer has a negative reduction potential.

3. The oxide semiconductor channel stack according to claim 2, wherein the adjustment layer is selected from the group including titanium, hafnium, zirconium, or tantalum.

4. The oxide semiconductor channel stack according to claim 1, wherein the oxide semiconductor channel layer is tin oxide and the adjustment layer is titanium.

5. The oxide semiconductor channel stack according to claim 1, wherein the oxide semiconductor channel layer is a nitrogen-fixed metal oxide.

6. The oxide semiconductor channel stack according to claim 1, wherein the oxide semiconductor channel layer is a layer of tin oxide having a thickness of about 3 nm to about 15 nm.

7. The oxide semiconductor channel stack according to claim 1, wherein the oxide semiconductor channel layer is a layer of tin oxide having a thickness of about 5 nm to about 10 nm.

8. The oxide semiconductor channel stack according to claim 1, wherein the undesirable atom includes an oxygen atom, and the region of the oxide semiconductor channel layer from which the oxygen atom is extracted has a thickness ranging from about 2 nm to the total thickness of the oxide semiconductor layer.

9. The oxide semiconductor channel stack according to claim 1, further comprising an intervening layer formed between the oxide semiconductor channel layer and the adjustment layer.

10. The oxide semiconductor channel stack according to claim 9, wherein the intervening layer is a gate dielectric and the adjustment layer is a gate contact.

11. The steps include forming an oxide semiconductor channel layer on a substrate, A method for forming an oxide semiconductor stack, comprising the step of forming the adjusting material on the oxide semiconductor channel layer in order to extract undesirable atoms from a region of the oxide semiconductor channel layer adjacent to the adjusting material.

12. The method according to claim 11, further comprising the step of forming a layer of interposing material between the oxide semiconductor channel layer and the adjustment material.

13. The method according to claim 12, wherein the intervening material is a gate dielectric and the adjusting material is a gate contact.

14. The method according to claim 12, wherein, after undesirable atoms are extracted from the region of the oxide semiconductor channel layer, the intervening material and the conditioning material are removed from the oxide semiconductor stack and replaced by a gate dielectric and a gate contact, respectively.

15. The method according to claim 11, further comprising the step of forming a metal layer on the adjustment material layer.

16. circuit board and A source formed on the substrate, A drain formed on the substrate and spaced apart from the source, A source channel interface member formed on the source, An oxide semiconductor channel layer formed on the substrate, extending between the source channel interface member and the drain and connecting them, An intervening layer including a gate dielectric formed on the oxide semiconductor channel layer, A thin-film transistor comprising a regulating material including a metal gate contact formed on the intervening layer, wherein the regulating material extracts undesirable atoms from a region of the oxide semiconductor channel layer adjacent to the regulating material, thereby reducing defects.

17. The thin-film transistor according to claim 16, wherein the undesirable atoms include an excess of oxygen atoms.

18. The thin-film transistor according to claim 16, wherein the aforementioned undesirable atoms are included in the impurities.

19. The thin-film transistor according to claim 16, wherein the adjusting material is a metal selected from the group including titanium, hafnium, zirconium, and / or tantalum.

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