Novel process technology for embedded memory

Abstract

A single integrated circuit is provided, comprising a memory region and a non-memory region. The memory region comprises a first conductive structure, a memory element disposed on the first conductive structure, and a first via disposed on the memory element. The non-memory region comprises a second conductive structure and a second via disposed on the second conductive structure. The first and second conductive structures are formed by a first photolithography process including a first photomask, and the first conductive structure is configured to become a first lower electrode in the memory region. The first and second vias are formed by a third photolithography process including a third photomask. The first and third photomasks have the same pattern.

Description

[Technical Field]

[0001] This invention relates in general to new process technologies for embedded memory, and more specifically to embedded memory integration technologies that reduce photomask costs. [Background technology]

[0002] Resistive random access memory (RRAM) is a type of non-volatile memory that can change its resistance to either a low resistance state (LRS) or a high resistance state (HRS) by applying an appropriate voltage to the device. It can store digital data "0" and "1" by utilizing the difference in resistance (LRS vs. HRS).

[0003] RRAM is a general-purpose memory technology. It can be used as both standalone and embedded memory. Regarding embedded memory, RRAM requires additional photomasks to be successfully integrated into an integrated circuit (IC). Conventional RRAM processes require the integration of two to three additional photomasks onto the IC chip.

[0004] In semiconductor processing, photomasks account for a significant portion of the total processing cost, and this portion increases as processes move to more sophisticated nodes. Therefore, processes using fewer photomasks are attracting considerable interest. This is a major advantage for non-volatile memory, as this type of memory technology requires far fewer photomasks compared to conventional embedded non-volatile memory (usually based on embedded flash technology), which requires >10 additional photomasks. Conventional embedded RRAM process flows require two or more additional photomasks: the first mask is used to define the RRAM bottom electrode (BE), and the second mask is used to define where the RRAM cells are located. [Overview of the project]

[0005] According to a first aspect of the present invention, a single integrated circuit is provided that includes a memory region and a non-memory region. The memory region includes a first conductive structure, a memory element disposed on the first conductive structure, and a first via disposed on the memory element. The non-memory region includes a second conductive structure and a second via disposed on the second conductive structure. The first and second conductive structures are formed by a first photolithography process including a first photomask, wherein the first conductive structure is configured to become a first lower electrode in the memory region.

[0006] In some embodiments, the memory element includes a dielectric layer disposed on a first lower electrode, a cap layer disposed on the dielectric layer, and an upper electrode disposed on the cap layer.

[0007] In some embodiments, the memory region further includes stacked lower electrodes positioned on top of the first lower electrode.

[0008] In some embodiments, the memory region further includes a first upper metal layer positioned on the first via.

[0009] In some embodiments, the memory region further includes a first lower metal layer. The first lower electrode is disposed on the first lower metal layer.

[0010] In some embodiments, the non-memory region is disposed on the second via Second upper metal layer and further includes.

[0011] In some embodiments, the non-memory region further includes a second lower metal layer. The second conductive structure is disposed on the second lower metal layer.

[0012] In some embodiments, the first lower metal layer and the second lower metal layer are formed using a first metallization process.

[0013] In some embodiments, the first upper metal layer and the second upper metal layer are formed using a second metallization process.

[0014] In some embodiments, the second via does not surround the side portion of the second conductive structure.

[0015] In some embodiments, the second via partially surrounds the side portion of the second conductive structure.

[0016] In some embodiments, the second via completely surrounds the side portion of the second conductive structure.

[0017] In some embodiments, a plurality of second conductive structures are disposed on a single second lower metal layer within the non-memory region.

[0018] In some embodiments, only a single first lower electrode is disposed on a single first lower metal layer within the memory region.

[0019] In some embodiments, the memory element is one of the following: resistive random access memory (RRAM), conductive-bridge random access memory (CBRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FeRAM), and phase-change random access memory (PCRAM).

[0020] In some embodiments, the first and second vias are formed by a third photolithography process including a third photomask.

[0021] In some embodiments, the first photomask and the third photomask have the same pattern.

[0022] A second aspect of the present invention provides a method for manufacturing an integrated circuit, the method comprising defining memory regions and non-memory regions on a semiconductor wafer, depositing a first interlayer dielectric layer on a first lower metal layer in the memory region and a second lower metal layer in the non-memory region, and etching the first interlayer dielectric layer using a first photolithography process including a first photomask to form a first conductive structure in the memory region and a second conductive structure in the non-memory region, wherein the first conductive structure becomes a first lower electrode in the memory region. The method comprises: depositing a memory stack layer in a memory region and a non-memory region; forming a memory element in the memory region by etching the memory stack layer using a second photolithography process including a second photomask; depositing a second interlayer dielectric layer in the memory region and a non-memory region; and forming a first via in the memory region and a second via in the non-memory region by etching the second interlayer dielectric layer using a third photolithography process including a third photomask. The first and third photomasks have the same pattern.

[0023] In some embodiments, the memory stack layer includes a dielectric layer, a capping layer, and an upper electrode layer.

[0024] In some embodiments, the memory stack layer further includes a lower electrode layer.

[0025] In some embodiments, the method further includes using a first metallization process to form a first lower metal layer in the memory area and a second lower metal layer in the non-memory area.

[0026] In some embodiments, the method further includes using a second metallization process to form a first upper metal layer in the memory area and a second upper metal layer in the non-memory area.

[0027] Non-limiting embodiments of the present invention will be more readily understood by referring to the following drawings. [Brief explanation of the drawing]

[0028] [Figure 1] This is a schematic diagram showing embedded RRAM manufactured using a conventional process. [Figure 2] This is a schematic diagram showing an embedded RRAM fabricated by a novel process according to an embodiment of the present invention. [Figure 3A-3C] This is a schematic diagram showing a modified example of via and BE connections in a non-RRAM area in a novel process of embedded RRAM according to an embodiment of the present invention. [Figure 4] This is a schematic diagram showing a top view of the non-RRAM region BE and the RRAM region RRAM BE in a novel process for embedded RRAM according to an embodiment of the present invention. [Figure 5A-5B] This is a schematic diagram showing the thickness and material of the RRAM stack layer in a novel process for embedded RRAM according to an embodiment of the present invention. [Figures 6A-6E] This is a schematic diagram illustrating a novel process flow for an embedded RRAM according to an embodiment of the present invention. [Figure 6F-6I] This is a schematic diagram illustrating a novel process flow for an embedded RRAM according to an embodiment of the present invention. [Modes for carrying out the invention]

[0029] Figure 1 shows an embedded RRAM fabricated using a conventional process that requires two or more additional photomasks. The wafer is divided into a non-RRAM region 110 and an RRAM region 120. In this example, the RRAM process involves a metal layer M x+1The process begins with layers 111 and 121. An interlayer dielectric (ILD) is then deposited, followed by a first lithography pattern formation. In the first lithography process, a first photomask is used to pattern the RRAM lower electrode (BE) 122 within the RRAM region 120. The wafer then undergoes deposition of the RRAM BE material, followed by a chemical mechanical polishing (CMP) process and RRAM stack deposition. The RRAM stack includes a dielectric layer 123, a cap layer 124, and an upper electrode 125. A hard mask layer 126 is also deposited on top of the RRAM stack. The wafer then undergoes a second photolithography to define the RRAM cells. In the non-RRAM regions, the RRAM stack is removed. The second lithography process is performed using an RRAM photomask, which is the second photomask used in this process flow. Subsequently, the ILD layer is deposited and CMP is performed again, and the upper electrode 125 of the RRAM cell is connected to other circuits using a standard CMOS wiring (BEOL: backend-of-the-line) process flow. In this example, via V x+1 127 and metal layer M x+2 128 is used, via V x+1 via 127 etches through the hard mask 126 and connects to the RRAM upper electrode 125 of the RRAM region 120. In the non-RRAM region 110, via V x+1 117 is the metal layer M x+1 It connects directly to 111. In short, this conventional RRAM process requires at least two different photomasks: one for patterning the RRAM lower electrodes and another for patterning the RRAM cells.

[0030] As shown in Figure 1, conventional processes generally require two or more different photomasks for embedded memory, which significantly increases the cost of implementing embedded memory. Therefore, there is an urgent need to reduce the number of different photomasks for embedded memory and thereby reduce the cost of photomask design.

[0031] FIG. 2 is a schematic diagram showing an embedded RRAM fabricated by a novel process according to an embodiment of the present invention. According to an embodiment of the present invention, in the case of this new process, only one additional photomask needs to be designed (the "one-mask" process), which can significantly reduce the cost of designing the additional photomask and enable the RRAM to be more competitive.

[0032] Compared with the embedded RRAM fabricated by the conventional process of FIG. 1, the embedded RRAM fabricated by the one-mask process shown in FIG. 2 has differences in the connection of vias and metal layers in the non-RRAM region 210. The via V x+1 217 is stacked on a conductive structure 212 connected to the metal layer M x+1 211. Such a conductive structure in the non-RRAM region has basically the same structure as the BE in the RRAM region and, for the sake of convenience, it is also referred to as BE throughout this specification. However, it does not function as a bottom electrode within the non-memory region. FIGS. 3A to 3C are schematic diagrams showing variations in the connection of vias V x+1 and BE in the non-RRAM region in the novel process of the embedded RRAM according to an embodiment of the present invention.

[0033] As shown in FIG. 3A, a via V x+1 317a is stacked on the BE312a of the non-RRAM region 310a. As shown in FIG. 3B, a via V x+1 317b completely surrounds the BE312b of the non-RRAM region 310b. As shown in FIG. 3C, a via V x+1 317c partially surrounds the BE312c of the non-RRAM region 310c.

[0034] FIG. 4 is a schematic top view showing the BE in the non-RRAM region and the RRAM BE in the RRAM region in the novel process of the embedded RRAM according to an embodiment of the present invention.

[0035] As shown in FIG. 4, in the non-RRAM region 410, an independent metal layer Mx+1 There can be zero, one, or more BEs on top of it. For example, metal layer M x+1 411d has 0 BEs. Metal layer M x+1 411c contains one BE412c. Metal layer M x+1 411b contains two BE412b. Metal layer M x+1 411a has four BE412a. In contrast, RRAM region 420 has only one RRAM BE422a, which is located in an independent metal layer M x+1 It is located at 421a.

[0036] Figures 5A and 5B are schematic diagrams showing the thickness and material of the RRAM stack layer in a novel process for embedded RRAM according to an embodiment of the present invention.

[0037] The RRAM region 520 can contain two types of RRAM stacks: (a) an RRAM with only one BE material as shown in Figure 5A, and (b) an RRAM with two lower electrodes as shown in Figure 5B. Referring to Figure 5A, the thickness of the RRAM BE522 may be 5 nm to 500 nm, and the material of the RRAM BE522 may be a metal (Ti, Hf, Ta, Ru, Ir, Pt, etc.), a metal oxide (TiOx, TaOx, HfOx, etc.), a metal nitride (TiN, TaN, AlN, etc.), a metal oxynitride (TiON, TaON, AlON, etc.), or another suitable conductive material. The thickness of the dielectric layer 523 may be 0.1 nm to 50 nm, and the material of the dielectric layer 523 may be a dielectric (SiO2, Ta2O5, TiO2, ZrO2, HfO2, Al2O3, etc.), including mixtures and / or combinations of these materials. The thickness of the cap layer 524 may be 1 nm to 500 nm, and the material of the cap layer 524 may be a metal (Ti, Hf, Ta, Ru, Ir, Pt, etc.), a metal oxide (TiOx, TaOx, HfOx, etc.), a metal nitride (TiN, TaN, AlN, etc.), a metal oxynitride (TiON, TaON, AlON, etc.), or another suitable conductive material. The thickness of the upper electrode 525 may be 1 nm to 500 nm, and the material of the upper electrode 525 may be a metal (Ti, Hf, Ta, Ru, Ir, Pt, etc.), a metal oxide (TiOx, TaOx, HfOx, etc.), a metal nitride (TiN, TaN, AlN, etc.), a metal oxynitride (TiON, TaON, AlON, etc.), or another suitable conductive material. Hard mask layer 526 The material may be SiN.

[0038] Referring to Figure 5B, there is a second RRAM BE522a deposited between the dielectric layer 523 and the first RRAM BE522. The thickness of the second RRAM BE522a may be 1 nm to 500 nm, and the material of the second RRAM BE522a may be a metal (Ti, Hf, Ta, Ru, Ir, Pt, etc.), a metal oxide (TiOx, TaOx, HfOx, etc.), a metal nitride (TiN, TaN, AlN, etc.), a metal oxynitride (TiON, TaON, AlON, etc.), or another suitable conductive material.

[0039] Figures 6A to 6I are schematic diagrams illustrating a novel process for an embedded RRAM according to an embodiment of the present invention. The novel process flow may include the following steps.

[0040] As shown in Figure 6A, the wafer can be divided into a non-RRAM region 610 and an RRAM region 620. In this example, the RRAM process is carried out on a metal layer M x+1 Start from here.

[0041] Next, interlayer dielectric (ILD) is deposited (Figure 6B), followed by the formation of the first lithography pattern of the BE in the non-RRAM region 610 and the RRAM region 620 (Figure 6C). In this first lithography pattern formation, via V x+1 It should be noted that the same photomask used to pattern the BE in the non-RRAM region 610 and the RRAM region 620 is used to pattern the BE in the non-RRAM region 610 and the RRAM region 620. In other words, no additional photomasks are required for lithographic patterning of the BE in the non-RRAM region 610 and the RRAM region 620.

[0042] The wafer then undergoes deposition of BE material (Figure 6D), followed by the deposition of a metal layer M in the non-RRAM region 610 and the RRAM region 620. x+1 A chemical mechanical polishing (CMP) process (Figure 6E) is then performed to deposit BE622 on top of this.

[0043] As shown in Figure 6F, the wafer then undergoes deposition of an RRAM stack. The RRAM stack includes a dielectric layer 623, a capping layer 624, and an upper electrode 625. A hard mask layer 626 is also deposited on top of the RRAM stack.

[0044] As shown in Figure 6G, the wafer then undergoes a second photolithography to define the RRAM cells. In the non-RRAM region 610, the RRAM stack will be removed. Note that the second photolithography is performed using an RRAM photomask, which is the only additional photomask used in this process flow.

[0045] As shown in Figure 6H, the ILD layer is deposited and CMP is performed again.

[0046] As shown in Figure 6I, the connection of the upper electrode 625 of the RRAM cell to other circuits is performed in a standard CMOS BEOL process flow. In this example, via V x+1 627 and metal layer M x+2 628 is used, via V x+1 627 is etched through the hard mask 626 and connects to the RRAM upper electrode 625. In the non-RRAM region 610, via V x+1 617 is directly connected to BE612, and BE612 is further connected to metal layer M x+1 Connects to port 611.

[0047] According to embodiments of the present invention, the metal layer M of the memory region x+1 and the metal layer M in the non-memory area x+1 (M in Figure 2) x+1 221 and M x+1 211 etc.) may be formed simultaneously using the same metallization process, and the metal layer M of the memory region x+1 However, the metal layer M in the non-memory area x+1 It is OK to connect to it.

[0048] According to embodiments of the present invention, the metal layer M of the memory region x+2 And the metal layer M in the non-memory area x+2 (M in Figure 2) x+2 228 and M x+2 218 etc.) may be formed simultaneously using the same metallization process, and the metal layer M of the memory region x+2 However, the metal layer M in the non-memory area x+2 It is OK to connect to it.

[0049] RRAM memory array is metal layer M x+1 and metal layer M x+2 In the proposed process flow described above, taking as an example that it is placed between via V, this one mask process for the embedded RRAM is via V x+1 The BE (Figure 6C) of the non-RRAM area 610 and RRAM area 620 is defined using the same photomask used to define the RRAM cell (Figure 6G). In this case, the only additional photomask required is for defining the RRAM cell. When the RRAM loop ends, via V x+1 The photomask used to define via V is reused. x+1 Place via V x+1 In the non-RRAM region 610, the metal layer M is accessed via BE. x+1 metal layer M x+2 Connected to the metal layer M in the RRAM region 620. x+2 Connect it to the upper electrode of the RRAM (Figure 6I).

[0050] The process flows according to embodiments of the present invention are not limited to those described herein and can be applied to other built-in-line (BEOL) memories, including conductive bridge RAM (CBRAM), magnetic RAM (MRAM), ferroelectric RAM (FeRAM), and phase-change RAM (PCRAM).

[0051] The novel process technology according to embodiments of the present invention has the advantage of reducing the number of additional photomasks required for embedded memory to just one, thereby significantly reducing mask costs. Compared to existing embedded memory integration methods, this technology has the potential to reduce photomask costs by more than 50%.

[0052] The above description of the exemplary embodiments of the Invention, including those described in the abstract, is not intended to be exhaustive or to limit the Invention to the embodiments disclosed herein. Specific embodiments and examples of the Invention are described herein for illustrative purposes, but as those skilled in the art will recognize, a variety of equivalent variations are possible within the scope of the Invention. Other embodiments may have different order of layers, additional layers, or fewer layers than those described.

[0053] Various operations are described as multiple separate operations, and in a manner most useful for understanding the present invention; however, the order of the descriptions should not be interpreted as suggesting that these operations are necessarily dependent on a specific order. In detail, these operations do not need to be performed in the order presented.

[0054] As used herein, the terms “on,” “above,” “below,” “between,” and “above” refer to the relative position of one material layer or component with respect to another layer or component. For example, one layer deposited above, on, or below another layer may be in direct contact with the other layer, or may have one or more intervening layers. Furthermore, one layer deposited between two layers may be in direct contact with these two layers, or may have one or more intervening layers. In contrast, the first layer “on” the second layer is in direct contact with the second layer. Similarly, unless expressly stated otherwise, one feature deposited between two feature parts may be in direct contact with those adjacent feature parts, or may have one or more intervening layers.

[0055] The words “example” or “exemplary” are intended in this specification to serve the role of example, case, or illustration. No aspect or design described herein as “example” or “exemplary” should necessarily be construed as preferable or advantageous to any other aspect or design. Rather, the use of the words “example” or “exemplary” is intended to concretely present a concept. Where used in this application, the word “or” is intended to mean inclusive “or” rather than exclusive “or.” That is, unless otherwise specified or evident from the context, “X includes A or B” is intended to mean either of the obvious inclusive substitutions. That is, if X includes A, X includes B, or X includes both A and B, then “X includes A or B” satisfies any of the above examples. In addition, the articles “a” and “an” as used in this application and the appended claims may generally be construed as meaning “one or more” unless otherwise specified to lead to a singular form or evident from the context. Furthermore, the phrase throughout the whole, "one embodiment" or "one embodiment" or " One example "or" One example The use of "" is the same embodiment or example It is not intended to mean that. The terms "first," "second," "third," "fourth," etc., used herein are intended as indicators to distinguish different elements from each other and do not necessarily carry the meaning of an order according to their numerical designations. The inventions disclosed herein include the following: [Aspect 1] A single integrated circuit, First conductive structure, A memory element disposed on the first conductive structure, and The first via is located on the memory element. A memory area comprising, A second conductive structure, and A second via placed on the second conductive structure A non-memory area comprising, A single integrated circuit comprising the first conductive structure and the second conductive structure, formed by a first photolithography process including a first photomask, wherein the first conductive structure is configured to become a first lower electrode in the memory region. [Aspect 2] The aforementioned memory element is A dielectric layer disposed on the first lower electrode, A cap layer disposed on the dielectric layer, A single integrated circuit according to embodiment 1, comprising an upper electrode disposed on the cap layer. [Aspect 3] The aforementioned memory area A single integrated circuit according to embodiment 2, further comprising a stacked lower electrode disposed on the first lower electrode. [Aspect 4] The aforementioned memory area A single integrated circuit according to embodiment 1, further comprising a first upper metal layer disposed on the first via. [Aspect 5] The aforementioned memory area A single integrated circuit according to embodiment 4, further comprising a first lower metal layer, wherein the first lower electrode is disposed on the first lower metal layer. [Aspect 6] The aforementioned non-memory area is A single integrated circuit according to embodiment 5, further comprising a second upper metal layer disposed on the second via. [Aspect 7] The aforementioned non-memory area is A single integrated circuit according to embodiment 6, further comprising a second lower metal layer, wherein the second conductive structure is disposed on the second lower metal layer. [Aspect 8] A single integrated circuit according to embodiment 7, wherein the first lower metal layer and the second lower metal layer are formed using a first metallization process. [Aspect 9] A single integrated circuit according to embodiment 8, wherein the first upper metal layer and the second upper metal layer are formed using a second metallization process. [Aspect 10] A single integrated circuit according to embodiment 1, wherein the second via does not surround the side of the second conductive structure. [Aspect 11] A single integrated circuit according to embodiment 1, wherein the second via partially surrounds the side of the second conductive structure. [Aspect 12] A single integrated circuit according to embodiment 1, wherein the second via completely encloses the side of the second conductive structure. [Aspect 13] A single integrated circuit according to embodiment 1, wherein a plurality of the second conductive structures are arranged on a single second lower metal layer in the non-memory region. [Aspect 14] A single integrated circuit according to embodiment 1, wherein only a single first lower electrode is located on a single first lower metal layer within the memory region. [Aspect 15] The aforementioned memory element is Resistive random-access memory (RRAM), Conductive bridge random access memory (CBRAM), Magnetic Random Access Memory (MRAM), Ferroelectric random-access memory (FeRAM), and Phase-change random-access memory (PCRAM) A single integrated circuit according to Embodiment 1, which is one of the features of the invention. [Aspect 16] A single integrated circuit according to embodiment 1, wherein the first via and the second via are formed by a third photolithography process including a third photomask. [Aspect 17] A single integrated circuit according to embodiment 16, wherein the first photomask and the third photomask have the same pattern. [Aspect 18] A method for manufacturing an integrated circuit, Defining memory areas and non-memory areas on a semiconductor wafer, A first interlayer dielectric layer is deposited on the first lower metal layer in the memory region and the second lower metal layer in the non-memory region. The invention relates to forming a first conductive structure within the memory region and a second conductive structure within the non-memory region by etching the first interlayer dielectric layer using a first photolithography process including a first photomask, wherein the first conductive structure is configured to become a first lower electrode of the memory region. Depositing a memory stack layer within the memory region and the non-memory region, Forming memory elements within the memory region by etching the memory stack layer using a second photolithography process including a second photomask, Depositing a second interlayer dielectric layer within the memory region and the non-memory region, A method comprising etching the second interlayer dielectric layer using a third photolithography process including a third photomask to form a first via in the memory region and a second via in the non-memory region, wherein the first photomask and the third photomask have the same pattern. [Aspect 19] The aforementioned memory stack layer, Dielectric layer and, The cap layer and Upper electrode layer and The method according to embodiment 18, including the method described in embodiment 18. [Aspect 20] The aforementioned memory stack layer, The method according to embodiment 19, further comprising a lower electrode layer. [Aspect 21] The method according to embodiment 18, further comprising using a first metallization process to form the first lower metal layer in the memory region and the second lower metal layer in the non-memory region. [Aspect 22] The method according to embodiment 21, further comprising using a second metallization process to form a first upper metal layer in the memory region and a second upper metal layer in the non-memory region.

Claims

1. A single integrated circuit, First conductive structure, A memory element disposed on the first conductive structure, and The first via is located on the memory element. A memory area comprising, A second conductive structure, and A second via placed on the second conductive structure A non-memory area comprising, A single integrated circuit comprising the first conductive structure and the second conductive structure, formed by a first photolithography process including a first photomask, wherein the first conductive structure is configured to become a first lower electrode in the memory region.

2. The aforementioned memory element is A dielectric layer disposed on the first lower electrode, A cap layer disposed on the dielectric layer, A single integrated circuit according to claim 1, comprising an upper electrode disposed on the cap layer.

3. The aforementioned memory area The single integrated circuit according to claim 2, further comprising a stacked lower electrode disposed on the first lower electrode.

4. The aforementioned memory area The single integrated circuit according to claim 1, further comprising a first upper metal layer disposed on the first via.

5. The aforementioned memory area A single integrated circuit according to claim 4, further comprising a first lower metal layer, wherein the first lower electrode is disposed on the first lower metal layer.

6. The aforementioned non-memory area is The single integrated circuit according to claim 5, further comprising a first upper metal layer disposed on the second via.

7. The aforementioned non-memory area is A single integrated circuit according to claim 6, further comprising a second lower metal layer, wherein the second conductive structure is disposed on the second lower metal layer.

8. The single integrated circuit according to claim 7, wherein the first lower metal layer and the second lower metal layer are formed using a first metallization process.

9. The single integrated circuit according to claim 8, wherein the first upper metal layer and the second upper metal layer are formed using a second metallization process.

10. The single integrated circuit according to claim 1, wherein the second via does not surround the side of the second conductive structure.

11. The single integrated circuit according to claim 1, wherein the second via partially surrounds the side of the second conductive structure.

12. The single integrated circuit according to claim 1, wherein the second via completely encloses the side of the second conductive structure.

13. A single integrated circuit according to claim 1, wherein a plurality of the second conductive structures are arranged on a single second lower metal layer in the non-memory region.

14. A single integrated circuit according to claim 1, wherein only a single first lower electrode is located on a single first lower metal layer within the memory region.

15. The aforementioned memory element is Resistive random-access memory (RRAM), Conductive bridge random access memory (CBRAM), Magnetic Random Access Memory (MRAM), Ferroelectric random-access memory (FeRAM), and Phase-change random-access memory (PCRAM) A single integrated circuit according to claim 1, which is one of the features of the invention.

16. The single integrated circuit according to claim 1, wherein the first via and the second via are formed by a third photolithography process including a third photomask.

17. A single integrated circuit according to claim 16, wherein the first photomask and the third photomask have the same pattern.

18. A method for manufacturing an integrated circuit, Defining memory areas and non-memory areas on a semiconductor wafer, A first interlayer dielectric layer is deposited on the first lower metal layer in the memory region and the second lower metal layer in the non-memory region. The invention involves forming a first conductive structure in the memory region and a second conductive structure in the non-memory region by etching the first interlayer dielectric layer using a first photolithography process including a first photomask, wherein the first conductive structure is configured to become the first lower electrode of the memory region. Depositing a memory stack layer within the memory region and the non-memory region, Forming memory elements within the memory region by etching the memory stack layer using a second photolithography process including a second photomask, Depositing a second interlayer dielectric layer within the memory region and the non-memory region, A method comprising etching the second interlayer dielectric layer using a third photolithography process including a third photomask to form a first via in the memory region and a second via in the non-memory region, wherein the first photomask and the third photomask have the same pattern.

19. The aforementioned memory stack layer, Dielectric layer and, The cap layer and Upper electrode layer and The method according to claim 18, including the method described in claim 18.

20. The aforementioned memory stack layer, The method according to claim 19, further comprising a lower electrode layer.

21. The method according to claim 18, further comprising using a first metallization process to form the first lower metal layer in the memory region and the second lower metal layer in the non-memory region.

22. The method according to claim 21, further comprising using a second metallization process to form a first upper metal layer in the memory region and a second upper metal layer in the non-memory region.

Images