Conductive pads in silicon through-vias

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate having a front side and a back side opposite the front side. Through-vias extend completely through the substrate. Through-vias include projections that extend beyond the back side of the substrate. A layer of silicon-carbon nitride is disposed on the back side of the substrate and along the sidewalls of the through-via projections. An oxide layer is disposed on the back side of the substrate and at least partially surrounds the through-via projections. A conductive pad is disposed on the bonding surface of the through-via and at least partially extends through the oxide layer. As a result, a reliable and cost-effective semiconductor device can be assembled.

Description

【Technical Field】 【0001】 The present disclosure generally relates to semiconductor device assemblies, and more particularly to conductive pads in through-silicon vias (TSVs). 【Background Art】 【0002】 Microelectronic devices generally have a die (e.g., a chip) that includes integrated circuits with very small components at high density. Typically, a die includes an array of bonding pads electrically coupled to the integrated circuit. The bonding pads are external electrical contacts through which supply voltages, signals, etc. pass when being transmitted to and from the integrated circuit. After the dies are formed, they are “packaged” to couple the bonding pads to a larger array of electrical terminals that can be more easily coupled to various power lines, signal lines, and ground lines. Conventional processes for packaging dies include coupling the bonding pads on the die to an array of lead wires, ball pads, or other types of electrical terminals and encapsulating the dies to protect them from ambient factors (e.g., moisture, particles, electrostatic charge, physical shock). 【Brief Description of the Drawings】 【0003】 [Figure 1] Shows a simplified schematic cross-sectional view of a semiconductor device assembly. [Figure 2] Shows a simplified schematic cross-sectional view of a semiconductor device assembly according to an embodiment of the present technology. [Figure 3] Shows a simplified schematic cross-sectional view of a series of steps for manufacturing a semiconductor device assembly according to an embodiment of the present technology. [Figure 4] Shows a simplified schematic cross-sectional view of a series of steps for manufacturing a semiconductor device assembly according to an embodiment of the present technology. [Figure 5] Shows a simplified schematic cross-sectional view of a series of steps for manufacturing a semiconductor device assembly according to an embodiment of the present technology. [Figure 6] A simplified schematic cross-sectional view of a series of steps for manufacturing a semiconductor device assembly according to an embodiment of this technology is shown. [Figure 7] This is a schematic diagram of a system including a semiconductor device assembly configured according to an embodiment of this technology. [Figure 8] This document describes a method for manufacturing a semiconductor device assembly according to an embodiment of this technology. [Modes for carrying out the invention] 【0004】 Semiconductor devices are integrated into many devices to implement memory cells, processor circuits, imaging devices, and other functional features. As more applications for semiconductor devices are discovered, designers are tasked with creating improved devices that can perform more operations per second, store more data, or operate at a higher level of safety. To accomplish this task, designers continue to develop new techniques to increase the number of circuit elements on a semiconductor device without simultaneously increasing the size of the device. This development, however, may not be sustainable due to the various challenges arising from designing semiconductor devices with high circuit density. Therefore, additional technologies may be required to sustain the growth in the capabilities of semiconductor devices. 【0005】 One such technique is the implementation of multiple circuit components within a single package. For example, stacking semiconductor devices allows for stacking multiple semiconductor dies on top of each other, increasing the number of circuit elements in a package without increasing its footprint. In some cases, individual semiconductor dies may be stacked on top of each other to create a vertical stack of semiconductor dies. A semiconductor die may include through-silicon vias (TSVs) extending between its front side (e.g., the active side where the circuit is located) and its opposite back side. Contact pads may be positioned on the back side of the semiconductor die that contacts the exposed portion of the TSV, so that additional semiconductor dies can be electrically coupled there. Various techniques exist for positioning contact pads on TSVs, but some of these techniques can be excessively time-consuming, or semiconductor devices manufactured using some of these techniques may have reliability or cost concerns. An example semiconductor device is shown in Figure 1. 【0006】 Figure 1 shows a semiconductor device assembly 100 including a semiconductor die 102. The semiconductor die 102 may be assembled on a carrier wafer so that it can withstand processing. The semiconductor die 102 includes a substrate 104 (e.g., a silicon substrate, an organic substrate, a printed circuit board (PCB) core, etc.) with a metallization layer 106 (e.g., connection circuits such as traces, lines, and vias) on its front side. The TSV 108 extends entirely through the substrate 104 from the front side to the back side opposite the front side. Contact pads 110 may be located on the bonding surface 112 of the TSV 108 exposed on the back side of the substrate 104. The contact pads 110 may be located within a layer 114 of oxide (e.g., high-temperature silicon oxide deposited at temperatures above 300°C, 400°C, 500°C, or 700°C). 【0007】 Various techniques can be used to position the contact pads 110 of the TSV108. For example, first, the TSV108 may protrude beyond the back side of the substrate 104 (e.g., by a difference of more than 3 microns). A layer 116 of silicon nitride (e.g., low-temperature silicon nitride deposited at temperatures below 200°C, 300°C, or 400°C) may be positioned on the back side of the substrate, along the sidewalls of the TSV108 and covering the top of the TSV108. In some cases, the silicon nitride layer is positioned with a thickness of more than 1 micron. A layer of oxide (not shown), such as a low-temperature oxide, may then be deposited on the back side of the semiconductor die 102, covering the silicon nitride layer 116. The oxide layer may be positioned with a thickness of about 0.5 microns (e.g., less than 0.1 microns, less than 0.2 microns, etc.). The material may then be removed from the back side of the semiconductor die 102 by chemical mechanical planarization (CMP) to expose the TSV108. For example, the oxide layer may be completely removed, and the silicon nitride layer 116 may be thinned to about 1 micron (e.g., 0.1 micron or less, 0.2 micron or less, 0.5 micron or less, etc.). In this way, the back side of the semiconductor die 102 may correspond to a planarized silicon nitride layer 116 having an exposed TSV 108 bonding surface 112. 【0008】 A layer 118 of silicon-carbon nitride (e.g., high-temperature silicon-carbon nitride) may then be placed on top of a silicon nitride layer 116 and covering the bonding surface 112 of the TSV 108. An oxide layer 114 may be placed on the back side of the semiconductor die 102 covering the silicon-carbon nitride layer 118. An additional layer 120 of silicon-carbon nitride (e.g., high-temperature silicon-carbon nitride) may then be placed over the oxide layer 114. The silicon-carbon nitride layer 118, the oxide layer 114, and the silicon-carbon nitride layer 120 may be etched (e.g., dry etched) to expose the bonding surface 112 of the TSV 108. A contact pad 110 may then be placed in an opening in the bonding surface 112 such that the contact pad 110 is exposed on the back side of the semiconductor die 102. In this case, an additional semiconductor die may be stacked within the semiconductor die 102 and electrically coupled by the contact pad 110. 【0009】 Using these techniques to place contact pads on TSVs may not be optimal for a number of reasons. As described above, the process may involve multiple deposition steps to place various layers on the back of the semiconductor die 102 (e.g., a silicon nitride layer 116 or an oxide layer that is later removed). As a result, the design process may be time-consuming and incur high material costs. Furthermore, the bonding surface 112 of the TSV 108 may be exposed by CMP, which may cause conductive material within the TSV 108 to spread to the back of the semiconductor die 102, or cause fracture of the semiconductor die 102. Thus, the use of CMP may reduce the reliability of the semiconductor die 102 or reduce the yield. In yet another embodiment, the use of CMP in a region that includes or does not include the TSV 108 may result in surface irregularities (e.g., variations in height up to 200 nanometers) on the back surface of the semiconductor die 102. This unevenness may arise from the tendency for the effects of CMP to be less pronounced in the region containing TSV108 compared to the region without TSV108. In some cases, this unevenness may make the semiconductor die 102 fragile, or make it difficult to stack additional semiconductor dies on semiconductor die 102. In some embodiments, the unevenness may reduce the reliability of the metal-metal bond in TSV108 (e.g., by DC resistance yield). Therefore, designing semiconductor devices using these techniques may result in semiconductor devices with reliability concerns, or incur unnecessary costs or manufacturing time. 【0010】 To address these and other drawbacks, various embodiments of the present technology provide semiconductor device assemblies including contact pads arranged on TSVs. The semiconductor device includes a substrate having a front side and a back side opposite to the front side. Through vias extend entirely through the substrate. Through vias include projections that extend beyond the back side of the substrate. A layer of silicon-carbon nitride is arranged on the back side of the substrate and along the sidewalls of the through via projections. An oxide layer is arranged on the back side of the substrate and at least partially surrounding the through via projections. Conductive pads are arranged on the bonding surface of the through vias and at least partially extending through the oxide layer. As a result, reliable and cost-effective semiconductor devices can be assembled, an example of which is shown in Figure 2. 【0011】 Figure 2 shows a semiconductor device assembly 200 including a semiconductor die 202. The semiconductor die 202 may be assembled onto a carrier wafer so that it can withstand processing. The semiconductor die 202 includes a substrate 204 having a metallization layer 206 on its front side (e.g., having connection circuits such as traces, lines, and vias). The TSV 208 extends entirely through the substrate 204 from the front side to the back side opposite the front side. Contact pads 210 may be located on the bonding surface 212 of the TSV 208. The contact pads 210 may be located within a layer 214 of oxide (e.g., high-temperature silicon oxide) and exposed on the back side of the semiconductor die 202. A layer 216 of silicon nitride (e.g., high-temperature silicon nitride) may be located on the back side of the substrate 204, and a layer 218 of silicon nitride may be located on the oxide layer 214 opposite the silicon nitride layer 216. 【0012】 In contrast to the semiconductor device assembly 100 shown in Figure 1, the TSV 208 may have a projection 220 that extends beyond the back side of the substrate 204. For example, the projection 220 may extend beyond the back side of the substrate 204 by a difference of more than 1 micron, more than 2 microns, more than 3 microns, more than 4 microns, or more than 5 microns. The silicon-carbon nitride layer 216 may be positioned on the back side of the substrate 204 so as to extend along the sidewall 222 of the projection 220 of the TSV 208 and to cover a portion of the bonding surface 212. In this way, the silicon-carbon nitride layer 216 may conform to the shape of the projection 220 of the TSV 208. In some embodiments, the silicon-carbon nitride layer 216 may have a thickness of about 0.15 microns (e.g., within 0.01 microns, within 0.05 microns, within 0.1 microns, etc.). As shown in the figure, the silicon-carbon nitride layer 216 may be in direct contact with the substrate 204 (for example, on the reverse side). For example, the silicon-carbon nitride layer 216 and the substrate 204 should not be separated by another material (for example, the silicon nitride layer 116 in Figure 1). 【0013】 The contact pad 210 may be positioned on the back side of the semiconductor die 202, on the coupling surface 212 of the TSV 208. Depending on the embodiment, the contact pad 210 may be smaller than the coupling surface 212 of the TSV 208 such that the contact pad 210 contacts only the portion of the coupling surface 212. For example, the cross-sectional area of ​​the contact pad 210 in a plane coplanar with the coupling surface 212 is smaller than the area of ​​the coupling surface 212. The surface of the contact pad 210 may be positioned on the back side of the semiconductor die 202 so that an additional semiconductor die can be stacked on the semiconductor die 202 and electrically coupled to the semiconductor die 202 by the contact pad 210. 【0014】 Although indicated and described as a semiconductor die, the semiconductor die 202 may be replaced by a wafer (e.g., a semiconductor wafer) on which multiple semiconductor dies are implemented. For example, the substrate 204 may be replaced by a wafer-level or panel-level substrate used to mount multiple semiconductor dies. Furthermore, although described as a TSV, the TSV 208 may generally refer to a through-substrate via. As such, the TSV 208 may be implemented by penetrating a non-silicon substrate, e.g., an organic substrate or another semiconductor substrate. In yet another embodiment, although described with reference to a specific material, other materials may be used to form various layers of the semiconductor die 202. Thus, the oxide layer 214, the silicon-carbon nitride layer 216, or the silicon-carbon nitride layer 218 may instead include any other material, such as different dielectric materials (e.g., silicon oxide, silicon nitride, silicon carbide, silicon-carbon nitride, etc.). 【0015】 This disclosure now moves on to a set of steps for manufacturing a semiconductor device assembly according to embodiments of the present art. Specifically, Figures 3 to 6 show simplified schematic cross-sectional views of a set of steps for manufacturing a semiconductor device assembly according to embodiments of the present art. The steps are shown in relation to a particular embodiment for the sake of simplicity of description. However, these steps may be performed to manufacture a semiconductor device assembly according to other embodiments. 【0016】 Starting from step 300 in Figure 3, a simplified schematic cross-sectional view of a semiconductor device assembly is shown. The semiconductor device assembly includes a semiconductor die 202 assembled on a carrier substrate. The semiconductor die 202 may be bonded to the carrier substrate (e.g., via an adhesive or dielectric material) in a face-down position, with the front side of the semiconductor die 202 facing the carrier substrate. The semiconductor die 202 may be mounted as a substrate 204. A metallization layer 206, including traces, lines, vias, and other connection structures, may be located on the front side of the semiconductor die 202. A TSV 208 extends entirely through the substrate 204 from the metallization layer 206. A projection 220 of the TSV 208 extends beyond the back side of the substrate 204. For example, the protrusion 220 of the TSV208 may extend beyond the back side of the substrate 204 by a difference of more than 1 micron, more than 2 microns, more than 3 microns, more than 4 microns, more than 5 microns, or other differences. 【0017】 Figure 4 shows a simplified schematic cross-sectional view of step 400, in which the passivation material is placed on the back side of the substrate 204 around the protrusions 220 of the TSV 208. The bonding surface 212 of the TSV 208 may be exposed distal to the protrusions 220 of the TSV 208. Depending on the embodiment, the protrusions 220 may not be planarized to be substantially coplane with the back side of the substrate 204 (e.g., less than 0.5 microns, less than 1 micron, less than 2 microns, less than 5 microns, etc.). Thus, the back side of the substrate 204 may have irregularities of less than 200 nanometers, less than 100 nanometers, or less than 50 nanometers. Instead of planarizing to the back side of the substrate 204, the silicon nitride carbon layer 216 may be deposited on the back side of the substrate 204 (e.g., in direct contact with the back side of the substrate 204) and around the protrusions 220 of the TSV 208. For example, the silicon nitride layer 216 may be positioned on the back side of the substrate 204, along the sidewall 222 of the protrusion 220, and covering the bonding surface 212. The silicon nitride layer 216 may include high-temperature silicon nitride deposited at temperatures exceeding 300°C, 400°C, 500°C, or 700°C. The silicon nitride layer 216 may be positioned with a thickness of approximately 0.15 microns (e.g., within 0.01 microns, within 0.05 microns, within 0.1 microns, etc.). 【0018】 The oxide layer 214 (e.g., high-temperature silicon oxide) may be positioned at least partially around the protrusion 220. For example, the oxide layer 214 may be deposited such that it extends more than 1 micron higher than the protrusion 220. The oxide layer 214 may be positioned on the silicon carbon nitride layer 216 such that the silicon carbon nitride layer 216 separates the substrate 204 and the TSV 208 from the oxide layer 214. An additional silicon carbon nitride layer 218 may then be positioned on the oxide layer 214 opposite the silicon carbon nitride layer 216 (e.g., opposite the substrate 204). 【0019】 Figure 5 shows a simplified schematic cross-sectional view of step 500, in which the contact pad 210 is positioned on the bonding surface 212 of the TSV 208 so that it is electrically coupled to the TSV 208. The oxide layer 214 and the silicon carbon nitride layers 216 and 218 can be removed to expose the bonding surface 212 of the TSV 208. For example, the material can be removed by etching. A conductive material can then be placed in the opening to implement the contact pad 210. The contact pad 210 may be smaller than the bonding surface 212 of the TSV 208. In this way, the silicon carbon nitride layer 216 can still cover a portion of the bonding surface 212 of the TSV 208. In some embodiments, CMP is not used to expose the bonding surface 212 of the TSV 208. As a result, the risk of contamination from the TSV 208 or fracture of the semiconductor die 202 can be eliminated. In yet another embodiment, by not planarizing the TSV 208 to the substrate, the steps of depositing passivation material onto the substrate 204 (for example, a layer of low-temperature oxide removed by CMP during the manufacturing of the semiconductor device assembly described with respect to Figure 1) or planarizing the TSV 208 can be eliminated, simplifying the manufacturing process and reducing the overall cost of manufacturing the semiconductor device assembly. Additional semiconductor dies may then be stacked on the semiconductor die 202, and the stacked semiconductor dies may be packaged as a packaged semiconductor device, an example of which is shown in Figure 6. 【0020】 Figure 6 shows a simplified schematic cross-sectional view of a semiconductor device assembly in stage 600. The semiconductor device assembly 600 includes stacked semiconductor dies 602. One or more of the stacked semiconductor dies 602 may include a TSV having contact pads positioned therein. In this case, interconnections (e.g., metal-metal interconnects) that electrically couple the semiconductor dies 602 may be formed between each contact pad on each die of the stacked semiconductor dies 602. The stacked semiconductor dies 602 may be assembled onto a package-level substrate 604 via conductive structures 606 (e.g., conductive pillars, solder joints, etc.). For example, contact pads on the base die of a stacked semiconductor die 602 may be electrically coupled to contact pads (not shown) on the upper surface of the package-level substrate 604 via conductive structures 606. The package-level substrate 604 may include internal circuits (traces, lines, vias, and other connecting structures) that connect the contact pads on the upper surface to contact pads (not shown) on the lower surface. Conductive structures 608 may be positioned on contact pads on the underside to provide external circuits (e.g., power, ground, input / output (I / O) signals, etc.) to the stacked semiconductor die 602. Underfill material 610 (e.g., capillary underfill) may be positioned around the conductive structures 606 to electrically insulate these structures and mechanically support the semiconductor device assembly 600. Encapsulating material 612 (e.g., molding resin) may be positioned at least partially around the stacked semiconductor die 602 and the package-level substrate 604 to protect the semiconductor device assembly 600 and prevent electrical contact with it. 【0021】 In the exemplary embodiments described above, the semiconductor device assembly has been shown and described as including semiconductor dies of a particular configuration, but in other embodiments, the assembly may provide semiconductor dies of various configurations. For example, the semiconductor device assembly shown in any of the embodiments described above may be implemented with modifications where appropriate, using vertical stacking of semiconductor dies (e.g., broadband memory (HBM protocol)), multiple stacks of semiconductor dies, multiple semiconductor dies, or a single semiconductor die. 【0022】 According to one aspect of the present disclosure, the semiconductor device shown in the assemblies of FIGS. 1 to 6 may include memory dies such as dynamic random access memory (DRAM) dies, NOT-AND (NAND) memory dies, NOT-OR (NOR) memory dies, magnetic random access memory (MRAM) dies, phase change memory (PCM) dies, ferroelectric random access memory (FeRAM) dies, static random access memory (SRAM) dies, and others. In embodiments where multiple dies are provided in a single assembly, the semiconductor device may include memory dies of the same type (e.g., both NAND, both DRAM, etc.), different types of memory dies (e.g., one DRAM and one NAND, etc.). According to another aspect of the present disclosure, the semiconductor die of the assembly shown and described above may be a logic die (e.g., a controller die, a processor die, etc.) or a mixture of a logic die and a memory die (e.g., a memory controller die and the memory die controlled thereby). 【0023】 Any of the semiconductor devices and semiconductor device assemblies described above, with reference to FIGS. 1-6, may be incorporated into any of a myriad of larger and / or more complex systems, a representative example of which is system 700 schematically shown in FIG. 7. System 700 may include a semiconductor device assembly 702 (e.g., an individual semiconductor device), a power supply 704, a driver 706, a processor 708, and / or other subsystems or components 710. The semiconductor device assembly 702 may include features generally similar to those of the semiconductor device assemblies described above with reference to FIGS. 1-6. The resulting system 700 may perform any of a wide range of functions, such as memory storage, data processing, and / or other suitable functions. Thus, representative systems 700 may include, without limitation, portable devices (e.g., cellular phones, tablets, e-book readers, and digital audio players), computers, vehicles, household appliances, and other products. The components of system 700 may be housed in a single unit or may be distributed across multiple interconnected units (e.g., via a communication network). The components of system 700 may also include remote devices and any of a wide range of computer-readable media. 【0024】 FIG. 8 shows an exemplary method 800 for manufacturing a semiconductor device assembly according to an embodiment of the present technology. Although shown in a particular configuration, one or more operations of method 800 may be omitted, repeated, or reconfigured. Additionally, method 800 may include other operations not shown in FIG. 8, such as operations detailed in one or more other methods described herein. 【0025】 In 802, a substrate is provided. The substrate may include a front side, a back side opposite the front side, and through vias having projections that extend completely through the substrate and beyond the back side of the substrate. In 804, a layer of silicon carbon nitride is placed on the back side of the substrate and around the projections of the through vias. In 806, an oxide layer is placed on the back side of the substrate and at least partially surrounds the projections of the through vias. In 808, the oxide layer and the silicon carbon nitride layer are etched to expose the bonding surface of the through vias. In 810, a conductive pad is placed on the bonding surface of the through vias and at least partially extends through the oxide layer. 【0026】 Specific details of several embodiments of semiconductor devices and related systems and methods have been described above. The term “substrate” may refer to a wafer-level substrate or a unified die-level substrate, depending on the context in which it is used. Furthermore, unless it is clear from the context that otherwise, the structures described herein may be formed using conventional semiconductor manufacturing techniques. Materials may be deposited using, for example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and / or other suitable techniques. Similarly, materials may be removed using, for example, plasma etching, wet etching, CMP, or other suitable techniques. 【0027】 The technologies disclosed herein relate to semiconductor devices, systems having semiconductor devices, and related methods for manufacturing semiconductor devices. The term “semiconductor device” generally refers to a solid-state device comprising one or more semiconductor materials. Semiconductor devices include, for example, logic devices, memory devices, diodes, and others. Furthermore, the term “semiconductor device” may refer to a finished device, assembly, or other structures at various stages of processing before becoming a finished device. The term “substrate” may, depending on the context in which it is used, refer to a structure that supports an electronic component (e.g., a die), such as a PCB, wafer-level substrate, die-level substrate, or another die for die stacking or three-dimensional integration (3DI) applications. 【0028】 Devices disclosed herein, including memory devices, may be formed on substrates or dies made of silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and others. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-glass (SOG) substrate, a silicon-on-sapphire (SOP) substrate, or a silicon-on-insulator (SOI) substrate such as an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate may be controlled by doping using various chemical species, not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation or by other doping means during the initial formation or growth of the substrate. 【0029】 The functions described herein may be implemented by hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of the claims disclosed and attached. The features that implement the functions may also be physically located in various locations, including being distributed so that the parts of the functions are implemented in separate physical locations. 【0030】 When used in this document, including in the claims, the words “or,” “or,” and “or” in lists of items (e.g., lists modified with phrases such as “at least one of” or “one or more of”) refer to compatible lists, such as the list “at least one of A, B, or C” meaning A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, when used herein, the phrase “based on” should not be interpreted as referring to a closed set of conditions. For example, an exemplary step described as “based on condition A” could be based on both condition A and condition B without departing from the scope of this disclosure. In other words, when used herein, the phrase “based on” should be interpreted similarly to the phrase “based at least partially on.” 【0031】 As used herein, terms such as “vertical,” “horizontal,” “up,” “down,” “higher,” and “lower” may refer to the relative orientation or position of features in a semiconductor device in relation to the orientation shown in the figure. For example, “up” or “top” may refer to a feature that is closer to the top of the page than other features. These terms should, however, be interpreted more broadly to include semiconductor devices with other orientations such as inverted or tilted orientations where up / down, left / right are interchangeable depending on the orientation, covering / below the top / bottom, higher / lower position, up / down, left / right. 【0032】 As stated above, specific embodiments of the invention have been described herein for illustrative purposes, but it will be understood that various modifications can be made without departing from the scope of the invention. Rather, many specific details have been included in the foregoing description in order to provide a complete and implementable description with respect to the embodiments of this disclosure. Those skilled in the art will, however, recognize that the disclosure can be implemented by omitting one or more of these specific details. In other instances, known structures or operations often associated with memory systems and devices are not illustrated or described in detail in order to avoid obscuring other aspects of the art. In general, it will be understood that various other devices, systems, and methods may be included in the scope of the art in addition to the specific embodiments disclosed herein.

Claims

[Claim 1] It is a semiconductor device, A substrate having a front side and a back side opposite to the front side, A through via having a projection that extends completely through the substrate and extends beyond the back side of the substrate, A layer of silicon nitride carbon is arranged on the back side of the substrate and extending along the side wall of the protruding portion of the through via, An oxide layer is disposed on the back side of the substrate and at least partially surrounding the protruding portion of the through via, and A conductive pad is positioned on the bonding surface of the through via and extending at least partially through the oxide layer, The semiconductor device including the above. [Claim 2] A semiconductor device according to claim 1, The silicon nitride carbon layer is in direct contact with the back side of the substrate in the semiconductor device. [Claim 3] A semiconductor device according to claim 1, The semiconductor device wherein the silicon nitride carbon layer extends to cover the portion of the bonding surface of the through via. [Claim 4] A semiconductor device according to claim 1, The semiconductor device further comprises an additional layer of silicon carbon nitride disposed opposite the oxide layer to the silicon carbon nitride layer. [Claim 5] A semiconductor device according to claim 1, The semiconductor device wherein the surface area of ​​the conductive pad on a plane coplanar with the bonding surface of the through via is smaller than the surface area of ​​the bonding surface of the through via. [Claim 6] A semiconductor device according to claim 1, The semiconductor device wherein the back side of the substrate has irregularities of less than 200 nanometers. [Claim 7] A semiconductor device according to claim 1, The semiconductor device wherein the oxide layer comprises tetraethyl orthosilicate, a spin-on dielectric, or spin-on glass. [Claim 8] A method for manufacturing semiconductor devices, To provide a substrate including a front side, a back side opposite to the front side, and through vias having protrusions that extend completely through the substrate and beyond the back side of the substrate, A layer of silicon nitride carbon is placed on the back side of the substrate and around the protruding portion of the through via. An oxide layer is placed on the back side of the substrate and at least partially surrounding the protruding portion of the through via. To expose the bonding surface of the through via, the oxide layer and the silicon nitride carbon layer are etched, and A conductive pad is placed on the bonding surface of the through via and extends at least partially through the oxide layer. The method, including the method described above. [Claim 9] The method according to claim 8, The method further comprises arranging the silicon nitride carbon layer in direct contact with the back side of the substrate. [Claim 10] The method according to claim 8, The method further comprises arranging the silicon nitride carbon layer at a temperature exceeding 700°C. [Claim 11] The method according to claim 8, The method further comprises etching the oxide layer and the silicon nitride layer to expose the bonding surface of the through via such that the portion of the silicon nitride layer extends to cover the portion of the bonding surface where the conductive pad is not placed. [Claim 12] The method according to claim 8, The method further comprises arranging an additional layer of silicon carbon nitride on the oxide layer opposite to the silicon carbon nitride layer. [Claim 13] The method according to claim 8, further comprising arranging the oxide layer by fluidized bed chemical vapor deposition, fluidized bed chemical vapor deposition, or spin coating. [Claim 14] It is a semiconductor device, A substrate having a front side and a back side opposite to the front side, A through via having a projection that extends completely through the substrate and extends beyond the back side of the substrate, A silicon nitride carbon layer that is in direct contact with the back side of the substrate, An oxide layer is disposed on the back side of the substrate and so as to cover the protruding portion of the through via, and A conductive pad is positioned on the bonding surface of the through via and extending at least partially through the oxide layer, The semiconductor device including the above. [Claim 15] A semiconductor device according to claim 14, The silicon nitride carbon layer extends along the side wall of the protrusion of the through via in the semiconductor device. [Claim 16] A semiconductor device according to claim 14, The semiconductor device wherein the silicon nitride carbon layer extends to cover the portion of the bonding surface of the through via. [Claim 17] A semiconductor device according to claim 14, The semiconductor device further comprises an additional layer of silicon carbon nitride disposed opposite the oxide layer to the silicon carbon nitride layer. [Claim 18] A semiconductor device according to claim 14, The semiconductor device wherein the cross-sectional area of ​​the conductive pad on a plane coplanar with the bonding surface of the through via is smaller than the area of ​​the bonding surface of the through via. [Claim 19] A semiconductor device according to claim 14, A semiconductor die including the substrate and the contact pad, and Further including an additional semiconductor die with additional contact pads, The semiconductor device wherein the semiconductor die and the additional semiconductor die are coupled by the contact pad and the additional contact pad in order to stack the semiconductor dies according to the high-bandwidth memory protocol. [Claim 20] A semiconductor device according to claim 14, Logic die and, A semiconductor die comprising the substrate and the contact pad, and coupled to the logic die at a first lateral location, An additional semiconductor die including additional contact pads, The semiconductor die and the additional semiconductor die are coupled by the contact pad and the additional contact pad in order to perform the first stacking of the semiconductor dies, and A second stack of semiconductor dies coupled with the logic die at a second lateral location, The semiconductor device further includes the following.

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