GaN transistors with front barriers of multiple thicknesses

Abstract

A gallium nitride (GaN) transistor comprising multiple layers / multiple thickness barrier layers formed by segments (40, 42, 44, 46) whose thickness gradually increases between the gate (22) and drain (20) to gradually increase the 2DEG density in the channel from gate to drain. To produce an amplified mode device with a positive threshold voltage, the GaN gate (26) can be formed on top of the base barrier layer (16). By forming the gate on thicker segments of the barrier layer, GaN transistors with a lower positive threshold voltage or depletion mode transistors with a negative threshold voltage can be produced.

Description

[Technical Field]

[0001] Field of Invention This invention relates to a group III nitride transistor, such as a gallium nitride (GaN) transistor. More specifically, this invention relates to a GaN transistor having a front barrier of multiple thicknesses. [Background technology]

[0002] Background of the Invention GaN semiconductor devices are increasingly desirable for power semiconductor devices due to their ability to carry large currents and support high voltages. The development of these devices is generally aimed at high-power / high-frequency applications. Devices manufactured for these types of applications are based on common device structures that exhibit high electron mobility and are called heterojunction field-effect transistors (HFETs), high electron mobility transistors (HEMTs), or modulation-doped field-effect transistors (MODFETs).

[0003] GaN HEMT devices contain a nitride semiconductor with a nitride layer. Different materials formed on the semiconductor or buffer layer give the layer different band gaps. Different crystallinity in adjacent nitride layers also induces polarity that contributes to a conductive two-dimensional electron gas (2DEG) region near the junction of the two layers, especially in layers with narrower band gaps. The nitride layers that induce polarity typically include a barrier layer and a buffer layer that forms the 2DEG, allowing current to flow through the device. Since the 2DEG region exists below the gate when the gate bias is 0, conventional nitride devices are usually on, or depletion-mode devices. If the 2DEG region is depleted below the gate when the applied gate bias is 0, the device is usually off, and is an amplified-mode device.

[0004] Figure 1 shows a cross-section of a prior art amplified mode GaN transistor device, which is more fully described in U.S. Patents 8,350,294 and 8,404,508. The GaN transistor 1 is formed on a substrate 10 which may include, for example, silicon (Si), silicon carbide (SiC), or sapphire. A transition layer 12 is in contact with the substrate 10. The transition layer 12 comprises AlN or AlGaN having a thickness between 0.1 and 1.0 μm. A buffer layer 14 separates the transition layer 12 from the front barrier 16. The buffer layer 14 is preferably formed of GaN and has a thickness between 0.5 and 3 μm. The front barrier 16 is formed of AlGaN and has a thickness between 0.005 and 0.03 μm and an Al content of about 10 to 50%. The front barrier 16 has the same thickness throughout the device.

[0005] Differences in crystallinity between the buffer layer 14 and the barrier layer 16 cause polarity that forms a two-dimensional electron gas (2DEG) near the junction of the buffer layer 14 and the barrier layer 16, particularly in channels within the buffer layer that have a narrower band gap.

[0006] Source and drain contacts 18, 20 are positioned on top of the barrier layer 16. The source and drain contacts are formed of Ti or Al with a cap metal such as Ni and Au or Ti and TiN. A gate contact 24, formed of Ta, Ti, TiN, W, or WSi2 and having a thickness between 0.05 and 1.0 μm, is provided between the source and drain contacts. The gate material 26 is formed on top of the barrier layer 16 and below the gate contact 24. In a preferred embodiment of the present invention, the gate material 26 is a compensating gate material, i.e., GaN with passivated p-type impurities such as Mg, Zn, Be, Cd, or Ca. The p-type doping of the compensating gate material 26 results in an amplified mode device. In addition, the insulating properties of the compensating gate material 26 lead to low gate leakage and reduced gate capacitance during device operation.

[0007] The passivation / insulating layer 27 is provided above the barrier layer 16 between the source and drain contacts 18 and 20 and extends to the p-type gate material 26 and gate contact 24. In most silicon devices, the insulator / barrier interface is not a critical parameter. In GaN transistors, however, it is a critical parameter that governs the performance of the device. A single layer of surface passivation insulator, such as the passivation layer 27 in Figure 1, can be designed to minimize leakage current and gate-to-drain capacitance, or it can be designed to give a high electron density in the channel and a low drain field. However, a single insulating passivation layer cannot do both at the same time.

[0008] To address this problem, a GaN transistor 2 may be provided with different surface passivation insulators 30, 32, 34, and 36 placed on top of the barrier layer 16 between the gate 22 and the drain contact 20, as shown in Figure 2 and as described in U.S. Patent No. 10,096,702. The different surface passivation insulators 30, 32, 34, and 36 induce multiple segments of 2DEG 28 with different densities within the channel. As shown, the transistor 2 has four insulators 30, 32, 34, and 36 with different densities between the gate 22 and the drain contact 20, thereby increasing the 2DEG density 28 in the channel further away from the gate 22. Insulator 30 minimizes gate leakage and the field near the gate, resulting in a high gate-drain charge (Qgd). Insulator 36 minimizes the electric field at the drain contact, providing a high charge density in the channel due to its low resistance. Insulators 32 and 34 provide transitions in the intermediate region between the gate and the drain. Insulators 30, 32, 34, and 36 can be formed from the same material such as SiN, but different process conditions and doping will cause insulator 30 to produce a lower donor state interface density than insulator 32, and insulator 34 to provide a lower donor state interface density than insulator 36. [Overview of the project] [Problems that the invention aims to solve]

[0009] An integrated circuit comprising both amplification-mode and depletion-mode transistors with threshold voltages having nearly equal absolute values ​​is disclosed in U.S. Patent No. 9,583,480. It would be desirable to obtain the advantages of that integrated circuit, while also obtaining the advantages of the stepped 2DEG density described in U.S. Patent No. 10,096,702, from the perspective of tuning the threshold voltage of the GaN transistors and providing two types of GaN transistors (amplified mode and depletion mode) in a single integrated circuit. [Means for solving the problem]

[0010] Summary of the Invention In the various embodiments described below, the present invention achieves the advantages discussed above by providing a group III nitride transistor, preferably a GaN transistor comprising multiple layers / multiple thickness barrier layers formed in segments of gradually increasing thickness between the gate and drain to gradually increase the 2DEG density from gate to drain within the channel. To produce an amplified mode device with a positive threshold voltage, the GaN gate can be formed on the base barrier layer. By forming the gate on a thicker segment of the barrier layer, a GaN transistor with a lower positive threshold voltage or a depletion mode transistor with a negative threshold voltage can be produced.

[0011] More specifically, in the transistor of the present invention, the front barrier formed of a group III nitride material is provided in a topology of multiple laterally varying thicknesses to induce a laterally varying 2DEG density downward. In some embodiments, the multiple thicknesses of the barrier layer are obtained by an alternating multilayer barrier structure of AlGaN and GaN layers etched at different laterally distances from the source. In other embodiments, the variation in barrier layer thickness is obtained by forming a uniform AlGaN barrier layer of multiple thicknesses at different laterally distances from the source. The variation in barrier layer thickness is advantageous in that the gate threshold voltage (V THprovides additional advantages that can be customized. Integrated circuits on a single substrate can be provided with transistors having different threshold voltages, including depletion mode transistors having a negative threshold voltage, and the different gate threshold voltages are produced by forming the gates on barrier layers of different thicknesses.

[0012] Additional embodiments and additional features of the embodiments for the GaN transistor and the method of manufacturing the GaN transistor of the present invention are described below and are hereby incorporated into this section.

[0013] Brief Description of the Drawings This application is further understood when read in conjunction with the accompanying drawings. For the purpose of illustrating the subject matter, exemplary embodiments of the subject matter are shown in the drawings, however, the presently disclosed subject matter is not limited to the specific methods, devices, and systems disclosed.

Brief Description of the Drawings

[0014] [Figure 1] FIG. 1 shows a cross-sectional view of a prior art enhancement mode GaN transistor. [Figure 2] FIG. 2 shows a cross-sectional view of a prior art enhancement mode GaN transistor of U.S. Patent No. 10,096,702 having four different insulators on a barrier layer. [Figure 3] FIG. 3 shows a cross-sectional view of an enhancement mode GaN transistor according to a first embodiment of the present invention. [Figure 4] FIG. 4 shows a cross-sectional view of an enhancement mode GaN transistor according to a second embodiment of the present invention. [Figure 5] FIG. 5 shows a cross-sectional view of an enhancement mode GaN transistor according to a third embodiment of the present invention. [Figure 6] FIG. 6 shows steps for a method of manufacturing the enhancement mode GaN transistors of FIGS. 3-5. [Figure 7] FIG. 7 shows steps for a method of manufacturing the enhancement mode GaN transistors of FIGS. 3-5. [Figure 8]FIG. 8 shows steps for a method of manufacturing the amplification mode GaN transistor of FIGS. 3-5. [Figure 9] FIG. 9 shows steps for a method of manufacturing the amplification mode GaN transistor of FIGS. 3-5. [Figure 10] FIG. 10 shows steps for a method of manufacturing the amplification mode GaN transistor of FIGS. 3-5. [Figure 11] FIG. 11 shows steps for a method of manufacturing the amplification mode GaN transistor of FIGS. 3-5. [Figure 12] FIG. 12 shows steps for a method of manufacturing the amplification mode GaN transistor of FIGS. 3-5. [Figure 13] FIG. 13 shows a cross-sectional view of a transistor according to a fourth embodiment of the present invention. [Figure 14] FIG. 14 shows steps for a method of manufacturing the GaN transistor of FIG. 13. [Figure 15] FIG. 15 shows steps for a method of manufacturing the GaN transistor of FIG. 13. [Figure 16] FIG. 16 shows steps for a method of manufacturing the GaN transistor of FIG. 13. [Figure 17] FIG. 17 shows a GaN transistor having a breakdown voltage higher than that of the transistor of FIG. 13. **Embodiments for Carrying Out the Invention**

[0015] Aspects of the present disclosure will now be described in detail with reference to the drawings, where like reference numerals refer to like elements throughout, unless otherwise specified.

[0016] **Detailed Description of Preferred Embodiments** In the following detailed description, reference is made to specific embodiments. This detailed description is intended only to teach further details to those skilled in the art for implementing the preferred aspects of the present teachings and is not intended to limit the scope of the claims. Therefore, the combination of features disclosed in the following detailed description may not be necessary to implement this instruction in its broadest sense, but rather is provided only to illustrate a particularly representative example of this instruction. It is understood that other embodiments may be employed and various structural, logical, and electrical modifications may be made.

[0017] This invention provides an amplified mode GaN transistor having a front barrier of varying thickness. The front barrier of varying thickness can be a multilayer front barrier formed of multiple AlGaN / GaN layers, where each AlGaN layer has a lower concentration of GaN than the GaN layer directly beneath it, or a single layer of the AlGaN of varying thickness. The front barrier is etched to different thicknesses with varying distances from the source to generate the varying thickness. Due to the varying thickness of the front barrier, the 2DEG at the junction of the front barrier and the buffer below has a corresponding varying electron density. In particular, the front barrier is designed to have a varying thickness such that the 2DEG has a lower electron density near the gate to reduce gate leakage and gate damage, and a higher electron density near the drain to reduce the on-resistance of the transistor. The threshold voltage (V) of the device TH The threshold voltage can be customized based on the thickness of the front barrier on which the gate is formed. In particular, the threshold voltage decreases when the gate is formed on a thicker segment of the front barrier.

[0018] Figure 3 shows a first embodiment of an amplification-mode GaN transistor 100 according to the present invention. The GaN transistor 100 has a buffer layer 14 made of GaN. Although not shown in Figure 3, the buffer layer 14 is formed on a transition layer 12 stacked on a substrate 10 as shown in Figure 1. A first barrier layer 16 made of AlGaN is deposited on the buffer layer 14, similar to Figure 1. The first barrier layer 16 has a substantially uniform thickness. As described above, a conductive two-dimensional electron gas (2DEG) forms a channel near the junction of the buffer layer 14 and the first barrier layer 16, particularly on top of the buffer layer 14. Thus, the buffer layer 14 is called a GaN channel layer.

[0019] As shown in Figure 3, according to the present invention, one or more pairs of GaN / AlGaN layers are laminated on the AlGaN first barrier layer 16. The pairs of GaN / AlGaN layers shown in Figure 3 are preferred, but the GaN / AlGaN paired layers are Al X In Y Ga Z The composition can be N, x+y+z=1 (containing 0% In and / or 0% Al). Embodiments of the present invention shown in Figure 3 have three additional GaN / AlGaN layer pairs, namely, a second GaN layer 14' / second AlGaN layer 16', a third GaN layer 14'' / third AlGaN layer 16'', and a fourth GaN layer 14''' / fourth AlGaN layer 16'''. More or fewer pairs of buffer / barrier layers may be provided to appropriately change the density of 2DEG in the channel beneath the barrier layer 16. Each AlGaN layer 16-16'' of the laminate has a lower GaN concentration than the GaN layer 14-14''' directly beneath it. The layers of the laminate have a thickness of approximately 1 nm to 20 nm.

[0020] As shown in Figure 3-5, in a preferred embodiment of the present invention, layers 14'-14''' and 16'-16''' are aligned or substantially aligned in pairs to the side closest to the source, so that layers 14' and 16' are aligned to the source side, and layers 14'', 16'' and 14''', 16''' are similarly aligned to the source side. The aligned layers 14', 16' extend a first distance from the source, the aligned layers 14'', 16'' extend a second distance greater than the first distance from the source, and the aligned layers 14'', 16''' extend a third distance greater than the second distance from the source, resulting in a stepped topology. Layers 14-14''' and 16-16''' are all aligned with each other and in contact with the drain contact 20; therefore, as shown in Figure 3-5, the number of stepped segments 40, 42, 44, and 46 with increasing height is defined by buffer layer 14, barrier layer 16, and layers 14'-14''' and 16'-16'''. More or fewer stepped segments may be formed depending on the intended application, as will be described more fully below. It should be understood that vertical surfaces may not be perfectly vertical, but may have rounded and / or tapered portions in the layers being manufactured. Additional patterns to provide varying thicknesses are being considered, including inclined patterns spanning one or more Group III nitride layers.

[0021] As a result of the 2DEGs generated at the GaN / AlGaN interface and by each pair of layers, each segment 40, 42, 44, and 46 produces a gradually increasing number of free electrons. The free electrons generated in each of the 2DEGs of segments 42, 44, and 46 diffuse downward into the 2DEG channel at the top of the GaN channel layer 14, thereby giving the 2DEG channel a higher free electron density near the drain and a lower electron density near the gate. The height of the segments (i.e., the vertical distance that free electrons must travel to reach the 2DEG channel) is also a factor. Therefore, the thickness of the layer pairs 14' / 16', 14'' / 16'', and 14''' / 16''' can also be changed to alter the electron density within the 2DEG channel.

[0022] As shown in Figure 3-5, the gate may be located on any of segments 40, 42, 44, or 46 (i.e., on any level above the first barrier 16), as will be explained more fully below, V TH The device mode (amplification mode / depletion mode) also depends on the gate height (i.e., the vertical distance between the gate and the 2DEG channel).

[0023] In the transistor 100 shown in Figure 3, the gate 22 is located on the first level of the first segment 40, directly on the first barrier layer 16. The segment 40 produces the lowest electron density in channel 2DEG, so that the p-doped material 26 of the gate depletes the free electrons in the lower 2DEG channel at zero voltage. A positive voltage must be applied to the gate 100 to replenish the electrons in the lower 2DEG and produce electron conduction paths between the source contact 18 and the drain contact 20. Therefore, the device operates in amplified mode (normally off). Because the 2DEG channel has the lowest electron density, the device's V TH The positive voltage required to replenish the electrons in 2DEG to turn the device ON is highest in this embodiment.

[0024] In the transistor 100’ shown in FIG. 4, the gate 22 is formed on the second barrier layer 16’ (i.e., at the same level as the second segment 42 in FIG. 3). Since the interface between the second buffer layer 14’ and the second barrier 16’ produces free electrons, resulting in a higher density of electrons in the 2DEG channel under the gate than in the device in FIG. 3, the V TH is lower and positive in this embodiment.

[0025] In the transistor 100’’ shown in FIG. 5, the gate is placed directly on the second barrier 16’ at the second level (similar to the device in FIG. 4). However, in the transistor 100’’, at least one of the lower buffer layers 14’, 14’’, 14’’’ and / or barrier layers 16’, 16’’, 16’’’ is doped with an n-type dopant such as silicon or germanium to produce an increased number of free electrons at a concentration of 1x10 16 cm -3 to 1x10 20 cm -3 . The increased number of free electrons increases the density of the 2DEG under the gate 22’’ and decreases the threshold voltage of the transistor. If the density of electrons in the 2DEG is greater than can be depleted by the p-doped GaN layer 26’’ at zero voltage, the device 100’’ operates in depletion mode and a negative voltage must be applied to the p-doped GaN layer 26’’ to deplete the 2DEG under the gate 22 and block the current path between the drain and the source.

[0026] An integrated circuit can be formed by individual transistors having different threshold voltages using the gate arrangements and / or dopings discussed above. Therefore, the integrated circuit includes one or more transistors having a first V TH (gate formed directly on the first barrier 16 of the first segment 40 as in FIG. 3), one or more transistors having a second V TH (gate formed on the second barrier 16’ of the second segment 42 as in FIG. 4), and / or a third V THIt may have one or more transistors having (a gate directly formed on the third barrier 16'' of the third segment 44), and the first V TH is the 2nd V TH Higher, 2V TH is the 3rd V TH Higher. Alternatively, or in addition, as in the embodiments of Figure 3 (amplification mode) and Figure 5 (depletion mode) described above, the integrated circuit may be formed by both amplification mode and depletion mode transistors.

[0027] Figure 6-12 shows a method for producing a transistor according to the present invention. As shown in Figure 1, the manufacturing process begins with growing or depositing a transition layer 12 on a substrate 10. As shown in Figure 6, a plurality of GaN layers 14-14'' and AlGaN layers 16-16''' are then deposited or grown on the transition layer 12.

[0028] As shown in Figures 7 and 8, the varied thickness of the barrier layer is produced by etching layers 14'-14''' and 16'-16''' using photolithography techniques. The thickness of the third segment 44 can be produced by etching the AlGaN layer 16''' and the GaN layer 14''', exposing a segment of the AlGaN layer 16'' at a first distance from the source. The thickness of the second segment 42 can be produced by etching the AlGaN layer 16'' and the GaN layer 14'', starting at a second distance from the source, and exposing a segment of the AlGaN layer 16'. The thickness of the first segment 40 can be produced by etching the AlGaN layer 16' and the GaN layer 14', starting at a third distance from the source, and exposing a segment of the AlGaN layer 16. Thus, the resulting structure is a stepped pattern of GaN and AlGaN layers as discussed herein.

[0029] As shown in Figure 9, a precursor layer 38 of the p-type GaN material 26 can be grown on the exposed segments of the barrier layers 16, 16', 16'', and 16'''. The precursor layer 38 can be patterned and etched on any level of the transistor to form a p-type GaN material layer 26 for the gate 22. For example, as shown in Figure 10, the gate 22 can be formed by patterning and etching the precursor layer 38 on the AlGaN 16 of the first segment 40 to produce the device of Figure 3. Alternatively, as shown in Figure 11, the gate 22' can be formed by patterning and etching the precursor layer 38 on the AlGaN layer 16' of the second segment 42 to produce the device of Figure 4. Alternatively, as shown in Figure 12, the gate can be formed by patterning and etching the precursor layer 38 on the AlGaN 16'' of the third segment 44. The gate contact 24 is patterned and etched on the p-type GaN material layer 26 to form the gate 22. The gate contacts 24 may be patterned and etched using a self-aligned technique for the p-type GaN material 26, as disclosed in U.S. Patents 8,404,508 and 9,748,347. The source contacts 18 and drain contacts 20 may then be patterned and etched.

[0030] Figure 13 shows a fourth embodiment of the transistor 200 of the present invention. In this embodiment, the stepped profile of the barrier layer, as described above with respect to the first, second, and third embodiments, is formed by a single AlGaN layer 16 with varying thickness rather than stacked GaN / AlGaN layers with varying height. In the fourth embodiment of the present invention shown in Figure 13, the gate 22 is formed on the first segment 40, but alternatively, as in the first, second, and third embodiments, the device V THTo adjust this, gates can be formed on any of segments 40, 42, 44, or 46. Similarly, as in the embodiments described above, the AlGaN layer 16 can be doped with an n-type material (e.g., silicon or germanium) to increase the 2DEG density or to adjust the threshold voltage of the transistor.

[0031] A method for forming a fourth embodiment of the present invention is shown in Figures 14-16. As in the first three embodiments, the manufacturing process begins with growing or depositing a transition layer 12 on a substrate 10 as shown in Figure 1. A GaN buffer layer 14 is deposited on the transition layer 12, and an AlGaN barrier layer 16 is deposited on the buffer layer 14. The barrier layer 16, which is deposited first, is relatively thick (approximately 20-30 nm) compared to the typical barrier layer thickness (10-15 nm) of the first three embodiments. The barrier layer 16 preferably contains approximately 25% Al, as is typical. The thickness and percentage of Al of the barrier layer 16 can be varied and are trade-offs with each other, i.e., a thicker barrier layer with a lower percentage of Al is functionally similar to a thinner barrier layer with a higher percentage of Al.

[0032] As shown in Figure 16, the barrier layer 16 is etched to form segments 40-46 of multiple heights. Although the barrier layer 16 is relatively thicker than a typical barrier layer, it is still a very thin layer, so atomic layer etching (ALE) with extremely fine depth control is preferably employed to form the structure. As shown in Figure 16, the p-GaN material 26 of the gate can be placed on the first segment 40, but as mentioned above, the V of the device TH To change it, it can be grown on top of any of the other segments 42, 44, and 46, patterned, and etched.

[0033] Accordingly, the transistor of the present invention includes multiple layers / multiple thickness barrier layers formed in segments whose thickness gradually increases between the gate and drain in order to gradually increase the 2DEG density from gate to drain in the channel, as in the embodiments described above. The GaN gate can be formed on the base barrier layer to produce an amplified mode device having a positive threshold voltage. By forming the gate on a thicker segment of the barrier layer, a GaN transistor with a lower positive threshold voltage or a depletion mode transistor with a negative threshold voltage can be produced. The variation in the thickness of the barrier layer provides the additional advantage that the threshold voltage of the device can be customized.

[0034] Advantageously, according to the present invention, an integrated circuit on a single substrate may be provided with transistors having different threshold voltages, or even a depletion-mode transistor having a negative threshold voltage.

[0035] While the system and method have been described in relation to various embodiments of various figures, it will be understood by those skilled in the art that modifications to the embodiments can be made without deviating from the broader concept of the invention. Therefore, it should be understood that this disclosure is not limited to the specific embodiments disclosed and is intended to cover modifications within the spirit and scope of this disclosure as defined by the claims.

Claims

1. A group III nitride transistor: circuit board and; A buffer layer disposed on the substrate, wherein the buffer layer comprises a group III nitride material; A barrier layer disposed directly above the buffer layer, wherein the barrier layer comprises a group III nitride material; A channel containing a conductive two-dimensional electron gas (2DEG) formed in the buffer layer near the junction of the buffer layer and the barrier layer; One or more Group III nitride material layers on the barrier layer, wherein a first segment and a second segment are defined by the barrier layer and / or the one or more Group III nitride material layers on the barrier layer, the first segment has a first thickness, the second segment has a second thickness, the first thickness is smaller than the second thickness, the number of free electrons in the first segment is lower than the number of free electrons in the second segment, and the 2DEG in the channel below the first segment has a lower electron density than the 2DEG in the channel below the second segment; A gate, a source, and a drain are respectively arranged on the buffer layer, wherein the gate is positioned on the barrier layer between the source and the drain; Group III nitride transistors, including those included.

2. The transistor according to claim 1, wherein the first segment is closer to the source than the second segment.

3. The one or more Group III nitride material layers on the barrier layer are Al Ｘ In Ｙ Ga Ｚ The transistor according to claim 1, wherein N includes x + y + z = 1.

4. The transistor according to claim 1, wherein the one or more Group III nitride material layers on the barrier layer include a pair of layers of GaN and AlGaN.

5. The transistor according to claim 2, wherein the transistor has a first threshold voltage due to the gate located on the first segment, and the transistor has a second threshold voltage lower than the first threshold voltage due to the gate located on the second segment.

6. The transistor according to claim 5, wherein the paired layers of GaN and AlGaN are doped with an n-type dopant in order to increase the electron density in the 2DEG and decrease the threshold voltage of the transistor.

7. The transistor according to claim 6, wherein the threshold voltage is negative and the transistor is a depletion-mode transistor.

8. An integrated circuit comprising a plurality of transistors according to claim 1.

9. The integrated circuit according to claim 8, wherein at least one of the transistors has a first threshold voltage, and at least one of the transistors has a second threshold voltage lower than the first threshold voltage.

10. A group III nitride transistor, circuit board and; A buffer layer disposed on the substrate, wherein the buffer layer comprises a group III nitride material; A barrier layer disposed on the buffer layer, wherein the buffer layer contains a group III nitride; A channel comprising a conductive two-dimensional electron gas (2DEG) formed in the buffer layer near the junction of the buffer layer and the barrier layer; The barrier layer comprises a first segment having a first thickness and a second segment having a second thickness, wherein the first thickness is smaller than the second thickness, the number of free electrons in the first segment is lower than the number of free electrons in the second segment, and the 2DEG density in the channel below the first segment is lower than the 2DEG density in the channel below the second segment; A gate, a source, and a drain are respectively arranged on the buffer layer, the gate contact being located between the source and the drain and on the barrier layer; Group III nitride transistors, including those included.

11. The transistor according to claim 10, wherein the first segment is closer to the source than the second segment.

12. The transistor according to claim 10, wherein the barrier layer comprises AlGaN.

13. The transistor according to claim 10, wherein the transistor has a first threshold voltage due to the gate located on the first segment, and the transistor has a second threshold voltage lower than the first threshold voltage due to the gate located on the second segment.

14. The transistor according to claim 12, wherein the barrier layer is doped with an n-type dopant in order to increase the electron density in the 2DEG and decrease the threshold voltage of the transistor.

15. An integrated circuit comprising a transistor according to one of the claims 10.

16. The integrated circuit according to claim 15, wherein at least one of the transistors has a first threshold voltage, and at least one of the transistors has a second threshold voltage lower than the first threshold voltage.

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