Interconnection chips and L-couplers for modular quantum links

Abstract

Interconnection chips and L-couplers for modular quantum links. Systems and techniques for facilitating the coupling of superconducting cables to interconnection chips and quantum processors. In various embodiments, the system may include a quantum processor, one or more interconnection chips, and one or more cable connectors. The quantum processor may have multiple qubits. Additionally, one or more interconnection chips may be coupled to the quantum processor, and one or more cable connectors may be coupled to one or more interconnection chips. According to embodiments, one or more interconnection chips may have one or more signal routings from one or more cable connectors to the quantum processor. In further embodiments, a first signal may pass from one or more cable connectors to at least one of the multiple qubits.

Claims

1. A quantum processor with multiple qubits; One or more interconnection chips joined to the quantum processor; and One or more cable connection parts coupled to one or more interconnection chips Equipped with, The system wherein one or more interconnection chips have one or more signal routings from the one or more cable connections to the quantum processor, and a first signal can pass from the one or more cable connections to at least one of the plurality of qubits.

2. The system according to claim 1, wherein the quantum processor is bonded to one or more interconnection chips.

3. The system according to claim 1 or 2, wherein the quantum processor is bonded to a substrate, and a second signal passes from the substrate to the quantum processor.

4. The system according to claim 3, wherein one or more interconnection chips are bonded to the substrate with an adhesive.

5. The system according to claim 4, wherein the substrate further has a machined portion having a surface below the upper surface of the substrate, and the one or more interconnection chips are bonded to the machined portion.

6. The system according to claim 5, wherein the upper surface of one or more interconnection chips is substantially coplanar with the upper surface of the substrate.

7. The system according to claim 6, wherein one or more cable connection points have soldering elements.

8. The system according to claim 7, wherein the soldering element is directly soldered to the one or more interconnection chips.

9. The system according to any one of the preceding claims, wherein the one or more cable connections have reusable connections.

10. The system according to claim 9, wherein the reusable connector comprises an outer layer containing a machinable and solderable metal and an inner layer containing a solderable metal, and the reusable connector is configured to receive at least the central conductor of a coaxial cable.

11. The system according to claim 10, wherein the solder material inside the reusable connector electrically connects the received coaxial cable to the one or more signal routings.

12. The system according to claim 11, wherein the one or more cable connection points are configured to receive low-loss cables.

13. The system according to any prior claim, further comprising one or more through-substrate vias connected to a ground plane from one or more interconnection chips.

14. The system according to any one of the preceding claims, wherein the one or more cable connectors are configured to receive a superconducting cable.

15. The quantum processor is the system according to any prior claim, comprising an interposer bonded to a quantum chip.

16. The system according to any prior claim, comprising a coupling device having an outer casing containing machinable metal and solderable metal, wherein the coupling device is configured to receive a first cable at a first end of the coupling device.

17. The stage where interconnect chips are attached to the circuit board using adhesive; The step of joining a quantum processor to the interconnection chip; and The step of connecting a superconducting cable to the aforementioned interconnection chip. A method for providing this.

18. The aforementioned quantum processor has multiple qubits; The method according to claim 17, wherein the one or more interconnection chips have one or more signal routings from the one or more cable connections to the quantum processor, and a first signal can pass from the one or more cable connections to at least one of the plurality of qubits.

19. The step of directly attaching the superconducting cable to the surface of the interconnection chip. The method according to claim 17 or claim 18, further comprising:

20. The step of attaching the connector of the superconducting cable to the surface of the interconnection chip. The method according to any one of claims 17 to 19, further comprising:

21. Step of joining the quantum processor to the interconnect chip. The method according to any one of claims 17 to 20, further comprising the above.

22. Before attaching the interconnection chip, a portion of the substrate is machined. The method according to any one of claims 17 to 21, further comprising:

23. The method according to claim 22, wherein, after the interconnection chip is attached, the upper surface of the interconnection chip is substantially planar with respect to the upper surface of the substrate, and the step of bonding the quantum processor to the interconnection chip further comprises the step of bonding the quantum processor to the substrate.

24. A coupling device, A coupling device comprising an outer casing having machinable metal and solderable metal, wherein the coupling device is configured to receive a first cable at a first end of the coupling device.

25. The coupling device according to claim 24, wherein the second end of the coupling device can be soldered to a substrate.

26. The coupling device according to claim 24 or 25, wherein the second end of the coupling device is capable of receiving a second cable.

27. The coupling device according to any one of claims 24 to 26, further comprising an inner cylinder having the machinable metal and the solderable metal, wherein the outer cylinder is configured to be connected to the shield of the first cable, and the inner cylinder is configured to be connected to the central core of the first cable.

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