Interconnection levels of multiple line types
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- INTERNATIONAL BUSINESS MACHINE CORPORATION
- Filing Date
- 2024-05-16
- Publication Date
- 2026-06-23
Smart Images
Figure 2026520424000001_ABST
Abstract
Claims
1. A plurality of first-type lines in a first metal level, each having a first line width and a first height, wherein each of the plurality of first-type lines has an uppermost surface wider than the bottom surface; and A second type of line in the first metal level having a second line width narrower than the first line width, wherein the second type of line lies between two adjacent first type lines, and the second type of line has an uppermost surface wider than the bottom surface. A semiconductor structure that includes this.
2. A plurality of first vias, each of which connects a line of either the plurality of first type lines or the second type lines to a second back metal level, where the first metal level is the first back metal level. The semiconductor structure according to claim 1, further comprising:
3. The semiconductor structure according to claim 2, wherein each of the plurality of first type lines and the second type line is connected to any of the plurality of through-silicon vias by any of the plurality of second vias.
4. The third backside metal level includes a plurality of second backside first type lines and second backside second type lines, wherein the second backside second type lines are located between two adjacent lines among the plurality of second backside first type lines; and Multiple third vias connect the multiple second backside first type lines and the second backside second type lines to the second backside metal level. The semiconductor structure according to claim 2, further comprising:
5. The semiconductor structure according to claim 2, wherein the second type of line has an uppermost surface located above the uppermost surface of the plurality of first type lines, and the second type of line has the same height as the first height of the plurality of first type lines.
6. The semiconductor structure according to claim 2, wherein the second type of line has an uppermost surface that is at the same height as the bottom surfaces of the plurality of first type lines, and the second type of line is made of a different metallic material from the plurality of first type lines.
7. The semiconductor structure according to claim 2, wherein the second type of line has an uppermost surface that is the same height as the bottom surface of the plurality of first type lines, and the second type of line has a height less than the first height.
8. The semiconductor structure according to claim 2, wherein the second type of line has an upper surface located below the uppermost surface of the plurality of first type lines and above the bottom surface of the plurality of first type lines.
9. The semiconductor structure according to claim 2, wherein the first back metal level includes a plurality of second type lines, each of which has a different height.
10. The semiconductor structure according to claim 2, wherein each of the plurality of first type lines and the second type line is connected by vias of any of the plurality of second vias to a metal level closer to the back side of the semiconductor substrate than the first back side metal layer.
11. A plurality of first type lines having a first line width in a first backside metal level, wherein each of the plurality of first type lines has an uppermost surface wider than the line bottom surface; and A second type of line in the first backside metal level having a second line width smaller than the first line width, wherein the second type of line is located between two adjacent first type lines. A semiconductor structure that includes this.
12. A plurality of first vias connecting each of the plurality of first type lines and the second type lines to any of the plurality of silicon through vias, wherein the second type lines having an uppermost surface wider than the bottom surface of the line have a different height from the plurality of first type lines; and Multiple second vias connecting each of the plurality of first type lines and the second type lines to the second back metal level. The semiconductor structure according to claim 11, further comprising:
13. A plurality of first vias connecting each of the plurality of first type lines and the second type line to a second back metal level closer to the semiconductor substrate than the first back metal level; and Multiple second vias connecting each of the plurality of first type lines and the second type line to a third back metal level below the first back metal level, wherein the second type line has a top surface located below the top surface of the plurality of first type lines. The semiconductor structure according to claim 11, further comprising:
14. A plurality of first type lines having a first line width in a first surface metal level, wherein each of the plurality of first type lines has an uppermost surface wider than the line bottom surface; A second type of line having a second line width wider than the first line width, wherein the second type of line has an uppermost surface wider than the line bottom surface, and the second type of line lies between two adjacent first type lines; and Multiple first vias connecting each of the plurality of first type lines and the second type lines to the second front metal level. A semiconductor structure that includes this.
15. The semiconductor structure according to claim 14, wherein the second type of line is shorter than the plurality of first type lines, and the second type of line is located above the bottom surface of the plurality of first type lines.
16. The semiconductor structure according to claim 14, wherein the second type of line is connected by any of a plurality of second vias to elements from a group consisting of a semiconductor device and a metal level below the first metal level.
17. The third front metal level above the second front metal level includes a second plurality of first type lines, and another second type line between two adjacent first type lines among the second plurality of first type lines. The semiconductor structure according to claim 14, further comprising:
18. The semiconductor structure according to claim 14, wherein the second type of line comprises a plurality of second type lines, each of which is selected from the group of second type lines having: a top surface located above the top surface of the plurality of first type lines; a top surface that is the same height as the central portion of the plurality of first type lines; and a top surface that is the same height as the top surface of the plurality of first type lines.
19. The second type of line is connected to one of the semiconductor devices among the plurality of semiconductor devices by any of the plurality of second vias; Any of the aforementioned semiconductor devices is connected to a third via on the underside of the semiconductor substrate via a through-silicon via; The third via connects to a second type of line on the back side of the first back side metal level. The semiconductor structure according to claim 16, further comprising:
20. The semiconductor structure according to claim 14, wherein the first front metal level is a metal level selected from the group consisting of intermediate process metal levels and wiring process metal levels.
21. A plurality of first-type lines having a first line width in a first surface metal level; A second type of line in the first surface metal level having a second line width smaller than the first line width, wherein the second type of line lies between two adjacent first type lines among the plurality of first type lines; Multiple first vias connecting multiple semiconductor devices to either the second type of line or the multiple first type lines; A plurality of through-silicon vias in a semiconductor substrate, wherein each of the plurality of through-silicon vias connects the plurality of semiconductor devices to a plurality of second vias in a first dielectric layer on the back side of the semiconductor substrate; A plurality of first type backing lines having a third line width in a first backing metal level, wherein each of the plurality of first type backing lines contacts one of the plurality of second vias; A second type of backline line in the first backline metal level having a fourth line width narrower than the third line width, wherein the second type of backline line lies between two adjacent lines of the plurality of first type backline lines; the second type of backline line contacts any of the plurality of second vias; and Multiple third vias connect the second type of backline line and the multiple first type of backline to the second backline metal level. A semiconductor structure comprising the above features.
22. The semiconductor structure according to claim 21, wherein the second type of back-side lines have the same height as the plurality of first type of back-side lines.
23. The semiconductor structure according to claim 21, wherein the second type of back-side line has the uppermost surface of a level selected from the group consisting of a level lower than the uppermost surface of the plurality of first type of back-side lines, the same level as the central portion of the plurality of first type of back-side lines, and a level higher than the uppermost surface of the plurality of first type of back-side lines.
24. A step of forming multiple first vias in a first dielectric material on the back side of a semiconductor substrate using a damascene process; A step of etching two first trenches for two first type lines on the vias of the plurality of first vias using a damascene process; A step of depositing metallic material in the two first trenches; The stage in which chemical mechanical polishing (CMP) is performed; The step of etching at least one third trench between the two first type lines using a damascene process, wherein the third trench is narrower than the two first trenches; The step of filling the third trench with the metal material; and Steps to perform CMP to form a second type of line. A method for forming a semiconductor structure, including [a specific component].
25. The method according to claim 24, wherein the metal material in the two first trenches and the metal material filling the third trench are different metal materials.