Zero-diffusion break between standard cells using three-dimensional cross-field-effect self-aligned transistors

Abstract

Apparatus and method are provided for efficiently generating standard cell layouts to improve the floor plan of a chip. The integrated circuit uses multiple standard cells without diffusion breaks at the cell boundaries. The standard cells use vertically stacked non-planar transistors. Multiple transistors are formed by an active region having a length between the source and drain regions of a single transistor. The active region of each transistor is not formed across multiple gate terminals. By forming the active region of each transistor across a single gate terminal of a single transistor, there is sufficient spacing to provide electrical isolation between the two active regions of two adjacent standard cells. This is true even if the two adjacent standard cells share a source / drain region at the cell boundary. Thus, it is possible to skip forming diffusion breaks at the edges of these standard cells.

Description

Background Art

[0001] (Description of Related Art) As semiconductor manufacturing processes have advanced and the on-die geometric dimensions have decreased, semiconductor chips are providing more functions and performance while consuming less space. Although many advancements have been made, modern technologies in processing and integrated circuit design that limit potential benefits still pose design problems. For example, capacitive coupling, electromigration, short-channel effects such as at least leakage current, and process yield are some of the problems that affect the placement of devices and the routing of signals across the die of a semiconductor chip. These problems can delay the completion of the design and affect the time to market.

[0002] To shorten the design cycle of semiconductor chips, manual full-custom design is replaced by automation if possible. In some cases, standard cell layouts are generated manually. In other cases, the rules used by place-and-route tools are adjusted to automate cell generation. However, automated processes sometimes do not meet each of the rules for both local and external signal routing, including performance, power consumption, signal integrity, process yield, internal cross-coupled connections, pin access, etc. Therefore, designers either generate these cells manually to achieve better results for multiple characteristics or rewrite the rules of the place-and-route tools. However, in many cases, layout tools and rules are set up for planar devices rather than for relatively recent non-planar devices.

[0003] In addition, the dimensions of individual components of a semiconductor chip impose constraints on placing all components on the same die or package. The dimensions of one or more standard cells, such as height or width, can be large enough to interfere with the placement of other components. Layout tools also adhere to rules regarding the minimum dimensions between multiple duplicated standard cells, which further increases the required on-die area. In some cases, multiple placed cells may not even fit within the same die or package. As a result, the chip becomes inoperable without significant redesign. In other cases, components fit within the same die or package, but their placement creates unused space on the die or package. In this case, the placement of components is considered inefficient if otherwise available space is rendered unusable for placement.

[0004] In light of the above, there is a need for methods and systems to efficiently generate standard cell layouts in order to improve the chip floor plan. [Brief explanation of the drawing]

[0005] [Figure 1] This is a generalized diagram of a cross-sectional view of a semiconductor device layout with vertically stacked transistors. [Figure 2] This is a generalized diagram of a cross-sectional and top view of a semiconductor device layout using vertically stacked transistors. [Figure 3] This is a generalized cross-sectional diagram of a semiconductor device layout with vertically stacked transistors and their corresponding power connections. [Figure 4] This is a generalized cross-sectional diagram of a semiconductor device layout of transistors in adjacent standard cells, utilizing diffusion breaks between adjacent standard cells. [Figure 5] This is a generalized top cross-sectional view of a semiconductor device layout of adjacent standard cells, where there are no diffusion breaks between adjacent standard cells. [Figure 6]This is a generalized top cross-sectional view of a semiconductor device layout of adjacent standard cells, where there are no diffusion breaks between adjacent standard cells. [Figure 7] This is a generalized top cross-sectional view of a semiconductor device layout of adjacent standard cells, where there are no diffusion breaks between adjacent standard cells. [Figure 8] This is a generalized top cross-sectional view of a semiconductor device layout of adjacent standard cells, where there are no diffusion breaks between adjacent standard cells. [Figure 9] This is a generalized top cross-sectional view of a semiconductor device layout of adjacent standard cells, where there are no diffusion breaks between adjacent standard cells. [Figure 10] This is a generalized diagram of a method for efficiently generating a layout of adjacent standard cells with no diffusion breaks between them. [Figure 11] This is a generalized diagram of a method that utilizes a layout that includes adjacent standard cells with no diffusion breaks between them. [Figure 12] This is a generalized diagram of a computing system having an integrated circuit that uses adjacent standard cells with no diffusion breaks between them. [Figure 13] This is a generalized diagram of a table showing the reduction in layout area for multiple types of standard cells, where there are no diffusion breaks between multiple types of standard cells. [Modes for carrying out the invention]

[0006] While the present invention is open to various modifications and alternative forms, specific embodiments are shown in the drawings as examples and described in detail herein. However, it should be understood that the drawings and their detailed description are not intended to limit the invention to any particular form disclosed, but rather, the invention encompasses all modifications, equivalents, and alternatives that fall within the scope of the invention as defined by the appended claims.

[0007] The following specification includes numerous specific details to provide a full understanding of the invention. However, those skilled in the art should recognize that the invention can be carried out without these specific details. In some examples, well-known circuits, structures, and techniques are not shown in detail to avoid obscuring the invention. Furthermore, for the sake of simplicity and clarity of explanation, please understand that the elements shown in the figures are not necessarily drawn to scale. For example, the dimensions of some elements are exaggerated relative to others.

[0008] To improve the floor planning of a chip, systems and methods are conceived for efficiently generating standard cell layouts. In various embodiments, the integrated circuit uses one or more standard cells containing a pair of vertically stacked non-planar transistors. As used herein, “transistor” is also referred to as “field-effect transistor (FET),” “semiconductor device,” or “device.” In some embodiments, the pair of transistors is a vertically stacked gate all-around (GAA) transistor, for example, an upper vertical GAA transistor (or GAA transistor) formed vertically on top of a lower GAA transistor, with at least an isolating oxide layer between the two GAA transistors. It should be understood that silicon wafers, integrated circuits, and semiconductor packages using silicon substrate layers may be rotated and inverted. Therefore, the materials and layers described will be rotated and inverted, and their orientation and direction will have different meanings. Thus, the terms “upper,” “lower,” “horizontal,” “vertical,” “left,” “right,” “upward,” and “downward” may change as the layout rotates or inverts.

[0009] As used herein, the “active layer” refers to the region of the semiconductor wafer on which doped silicon is formed. The “active layer” may also be referred to as the “active region” or “diffusion region.” In the case of a planar transistor (device), the active layer defines the region of the silicon substrate that is doped with either p-type atoms (dopants) or n-type atoms (dopants). During doping of the silicon substrate material in the semiconductor manufacturing process, impurity atoms (dopants) move into the silicon substrate material by diffusion at high temperatures (or movement or migration based on the doping gradient). In the case of a non-planar transistor (device), the active layer defines the region of the three-dimensional structure above the silicon substrate containing the doped silicon, such as the location where the channel is formed. In various embodiments, multiple transistors are formed using active regions having a length less than or equal to the distance between the source and drain regions of a single transistor. Therefore, the active regions of these transistors are formed over a single gate terminal of a single transistor, rather than over multiple gate terminals. As used herein, the “terminals” of a transistor are also referred to as the “regions” of a transistor. For example, the source region is also referred to as the source terminal, the drain region as the drain terminal, and the gate region as the gate terminal.

[0010] One or more standard cells using these transistors are formed with zero diffusion breaks on one or more edges of the corresponding standard cell. For example, at least one edge of the standard cell does not have a diffusion break. As used herein, a "diffusion break" is a region where doped silicon is not formed. Therefore, no active layer (or active or diffusing region) exists in such a region. Diffusion breaks are typically used to provide electrical insulation between regions. In one embodiment, source / drain regions are also not formed. In some embodiments, the diffusion breaks are formed on an insulating layer rather than on a silicon substrate. The isolation layer may be a silicon oxide layer such as a silicon nitride layer or a silicon dioxide layer, or another type of dielectric layer.

[0011] In one embodiment, the diffusion break region includes a dummy gate structure that allows the semiconductor manufacturing process to continuously form a gate structure in a repeating pattern (width and pitch) using a metal gate material, thereby increasing the yield of the semiconductor die. However, there is no active region formed for the dummy gate structure. Therefore, even if a voltage level is applied to the dummy gate structure (or dummy gate) and one or more of the regions on either side of the dummy gate, such as the source / drain region, no electrical path is provided and no current flows across the dummy gate. In contrast, an active gate structure is a gate structure formed of a metal gate material, and an active region is formed relative to the gate structure. Therefore, when a voltage level is applied to the active gate structure (or active gate) and one or more of the regions on either side of the active gate, such as the source / drain region, an electrical path is provided and current flows across the active gate.

[0012] Diffusion breaks provide electrical isolation between silicon-doped regions. An example of these regions is the active region of two separate but adjacent standard cells. However, an integrated circuit contains at least two adjacent standard cells that do not have a diffusion break between them. By forming the active region of these transistors over a single gate terminal of a single transistor, rather than over multiple gate terminals, it is possible to avoid forming a diffusion break at the edges of these standard cells. In other words, there is no need to form a diffusion break at the edges of these standard cells. This is true even if the two adjacent standard cells share a source / drain region at the cell boundary. There is sufficient spacing to provide electrical isolation between the two active regions of the two adjacent standard cells. Thus, each of the multiple n-type gates of the two adjacent standard cells is an active gate, and each of the multiple p-type gates of the two adjacent standard cells is an active gate. Further details of standard cells without a diffusion break at the cell boundary are provided in the following description of Figures 1 to 12.

[0013] Referring to Figure 1, a generalized block diagram of a cross-sectional view of semiconductor device layout 100 using vertically stacked transistors is shown. The semiconductor material of the cross field-effect transistor (FET) 102 is shown in the figure or frame on the left. Cross FETs are also referred to as "XFETs". Therefore, cross FET 102 is also referred to as XFET 102. The gate terminals of XFET 102 are oriented in directions orthogonal to each other, and the gate terminals overlap each other. Therefore, these gate terminals form a cross or X shape from the top view, as shown for XFET 102. The gate terminals of T-type FETs are oriented in directions orthogonal to each other, but the gate terminals do not overlap each other. Therefore, these gate terminals form a T shape from the top view. T-type FETs are also referred to as "TFETs". The semiconductor material of TFET 104 is shown in the figure or frame on the right. Three-dimensional (3-D) diagrams of p-type and n-type cross FETs 102 and TFET 104 are shown. Each of the XFET102 and TFET104 includes a p-type device stacked vertically on an n-type device. The n-type device includes at least one n-type gate 116 formed around the entire circumference of an n-type channel 110. Similarly, a p-type gate 136 is formed around the entire circumference of a p-type channel 130. Thus, the p-type channel 130 has a doping polarity that is the opposite polarity to the n-type channel 110 of the lower n-type device.

[0014] Each pair of non-planar n-type and p-type adjacent transistors in XFET102 and TFET104 contains only one transistor from a pair of transistors adjacent to the silicon substrate. For example, XFET102 includes only n-type transistors whose n-type gate 116 is adjacent to the silicon substrate (not shown, but located below the n-type transistor). A p-type transistor with a p-type gate 136 is adjacent to an n-type transistor with an n-type gate 116, but the p-type transistor is not adjacent to the silicon substrate. The transistors in TFET104 are shown to have the same arrangement relationship with respect to the silicon substrate.

[0015] For the cross-FET 102, a single n-type channel 110 and a single p-type channel 130 are shown, but in other embodiments, the semiconductor device includes a different number of conduction channels. For example, the TFET 104 includes an n-type channel 110 and an n-type channel 111. The n-type channel 110 is used to form an n-type active gate, and the p-type channel 130 is used to form a p-type active gate. In some embodiments, the channel includes one or more conduction lateral nanowires. In other embodiments, the channel includes one or more conduction nanosheets. Nanosheets are doped silicon sheets, not doped silicon wires. In other words, nanosheets are conduction wires that are wider than lateral nanowires. Also, nanosheets can be thought of as fins that are rotated so that they do not have physical contact with the silicon substrate and are positioned on their sides perpendicular to the silicon substrate. More precisely, a metallic gate is formed between the nanosheet and the silicon substrate. However, this embodiment does not describe the actual manufacturing process for forming the nanosheets.

[0016] Compared to FinFETs, the use of gate-all-around (GAA) nanowires or nanosheets results in lower threshold voltages, faster switching times, lower leakage currents, and further reductions in short-channel effects. Examples of short-channel effects other than leakage current include latch-up effects, drain-induced barrier lowering (DIBL), punch-through, temperature dependence of performance, collisional ionization, and parasitic capacitance to the silicon substrate. As mentioned above, the “active layer” refers to the region of the semiconductor wafer on which the doped silicon is formed. In the case of planar transistors (devices), the active layer defines the region where the silicon substrate is doped with either p-type atoms (dopants) or n-type atoms (dopants). In the case of non-planar transistors (devices), the active layer defines the region of the three-dimensional structure above the silicon substrate containing the doped silicon, such as where the channel is formed.

[0017] In the illustrated embodiment, XFET 102 has an n-type active layer (unlabeled) containing a single n-type channel 110. In other embodiments, the n-type active layer of the n-type device contains multiple n-type channels instead of a single n-type channel 110. XFET 102 has a p-type active layer (unlabeled) containing a single p-type channel 130. In other embodiments, the p-type active layer of the p-type device contains multiple p-type channels instead of a single p-type channel 130. In the illustrated embodiment, TFET 104 has an n-type active layer 180 containing n-type channels 110 and n-type channels 111. In other embodiments, the n-type active layer 180 of the n-type device contains a different number of n-type channels.

[0018] The TFET 104 has a p-type active layer 182 containing a single p-type channel 130. In other embodiments, the p-type active layer 182 of a p-type device contains multiple p-type channels instead of a single p-type channel 130. In various embodiments, the n-type active layer 180 and the p-type active layer 182 have a length less than or equal to the distance between the source and drain regions (these source / drain regions are not shown) of a single transistor such as an n-type and a p-type device. The source and drain regions are typically formed in the same orientation (horizontal or vertical) as the corresponding gate metal of the same device. An example of a source and drain region is a trench silicide contact. In some embodiments, the source and drain regions contain cobalt silicide (CoSi2). In other embodiments, the source and drain regions contain titanium silicide (TiSi2) or ruthenium (Ru). These active layers 180, 182 are not formed across multiple gate terminals. By forming the active layers 180 and 182 across a single gate terminal of a single transistor, there is sufficient spacing to provide electrical isolation between the two active regions of two adjacent standard cells.

[0019] In the case of one or more channels, the p-type active layer 182 of the p-type device includes a three-dimensional area having dimensions such as length, width, and height. These dimensions correspond to the dimensions of one or more p-type channels (or p-type nanosheets). For example, the p-type active layer length 126 is the same as the length of one or more p-type channels such as the p-type channel 130. Similarly, the n-type active layer length 124 is the same as the length of one or more n-type channels, such as the length of the n-type channel 110, or the same as the length of the n-type channel 111. The height 125 of the n-type active layer of the n-type active layer 180 is the same as the overall height of one or more n-type channels, such as the overall height of the n-type channel 110 and the n-type channel 111. The width of the p-type active layer (without label) is the same as the width of one or more p-type channels. Similarly, the n-type active layer width (without label) of the n-type active layer 180 is the same as the width of the n-type channel 111, which is the same as the width of the n-type channel 110.

[0020] The n-type channel 110 and the n-type gate 116 are oriented in a direction orthogonal to the p-type channel 130 and the p-type gate 136. In other words, the n-type channel 110 and the n-type gate 116 are oriented in a direction that makes a 90-degree angle from the direction of the p-type channel 130 and the p-type gate 136. Therefore, the direction of current flow in the lower n-type device through the n-type channel 110 is orthogonal to the direction of current flow in the p-type channel 130 of the upper p-type device. The direction of current flow for each of the XFET 102 and the TFET 104 is indicated by an arrow and the label "Iflow". In the orthogonal orientation between the upper p-type device and the lower n-type device, both devices have the maximum mobility of their respective carriers based on their orientation. In addition, the orthogonal orientation of the upper p-type device and the lower n-type device enables the connection between the vertically stacked devices to use a single via layer.

[0021] A complementary FET (CFET) (not shown) includes an upper GAA transistor vertically stacked on a lower GAA transistor and has at least an oxide layer for isolation therebetween. Thus, CFETs, XFETs, and TFETs use vertically stacked GAA transistors. Each pair of non-planar n-type and p-type adjacent transistors in a CFET, XFET, and TFET has only one of the transistors of a pair of transistors adjacent to the silicon substrate. Vertically stacking the upper GAA transistor on the lower GAA transistor further increases performance, reduces power consumption, and reduces the on-die area consumed by the GAA transistors. However, a CFET uses an upper GAA transistor having one or more channels aligned in the same direction as one or more channels of the lower GAA transistor. A CFET does not rotate the upper and lower GAA transistors relative to each other. However, as shown here, XFET 102 and TFET 104 have an orthogonal orientation between one or more channels of the upper GAA transistor and one or more channels of the lower GAA transistor.

[0022] Compared to a complementary FET, XFET 102 and TFET 104 have a better drive current for each of the upper GAA transistor and the lower GAA transistor, thereby obtaining higher performance. Typically, a complementary FET uses at least two metal layers and three via layers to create a connection between the upper GAA transistor and the lower GAA transistor. In contrast, XFET 102 and TFET 104 utilize a single metal layer and a single via layer for connecting the upper GAA transistor and the lower GAA transistor.

[0023] An insulating layer lies between the upper p-type device and the lower n-type device, and when the gate terminals of the device pair (p-type device and n-type device) receive the same input signal, a gate contact 122 is formed between the devices in the insulating layer. The gate contact 122 between the vertically stacked devices connects directly to the p-type metal gate 136 and the n-type metal gate 116 without crossing any metal layers. One advantage of the orthogonal orientation of the XFET 102 and TFET 104 is that only one via layer is used, which will be shown later in the memory bit cell layout. The use of this single via layer reduces the resistance and capacitance of the corresponding circuit.

[0024] As illustrated, the gate contact 122 of XFET 102 overlaps with the n-type active layer and the p-type active layer of the two vertically stacked transistors. Since the embodiment shown for XFET 102 includes a single channel for each of the p-type and n-type devices, the active layers in the shown embodiment include single channels 110 and 130. The gate contact 122 overlaps with each of the n-type channel 110 and the p-type channel 130. On the other hand, the gate contact 122 of TFET 104 overlaps with only one of the active layers, either the p-type active layer 182 of the p-type device or the n-type active layer 180 of the n-type device, and the p-type and n-type devices form two vertically stacked devices. In the shown embodiment, the gate contact 122 of TFET 104 overlaps only with the n-type active layer 180, which includes the n-type channels 110 and 111. Therefore, the gate contact 122 of TFET 104 overlaps only with the n-type active layer 180. The gate contact 122 of TFET104 does not overlap with the p-type active layer 182.

[0025] In the case of TFET 104, in various embodiments, the p-type active layer 182 does not overlap with the n-type active layer 180. The distance between the p-type active layer 182 and the n-type active layer 180 is indicated as width (or offset) 106. Width 106 includes at least the width of the source contact or drain contact. In some embodiments, width 106 includes another minimum distance between the p-type channel 130 and the source or drain contact, which is determined by the design rules and checks of the specific semiconductor manufacturing process used to manufacture TFET 104. In one embodiment, this minimum distance is 3 nanometers (nm), and the width of the source or drain contact is 18 nm. In such embodiments, the minimum width of width 106 is 21 nm (3 nm + 18 nm = 21 nm).

[0026] Referring to Figure 2, a generalized block diagram of a top view of a semiconductor device layout 200 using TFETs is shown. The same reference numerals are used for the contacts (or vias), semiconductor materials, and structures described earlier. Standard cell layout 200 (or layout 200) is a top view of a standard cell layout for an inverter using TFET 104. The three-dimensional (3-D) diagrams of the p-type and n-type TFET 104 shown in the left frame are accompanied by the top view of the inverter layout 200 shown on the right. The inverter corresponding to layout 200 uses p-type TFETs and n-type TFETs of TFET 104 in addition to interconnecting materials to complete the electrical connections that provide the inverter's functionality. For example, nodes labeled "IN" and "OUT" store Boolean complementary values ​​to each other. In this inverter, the p-type devices are stacked vertically on top of the n-type devices. However, in other embodiments, it is possible and intended to stack the n-type devices vertically on top of the p-type devices. Each inverter device corresponding to layout 200, which provides a top view of a standard cell layout, uses a gate all-around (GAA) metal that encloses one or more nanosheets in the gate region in a 360-degree manner. The lower n-type device is fabricated on a first wafer. The upper p-type device is fabricated on a separate second wafer, and then the oxides are bonded together to the first wafer. As shown, the gate contact 122 overlaps with only one of the active layers, either the n-type or the p-type active layer.

[0027] The inverter corresponding to layout 200, which provides a top view of a standard cell layout, uses a front power metal zero (or metal 0 or M0 or Metal0) layer 150 to provide a power reference level indicated as "VDD". The inverter uses an n-type through silicon via (TSV) local interconnect layer 112 to provide a ground reference level indicated as "VSS". Contact 140 connects the front M0 layer 150 to the p-type local interconnect 134 to route VDD to the source area of ​​the p-type device. The front M0 layer 150 is also used to route the input signal "IN" and the output signal "OUT". For the input signal "IN", contact 142 connects the front M0 layer 150 to the p-type gate 136. For the input signal "IN", contact 122 connects the p-type gate 136 to the n-type gate 116. The drain area of ​​the n-type device uses the n-type local interconnect 114. The drain area of ​​the p-type device uses the p-type local interconnect 134. Contact 120 connects these two drain regions to each other. Contact 120 is located between the drain node of the p-type transistor and the drain node of the n-type transistor and is in contact with the area of ​​the p-type local interconnect 134 of the p-type transistor.

[0028] For the output signal "OUT", contact 140 overlaps with the area of ​​contact 120, and the p-type local interconnect 134 connects to the front M0 layer 150. The inverter uses a rear power metal zero (or metal 0 or M0 or Metal0) layer located beneath the silicon substrate layer and an oxide layer (not shown) used for insulation. Micro-through silicon vias (TSVs) traverse the silicon substrate layer to be positioned between the rear power M0 rail and the source region of the n-type device. The inverter corresponding to layout 200 uses TFET 104, so the current in the n-type device flows in a direction perpendicular to the current flow of the p-type device. The orthogonality of the current flow is shown in the top view provided by TFET 104 and layout 200. The direction of current flow in the n-type and p-type devices, respectively, is indicated by arrows and the label "Iflow".

[0029] In addition to the direction of current flow (Iflow) of the two devices, the length dimensions 124 and 126 of the active layers are shown. The width 106 between the p-type active layer and the n-type active layer preferably includes the width of at least the source or drain contact 120. In some embodiments, rules used in placement and routing tools indicate that the width 106 should be at least the width of the source or drain contact 120. In other embodiments, these rules indicate a different distance threshold. These rules in placement and routing tools are determined by the semiconductor manufacturer and set to increase the yield of the semiconductor integrated circuits to be manufactured. Here, the inverter uses contact 120 as the drain contact. The length dimensions 124 and 126 of the active layers have multiple lengths that are shorter than the dimensions of a standard cell in the inverter, rather than traversing the inverter. The p-type active layer length 126 is less than or equal to the distance between the source and drain regions of a single p-type transistor.

[0030] Similar to the p-type active layer length 126, the n-type active layer length 124 is preferably less than or equal to the distance between the source and drain regions of a single n-type transistor. In one embodiment, the n-type active layer length 124 (and the p-type active layer length 126) is limited by a threshold distance based on rules used by the placement and routing tool, which are provided by the semiconductor manufacturer. Thus, the distance to the active layer of any adjacent standard cell can be large enough to provide electrical insulation between the active layers without diffusion breaks between adjacent standard cells. Distance 202 is the distance from the n-type active layer mounted by the n-type nanosheet 110 to the top of the inverter standard cell. Distance 204 is the distance from the n-type active layer to the bottom of the inverter standard cell. Distances 202 and 204 will have additional distances within adjacent standard cells before reaching another active layer. These combined distances between adjacent standard cells using distances 202 and 204 are long enough to provide electrical insulation between the active layers without diffusion breaks between adjacent standard cells. Distance 206 is the distance from the p-type active layer, which is mounted by the p-type nanosheet 130, to the bottom of the inverter standard cell. Distance 206 will have additional distance within adjacent standard cells before reaching another active layer. These combined distances between adjacent standard cells using distance 206 are long enough to provide electrical insulation between the active layers without diffusion breaks between adjacent standard cells. A similar distance exists between the p-type active layer and the top of the inverter standard cell.

[0031] Referring to Figure 3, a generalized block diagram of a cross-sectional view of a standard cell layout 300 that utilizes power connections routed in the front and back metal layers is shown. The same reference numerals are used for the contacts (or vias), semiconductor materials, and structures described earlier. The standard cell layout 300 is for any of the various types of Boolean gates and composite gates, including transistors arranged in a particular manner to provide data processing functions or data storage. The standard cell layout 300 (or layout 300) uses TFETs. In other embodiments, the standard cell layout 300 uses XFETs. The TFETs include n-type devices 340 and p-type devices 342. The cross-sectional view shows each of the two transistors (devices) 340 and 342 with their metal gates oriented in the same direction, but the actual arrangement of these transistors in the semiconductor layout includes orthogonal arrangements relative to each other. Power signals are routed using both the front and back metal layers.

[0032] Here, a first transistor of the TFET, such as the n-type device 340, has an n-type active layer 380 that provides a current flow oriented in a first direction perpendicular to a second direction of current flow in the p-type active layer 382. In layout 300, the direction of current flow in the p-type device 342 and the n-type device 340, respectively, is indicated by arrows and the label "Iflow". These directions of current flow in layout 300 are not shown as perpendicular to each other as illustrated, since cross-sectional views, rather than top views, of the p-type device 342 and the n-type device 340 are provided. The current flows through the p-type active layer 382 and the n-type active layer 380, which are arranged in an orthogonal orientation to each other, as previously shown in layouts 100 and 200 (Figures 1 and 2). In one embodiment, the n-type active layer 380 includes one or more n-type nanosheets. In the key or legend, the label "n-type nanosheet 110" is used. However, it should be understood that n-type active layers, such as n-type active layer 380 (and n-type active layer 180 in Figure 1), can contain multiple n-type nanosheets, as shown in the cross-sectional view provided in layout 300. The following layouts 500-900 (in Figures 5-9) provide top views rather than cross-sectional views, and therefore only a single n-type nanosheet is shown. However, it should be understood that one or more additional n-type nanosheets are formed beneath the topmost n-type nanosheet, as shown in layout 300 and layout 100 (in Figure 1). This also applies to the p-type nanosheet 130.

[0033] In various embodiments, each of the n-type nanosheets 110 of the n-type active layer 380 is composed of an epitaxially grown silicon semiconductor layer doped with n-type atoms. Similarly, each of the p-type nanosheets 130 is composed of an epitaxially grown silicon semiconductor layer doped with p-type atoms. Each of the n-type nanosheets 110 and p-type nanosheets 130 is terminated within the edges of their respective drain and source regions. The drain and source regions of the n-type device 340 use the n-type local interconnect 114 described above. The drain and source regions of the p-type device 342 use the p-type local interconnect 134 described above.

[0034] Unlike complementary FETs, the n-type nanosheets 110 do not traverse the entire drain and source regions. Rather, the n-type nanosheets 110 utilize the metal sidewall contacts 350 at their edges within the source and drain regions, thereby enabling the generation of more nanosheets in the n-type active layer. The p-type nanosheets 130 of the p-type active layer 382 are formed in a similar manner, and in this case as well, the metal sidewall contacts 352 are also utilized at their edges within the respective source and drain regions.

[0035] As described above, the n-type active layer 380 refers to the region of the semiconductor wafer on which the doped silicon is formed. The n-type active layer 380 of the n-type device 340 is a three-dimensional area with a length 324 equal to the distance between the metal sidewall contacts 350 at the edges of the nanosheets in the source and drain regions. Similar to the n-type active layer height 125 of the n-type active layer 180 (in Figure 1), the n-type active layer 380 has an n-type active layer height 325 equal to the distance from the bottom of the lower n-type nanosheet 110 to the top of the upper n-type nanosheet 110. Additionally, this n-type active layer 380 has a width equal to the distance that the n-type nanosheet 110 traverses along the direction in which it enters (or leaves) the page. The p-type active layer 382 of the p-type device 342 has dimensions defined in a similar manner. For example, the p-type active layer 382 of the p-type device 342 is a three-dimensional area with a length 326 equal to the distance between the metal sidewall contacts 352 at the edges of the nanosheets in the source and drain regions.

[0036] Active layers 380 and 382 are formed across a single gate terminal of a single transistor, and by having active layer lengths 324 and 326, there is sufficient spacing to provide electrical isolation between the two active regions of two adjacent standard cells. These distances between active layers across two adjacent standard cells are shown in standard cell layouts 500-900 (Figures 5-9). The n-type device 340 is connected to a first voltage level reference provided by a back metal layer. This back power metal zero (or metal 0 or M0 or Metal0) layer 302 is located beneath the silicon substrate layer and any oxide layers (not shown) used for insulating purposes. Micro-through-silicon vias (TSVs) 304 traverse the silicon substrate layer to be located between the back power M0 layer 302 and the source region of the n-type device 340.

[0037] Furthermore, the TFET uses a second transistor, such as a p-type device 342, which has a second channel oriented in a second direction perpendicular to the first direction and connected to a second voltage level reference provided by a front metal layer. This front power metal zero (or metal 0 or M0 or Metal0) layer 320 is located above the silicon substrate layer and any oxide layer (not shown) used for insulating purposes. The drain and source regions of the p-type device 342 use the previously described p-type local interconnect 134. The p-type source / drain contact 308 connects the source region (p-type local interconnect 134) to the M0 layer 320. In other embodiments, the n-type transistor 340 and the p-type transistor 342 are switched with a type of voltage reference level connected to a back power M0 layer 302 and a front power M0 layer 320.

[0038] A "micro-TSV" 304 is a through-silicon via that traverses the silicon substrate layers from the back power M0 layer 302 to the source region using an n-type local interconnect 114, and terminates at physical contact with the source region in each of the back power M0 rails 302. The distance from the back power M0 layer 302 to the n-type local interconnect 114 used as the source region defines the height or length of the micro-TSV 304 that traverses only the silicon substrate layers and any oxide layers above the back power M0 layer 302. The micro-TSV 304 does not physically extend within the multiple insulating layers of the semiconductor die used to route multiple front metal layers. Similarly, the micro-TSV 304 does not physically extend within the multiple insulating layers of the semiconductor die used to route multiple back metal layers.

[0039] Referring to Figure 4, a generalized block diagram of a standard cell layout 400 of adjacent standard cells is shown, utilizing diffusion breaks between adjacent standard cells. The same reference numerals are used for the contacts (or vias), semiconductor materials, and structures described earlier. A top view of an n-type device in a standard cell using an n-type active layer 480 is shown in the upper left corner of the standard cell layout 400 (or layout 400). The n-type device is used in a standard cell using a CFET. Adjacent p-type devices are not shown. Unlike standard cells using XFETs or TFETs, this standard cell utilizes an n-type active layer 480 with an n-type active layer length 424 (or length 424) spanning multiple gate terminals. A cross-sectional view of this standard cell is shown below the top view.

[0040] Layout 400 shows that the n-type nanosheets 410 of the n-type active layer 480 are formed over three gate terminals, rather than over a single gate terminal of a single transistor. Therefore, measuring the length as the number of gate terminals, the length 424 is greater than the length 124. The source and drain regions contain the n-type nanosheets 410 over the entire length of these regions. The n-type local interconnects 114 are formed above and below the n-type nanosheets 410. Unlike the n-type active layers 180 and 380, the n-type active layer 480 does not terminate in the source and drain regions using metal sidewall contacts 350 at the edges of the n-type nanosheets 410 within the source and drain regions. Rather, the n-type active layer 480 terminates at the gate terminals (n-type gates 116).

[0041] A top view of an n-type device in an adjacent standard cell using an n-type active layer 482 is shown in the upper right corner of the standard cell layout 400 (or layout 400). Similar to the n-type active layer 480, the n-type active layer 482 does not terminate in the source and drain regions, using metal sidewall contacts 350 at the edges of the n-type nanosheets 410 in the source and drain regions. Rather, the n-type active layer 482 terminates at the gate terminal (n-type gate 116). In the semiconductor chip floor plan, the spacing 410 between standard cells is required to provide electrical insulation between the n-type active layer 480 and the n-type active layer 482 in order to arrange adjacent standard cells. Two standard cells cannot be placed on a semiconductor die (or die) without a diffusion break between them.

[0042] Referring to Figures 5 and 6, generalized block diagrams of top views of semiconductor device layouts 500 and 600 of adjacent standard cells, where there is no diffusion break between adjacent standard cells, are shown. The same reference numerals are used for the contacts (or vias), semiconductor materials, and structures described earlier. Standard cell layout 500 (or layout 500) is for an inverter using TFETs within a standard cell boundary 502. Layout 500 can be used for two separate inverters, or for a single inverter having twice the drive strength when separate input signals are electrically short-circuited to each other and separate output signals are electrically short-circuited to each other.

[0043] Distance 504 is the distance between two n-type active layers of two inverters using n-type nanosheets 110. Distance 504 is large enough to provide electrical insulation between the two n-type active layers without diffusion breaks between adjacent standard cells (adjacent inverters). Similarly, distance 506 is the distance between two p-type active layers of two inverters using p-type nanosheets 130. Regardless of whether another adjacent standard cell of one or two inverters is located above or below layout 500, distance 506 is large enough to provide electrical insulation between the two p-type active layers without diffusion breaks between adjacent standard cells.

[0044] Standard cell layouts 500-900 (Figures 5-9) use TFETs, while in other embodiments, standard cell layouts 500-900 use XFETs. In embodiments of standard cell layouts 500-900 using TFETs or XFETs, the n-type and p-type active layers have a distance between them that provides electrical insulation between the two active layers without diffusion breaks between adjacent standard cells. These distances between two n-type active layers and two p-type active layers in standard cell layouts 500-900 using TFETs or XFETs result from each of these active layers being formed across a single gate terminal of a single transistor. In other words, in embodiments of standard cell layouts 600-1000 using TFETs or XFETs, each of the plurality of p-type gates 136 and each of the plurality of n-type gates 116 are active gates. Thus, each metal gate (p-type gate 136 or n-type gate 116) is an active gate in standard cell layouts 600-1000. In embodiments of standard cell layouts 500-900 using TFETs or XFETs, dummy gate structures are not used. This is true even when two adjacent standard cells share a source / drain region at the cell boundary. While standard cell layouts 500-900 demonstrate the functionality of certain types of Boolean and composite gates, it should be noted that other embodiments also utilize various other types of Boolean and composite gates, including transistors arranged in a specific manner to provide data processing functions or data storage, as described below.

[0045] Standard cell layout 600 (or layout 600) is for inverters that use TFETs within a standard cell boundary 602 containing transistors for four inverters. Layout 600 can be used for two separate inverters, or for a single inverter having four times the drive strength when separate input signals are electrically short-circuited to each other and separate output signals are electrically short-circuited to each other. Each of the distances 604 and 606 between active layers within the cell boundary 602 is large enough to provide electrical isolation between the two active layers without diffusion breaks between adjacent standard cells. In addition, each of the n-type and p-type active layers above and below the cell boundary 602 has an approximate distance 608 to the cell boundary 602. This distance 608 is doubled when another standard cell using layout 600 is instantiated above and / or below the cell boundary 602. This total distance provides electrical isolation between the two active layers without diffusion breaks between adjacent standard cells.

[0046] Referring to Figures 7-9, generalized block diagrams of the top views of standard cell layouts 700-900 (or layouts 700-900) are shown. The same reference numerals are used for the contacts (or vias), materials, and structures described earlier. To avoid obscuring the n-type and p-type active layers, one or more semiconductor manufacturing elements are not included in layouts 700-900. Layout 700 is for a Boolean composite gate within a cell boundary 702, providing the functionality of a 3-input AND-OR-Invert (AOI) Boolean composite gate. Layout 700 also uses adjacent (instantiated and sometimes mirrored) standard cells to provide its functionality. Furthermore, layout 700 also uses vias 160 to connect the front M0 layer 150 to the front Metal 1 (or Metal 1 or M1 or Metal1) layer 170. Adjacent standard cells are positioned vertically above the previous standard cell. Since the distance between the active layers is already large enough to electrically insulate the active layers of adjacent standard cells, no diffusion breaks are present between adjacent standard cells.

[0047] The distance 704 between n-type active layers within the cell boundary 702 is large enough to provide electrical isolation between the two active layers without diffusion breaks between adjacent standard cells. Thus, two adjacent standard cells can share a source / drain region between them using a p-type local interconnect 134 with no diffusion breaks between adjacent standard cells. In addition, each of the n-type and p-type active layers above and below the cell boundary 702 has an approximate distance 706 to the cell boundary 702. This distance 706 is doubled when another standard cell using layout 700 is instantiated above and / or below the cell boundary 702. This total distance provides electrical isolation between the two active layers without diffusion breaks between adjacent standard cells. Similar to the metal gates in layouts 500-600 and 800-900, each of the metal gates in layout 700 is an active gate in two adjacent standard cells.

[0048] Layout 800 is for sequential data storage elements, also known as latches, within a cell boundary 802. Layout 800 provides its functionality using adjacent standard cells (instantiated and sometimes mirrored). Adjacent standard cells are positioned both horizontally and vertically relative to the previous standard cell. There are no diffusion breaks between adjacent standard cells. The distance 804 between n-type active layers within the cell boundary 802 indicates that the n-type active layer does not extend across the entire standard cell, and each n-type active layer traverses a single gate terminal, as also shown in layouts 500-900 (Figures 5-9). In addition, each of the n-type and p-type active layers above and below the cell boundary 802 has an approximate distance 806 to the cell boundary 802. This distance 806 is doubled when another standard cell using layout 800 is instantiated above and / or below the cell boundary 802. This total distance provides electrical isolation between the two active layers without diffusion breaks between adjacent standard cells.

[0049] Layout 900 is for a two-input AOI Boolean composite gate within a cell boundary 902. Layout 900 provides its functionality using adjacent standard cells (instantiated and sometimes mirrored). Adjacent standard cells are positioned both horizontally and vertically relative to the previous standard cell. No diffusion breaks are included between adjacent standard cells. Layout 900 includes an L-shape to another non-instantiated standard cell to provide available on-die area. The distance 904 between n-type active layers within the cell boundary 902 is large enough to provide electrical isolation between the two active layers, given that there are no diffusion breaks between adjacent standard cells. Similarly, the distance 906 between active layers within the cell boundary 902 is large enough to provide electrical isolation between the two active layers, given that there are no diffusion breaks between adjacent standard cells. In addition, each of the n-type and p-type active layers above and below the cell boundary 902 has an approximate distance 908 to the cell boundary 902. This distance 908 is doubled if another standard cell using layout 900 is instantiated above and / or below the cell boundary 902. This total distance provides electrical isolation between the two active layers without diffusion breaks between adjacent standard cells.

[0050] Referring to Figure 10, a generalized block diagram of Method 1000 is shown, which efficiently generates a layout of adjacent standard cells with no diffusion breaks between them. For illustrative purposes, the steps in this embodiment (and Method 1100 in Figure 11) are shown in order. However, in other embodiments, some steps occur in a different order than illustrated, some steps are performed simultaneously, some steps are combined with others, and some steps are absent.

[0051] A semiconductor manufacturing processor (or process) forms multiple transistors in a vertically stacked manner with orthogonal orientation (block 1002). Non-planar n-type and p-type adjacent transistor pairs have only one transistor from the pair of transistors adjacent to the silicon substrate. In various embodiments, the process forms an XFET or a TFET. The process forms multiple transistors, the active region having the length between the source and drain regions of a single transistor (block 1004). The process forms one or more standard cells from a plurality of standard cells, with no diffusion breaks at one or more edges (block 1006). The process arranges at least one adjacent standard cell pair on the die, with no diffusion breaks such as dummy gate structures between adjacent standard cell pairs (block 1008).

[0052] Referring to Figure 11, a generalized block diagram of Method 1100 for utilizing a layout including adjacent standard cells with no diffusion breaks between them is shown. A potential is applied to the input node of an integrated circuit including at least one pair of adjacent standard cells with no diffusion breaks or dummy gate structures between the pairs of adjacent standard cells (block 1102). As with the standard cell layouts 200-300 and 500-900 (in Figures 2 and 3 and Figures 5-9), in various embodiments the integrated circuit provides various types of functions using XFETs and / or TFETs. Thus, one or more active layers of the standard cells of the integrated circuit are formed across a single gate terminal of a single transistor, which provides electrical isolation between the two active layers with no diffusion breaks between adjacent standard cells. The integrated circuit transmits (carries) current from the input node to the output node through the pair of adjacent standard cells (1104).

[0053] Referring to Figure 12, a generalized block diagram of the computing system 1200 is shown. The computing system 1200 includes a processor 1210 and memory 1230. Interfaces such as the memory controller, bus or communication fabric, one or more phased locked loops (PLLs) and other clock generation circuits, power tube circuits, etc., are not shown for the sake of clarity. In other embodiments, it should be understood that the computing system 1200 includes one or more other processors of the same or different type as the processor 1210, one or more peripheral devices, network interfaces, one or more other memory devices, etc. In some embodiments, the functions of the computing system 1200 are integrated on a system on a chip (SoC). In other embodiments, the functions of the computing system 1200 are integrated on a peripheral card inserted into a motherboard. The computing system 1200 is used in any of the various computing devices such as desktop computers, tablet computers, laptops, smartphones, smartwatches, game consoles, and personal assistant devices.

[0054] The processor 1210 includes hardware such as circuit elements. For example, the processor 1210 includes a computing core or other circuit that uses at least one integrated circuit 1220. The integrated circuit 1220 utilizes standard cells 1222 (or cell 1222). Similar to the standard cell layouts 200-300 and 500-900 (in Figures 2-3 and 5-9), cell 1222 uses XFETs and / or TFETs to provide various types of functionality. Thus, one or more active layers of cell 1222 are formed across a single gate terminal of a single transistor, which provides electrical isolation between the two active layers without diffusion breaks between adjacent standard cells. The computing core is configured to execute instructions, including instructions retrieved from memory 1230. Cell 1222 includes at least one pair of adjacent standard cells without diffusion breaks between them. In some embodiments, these bit cells 1222 use circuitry of standard cell layouts 200-300 and 500-900 (Figures 2-3 and 5-9). In various embodiments, the processor 1210 includes circuitry consisting of one or more processor cores capable of general-purpose data processing and an associated cache memory subsystem. In such embodiments, the processor 1210 is a central processing unit (CPU). In another embodiment, the processing core includes circuitry of a highly parallel data microarchitecture having multiple parallel execution lanes and associated data storage buffers. In such embodiments, the processor 1210 is a graphics processing unit (GPU), a digital signal processor (DSP), etc.

[0055] In some embodiments, memory 1230 includes one or more of the following: a hard disk drive, a solid-state disk, other types of flash memory, a portable solid-state drive, and a tape drive. Memory 1230 stores an operating system (OS) 1232, one or more applications represented by code 1234, and at least source data 1236. Memory 1230 can also store intermediate and final result data generated by the processor 1210 when executing a particular application of code 1234. Although a single instance of the operating system 1232, code 1234, and source data 1236 is shown, in other embodiments, a different number of these software components are stored in memory 1230. The operating system 1232 includes instructions for starting the boot-up of the processor 1210, assigning tasks to hardware circuits (such as the processor 1210 including the integrated circuit 1220), managing resources of the computing system 1200, and hosting one or more virtual environments.

[0056] Each of the processor 1210 and memory 1230 includes interface circuits for communicating with each other and with any other hardware components included in the computing system 1200. The interface circuits include queues for handling memory requests and memory responses, and control circuits for communicating with each other based on a specific communication protocol. The communication protocol determines various parameters such as power performance status which determines the supply voltage level, operating supply voltage and operating clock frequency, data rate, and one or more burst modes.

[0057] Referring to Figure 13, this is a generalized diagram of Table 1300, which shows a reduction in the layout area of ​​multiple types of standard cells where there are no diffusion breaks between multiple types of standard cells. Table 1300 includes Table 1310 and Table 1320. Table 1310 shows a reduction in the layout area of ​​multiple types of standard cells using a single height with no diffusion breaks in between. By using a single height, these cells do not contain one or more instantiated copies of cells placed above or below another cell. Each of the upper or lower halves of layout 500 (in Figure 5) shows inverter cells with a single height.

[0058] While specific Boolean composite gate and flip-flop circuits are listed in Table 1310, other types of standard cells also provide a reduction in layout area to adjacent standard cells without a diffusion break in between, when these standard cells utilize XFETs or TFETs such as transistors 102 and 104 (in Figure 1).

[0059] Tables 1310 (and 1320) provide CPP counts for different types of standard cell layouts generated using different types of transistors. Layouts 500–900 (Figures 5–9) are characterized by the number of contacted gate pitches (CPPs). The acronym CPP is used because, since metallic gates can be formed using polysilicon, there will be several contacted polysilicon (poly) pitches, i.e., CPPs, in these layouts. However, metallic gates can now also be formed from a variety of other materials. Titanium nitride (TiN) is one example of a material used to form metallic gates in layouts 500–900. Other materials can be used to form metallic gates in layouts 500–900, but the acronym CPP is still used to indicate the number of contacted gate pitches. Table 1320 shows a reduction in the layout area of ​​multiple types of standard cells using double height with no diffusion breaks in between. By using double height, these cells contain one or more instantiated copies of cells placed above or below another cell. Layouts 600, 800, and 900 show standard cells with twice the height. Although not shown in Tables 1310 and 1320, layout 700 shows standard cells with three times the height.

[0060] It should be noted that one or more of the embodiments described above include software. In such embodiments, program instructions for implementing the method and / or mechanism are transported or stored on a computer-readable medium. Numerous types of media configured to store program instructions are available, including hard disks, floppy disks, CD-ROMs, DVDs, flash memory, programmable ROM (ROM, PROM), random access memory (RAM), and various other forms of volatile or non-volatile storage devices. Generally speaking, computer-accessible storage media include any storage media that is accessible by a computer during use to provide instructions and / or data to the computer. For example, computer-accessible storage media include magnetic or optical media such as disks (fixed or removable), tapes, CD-ROMs, DVD-ROMs, CD-Rs, CD-RWs, DVD-Rs, DVD-RWs, or Blu-Ray® discs. Examples of storage media include volatile or non-volatile memory media such as RAM (e.g., synchronous dynamic RAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, low power DDR (LPDDR2, etc.) SDRAM, Rambus DRAM (Rambus DRAM, RDRAM), static RAM (static RAM, SRAM), etc.), ROM, and flash memory, as well as non-volatile memory (e.g., flash memory) accessible via peripheral interfaces such as the Universal Serial Bus (USB) interface. Other examples of storage media include microelectromechanical systems (MEMS) and storage media accessible via communication media such as networks and / or wireless links.

[0061] Additionally, in various embodiments, program instructions include operational-level or register-transfer-level (RTL) descriptions of hardware functions in a high-level programming language such as C, or a design language (HDL) such as Verilog or VHDL, or a database format such as the GDSII stream format (GDSII). In some cases, the descriptions are read by a synthesis tool that synthesizes the descriptions to generate a netlist containing a list of gates from a synthesis library. The netlist contains a set of gates that also represent the functions of the hardware, including the system. The netlist is then arranged and routed to generate a dataset describing the geometric shapes applied to a mask. The mask can then be used in various semiconductor manufacturing processes to generate semiconductor circuits or circuits corresponding to the system. Alternatively, instructions on a computer-accessible storage medium may be a netlist (with or without a synthesis library) or a dataset, as needed. Additionally, instructions are used for emulation by hardware-based emulators from vendors such as Cadence®, EVE®, and Mentor Graphics®.

[0062] Although the embodiments described above are explained in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully understood. The following claims are intended to be construed as encompassing all such variations and modifications.

Claims

1. It is an integrated circuit, A plurality of standard cells, wherein one or more of the standard cells are equipped with a non-planar transistor, Each of the multiple metal gates in at least one adjacent pair of standard cells among the multiple standard cells is an active gate. Integrated circuit.

2. The standard cell of the pair of at least one adjacent standard cell has one or more active regions having a length equal to the distance between the source region and the drain region of a single transistor. The integrated circuit according to claim 1.

3. The standard cell of the aforementioned pair of at least one adjacent standard cell includes a source region or a drain region at one edge of the standard cell. The integrated circuit according to claim 2.

4. The standard cells of the at least one adjacent standard cell pair share the source region or the drain region at the edge. The integrated circuit according to claim 3.

5. The plurality of standard cells comprises a predetermined group of instantiated standard cells that form an L-shape, providing an on-die area available for another non-instantiated standard cell. The integrated circuit according to claim 2.

6. The non-planar transistor includes a pair of transistors having channels with opposite doping polarities, where only one of the corresponding transistor pairs is adjacent to the silicon substrate. The integrated circuit according to claim 2.

7. In response to the application of a potential to the input node of the integrated circuit, one or more of the standard cells transmit current from the input node to the output node of the integrated circuit. The integrated circuit according to claim 6.

8. It is a method, Forming a plurality of standard cells, each having one or more standard cells comprising a non-planar transistor, comprising: forming a first transistor in at least one integrated circuit of the one or more standard cells, wherein the first channel is oriented in a first direction; forming an oxide layer adjacent to the first transistor in the integrated circuit; and forming a second transistor in the integrated circuit, adjacent to the oxide layer, wherein the second transistor has a second channel oriented in a direction orthogonal to the first direction. The integrated circuit includes arranging the plurality of standard cells, Each of the multiple metal gates in at least one adjacent pair of standard cells among the multiple standard cells is an active gate. method.

9. The plurality of standard cells are formed such that the standard cells of at least one adjacent pair of standard cells have one or more active regions having a length equal to the distance between the source region and the drain region of a single transistor. The method of claim 8.

10. The plurality of standard cells are formed such that the standard cells of at least one adjacent pair of standard cells include a source region or a drain region at one edge of the standard cell. The method of claim 9.

11. The plurality of standard cells are formed such that the standard cells of at least one adjacent pair of standard cells share the source region or the drain region at the edge, The method of claim 10.

12. The process involves shaping a plurality of standard cells such that the plurality of standard cells comprise a predetermined group of instantiated standard cells that form an L-shape, providing an on-die area available to another non-instantiated standard cell. The method of claim 9.

13. The non-planar transistors include pairs of transistors having channels with opposite doping polarities, and the plurality of standard cells are formed such that only one transistor in the corresponding pair of transistors is adjacent to the silicon substrate. The method of claim 9.

14. In response to a potential being applied to the input node of the integrated circuit, one or more of the standard cells transmit current from the input node to the output node of the integrated circuit, The method of claim 13.

15. It is a processor, A memory configured to store instructions for one or more tasks and source data processed by the one or more tasks, A computing core circuit configured to execute instructions for one or more tasks using the source data, The computing core circuit includes an integrated circuit, The aforementioned integrated circuit is A plurality of standard cells, wherein one or more of the standard cells are equipped with a non-planar transistor, Each of the multiple metal gates in at least one adjacent pair of standard cells among the multiple standard cells is an active gate. Processor.

16. The standard cell of the pair of at least one adjacent standard cell has one or more active regions having a length equal to the distance between the source region and the drain region of a single transistor. The processor according to claim 15.

17. The standard cell of the aforementioned pair of at least one adjacent standard cell includes a source region or a drain region at one edge of the standard cell. The processor according to claim 16.

18. The standard cells of the at least one adjacent standard cell pair share the source region or the drain region at the edge. The processor according to claim 17.

19. The plurality of standard cells comprises a predetermined group of instantiated standard cells that form an L-shape, providing an on-die area available for another non-instantiated standard cell. The processor according to claim 16.

20. The non-planar transistor includes a pair of transistors having channels with opposite doping polarities, where only one of the corresponding transistor pairs is adjacent to the silicon substrate. The processor according to claim 16.

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