Integrated devices with conductive barrier structures

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The conductive barrier structure addresses substrate parasitic leakage and voltage issues by isolating devices with opposite polarity charge carriers, enhancing device performance and integration in IC dies.

JP2026520507APending Publication Date: 2026-06-23TEXAS INSTRUMENTS INC

Patent Information

Authority / Receiving Office: JP · JP
Patent Type: Applications
Current Assignee / Owner: TEXAS INSTRUMENTS INC
Filing Date: 2024-05-31
Publication Date: 2026-06-23

AI Technical Summary

Technical Problem

Substrate parasitic leakage and parasitic voltage are issues when devices are integrated within the same integrated circuit (IC) die, particularly in high-voltage applications, affecting the performance and integration of semiconductor devices.

Method used

Implementing a conductive barrier structure that isolates devices from substrate voltage by conducting charge carriers of opposite polarity, using materials like 2DHG and quantum wells, and incorporating techniques such as doping and hybrid drain/source contacts to introduce and bias charge carriers, thereby shielding devices from parasitic voltages.

Benefits of technology

The conductive barrier structure effectively isolates devices from substrate voltages, enabling faster switching and reducing leakage, allowing integration of multiple devices on the same IC die while maintaining robust functionality.

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Abstract

This specification generally relates to integrated devices having a conductive barrier structure. In one example, a semiconductor device (200) includes a substrate (202), a conductive barrier structure (206), a channel layer (208), a barrier layer (210), and a gate (222). The substrate is made of a first semiconductor material. The conductive barrier structure is located on the substrate. The channel layer is made of a second semiconductor material and is located on the conductive barrier structure. The barrier layer is located on the channel layer, and the channel layer is located between the barrier layer and the conductive barrier structure. The gate is located on the barrier layer opposite the channel layer.

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