A system and method for controlling the main electrode and edge ring using non-sinusoidal pulses to achieve process speed uniformity.

Abstract

A system for achieving process speed uniformity is described. The system includes a first power supply comprising a DC power source that generates a direct current (DC) voltage waveform, a capacitor coupled in parallel to the DC power supply, and multiple voltage sources coupled to the capacitor. The multiple voltage sources receive the DC voltage waveform to facilitate the generation of a first set of non-sinusoidal radio frequency (RF) pulses supplied to the main electrodes of the plasma chamber. The system includes a second power supply that facilitates the generation of a second set of non-sinusoidal RF pulses. The second set of non-sinusoidal RF pulses is supplied to the edge electrodes of the plasma chamber.

Description

Technical Field

[0001] This embodiment relates to a system and method for controlling a main electrode and an edge ring using non-sinusoidal radio frequency (RF) pulses to achieve process speed uniformity.

Background Art

[0002] The background description provided here is for the purpose of generally presenting the content of the present disclosure. Within the scope described in this background art section, research by the inventors named at the present time, as well as aspects of the description that cannot be separately regarded as prior art at the time of filing, whether explicitly or implicitly, are not recognized as prior art against the present disclosure.

[0003] Plasma tools are used to process substrates. The radio frequency (RF) generator of a plasma tool is connected to the matching network of the plasma tool. The matching network is connected to the chuck of the plasma chamber. The matching network includes a network of capacitors and inductors. The substrate is placed on the chuck within the plasma chamber. One or more gases are supplied to the plasma chamber. Also, an RF signal is generated by the RF generator. The network of capacitors and inductors receives the RF signal, matches the impedance between the output and input of the matching network, outputs another RF signal, and transmits that another RF signal to the plasma chamber for substrate processing. However, the substrate is not processed in a uniform and efficient manner.

Summary of the Invention

[0004] Embodiments of this disclosure provide systems, apparatus, methods, and computer programs for controlling main electrodes and edge rings using non-sinusoidal radio frequency (RF) pulses to achieve process speed uniformity. It should be understood that these embodiments can be implemented in various ways, for example, as processes, apparatus, systems, devices, or on computer-readable media. Several embodiments are described below.

[0005] In one embodiment, a non-sinusoidal shaping waveform (also referred to herein as a non-sinusoidal bias (NSB)) is described, in which the voltage changes rapidly at both the rising and falling edges to supply power to the bias electrode.

[0006] In one embodiment, a main power supply is described that provides NSB to a substrate such as a semiconductor wafer via a main electrode, and is coupled with a cooperative variable edge sheath (TES) power supply that provides NSB to the edge ring surrounding the main electrode. For example, the main power supply is a circuit housed in a first compartment, and the TES power supply is another circuit housed in another compartment, with a control connection between the main power supply and the TES power supply. In another example, an integrated single compartment includes a single integrated circuit having a first part as the main power supply and a second part as the TES power supply. Placing both the main power supply and the TES power supply in the same compartment and bringing the outputs close to the main electrode and edge ring reduces parasitic elements compared to a remote system with long cables. A remote system may distort the non-sinusoidal bias voltage waveform output from the main power supply and TES power supply further downstream.

[0007] In one embodiment, independent control of the NSB voltage level for the main power supply and the NSB voltage level for the TES power supply is provided. For example, the main electrode is provided with a main non-sinusoidal voltage waveform, and the edge electrode is provided with a TES non-sinusoidal voltage waveform. Ion flux control at the main electrode is achieved by controlling the voltage of the main non-sinusoidal voltage waveform, and ion flux control at the edge ring is achieved by controlling the voltage of the TES non-sinusoidal voltage waveform.

[0008] In one embodiment, ion flux compensation is provided for both the main power supply and the TES power supply. For example, the current level of the ion current compensator is controlled independently by separately controlling the slopes of both the main non-sinusoidal voltage waveform and the TES non-sinusoidal voltage waveform. Furthermore, as another example, ion flux compensation is achieved by controlling the phase relationship between the main non-sinusoidal voltage waveform and the TES non-sinusoidal voltage waveform.

[0009] In one embodiment, a coordinated multilevel voltage pulsation of the voltage levels of the main non-sinusoidal voltage waveform and the TES non-sinusoidal voltage waveform generated by the main power supply and the TES power supply is provided.

[0010] In one embodiment, a coplanar sheath of plasma is generated in the edge ring and the main electrode. The coplanar sheath has a predetermined sheath voltage. The edge ring is a consumable part and therefore wears down over time. By controlling the main non-sinusoidal voltage waveform, the TES non-sinusoidal voltage waveform, or both, the substrate can be processed uniformly regardless of the condition of the edge ring.

[0011] In one embodiment, a method for performing a single control for energy recovery and ion flux compensation is described. Energy stored in a plasma chamber, which is an example of a plasma load, can be recovered and shaped by an active discharge of the output. Energy discharge shaping can be performed by pulse width modulation of a switch. The method provides ion flux compensation, and different discharge shapes can be achieved by controlling the pulse width modulation. However, since the plasma load is an active load, voltage ripple can be generated by ion flux when energy is not being discharged. Voltage ripple can be reduced by using high-frequency pulse width modulation.

[0012] In one embodiment, energy recovery and ion flux compensation are controlled separately. For example, energy recovery is achieved using an energy recovery circuit, and ion flux compensation is achieved by generating a non-sinusoidal waveform using a high-voltage (HV) source.

[0013] In one embodiment, a system is provided having two HV DC sources in a voltage source system, including a first DC source and a second DC source. The first and second DC sources are connected to ground potential between them. The first DC source is for charging the capacitance of the plasma chamber for charging operations such as wafer charging, and the second DC source is implemented as a controllable DC current source, providing a negative linear charge and generating a ramp slope, such as a negative slope, at the output of the system. The slope of the non-sinusoidal voltage waveform generated at the output of the system can be controlled by controlling the DC current of the non-sinusoidal voltage waveform. Thus, active adjustment of the slope for different plasma densities is achieved. In addition, a zero-current switched energy converter is used with the system to recover radio frequency (RF) energy stored in the plasma chamber. Multiple switches are connected to a bus coupled to the system and zero-voltage switched. All of this results in excellent power delivery efficiency of over 85%, and large powers such as 30 kilowatts (kW) can be delivered to the plasma chamber.

[0014] In one embodiment, multiple combined HV sources are provided. When it is necessary to reduce the voltage at the input to the plasma load, the RF energy stored in the plasma chamber is discharged. Discharge is performed by an active magnetic energy recovery (MER) circuit, and a modified waveform HV output is obtained. The waveform shape can be modified by increasing or decreasing the output of the HV source combination over time. The RF energy stored in the plasma chamber is recovered by the discharge and supplied to the input of the mains power or TES power supply.

[0015] In one embodiment, multiple voltage sources are combined to generate a positive voltage pulse. Separate functions are also provided to enable energy recovery using a power converter. The power converter recovers RF energy from the plasma chamber and feeds this RF energy back into the NSB power supply input. A controllable current source allows control of the current drawn from the plasma chamber, compensating for wafer charging by the ion flux. By controlling the current drawn from the plasma chamber during the wafer charging phase, the wafer voltage is flattened and the ion energy distribution is narrowed.

[0016] In one embodiment, the main power supply unit and the TES unit are integrated into a single system. This integration allows for good coordination between the main unit and the TES unit, enabling the plasma sheath on the wafer and the plasma sheath on the edge ring to maintain a coordinated state. Without this coordination, the plasma sheath may oscillate radially at the wafer edge, and such oscillation may cause elliptical shapes in etched features as ions follow the electric field from the oscillation.

[0017] In one embodiment, a system for use with a plasma chamber is described. The plasma chamber has a substrate support and an edge ring surrounding the substrate support. The system includes a non-sinusoidal voltage waveform source, a first output of the non-sinusoidal voltage waveform source connected to the substrate support, and a second output of the non-sinusoidal voltage waveform source connected to the edge ring. The system includes a controller that controls the non-sinusoidal voltage waveform source to generate a first NSB waveform for the substrate support via the first output and a second NSB waveform for the edge ring via the second output. The first and second NSB waveforms provide a pulsed bias voltage to the plasma generated in the plasma chamber.

[0018] In one embodiment, a system is described. The system includes a first power supply and a second power supply. The first power supply includes a first DC power source that generates a first DC voltage waveform, a first capacitor coupled in parallel to the first DC power source, and a first plurality of voltage sources coupled to the first capacitor. The first plurality of voltage sources receive the first DC voltage waveform to facilitate the output of a first non-sinusoidal voltage waveform to the main electrodes of the plasma chamber. The second power supply includes a second DC power source configured to generate a second DC voltage waveform, a second capacitor coupled in parallel to the second DC power source, and a second plurality of voltage sources coupled to the second capacitor. The second plurality of voltage sources receive a second DC voltage waveform to facilitate the output of a second non-sinusoidal voltage waveform to the edge electrodes of the plasma chamber. The system includes a controller coupled to the first and second plurality of voltage sources that controls multiple amplitudes of the first and second non-sinusoidal voltage waveforms to achieve uniformity of process speed on the substrate.

[0019] In one embodiment, a method is described. The method includes generating a first DC voltage waveform with a first DC power source and receiving the first DC voltage waveform to facilitate the output of a first non-sinusoidal voltage waveform to the main electrode of a plasma chamber. The method includes generating a second DC voltage waveform with a second DC power source and receiving the second DC voltage waveform to facilitate the output of a second non-sinusoidal voltage waveform to the edge electrode of a plasma chamber. The method includes controlling multiple amplitudes of the first and second non-sinusoidal voltage waveforms to achieve uniformity of process speed on the substrate.

[0020] Other embodiments will become apparent from the following detailed description in conjunction with the attached drawings. [Brief explanation of the drawing]

[0021] The embodiments can be best understood by referring to the following description in conjunction with the attached drawings.

[0022] [Figure 1]FIG. 1 is a diagram of one embodiment of a system illustrating a method for supplying a non-sinusoidal radio frequency (RF) signal to a main electrode and an edge electrode of a plasma chamber.

[0023] [Figure 2] FIG. 2 is a diagram of one embodiment of a system illustrating the use of ion flux compensation associated with a main electrode and an edge electrode to control non-sinusoidal pulses of a non-sinusoidal voltage waveform supplied to the main electrode and the edge electrode.

[0024] [Figure 3] FIG. 3 is a diagram of one embodiment of a system illustrating the use of a single clock source to synchronize the operation of a main power supply and a variable edge sheath (TES) power supply.

[0025] [Figure 4] FIG. 4 is a diagram showing one embodiment of a graph illustrating that different plasma sheath voltages are generated by a main power supply and a TES power supply in a main region and an edge region of a plasma chamber, and the plasma sheath voltages are controlled to be substantially horizontal to achieve a flat sheath potential.

[0026] [Figure 5] FIG. 5 is a diagram showing one embodiment of a system illustrating details of a non-sinusoidal bias (NSB) source having a main power supply and a TES power supply.

[0027] [Figure 6] FIG. 6 is a diagram showing one embodiment of a system illustrating energy recovery by using a switch and a direct current (DC) voltage source.

[0028] [Figure 7] FIG. 7 is a diagram showing one embodiment of a system illustrating energy recovery by using a current source.

[0029] [Figure 8A]Figure 8A shows one embodiment of a system illustrating the use of a single control to achieve compensation for ion flux and energy recovery.

[0030] [Figure 8B] Figure 8B is a diagram illustrating one embodiment of the graph illustrating the operation of the system shown in Figure 8A.

[0031] [Figure 9A] Figure 9A shows one embodiment of a system illustrating the use of an energy recovery circuit to recover RF energy stored in the stray capacitance of a plasma chamber.

[0032] [Figure 9B] Figure 9B shows an example of the operation of the system in Figure 9A, along with another graph illustrating one embodiment.

[0033] [Figure 10] Figure 10 is a diagram illustrating one embodiment of a system that demonstrates the use of a voltage source system having a constant current source.

[0034] [Figure 11] Figure 11 is a diagram illustrating one embodiment of the system, illustrating the details of the system shown in Figure 10.

[0035] [Figure 12] Figure 12 shows one embodiment of a graph illustrating the voltage generated by an NSB source.

[0036] [Figure 13] Figure 13 shows one embodiment of a system illustrating the combination of a DC power supply, a high-voltage (HV) source, and the control of an energy recovery circuit to achieve a predetermined sheath potential.

[0037] [Figure 14] Figure 14 shows one embodiment of an integrated combination of HV sources. [Modes for carrying out the invention]

[0038] The following embodiments describe a system and method for controlling the main electrode and edge ring using non-sinusoidal radio frequency (RF) pulses to achieve process speed uniformity. It will be apparent that these embodiments can be implemented without some or all of these specific details. In other examples, well-known process behaviors are not described in detail so as not to unnecessarily obscure these embodiments.

[0039] Figure 1 is a diagram of one embodiment of system 100 illustrating a method for supplying non-sinusoidal voltage waveforms to main electrodes and edge electrodes. System 100 includes a plasma chamber 102 and a non-sinusoidal bias (NSB) source 104. The NSB source may also be referred to herein as a pulser or non-sinusoidal voltage source. An example of a pulser is a nanopulser that generates one or more nanopulse voltage waveforms, each nanopulse voltage waveform comprising a series of nanopulses. As an example, the pulser generates at least one non-sinusoidal voltage waveform, each non-sinusoidal voltage waveform having a frequency in the range of 400 kilohertz (kHz) to 1 megahertz (MHz). An example of a plasma chamber 102 is a capacitively coupled plasma (CCP) chamber. System 100 further includes a source power supply 106. An example of a source power supply 106 is a 2 MHz power supply, a 13.56 MHz power supply, a 60 MHz power supply, or a 400 kHz power supply.

[0040] The plasma chamber 102 includes a main electrode embedded in an electrostatic chuck (ESC) 108 and an edge ring 110, which is an example of an edge electrode. The edge ring 110 surrounds the ESC 108. For example, the edge ring 110 encircles the ESC 108.

[0041] The source power supply 106 is coupled to the upper electrode 112 of the plasma chamber 102. The NSB source 104 is coupled to the ESC 108 and the edge electrode 110.

[0042] The source power supply 106 generates an RF signal and supplies it to the upper electrode 112 of the plasma chamber 102. When one or more process gases are supplied to the plasma chamber 102 in combination with the RF signal supplied to the upper electrode 112, plasma is generated within the plasma chamber 102.

[0043] Furthermore, the NSB source 104 facilitates the output of multiple non-sinusoidal voltage waveforms, including the main non-sinusoidal voltage waveform 114 and the TES non-sinusoidal voltage waveform 116. For example, each non-sinusoidal voltage waveform 114 and 116 is a 400 kHz signal. The NSB source 104 facilitates the output of the main non-sinusoidal voltage waveform 114 to the ESC 108 and the output of the TES non-sinusoidal voltage waveform 116 to the edge electrode 110.

[0044] The main non-sinusoidal voltage waveform 114 is supplied to the main electrode, providing a pulsed bias voltage to the main electrode, and the TES non-sinusoidal voltage waveform 116 is supplied to the edge electrode 110, providing a pulsed bias voltage to the edge electrode 110. The pulsed bias voltage is provided to attract ions from the plasma generated by the RF signal supplied to the upper electrode 112. The ions are used to process a substrate S, such as a semiconductor wafer, placed on top of the ESC 108.

[0045] In one embodiment, the upper electrode 112 is coupled to the ground potential.

[0046] In one embodiment, the source power supply 106 is coupled to the main electrode, and the upper electrode 112 is coupled to the ground potential.

[0047] In one embodiment, an inductively coupled plasma (ICP) chamber is used instead of a CCP chamber. In the ICP chamber, one or more upper coils are used instead of upper electrodes 112 such as plate electrodes. One or more upper coils are an example of electrodes.

[0048] Figure 2 is a diagram of one embodiment of system 200 illustrating the use of ion flux compensation associated with the main electrode and edge electrode 110 to generate non-sinusoidal pulses of non-sinusoidal voltage waveforms 114 and 116 to be supplied to the main electrode 108 and edge electrode 110.

[0049] System 200 includes an NSB source 202, which is an example of an NSB source 104 (Figure 1). The NSB source 202 includes a splitter and a phase controller 204. The splitter and phase controller 204 control the phase relationship between non-sinusoidal voltage waveforms 114 and 116. For example, the splitter and phase controller 204 synchronizes the non-sinusoidal voltage waveforms 114 and 116 by controlling them so that they are in phase with each other or out of phase by a predetermined phase difference.

[0050] System 200 further includes a host computer 201. Examples of the host computer 201 include a desktop computer, a laptop computer, a smartphone, a tablet, or a controller. The host computer 201 includes a processor 203 and a memory device 205. Examples of processors, as used herein, include a central processing unit (CPU) and a microprocessor. Examples of memory devices include random access memory, read-only memory, and combinations thereof. Examples of controllers, as used herein, include a combination of one or more processors and another memory device. One or more processors are coupled to one or more memory devices. Processor 203 is coupled to an NSB source 202.

[0051] The processor 203 provides the main setpoint and the TES setpoint to the NSB source 202. An example of the main setpoint is the maximum amplitude of the voltage of the main non-sinusoidal voltage waveform 114. An example of the TES power setpoint is the maximum amplitude of the voltage of the TES non-sinusoidal voltage waveform 116.

[0052] Furthermore, the main ion flux control circuit 206 is coupled to the plasma chamber 102 and the processor 203 to control the main non-sinusoidal voltage waveform 114 and achieve a predetermined amount of compensation for the main ion flux. The main ion flux is the ion flux in the main region 208 above the main electrode 108 in the plasma chamber 102. For example, a main ion flux probe is placed in the main region 208, and the amount of main ion flux is detected by the main ion flux sensor. Based on the amount of main ion flux, the processor 203 controls the NSB source 202 to further control the main non-sinusoidal voltage waveform 114 and achieve a predetermined amount of compensation for the main ion flux. In another example, the main ion flux probe and main ion flux sensor are not used. Rather, during processing of the substrate S, the processor 203 controls the NSB source 202 to enhance the output of the main non-sinusoidal voltage waveform 114 and achieve a predetermined amount of compensation for the main ion flux. In this example, a predetermined amount of compensation for the main ion flux is determined experimentally or estimated by the processor 203 before processing the substrate S.

[0053] Similarly, the TES ion flux control circuit 210 is coupled to the plasma chamber 102 and the processor 203 to control the TES non-sinusoidal voltage waveform 116 to achieve a predetermined amount of compensation for the TES ion flux (ion flux in the edge region 112 above the edge ring 110 of the plasma chamber 102). For example, a TES ion flux probe is placed in the edge region 112, and the amount of TES ion flux is detected by a TES ion flux sensor. Based on the amount of TES ion flux, the processor 203 controls the NSB source 202 to further control the TES non-sinusoidal voltage waveform 116 to achieve a predetermined amount of compensation for the TES ion flux. In another example, the TES ion flux probe and TES ion flux sensor are not used. Rather, during processing of the substrate S, the processor 203 controls the NSB source 202 to enhance the output of the TES non-sinusoidal voltage waveform 116 to achieve a predetermined amount of compensation for the TES ion flux. In the example, a predetermined amount of compensation for the TES ion flux is determined experimentally or estimated by the processor 203 before processing the substrate S.

[0054] The main ion flux is the ion flux in the main region 208 (Figure 2) of the plasma chamber 102, and the TES ion flux is the ion flux in the edge region 212 of the plasma chamber 102. The edge region 212 surrounds the main region 208 and is closer to the edge of the substrate S compared to the main region 208. The main region 208 is closer to the central part of the substrate S compared to the edge region 212.

[0055] An example of an ion flux control circuit includes a combination of an ion flux probe and an ion flux sensor. For example, the ion flux probe is a Langmuir probe that interfaces with a Langmuir probe and generates a measured amount of current based on the measured amount of ion flux, and the ion flux sensor determines the measured amount of ion flux based on the measured amount of current, based on the correspondence between the amount of current and the amount of ion flux.

[0056] The processor 203 is coupled to the main ion flux control circuit 206 and the TES ion flux control circuit 210. The processor 203 receives the amount of main ion flux from the main ion flux control circuit 206 and the amount of TES ion flux from the TES ion flux control circuit 210, and controls the NSB source 202 to further control the amplitude (e.g., maximum amplitude) of the main non-sinusoidal voltage waveform 114 and the TES non-sinusoidal voltage waveform 116. For example, the processor 203 increases or decreases the amplitude of the main non-sinusoidal voltage waveform 114 or the amplitude of the TES non-sinusoidal voltage waveform 116 until the amount of TES ion flux is compensated to be within a predetermined range from the compensation for the amount of main ion flux (e.g., equal to the compensation for the amount of main ion flux). The predetermined range is stored in the memory device 205 for access by the processor 203.

[0057] When the amount of TES ion flux is compensated to a predetermined range from the amount of main ion flux, plasma sheath uniformity is achieved between portion 207 and portion 209 of the lower plasma sheath. Portion 207 is adjacent to the main region 208, for example, adjacent to or continuous with the main region 208, and is located between the main region 208 and the ESC 108. Portion 209 is adjacent to the edge region 212, for example, adjacent to or continuous with the edge region 212, and is located between the edge region 212 and the edge ring 209. Once plasma sheath uniformity is achieved, process rate uniformity is achieved, such as uniformity of etching rate, uniformity of deposition rate, or a combination thereof, for processing the substrate S.

[0058] In one embodiment, the main ion flux control circuit 206 also provides energy recovery, which will be described later. Similarly, the TES ion flux control circuit 210 also provides energy recovery, which will be described later.

[0059] In one embodiment, the NSB source 202 includes a single direct current (DC) source that generates a DC voltage waveform. As used herein, an example of a DC source is a DC voltage source or a DC power source. The DC voltage waveform generated by the DC source is split into two DC voltage waveforms by a splitter in the NSB source 202, each of which is supplied to each of the two sets of high voltage (HV) sources in the NSB source 202. Of the two sets of HV sources, the first HV source enhances the output of the main non-sinusoidal voltage waveform 114, and the second HV source enhances the output of the TES non-sinusoidal voltage waveform 116. As an example, each HV source described herein converts the voltage amplitude of the DC voltage waveform received from the splitter to the amplitude of another voltage, outputting a modified DC voltage waveform. For example, the HV source converts the amplitude of the first voltage to the amplitude of the second voltage, which is either greater than or less than the first amplitude. The modified DC voltage waveform is transmitted through a resonant inductor to generate a non-sinusoidal voltage waveform such as the main non-sinusoidal voltage waveform 114 or the TES non-sinusoidal voltage waveform 116.

[0060] In one embodiment, an application-specific integrated circuit (ASIC) or a programmable logic device (PLD) is used to perform the same operations as those described herein as being performed by a processor.

[0061] In one embodiment, the splitter and phase controller 204 are part of the host computer 201.

[0062] In one embodiment, the terms power source and voltage source are used interchangeably herein.

[0063] In one embodiment, the terms power supply and voltage source are used interchangeably herein.

[0064] Figure 3 is a diagram of one embodiment of system 300 illustrating a single clock source 302 in an NSB source 304 for synchronizing the operation of the mains power supply and variable edge sheath (TES) power supply. NSB source 304 is an example of NSB source 104 or 202 (Figures 1 & 2). NSB source 304 includes a signal controller 305, a mains power supply 306, and a TES power supply 308. The clock source 302 and signal controller 305 are components of the splitter and phase controller 204. The signal controller 305 is coupled to processor 203 (Figure 2) and receives mains setpoints and TES setpoints from processor 203.

[0065] The main power supply 306 is coupled to the main electrode of the plasma chamber 102 via output O1 and RF connection 314. An example of output O1 is the connector of the NSB source 304. RF connection 314 is coupled to output O1 and the main electrode. The TES power supply 308 is coupled to the edge ring 110 of the plasma chamber 102 via output O2 and RF connection 316. An example of output O2 is the connector of the NSB source 304. RF connection 316 is coupled to output O2 and the edge ring 110. An example of an RF connection is one or more RF straps coupled to each other in series.

[0066] The clock source 302 generates a clock signal and supplies it to the signal controller 305, synchronizing the operation of the main power supply 306 and the TES power supply 308. For example, in synchronization with the clock signal, the signal controller 305 outputs a main control signal and transmits it to the main power supply 306, and the signal controller 305 outputs a TES control signal and transmits it to the TES power supply 308. For example, when the clock signal transitions from a low logic level to a high logic level in a first time period, the signal controller 305 outputs the main control signal and the TES control signal. In this example, when the clock signal transitions from a low logic level to a high logic level in a second time period, the signal controller 305 again outputs the main control signal and the TES control signal. The second time period is continuous with the first time period in that there is no transition from a low logic level to a high logic level between the first and second time periods. As an example, the main control signal represents the phase or voltage amplitude (e.g., maximum amplitude) of the main non-sinusoidal voltage waveform 114, or a combination thereof. As an example, the TES control signal indicates the phase or voltage amplitude (e.g., maximum amplitude) of the TES non-sinusoidal voltage waveform 116, or a combination thereof.

[0067] The main power supply 306 boosts the output of the main non-sinusoidal voltage waveform 114 based on the main control signal, and the TES power supply 308 boosts the output of the TES non-sinusoidal voltage waveform 116 based on the TES control signal. For example, the main power supply 306 boosts the output of the main non-sinusoidal voltage waveform 114 when the main control signal is received, and the TES power supply 308 boosts the output of the TES non-sinusoidal voltage waveform 160 when the TES control signal is received. The main non-sinusoidal voltage waveform 114 is generated to achieve the maximum amplitude of the voltage indicated in the main control signal, and the TES non-sinusoidal voltage waveform 116 is generated to achieve the maximum amplitude of the voltage indicated in the TES control signal.

[0068] When both the main non-sinusoidal voltage waveform 114 and the TES non-sinusoidal voltage waveform 116 are synchronized with the clock signal, the phases of the main non-sinusoidal voltage waveform 114 and the TES non-sinusoidal voltage waveform 116 are controlled to fall within a predetermined range relative to each other. For example, the phases of both the main non-sinusoidal voltage waveform 114 and the TES non-sinusoidal voltage waveform 116 are equal to each other. When the phases of the main non-sinusoidal voltage waveform 114 and the TES non-sinusoidal voltage waveform 116 are controlled to fall within a predetermined range, uniformity of process speed is achieved between the main region 208 (Figure 2) and the edge region 212 (Figure 2).

[0069] In one embodiment, instead of an ion flux sensor and ion flux probe, a voltage sensor is used to measure ion flux. For example, a main voltage sensor 310 is coupled to point 318 on an RF connection 314 and to a processor 203 (Figure 2) of a host computer 201. Similarly, a TES voltage sensor 312 is coupled to point 320 on an RF connection 316 and to a processor 203. The main voltage sensor 310 measures the voltage at point 318 to generate a main measurement signal and provides this signal to the processor 203. The main measurement signal represents the ion flux in the main region 208 (Figure 2). For example, the main measurement signal includes main V&I measurements such as main voltage amplitude and main current amplitude, as well as the phase between the main voltage amplitude and the main current amplitude. The TES voltage sensor 312 measures the voltage at point 320 to generate a TES measurement signal and provides this signal to the processor 203. The TES measurement signal represents the ion flux in the edge region 212 (Figure 2). For example, the TES measurement signal includes TES V&I measurements such as TES voltage amplitude and TES current amplitude, as well as the phase between the TES voltage amplitude and the TES current amplitude.

[0070] In the embodiment, the processor 203 receives the main measurement signal and the TES measurement signal and determines the main ion flux corresponding to the main measurement signal and the TES ion flux corresponding to the TES measurement signal. For example, the processor 203 accesses a table stored in the memory device 205 (Figure 2) that contains the correspondence between the amount of ion flux and the V&I measurement value to determine the main ion flux and the TES ion flux. For example, one of the V&I measurement values ​​stored in the memory device 205 matches the main V&I measurement value and has a one-to-one correspondence with one of the ion flux values. The processor 203 determines that one of the ion flux values ​​is the main ion flux. As another example, one of the V&I measurement values ​​stored in the memory device 205 matches the TES V&I measurement value and has a one-to-one correspondence with one of the ion flux values. The processor 203 determines that one of the ion flux values ​​is the TES ion flux.

[0071] In further embodiments, the processor 203 controls the main power supply 306 or the TES power supply 308, or both power supplies 306 and 308, until the amount of main ion flux determined from the main measurement signal is compensated to fall within a predetermined range (e.g., equal to the compensation for the amount of TES ion flux) from the compensation for the amount of TES ion flux determined from the TES measurement signal. For example, the processor 203 modifies (e.g., increases or decreases) the maximum amplitude of the main non-sinusoidal voltage waveform 114 from the main setpoint to generate a modified main setpoint and transmits the modified main setpoint to the signal controller 305. Upon receiving the modified main setpoint, the signal controller 305 controls the main power supply 306 to modify the maximum amplitude of the voltage of the main non-sinusoidal voltage waveform 114. In another example, the processor 203 modifies (e.g., increases or decreases) the maximum amplitude of the TES non-sinusoidal voltage waveform 116 from the TES setpoint to generate a modified TES setpoint and transmits the modified TES setpoint to the signal controller 305. Upon receiving the corrected TES setpoint, the signal controller 305 controls the TES power supply 308 to correct the maximum amplitude of the TES non-sinusoidal voltage waveform 116.

[0072] Figure 4 is an embodiment of Graph 400 illustrating that different plasma sheath voltages in the main region 208 and the edge region (Figure 2) are generated by non-sinusoidal voltage waveforms 114 and 116 produced by the main power supply 306 and the TES power supply 308 (Figure 3), and that the plasma sheath voltages are controlled separately to achieve process speed uniformity. Graph 400 plots voltage on the y-axis and time t on the x-axis. Time t includes consecutive times t0, t1, t2, t3, and t4. For example, time t1 occurs after time t0, time t2 occurs after time t1, time t3 occurs after time t2, and time t4 occurs after time t3.

[0073] Graph 400 includes voltage waveform 402 and another voltage waveform 404. For example, voltage waveform 402 is an example of the main non-sinusoidal voltage waveform 114 (Figure 1), and voltage waveform 404 is an example of the TES non-sinusoidal voltage waveform 116 (Figure 1). As another example, voltage waveform 402 represents the voltage of the plasma sheath in the main region 208, and voltage waveform 404 represents the voltage of the plasma sheath in the edge region 212.

[0074] The voltage waveform 402 has multiple pulses 402A and 402B. For example, pulse 402A occurs from time t1 to time t2, transitioning from a low voltage level (e.g., V1a) to a high voltage level (e.g., V2a), and then further transitioning from the high voltage level to a low voltage level. As another example, pulse 402B occurs from time t3 to time t4, transitioning from a low voltage level (e.g., V1a) to a high voltage level (e.g., V2a), and then further transitioning from the high voltage level to a low voltage level. For example, the high voltage level V2a contains a voltage amplitude that is mutually exclusive with the voltage amplitude of the low voltage level V1a, and the high voltage level V2a is greater than the low voltage level V1a. As yet another example, the high voltage level V2a is an example of the maximum voltage amplitude of the voltage waveform 402.

[0075] Similarly, the voltage waveform 404 has multiple pulses 404A and 404B. For example, pulse 404A occurs from time t1 to time t2, transitioning from a low voltage level (e.g., V1b) to a high voltage level (e.g., V2b), and then further transitioning from the high voltage level to a low voltage level. As another example, pulse 404B occurs from time t3 to time t4, transitioning from a low voltage level (e.g., V1b) to a high voltage level (e.g., V2b), and then further transitioning from the high voltage level to a low voltage level. Exemplarily, the high voltage level V2b contains a voltage amplitude that is mutually exclusive with the voltage amplitude of the low voltage level V1b, and the high voltage level V2b is greater than the low voltage level V1b. Exemplarily, the high voltage level V2b is an example of the maximum voltage amplitude of the voltage waveform 404.

[0076] Each pulse of voltage waveform 402 or 404 occurs during one cycle of the clock signal. For example, pulse 402A occurs during the first cycle of the clock signal, and pulse 402B occurs during the second cycle of the clock signal. The second cycle is continuous with the first cycle.

[0077] Processor 203 (Figure 2) controls parameters such as the ramp slope, maximum amplitude, or combination thereof of non-sinusoidal voltage waveforms 114 or 116, or controls parameters of both non-sinusoidal voltage waveforms 114 and 116 to control voltage waveforms 402 and 404. For example, the positive slope of voltage waveform 402 between time t2 and time t3 is reduced to match the substantially zero slope (e.g., zero slope) of voltage waveform 404 between time t2 and t3. As another example, the positive slopes of voltage waveforms 402 and 404 are reduced between time t2 and t3 to achieve substantially zero slope (e.g., zero slope) and achieve process speed uniformity. By controlling the parameters, ion flux uniformity between the main region 208 and the edge region 212 is achieved. Once ion flux uniformity is achieved, the slope between portions 207 and 209 (Figure 2) of the lower plasma sheath is reduced. As yet another example, the parameters of non-sinusoidal voltage waveforms 114 or 116, or the parameters of non-sinusoidal voltage waveforms 114 and 116, are controlled to achieve a positive slope for voltage waveform 402 between times t2 and t3, and a substantially zero slope for voltage waveform 404 between times t2 and t3.

[0078] Figure 5 shows an embodiment of system 500 illustrating the details of a non-sinusoidal bias (NSB) source 502 having a mains power supply and a TES power supply. The NSB source 502 is an example of an NSB source 104 (Figure 1), 202 (Figure 2), or 304 (Figure 3). The NSB source 502 includes a mains power supply 504 and a TES power supply 506. The mains power supply 504 is an example of a mains power supply 306 (Figure 3), and the TES power supply 506 is an example of a TES power supply 308 (Figure 3). The NSB source 502 also includes a clock source 302 and a splitter and phase controller 204.

[0079] The main power supply 504 includes a main DC source 508, a main capacitor 510 in parallel with the main DC source 508, and a main combination 512 of an HV source in parallel with the main DC source 508 and the main capacitor 510. For example, each of the main DC source 508, the main capacitor 510, and the main combination 512 is coupled in parallel between points 507 and 511. For example, the voltages across each of the main DC source 508, the main capacitor 510, and the main combination 512 are equal. Similarly, the TES power supply 506 includes a TES DC source 514, a TES capacitor 516 in parallel with the TES DC source 514, and a TES combination 518 of an HV source in parallel with the TES DC source 514 and the TES capacitor 516. For example, each of the TES DC source 514, the TES capacitor 516, and the TES combination 518 is coupled in parallel between points 509 and 513. For example, the voltages across the TES DC source 514, the TES capacitor 516, and the TES combination 518 are equal. As an example, the DC sources described herein are voltage sources or power sources.

[0080] The splitter and phase controller 204 are coupled to the main combination 512 and the TES combination 518. The main combination 504 is coupled to the main electrode of the ESC 108 via RF connection 314, and the TES combination 518 is coupled to the edge ring 110 via RF connection 316.

[0081] The system 500 also includes a main energy recovery circuit 520 and a TES energy recovery circuit 522. The main energy recovery circuit 520 is coupled to point 503 on RF connection 314, and the TES energy recovery circuit 522 is coupled to point 505 on RF connection 316. The main energy recovery circuit 520 is also coupled to the main capacitor 510 at point 507, and the TES energy recovery circuit 522 is coupled to the TES capacitor 516 at point 509.

[0082] The main DC source 508 generates a main DC voltage waveform 501 and supplies it to the main combination 512. The main combination 512 propels the output of a main non-sinusoidal voltage waveform 114 based on the voltage of the main DC voltage waveform 501, and the main non-sinusoidal voltage waveform 114 is supplied for resonant charging of the main region 208 to the main electrodes of the ESC 108. For example, the signal controller 305 (Figure 3) of the splitter and phase controller 204 provides the main control signal to the main combination 512. In the example, upon receiving the main control signal, one or more of the HV sources of the main combination 512 are activated, e.g., enabled or deactivated, e.g., disabled to modify the voltage of the main DC voltage waveform 501 and further modify the voltage of the main non-sinusoidal voltage waveform 114 to achieve the maximum amplitude indicated by the main control signal. In the example, the voltage of the main DC voltage waveform 501 is modified, and the main combination 512 outputs the modified main DC voltage waveform 517. The modified main DC voltage waveform 517 is converted to a main non-sinusoidal voltage waveform 114 by the main diode and main resonant inductor. The main diode and main resonant inductor are coupled between the main combination 512 and the main electrode. One end of the main diode is connected to the main combination 512, and the other end is coupled to the main resonant inductor via a main switch. The main resonant inductor is coupled to the main electrode via a main blocking capacitor.

[0083] To illustrate further, of the total 10 HV sources in the main combination 512, two HV sources are controlled by the signal controller 305 and coupled to the main DC source 508 and RF connection 314, while the remaining eight HV sources are controlled by the splitter and phase controller 204 and isolated from either the main DC source 508 or the RF connection 314, or both. The voltage of the main DC voltage waveform 501 and the voltage of the main non-sinusoidal voltage waveform 114 increase with increasing numbers of HV sources in the main combination 512 coupled to the main DC source 508 and RF connection 314. Conversely, the voltage of the main DC voltage waveform 501 and the voltage of the main non-sinusoidal voltage waveform 114 decrease with decreasing numbers of HV sources in the main combination 512 coupled to the main DC source 508 and RF connection 314. In the example, one or more HV sources of the main combination 512 are activated or deactivated to modify the voltage of the main DC voltage waveform 501 and output the voltage of the main non-sinusoidal voltage waveform 114.

[0084] The TES DC source 514 generates a TES DC voltage waveform 515 and supplies the TES DC voltage waveform 515 to the TES combination 518. The TES combination 518 promotes the output of a TES non-sinusoidal voltage waveform 116 based on the TES DC voltage waveform 515, and the TES non-sinusoidal voltage waveform 116 is supplied for resonant charging of the edge region 212 to the edge ring 110. As an example, the signal controller 305 provides a TES control signal to the TES combination 518. In the example, upon receiving the TES control signal, one or more of the HV sources of the TES combination 518 are activated, e.g., enabled or deactivated, e.g., disabled to modify the voltages of the TES DC voltage waveform 515 and the TES non-sinusoidal voltage waveform 116 to achieve the maximum amplitude indicated by the TES control signal. In the example, the voltage of the TES DC voltage waveform 515 is modified, and the modified TES DC voltage waveform 519 is output from the TES combination 518. The modified TES DC voltage waveform 519 is converted to a TES non-sinusoidal voltage waveform 116 by a TES diode and a TES resonant inductor. The TES diode and TES resonant inductor are coupled between a TES combination 518 and an edge ring 110. One end of the TES diode is connected to the TES combination 518, and the other end is coupled to the TES resonant inductor via a TES switch. The TES resonant inductor is coupled to the edge ring 110 via a TES blocking capacitor.

[0085] To illustrate further, of the 15 HV sources in the TES combination 518, 10 HV sources are controlled by the signal controller 305 and coupled to the TES DC source 514 and RF connection 316, while the remaining 5 HV sources are controlled by the splitter and phase controller 204 and isolated from either the TES DC source 514 or the RF connection 316, or both. The voltage of the TES DC voltage waveform 515 and the voltage of the TES non-sinusoidal voltage waveform 116 increase with increasing number of HV sources in the TES combination 512 coupled to the TES DC source 514 and RF connection 316. On the other hand, the voltage of the TES DC voltage waveform 515 and the voltage of the TES non-sinusoidal voltage waveform 116 decrease with decreasing number of HV sources in the TES combination 518 coupled to the TES DC source 514 and RF connection 316. In the example, one or more HV sources of the TES combination 518 are activated or deactivated to modify the voltage of the TES DC voltage waveform 515 and output the voltage of the TES non-sinusoidal voltage waveform 116.

[0086] The main combination 512 generates a modified main DC voltage waveform 517 to enhance the output of the main non-sinusoidal voltage waveform 114, which is supplied to the main electrode. For example, one or more resonant inductors (e.g., one or more inductors, parasitic inductances, or stray inductances) coupling the main combination 512 to the main electrode provides resonant charging from the main combination 512 to the main electrode. For example, there is no cable such as a long cable coupling the main combination 512 to the main electrode. Also, the TES combination 518 generates a modified TES DC voltage waveform 519 to enhance the output of the TES non-sinusoidal voltage waveform 116, which is supplied to the edge ring 110. For example, one or more resonant inductors (e.g., one or more inductors, parasitic inductances, or stray inductances) coupling the TES combination 518 to the edge ring 110 provides resonant charging from the TES combination 518 to the edge ring 110. For example, there are no cables such as long cables connecting the TES combination 518 to the edge ring 110.

[0087] The main energy recovery circuit 520 recovers main RF energy from the main region 208 and stores the main RF energy in the capacitor 510. The main RF energy is then used by the main power supply 504 from the capacitor 510 to generate the voltage of the main DC voltage waveform 501, which further outputs the voltage of the main non-sinusoidal voltage waveform 114. For example, as the voltage across capacitor 510 increases, the voltage across the main DC source 508 also increases. In this example, the voltage across capacitor 510 increases due to the recovered RF energy. Furthermore, in this example, the processor 203 (Figure 2) controls (e.g., enables or disables) one or more of the HV sources of the main combination 512 to modify the voltage of the main DC voltage waveform 501, and further modifies the voltage of the modified main DC voltage waveform 517 output from the main combination 512 to modify the voltage of the main non-sinusoidal voltage waveform 114.

[0088] Similarly, the TES energy recovery circuit 522 recovers TES RF energy from the edge region 212 and stores the TES RF energy in the capacitor 516. The TES RF energy is then used by the TES power supply 506 from the capacitor 516 to generate the voltage of the TES DC voltage waveform 515, which further outputs the voltage of the TES non-sinusoidal voltage waveform 116. For example, as the voltage across capacitor 516 increases, the voltage across the TES DC source 514 also increases. In this example, the voltage across capacitor 516 is increased by the RF energy recovered from the edge region 212. Furthermore, in this example, the processor 203 (Figure 2) controls (e.g., enables or disables) one or more of the HV sources of the TES combination 518 to modify the voltage of the TES DC voltage waveform 515, and further modifies the voltage of the modified TES DC voltage waveform 519 output from the TES combination 518 to change the voltage of the TES non-sinusoidal voltage waveform 116.

[0089] Figure 6 shows one embodiment of system 600 illustrating energy recovery using switch 602 and a DC voltage source Vdc (indicated as energy recovery circuit 604). Energy recovery circuit 604 is an example of energy recovery circuit 520 or 522 (Figure 5). An example of a switch described herein includes one or more transistors. For example, a switch includes a single transistor or multiple transistors coupled in series with each other. Capacitor 606 in system 600 represents the capacitance of the plasma chamber 102. Switch 602 is controlled by processor 203 (Figure 2) to discharge capacitor 606 and store the RF energy recovered from capacitor 706 in energy recovery circuit 604.

[0090] In one embodiment, the diode is coupled in series with the switch 602 and the energy recovery circuit 604. For example, the diode is coupled between the switch 602 and the energy recovery circuit 604.

[0091] Figure 7 shows one embodiment of system 700 illustrating energy recovery using a current source 702. The current source 702 is controlled by processor 203 (Figure 2) and discharges RF energy from capacitor 606, transmitting the recovered RF energy to capacitor 510 or 516 (Figure 5).

[0092] Figure 8A shows one embodiment of system 800 illustrating the use of a single control for ion flux compensation and energy recovery to achieve process speed uniformity. System 800 includes an energy recovery circuit 802 and a nonlinear load 801. The nonlinear load 801 is an example of a plasma chamber 102 (Figure 1), such as a triode model. The nonlinear load 801 includes current sources I1 and I2 that illustrate the ion flux of the plasma in the plasma chamber 102.

[0093] Energy recovery circuit 802 is an example of a main energy recovery circuit 520 (Figure 5) or a TES energy recovery circuit 522 (Figure 5). Energy recovery circuit 802 includes a switch 808 and a voltage source 810. An example of a voltage source 810 is a main capacitor 510 or a TES capacitor 516 (Figure 5). For example, voltage source 810 represents a voltage across main DC source 508 (Figure 5), which is the same voltage as across main capacitor 510. Another example is voltage source 810 representing a voltage across TES DC source 514 (Figure 5), which is the same voltage as across TES capacitor 516. System 800 further includes an HV source combination 804. HV source combination 804 is an example of a main combination 512 or a TES combination 518 (Figure 5).

[0094] System 800 includes an RF connection 816 between combination 804 and a nonlinear load 801. Combination 804 is coupled to the nonlinear load 801 via RF connection 816, which includes a diode 805 and an inductor 807. RF connection 816 is an example of either RF connection 314 or 316 (Figure 3).

[0095] The energy recovery circuit 802 includes a transformer 822 which includes a first inductor 824, such as a coil, and a second inductor 826, also such as a coil. The energy recovery circuit 802 includes a voltage source 810 connected to the second inductor 826. The energy recovery circuit 802 is coupled to point 818 on the RF connection 816. For example, the first inductor 824 is coupled to point 818. A switch 808 is coupled to the processor 203 (Figure 2).

[0096] The processor 203 (Figure 2) charges the nonlinear load 801, and after the nonlinear load 801 is charged, the processor 203 controls the switch 808 to recover RF energy from the nonlinear load 801. In order to charge the nonlinear load 801, the processor 203 also controls the switch 808 to the off state, for example, the open state. For example, the processor 203 sends an off control signal to the switch 808 to turn the switch 808 off. In order to charge the nonlinear load 801, the processor 203 provides a setpoint, such as a main setpoint or a TES setpoint, to the combination 804. Upon receiving the setpoint, the combination 804 outputs a DC voltage waveform 806 and transmits the DC voltage waveform 806 to a circuit having a diode 805 and an inductor 807. Upon receiving the DC voltage waveform 806, the diode 805 and inductor 809 output a nonsinusoidal voltage waveform 809 and provide the nonsinusoidal voltage waveform 809 to the nonlinear load 801 via the RF connection 816. The non-sinusoidal signal voltage waveform 809 is an example of the main non-sinusoidal voltage waveform 114 (Figure 1) or the TES non-sinusoidal voltage waveform 116 (Figure 1).

[0097] When switch 808 is controlled to turn off by processor 203 (Figure 1) while the nonlinear load 801 is charging, the ion flux of the plasma formed within the nonlinear load 801 charges one or more capacitors of the nonlinear load 801 (e.g., capacitor 812, capacitor 814, or a combination thereof) with RF energy. The charging of one or more capacitors of the nonlinear load 801 increases the voltage across the nonlinear load 801.

[0098] After one or more capacitors of the nonlinear load 801 are charged, switch 808 is controlled by processor 203 to be turned on, for example, to a closed state. For example, processor 203 sends an on control signal to switch 808, turning switch 808 on. When switch 808 is turned on after the nonlinear load 801 has been charged, one or more capacitors of the nonlinear load 801 are discharged, and the RF energy stored in one or more capacitors is recovered and stored in the voltage source 810 of the energy recovery circuit 802. For example, while switch 808 is on, RF energy is stored in the first inductor 824 in the form of electromagnetic energy, and RF energy is recovered. During the period when RF energy is recovered, processor 203 controls switch 808 to be turned off, for example, to an open state after it has been turned on. While switch 808 is off, the electromagnetic energy stored in the first inductor 824 is transmitted from the first inductor 824 through the second inductor 826 to the voltage source 810 and stored in the form of RF energy. The RF energy recovered in this way is then supplied from the voltage source 810 to the combination 804, where the voltage of the output of the non-sinusoidal voltage waveform 809 is modified based on the DC voltage waveform 806.

[0099] Furthermore, when the processor 203 controls the on / off state of switch 808 and changes the duty cycle of switch 808's operation, the shape of the negative transition 803 (see Figure 8B) of the non-sinusoidal voltage waveform 809 is controlled, and ion flux compensation is achieved. For example, when switch 808 is turned on, the negative transition 803 of the non-sinusoidal voltage waveform 809 has a negative slope, and the amount of time interval until the negative transition 803 is achieved is shortened. On the other hand, in the example, when switch 808 is turned off, the negative transition 803 of the non-sinusoidal voltage waveform 809 has a positive slope, and the amount of time interval until the negative transition 803 is achieved is lengthened. Thus, the time taken to achieve the negative transition 803 and the statistical slope (e.g., average slope) of the negative transition 803 are increased or decreased by controlling the number of times switch 808 is turned on and off during the negative transition 803. In the example, the negative transition 803 occurs from the point when the non-sinusoidal voltage waveform 809 has its maximum amplitude until the point when the non-sinusoidal voltage waveform 809 has its minimum amplitude. An example of the duty cycle of switch 808 operation is the period during which switch 808 is ON, as a percentage of the total period during which switch 808 is ON and OFF during each cycle of the clock signal.

[0100] The duty cycle of switch 808 is controlled to achieve pulse width modulation. Therefore, energy recovery and ion flux compensation are performed simultaneously by controlling switch 808. For example, the negative transition 803 includes the time interval for RF energy recovery and the time interval for generating the ramp slope of the non-sinusoidal voltage waveform 809. Switch 808 performs energy recovery and ion flux compensation with a single control. Ion flux compensation is performed to achieve a predetermined sheath voltage in the lower plasma sheath, further achieving process speed uniformity.

[0101] Figure 8B is an embodiment of graphs 850 and 852 illustrating the operation of system 800 in Figure 8A. Graph 850 plots the non-sinusoidal voltage waveform 809 (Figure 8A) output from combination 804 (Figure 8A) on the y-axis and time t on the x-axis. By using processor 203 and energy recovery circuit 802, a negative transition 803 occurs between the time of maximum amplitude of the non-sinusoidal voltage waveform 809 and the time of minimum amplitude of the non-sinusoidal voltage waveform 809. The negative transition 803 corrects the lower plasma sheath to a coplanar sheath formed within the plasma chamber 102 (Figure 1). The negative transition 803 occurs during the discharge phase, and a substantially flat slope with a positive gradient and maximum amplitude occurs during the charge phase. During the charging phase, the capacitor formed by the ESC108 and the substrate S, or the capacitor formed between the edge ring 110 (Figure 1) and the portion 209 of the lower plasma sheath (Figure 2), is charged by the non-sinusoidal voltage waveform 809, and during the discharging phase, the capacitor is discharged to achieve RF energy recovery.

[0102] Furthermore, by using the processor 203 and the energy recovery circuit 802, negative transitions 803 are corrected and process speed uniformity is achieved. For example, during the discharge phase, the processor 203 controls the duty cycle of switch 808 until the amount of TES ion flux is compensated within a predetermined range from the compensation for the amount of main ion flux. For example, the processor 203 controls switch 808 to be turned on in a first time and off in a second time to achieve the first duty cycle of switch 808. Switch 808 is turned off in a second time immediately following the on state to achieve a first time interval between on and off. In this example, the processor 203 determines whether the amount of TES ion flux is compensated within a predetermined range from the compensation for the amount of main ion flux. Further in this example, if it is determined that the amount of TES ion flux is compensated outside the predetermined range from the compensation for the amount of main ion flux, the processor 203 corrects the first duty cycle. Continuing this example, to achieve the second duty cycle of switch 808, processor 203 controls switch 808 to be turned on in the third time and off in the fourth time. Switch 808 is turned off in the fourth time, consecutive to when it was turned on, achieving a second time interval between on and off. The second time interval is different from the first time interval, for example, greater or less than the first time interval. In this way, processor 203 continues to modify the duty cycle of switch 808's operation until it is determined that the amount of TES ion flux is compensated within a predetermined range from the compensation of the amount of main ion flux. Once the amount of TES ion flux is compensated within a predetermined range from the compensation of the amount of main ion flux, uniformity of process speed between the main region 208 and the edge region 212 (Figure 2) is achieved. Graph 852 plots the logical state, such as the ON or OFF state of switch 808 (Figure 8A), on the y-axis and time t on the x-axis. The x-axis of graph 850 is the same as the x-axis of graph 852.

[0103] Figure 9A shows an embodiment of system 900 illustrating the use of an energy recovery circuit 902 for recovering energy from a plasma chamber 102 (Figure 1). An example of the energy recovery circuit 902 is energy recovery circuit 802 (Figure 8A). System 900 includes an HV source combination 904. Combination 904 is an example of a main combination 512 or a TES combination 518 (Figure 5). System 900 further includes an energy recovery circuit 902 coupled in parallel to combination 904 and a plasma load 906. Energy recovery circuit 902 is an example of a main energy recovery circuit 520 on a TES energy recovery circuit 522 (Figure 5). An example of a plasma load 906 is a plasma chamber 102 (Figure 1).

[0104] Combination 904 is coupled to the plasma load 906 via RF connection 903. RF connection 903 is an example of RF connection 314 or 316 (Figure 3). The energy recovery circuit 902 is coupled to point 905 on RF connection 903. An example of point 905 is point 818 (Figure 8A).

[0105] Combination 904 outputs a DC voltage waveform 905, which is supplied to the diode and resonant inductor of RF connection 903, outputting a non-sinusoidal voltage waveform 907. The non-sinusoidal voltage waveform 907 is an example of the main non-sinusoidal voltage waveform 114 or the TES non-sinusoidal voltage waveform 116 (Figure 1). An example of the DC voltage waveform output from combination 904 is the modified main DC voltage waveform 517 (Figure 5). Another example of the DC voltage waveform 905 output from combination 904 is the modified TES DC voltage waveform 519 (Figure 5). Processor 203 (Figure 2) controls combination 904 and shapes the non-sinusoidal voltage waveform 907. For example, processor 203 controls the positive slope during the charging phase of the non-sinusoidal voltage waveform 907, the maximum amplitude during the charging phase, or a combination thereof.

[0106] The energy recovery circuit 902 includes a switch 908, a DC source 910, an inductor 824, an inductor 826, and a diode 914. An example of the DC source 910 is a main capacitor 510 or a TES capacitor 516 (Figure 5). For example, the DC source 910 represents the voltage across the main DC source 508, which is the same voltage as the voltage across the main capacitor 510. Another example is the DC source 910 representing the voltage across the TES DC source 514, which is the same voltage as the voltage across the TES capacitor 516. Inductor 826 is connected in series with diode 914, and diode 914 is connected in series with the DC source 910.

[0107] When switch 908 is controlled to close by processor 203, the voltage in the plasma load 906 is discharged and inductor 824 is charged. For example, the RF energy of the plasma load 906 is stored in the form of electromagnetic energy by inductor 824. On the other hand, when switch 908 is open, the electromagnetic energy stored in inductor 824 is transmitted to DC source 910 via diode 914 to store RF energy.

[0108] The energy recovery circuit 902 acts as a switch 901, supplying a predetermined amount of voltage to the plasma load 906. For example, when switch 901 acts as the open state, combination 904 generates a DC voltage waveform 905, which is used to output a non-sinusoidal voltage waveform 907 with a maximum amplitude of 10 kilovolts (kV), and the same maximum amplitude is achieved at the input I1 of the plasma load 906. When switch 901 acts as the closed state, the energy recovery circuit 902 stores RF energy from the plasma load 906 and reduces the maximum amplitude from 10kV to 5kV. Thus, without modifying the maximum amplitude output from combination 904, the voltage at input I1 is reduced to 5kV. When switch 901 acts as the closed state, the energy recovery circuit 902 stores the RF energy recovered from the plasma load 906 and reduces the voltage at input I1 from 5kV to 3kV. An example of switch 901 is switch 908. When the voltage at input I1 is to be returned from 3kV to 10kV, switch 901 is controlled to the open state by processor 203, and the non-sinusoidal voltage waveform 907 returns the voltage at input I1 to 10kV.

[0109] Figure 9B shows one embodiment of graphs 980 and another graph 982 illustrating the operation of system 900 (Figure 9A). Graph 980 plots the sheath voltage of the plasma formed in the plasma chamber 102 on the y-axis and time t on the x-axis. For example, graph 980 plots the sheath voltage in the main region 208 or the edge region 212 (Figure 2). Graph 982 plots the voltage of a non-sinusoidal voltage waveform 907 (Figure 9A) on the y-axis and time t on the x-axis. The x-axis of graph 982 is the same as the x-axis of graph 980.

[0110] Figure 10 is a diagram of one embodiment of system 1000 illustrating the use of a voltage source 1002. The voltage source 1002 includes an HVDC source 1004 which includes a combination of HV sources. The HV source combination of the HVDC source 1004 is also an example of a main combination 512 or a TES combination 518 (Figure 5). An example of the HVDC source 1004 is a main power supply 504 or a TES power supply 506 (Figure 5). The voltage source 1002 includes a current source 1006, a switch 1008, and another switch 1010. System 1000 further includes an energy recovery circuit 1012 and a plasma chamber 102. An example of the energy recovery circuit 1012 is an energy recovery circuit 802 (Figure 8A) or 902 (Figure 9A).

[0111] The HV source combination of HVDC source 1004 is coupled in series to switch 1008. Switch 1008 is coupled to plasma chamber 102 via RF connection 1001. RF connection 1001 is an example of RF connection 903 (Figure 9A). Switch 1010 is coupled to point 1003 on RF connection 1001 and is coupled to current source 1006. Current source 1006 is coupled to ground potential, and the HV source combination of HVDC source 1004 is also coupled to ground potential. Processor 203 is coupled to switches 1008 and 1010.

[0112] During the charging phase, the processor 203 controls switch 1008 to close and switch 1010 to open. During the discharging phase, the processor 203 controls switch 1008 to open and switch 1010 is open. After RF energy is recovered from the plasma chamber 102 during the discharging phase, the processor 203 (Figure 2) controls switch 1010 to close to achieve ion flux compensation. When switch 1010 is closed, current flows from the plasma chamber to the current source 1006. To achieve ion flux compensation, the processor 203 controls switch 1008 to the open state.

[0113] Figure 11 is a diagram of one embodiment of system 1100 illustrating the details of charging and ion flux compensation within system 1000 (Figure 10). System 1100 includes a voltage supply system 1102, an energy recovery circuit 1104, and a nonlinear load 801. Voltage supply system 1102 is an example of the voltage source 1002 in Figure 10. Energy recovery circuit 1104 is an example of the energy recovery circuit 1012 (Figure 10). Voltage supply system 1102 includes a constant current source 1106 and a voltage source system 1108. Constant current source 1106 includes a resistor or inductor and a diode. Voltage source system 1108 includes voltage source 1101 and another voltage source 1103. An example of voltage source 1101 is part of main combination 512 or TES combination 518 (Figure 5). For example, the voltage source 1103 is part of the main combination 512 or the TES combination 518. The voltage supply system 1102 further includes several diodes 1110 and 1112 and switches 1008 and 1010. The energy recovery circuit 1104 includes a DC source 910.

[0114] The voltage source 1103, the constant current source 1106, and the switch 1010 form an ion flux compensation circuit, such as a main ion flux compensation circuit or a TES ion flux compensation circuit. For example, the main ion flux compensation circuit is coupled to the main electrode via RF connection 314 (Figure 3), and the TES ion flux compensation circuit is coupled to the edge ring 110 via RF connection 316 (Figure 3).

[0115] The resistor of constant current source 1106 is coupled in series with the inductor of constant current source 1106 to form a series circuit, and this series circuit is coupled in parallel with the diode of constant current source 1106 to form a parallel circuit. Constant current source 1106 is coupled in series with diode 1112, and diode 1112 is coupled in series with switch 1010. Point 1003 between switches 1008 and 1110 is connected to nonlinear load 801 via inductor 1105 and capacitor 1107. There is also a ground connection between voltage sources 1101 and 1103. Voltage source 1101 is coupled to switch 1008 via diode 1110, and voltage source 1103 is coupled to diode 1112 via constant current source 1106. Processor 203 (Figure 2) is coupled to voltage sources 1101 and 1103.

[0116] The voltage source 1101 generates a DC voltage waveform 1114, such as a modified main DC voltage waveform 517 or a modified TES DC voltage waveform 519 (Figure 5). The DC voltage waveform 1114 is supplied from the voltage source 1101 to a circuit including a combination of inductor 1105 and capacitor 1107, which converts the DC voltage waveform 1114 into a non-sinusoidal voltage waveform 1109, such as a main non-sinusoidal voltage waveform 114 or a TES non-sinusoidal voltage waveform 116 (Figure 1). The processor 203 controls the switch 1008 to close and the switch 1010 to open. When switch 1008 is closed, the DC voltage waveform 1114 is transmitted to the inductor 1105 via diode 1110 and switch 1008, which outputs a non-sinusoidal voltage waveform 1109. The non-sinusoidal voltage waveform 1109 is transmitted from the voltage supply system 1102 to the non-linear load 801, which is charged with RF energy during the charging phase. After the non-linear load 801 is charged, the processor 203 controls the switch 908 to close. When the switch 908 is closed, the inductor 824 is charged with RF energy recovered from the non-linear load 801 during the discharge phase. The processor 203 also controls the switch 908 to open during the discharge phase. When the switch 908 is open, the RF energy stored in the inductor 824 charges the DC source 910 of the energy recovery circuit 1104 with RF energy. The RF energy stored in the DC source 910 is supplied to the voltage source system 1108 to correct the amplitude of the non-sinusoidal voltage waveform 1109.

[0117] After the discharge phase, during the ion compensation phase, the processor 203 controls the closing of switch 1010 and the opening of switch 1008. When switch 1010 is closed, current is supplied from the voltage source system 1108 to the nonlinear load 801 in a negative manner, for example, in the negative direction. For example, when switch 1010 is closed, the current signal 1107 flows from the nonlinear load 801 to the voltage source 1103 through the RF connection 1001, point 905, switch 1110, diode 1112, and the resistor and inductor of the constant current source 1106. Furthermore, the processor 203 controls the opening of switch 1010 after it has been closed. When switch 1010 is open, the current signal 1107 output from voltage source 1103 flows through the diode and resistor of the constant current source 1112 to the inductor of the constant current source 1112. Note that when the current signal 1107 flows from the nonlinear load 801 towards the voltage source 1103, the current signal 1107 flows in the positive direction and is represented by a positive value. On the other hand, when the current signal 1107 flows from the voltage source 1103 towards the nonlinear load 801, the current signal 1107 flows in the negative direction and is represented by a negative value. The constant current source 1106 is called a constant current source because current flows through it when the switch 1010 is open or closed.

[0118] The processor 203 controls the voltage of the voltage source 1103 to achieve uniformity of process speed. For example, upon receiving the amounts of the main ion flux and the TES ion flux, the processor 203 controls the voltage source 1103 to modify (e.g., increase or decrease) the voltage output from the voltage source 1103 until the amount of TES ion flux is compensated to a predetermined range from the amount of main ion flux. The voltage output from the voltage source 1103 (e.g., a negative voltage) is modified to change (e.g., increase or decrease) the amount (e.g., magnitude) of the current signal 1107. During the ion compensation stage, modifying the magnitude of the current signal 1107 changes the ramp slope of the non-sinusoidal voltage waveform 1109. For example, as the voltage output from the voltage source 1103 increases, the magnitude of the current signal 1107 increases, and the magnitude of the ramp slope of the non-sinusoidal voltage waveform 1109 increases, for example, from zero to negative. On the other hand, when the voltage output from the voltage source 1103 decreases, the magnitude of the current signal 1107 decreases, and the magnitude of the ramp slope of the non-sinusoidal voltage waveform 1109 decreases, for example, from a negative value to approach zero.

[0119] Figure 12 is an embodiment of graph 1200 illustrating the charging, discharging, and ion compensation phases. As an example, graph 1200 plots the voltage at input I1 of the nonlinear load 801 (Figure 11) on the y-axis and time t on the x-axis. As another example, graph 200 plots the voltage of the main nonsinusoidal voltage waveform 114 or the TES nonsinusoidal voltage waveform 116 (Figure 1) on the y-axis and time t on the x-axis. Referring back to Figure 11, during the charging phase, when switch 1008 is closed and switch 1010 (Figure 11) is opened, a voltage transition indicated by the number "1" occurs from a negative voltage, such as -8kV, to a positive voltage, such as 5kV, charging the plasma chamber 102 with the RF energy of the nonsinusoidal voltage waveform 1109 (Figure 11). For example, the RF energy of the DC voltage waveform 1114 is transmitted from the voltage source 1101 through the diode 1110, switch 1108, and point 1003 to the inductor 1105 of the RF connection 1001, which outputs a non-sinusoidal voltage waveform 1114. The RF energy of the non-sinusoidal voltage waveform 1114 is then transmitted through the RF connection 1001 to the nonlinear load 801. After the plasma in the plasma chamber 102, indicated by the nonlinear load 801, is charged, during the discharge phase, switch 908 (Figure 11) is closed, causing a discharge of the plasma's RF energy to charge the inductor 824. Charging the inductor 824 causes a drop from, for example, a positive voltage of 5kV to zero voltage. The transition from positive voltage to zero voltage is indicated using the number "2".

[0120] During the ion compensation stage, a transition from zero voltage to a negative voltage, indicated by the number "3", occurs using the constant current source 1106 (Figure 11). For example, when switch 1008 is opened and switch 1010 is closed, a transition from zero voltage to a negative voltage occurs. For example, power is supplied from voltage source 1103 to nonlinear load 801, but in the negative direction. For example, current signal 1107 is the current flowing from nonlinear load 801 to voltage source 1103 through the resistor and inductor of constant current source 1106. The negative direction is from nonlinear load 801 to voltage source 1103 through switch 1010 and the resistor and inductor of constant current source 1106.

[0121] In this way, the charging, discharging, and ion compensation phases are periodically repeated, for example, during each cycle of the clock signal. For example, after the ion compensation phase, switch 1008 is controlled by processor 203 to close again, and switch 1010 is controlled by processor 203 to open again, resulting in a voltage transition from a negative voltage to a positive voltage (e.g., 5kV), indicated by the number "1". For example, the RF energy of a non-sinusoidal voltage waveform 1114 is transmitted from the voltage source 1101 to the nonlinear load 801.

[0122] Figure 13 shows one embodiment of system 1300 illustrating the control of a DC source 1302, an HV source combination 1304, an energy recovery circuit 1012, a capacitor 1308, and a plasma load 906 to achieve uniformity of process speed. The DC source 1302, capacitor 1308, and combination 1304 are components of the HVDC source 1301. The HVDC source 1301 is an example of a mains power supply 306 (Figure 3) or a TES power supply 308 (Figure 3).

[0123] DC source 1302 is an example of a main DC source 508 or a TES DC source 514 (Figure 5). For example, the combination of DC source 1302, capacitor 1308, and combination 1304 is an example of DC source 1004 (Figure 10). Combination 1304 is an example of a main combination 512 or a TES combination 518 (Figure 5). Furthermore, capacitor 1308 is an example of capacitor 510 or 516 (Figure 5). Energy recovery circuit 1012 is an example of a main energy recovery circuit 520 or a TES energy recovery circuit 522 (Figure 5). For example, energy recovery circuit 802 (Figure 8A) or energy recovery circuit 902 (Figure 9A) is an example of energy recovery circuit 1012.

[0124] System 1300 further includes a processor 203. The processor 203 controls one or more of the DC source 1302, the combination 1304, and the energy recovery circuit 1012 to achieve uniformity of process speed. For example, a voltage sensor detects voltages such as the main voltage associated with the main electrode and the TES voltage associated with the edge ring 110. For example, the voltage sensor detects the voltage at the input of the main electrode and another voltage at the input of the edge ring 110 to achieve uniformity of process speed. Based on the voltages, the processor 203 controls the DC source 1302 or the combination 1304, or both, to control (e.g., increase or decrease) the amplitude (e.g., maximum amplitude) of the non-sinusoidal voltage waveform 1109 that is output based on the DC voltage waveform 1114. The DC voltage waveform 1114 is generated by the combination 1304. As another example, an ion flux sensor detects the amount of main ion flux associated with the main electrode and the amount of TES ion flux associated with the edge ring 110. Based on the amounts of the main ion flux and the TES ion flux, the processor 203 controls one or more HV sources of the DC source 1302 or combination 1304 to modify (e.g., increase or decrease) the amplitude of the non-sinusoidal voltage waveform 1109. As yet another example, based on the amounts of the main ion flux and the TES ion flux, the processor 203 controls the energy recovery circuit 1012 to modify (e.g., increase or decrease) the negative slope of the voltage of the non-sinusoidal voltage waveform 1109 during the discharge phase. The negative slope is an example of a negative transition of the non-sinusoidal voltage waveform 1109 from its maximum amplitude. Similarly, the processor 203 controls one or more of the HVDC source 1301, the energy recovery circuit 1012, and the voltage source 1103 (Figure 11) until the amount of TES ion flux is compensated to within a predetermined range from the amount of main ion flux. The non-sinusoidal voltage waveform 1109 is an example of the main non-sinusoidal voltage waveform 114 (Figure 1) or the TES non-sinusoidal voltage waveform 116 (Figure 1).

[0125] Figure 14 shows one embodiment of an integrated combination 1400 of HV sources. Combination 1400 includes voltage source 1402, another voltage source 1404, another voltage source 1406, and another voltage source 1408. Outputs 1410 and another output 1416 of combination 1400 are coupled to the main electrode. Outputs 1412 and another output 1414 of combination 1400 are coupled to the edge ring 110 (Figure 1).

[0126] Voltage sources 1402 and 1404 are controlled by processor 203 (Figure 13) to achieve peak-to-peak voltage control of non-sinusoidal voltage waveforms generated based on DC voltage waveforms supplied from outputs 1410 and 1412. These non-sinusoidal voltage waveforms are supplied to the main electrodes and edge ring 110. Additionally, voltage sources 1406 and 1408 are controlled by processor 203 to achieve ion flux compensation using non-sinusoidal voltage waveforms.

[0127] The embodiments described herein can be implemented in a variety of computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, and mainframe computers. The embodiments can also be implemented in distributed computing environments where tasks are performed by remote processing hardware units linked over a network.

[0128] In some embodiments, the controllers described herein are part of a system which may be part of the examples described above. Such a system includes semiconductor processing equipment comprising one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (such as wafer pedestals, gas flow systems, etc.). These systems are integrated with electronic equipment for controlling pre-processing, processing, and post-processing operations of semiconductor wafers or substrates. Such electronic equipment may be referred to as a “controller” and may control various components or sub-components of one or more systems. The controller is programmed to control one of the processes disclosed herein, depending on the processing requirements and / or the type of system. Such processes include supplying process gases, setting temperature (e.g., heating and / or cooling), setting pressure, setting vacuum, setting power, setting RF generators, setting RF matching circuits, setting frequency, setting flow rates, setting fluid supply, setting position and operation, loading and unloading wafers to and from tools and other transfer tools coupled to or interlocked with the system, and / or loading and unloading wafers to and from load locks.

[0129] In a broad sense, in various embodiments, a controller is defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive and issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. Integrated circuits include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, and / or one or more microprocessors, i.e., microcontrollers that execute program instructions (e.g., software). Program instructions are instructions communicated to the controller in the form of various individual settings (or program files) that define parameters, coefficients, variables, etc., for carrying out a particular process on or for a semiconductor wafer or in a system. In some embodiments, program instructions are part of a recipe defined by a process engineer to realize one or more processing steps in the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0130] In some embodiments, the controller is part of a computer that is integrated with or coupled to the system, or otherwise networked to the system, or is coupled to such a computer, or a combination thereof. For example, the controller resides in the “cloud” and is all or part of the fab host computer. This enables remote access to wafer processing. The computer enables remote access to the system to monitor the current progress of fabrication operations, review the history of past fabrication operations, examine trends or performance criteria from multiple fabrication operations, modify parameters of the current process, set processing steps following the current process, or start a new process.

[0131] In some embodiments, a remote computer (e.g., a server) provides process recipes to the system via a network. Such a network may include a local network or the Internet. The remote computer includes a user interface that enables the entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data, which specify the parameters, coefficients, and / or variables for each processing step performed during one or more operations. It should be understood that the parameters, coefficients, and / or variables are specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Thus, as described above, the controller is distributed by including, for example, one or more separate controllers that are networked together and cooperate toward a common purpose (such as the processes and controls described herein). An example of a distributed controller for such purposes is one or more integrated circuits on a chamber that communicate with one or more integrated circuits that are remotely located (e.g., at the platform level or as part of a remote computer) and combined to control the processes in the chamber.

[0132] In various embodiments, exemplary systems to which the method is applied include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, tracking chambers or modules, and any other semiconductor processing systems related to or used in the fabrication and / or manufacture of semiconductor wafers.

[0133] It should be further noted that in some embodiments, the above-described operation applies to several types of plasma chambers, such as plasma chambers containing inductively coupled plasma (ICP) reactors, capacitively coupled plasma (CCP) chambers, transformer-coupled plasma chambers, conductive tools, dielectric tools, and plasma chambers containing electron cyclotron resonance (ECR) reactors. For example, one or more RF generators are coupled to inductors within an ICP reactor. Examples of inductor shapes include solenoids, dome coils, and flat coils.

[0134] As described above, depending on one or more process steps performed by the tool, the host computer communicates with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, the main computer, another controller, or tools used for material handling to load and unload wafer containers to and from tool locations and / or load ports within the semiconductor manufacturing plant.

[0135] With the above embodiments in mind, it should be understood that some embodiments utilize various computer implementation operations involving data stored in a computer system. These operations are operations that physically manipulate physical quantities. Any of the operations described herein that form part of the embodiments are useful mechanical operations.

[0136] Some embodiments also relate to hardware units or devices for performing these operations. These devices are specifically built for dedicated computers. When defined as a dedicated computer, the computer is capable of operating for its dedicated purpose, but performs other processes, program executions, or routines that are not part of its dedicated purpose.

[0137] In some embodiments, the operation may be processed by a computer that is selectively activated or configured by one or more computer programs stored in computer memory, a cache, or retrieved via a computer network. If the data is retrieved via a computer network, that data may be processed by other computers on the computer network (e.g., a cloud of computing resources).

[0138] One or more embodiments may also be fabricated as computer-readable code on a non-temporary computer-readable medium. A non-temporary computer-readable medium is any data storage hardware unit that stores data (e.g., a memory device), which is then read by a computer system. Examples of non-temporary computer-readable media include hard drives, network-attached storage (NAS), read-only memory (ROM), random-access memory (RAM), compact disk ROM (CD-ROM), CD recordable (CD-R), CD rewritable (CD-RW), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, the non-temporary computer-readable medium includes computer-readable tangible media distributed on a network-connected computer system so that the computer-readable code is stored and executed in a distributed manner.

[0139] Although the above method operations were described in a specific order, it should be understood that in various embodiments, other housekeeping operations may be performed between each operation, or each method operation may be timed to occur at slightly different times, or they may be distributed in a system that allows each method operation to occur at various intervals, or they may be performed in an order different from the order described above.

[0140] It should be further noted that in one embodiment, one or more features of any of the embodiments described above may be combined with one or more features of any other embodiments without departing from the scope described in the various embodiments described herein.

[0141] Although the embodiments described above have been explained in some detail for clearer understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. Therefore, these embodiments should be considered illustrative rather than restrictive, and embodiments should not be limited to the details described herein.

Claims

1. It is a system, The first power source, A first DC power source configured to generate a first direct current (DC) voltage waveform, A first capacitor is coupled in parallel to the first DC power source, A first power supply comprising: a plurality of first voltage sources coupled to the first capacitor, each configured to receive the first DC voltage waveform in order to facilitate the output of a first non-sinusoidal radio frequency (RF) signal to the main electrode of the plasma chamber; The second power source is A second DC power source configured to generate a second DC voltage waveform, A second capacitor connected in parallel to the second DC power source, A second power supply comprising: a second plurality of voltage sources coupled to the second capacitor, each configured to receive the second DC voltage waveform in order to facilitate the output of a second non-sinusoidal voltage waveform to the edge electrodes of the plasma chamber; A controller coupled to the first and second plurality of voltage sources controls the amplitudes of the first and second non-sinusoidal voltage waveforms in order to achieve uniformity of process speed between the main region and the edge region in the plasma chamber. A system equipped with these features.

2. The system according to claim 1, A system comprising an energy recovery circuit coupled to the plasma chamber, the energy recovery circuit being configured to receive RF energy from the plasma chamber and store the RF energy.

3. The system according to claim 2, The energy recovery circuit is a system that includes an inductor configured to store the RF energy.

4. The system according to claim 3, The energy recovery circuit includes a switch, the controller is coupled to the switch to control the period during which the RF energy is recovered for storage in the inductor, and the system controls the negative transition of the first or second non-sinusoidal voltage waveform to facilitate the achievement of uniformity of the process speed.

5. The system according to claim 1, The controller is coupled to the first and second DC power sources and controls the DC voltages of the first and second DC power sources to correct the amplitudes of the first and second non-sinusoidal voltage waveforms in the system.

6. The system according to claim 1, The system is configured such that the controller controls the phase of the first and second non-sinusoidal voltage waveforms.

7. The system according to claim 1, A system further comprising a clock source coupled to the first and second power supplies for synchronizing the first and second non-sinusoidal voltage waveforms.

8. The system according to claim 1, The plasma chamber is a nonlinear load, and the controller is configured to control multiple slopes of multiple ramps of the first and second non-sinusoidal voltage waveforms in order to achieve uniformity of the process speed.

9. It is a method, A first DC power source generates a first DC voltage waveform. To facilitate the output of a first non-sinusoidal radio frequency (RF) signal to the main electrode of the plasma chamber, the first DC voltage waveform is received, A second DC power source generates a second DC voltage waveform. In order to facilitate the output of a second non-sinusoidal voltage waveform to the edge electrode of the plasma chamber, the second DC voltage waveform is received, To achieve uniformity of process speed between the main region and the edge region in the plasma chamber, the amplitudes of the first and second non-sinusoidal voltage waveforms are controlled. A method that includes [a certain feature].

10. The method according to claim 9, RF energy is received from the plasma chamber, The RF energy is stored in the energy recovery circuit. A way to prepare further.

11. The method according to claim 10, The RF energy is stored in an inductor in a manner.

12. The method according to claim 11, The energy recovery circuit includes a switch, and the method further comprises controlling the period during which the RF energy is recovered for storage in the inductor, wherein the period during which the RF energy is recovered for storage controls a negative transition of the first or second non-sinusoidal voltage waveform to facilitate the achievement of uniformity of the process speed.

13. The method according to claim 9, A method further comprising controlling the DC voltages of the first and second DC power sources in order to modify the plurality of amplitudes of the first and second non-sinusoidal voltage waveforms.

14. The method according to claim 9, A method further comprising controlling the phases of the first and second non-sinusoidal voltage waveforms.

15. The method according to claim 9, A method further comprising synchronizing the operation of the first and second DC power sources.

16. The method according to claim 9, The plasma chamber is subjected to a nonlinear load.

17. A non-temporary computer-readable medium containing program instructions for controlling non-sinusoidal radio frequency (RF) signals supplied to the main electrode and edge electrode of a plasma chamber, wherein the execution of the program instructions by one or more processors of a computer system is performed by the one or more processors, A first DC power source generates a first DC voltage waveform. To facilitate the output of a first non-sinusoidal voltage waveform to the main electrode of the plasma chamber, the first DC voltage waveform is received. A second DC power source generates a second DC voltage waveform. To facilitate the output of a second non-sinusoidal voltage waveform to the edge electrode of the plasma chamber, the second DC voltage waveform is received. To achieve uniformity of process speed between the main region and the edge region in the plasma chamber, the operation controls the amplitudes of the multiple amplitudes of the first and second non-sinusoidal voltage waveforms. A non-temporary, computer-readable medium that makes this possible.

18. A non-temporary computer-readable medium according to claim 17, The aforementioned operation further, The operation of receiving RF energy from the plasma chamber, Operation to store the RF energy in the energy recovery circuit. A non-temporary computer-readable medium comprising [a specific feature].

19. A non-temporary computer-readable medium according to claim 18, The aforementioned RF energy is stored in an inductor in a non-transient, computer-readable medium.

20. A non-temporary computer-readable medium according to claim 19, The energy recovery circuit includes a switch, and the method further comprises controlling the period during which the RF energy is recovered for storage in the inductor, wherein the period during which the RF energy is recovered for storage controls a negative transition of the first or second non-sinusoidal voltage waveform to facilitate the achievement of uniformity of the process speed, in a non-transient computer-readable medium.

21. A system for use with a plasma chamber, wherein the plasma chamber has a substrate support and an edge ring surrounding the substrate support. Voltage waveform source, The first output of the voltage waveform source connected to the substrate support, The second output of the voltage waveform source connected to the edge ring, A controller configured to output a first non-sinusoidal bias (NSB) waveform for the substrate support and to control the voltage waveform source to output a second NSB waveform for the edge ring via the second output. Equipped with, The first and second NSB waveforms provide a pulsed bias voltage to the plasma generated in the plasma chamber. system.

22. The system according to claim 21, The voltage waveform source is a system comprising a combination of a direct current (DC) source, a capacitor coupled in parallel to the DC source, and a voltage source coupled in parallel to the DC source.

23. The system according to claim 22, The system further comprises an energy recovery circuit coupled to the capacitor, wherein the energy recovery circuit is configured to recover and store radio frequency (RF) energy from the plasma chamber.

24. The system according to claim 23, The energy recovery circuit is configured to supply the RF energy to the combination of voltage sources, and the combination of voltage sources is configured to modify the first NSB waveform or the second NSB waveform based on the RF energy, in a system.

25. The system according to claim 21, A system further comprising an ion flux compensation circuit having a voltage source, wherein the controller is configured to control the voltage output from the voltage source of the ion flux compensation circuit in order to control the slope of the ramp of the first or second NSB waveform.

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