Phase-change memory cell having a crystal structure aligned with the seed layer

Abstract

The phase-change memory cell includes an insulating layer; a first electrode embedded in the insulating layer, wherein the outer end of the first electrode is locally flush with the outer surface of the insulating layer; a second electrode that is larger than the first electrode and spaced apart from the first electrode; a compositionally homogeneous crystalline phase-change material layer; and a highly oriented seed layer. The crystalline structure of the homogeneous phase-change material layer correlates with the crystalline structure of the highly oriented seed layer. The compositionally homogeneous phase-change material layer and the highly oriented seed layer are located at least partially between the first and second electrodes.

Description

[Background technology]

[0001] This invention generally relates to electrical, electronic, and computer technologies, and more specifically to phase change memory (PCM).

[0002] Phase-change memory (PCM) employs a phase-change material (also abbreviated as PCM; those skilled in the art will understand from the context whether "memory" or "material" is intended) that can exist in two phases, namely a (poly)crystalline phase and an amorphous phase. One exemplary class of phase-change materials is the germanium-antimony-tellurium (GST) alloy, which is a type of phase-change material belonging to the general group of chalcogenide glasses. GST225 (Ge2Sb2Te5) is one example, not limited to this one. A phase-change memory cell can store bits (0 or 1) by changing the phase of the phase-change material. A typical device has the phase-change material sandwiched between two contacts. When the phase-change material is in the crystalline phase, the phase-change material is relatively conductive and conducts relatively large currents. When a phase-change material is in an amorphous phase, it has relatively high resistance and conducts relatively low currents. Phase-change memory is non-volatile; once the material becomes crystalline, it remains crystalline; once the material becomes amorphous, it remains amorphous (provided the material is kept below its crystallization temperature).

[0003] One prior art "mushroom" PCM cell includes a polycrystalline PCM region and may or may not have a protruding liner. Another prior art "mushroom" PCM cell includes a superlattice (a layer in which two different phase-change materials are alternately stacked, or a layer in which a phase-change material and TiTe2 are alternately stacked). Single-crystal PCM devices are known that require growth on a Si(111) substrate, where the substrate serves as a growth template. [Overview of the project]

[0004] The principle of the present invention provides a phase-change memory having a crystalline structure aligned with a seed layer. In one embodiment, an exemplary phase-change memory includes an insulating layer; a first electrode embedded in the insulating layer, wherein the outer end of the first electrode is locally flush with the outer surface of the insulating layer; a second electrode that is larger than the first electrode and spaced apart from the first electrode; a compositionally homogeneous crystalline phase-change material layer; and a highly oriented seed layer. The crystalline structure of the homogeneous phase-change material layer correlates with the crystalline structure of the highly oriented seed layer, and the compositionally homogeneous phase-change material layer and the highly oriented seed layer are at least partially located between the first and second electrodes.

[0005] Optionally, the compositionally homogeneous phase-change material layer and the highly oriented seed layer are made of different materials.

[0006] Optionally, the seed layer has an out-of-plane crystal axis, and the homogeneous phase-change material layer has an out-of-plane crystal axis aligned with the out-of-plane crystal axis of the seed layer.

[0007] In another embodiment, a phase-change memory array of such phase-change memory cells includes a plurality of horizontal lines; a plurality of vertical lines intersecting the plurality of horizontal lines at a plurality of cell locations; a plurality of phase-change memory cells located at each of the plurality of cell locations; and a plurality of transistors associated with each of the plurality of phase-change memory cells. Each of the phase-change memory cells includes an insulating layer; a first electrode embedded in the insulating layer, wherein the outer end of the first electrode is locally flush with the outer surface of the insulating layer; a second electrode that is larger than the first electrode and spaced further apart from the first electrode; a compositionally homogeneous crystalline phase-change material layer; and a highly oriented seed layer, wherein the crystalline structure of the homogeneous phase-change material layer is correlated with the crystalline structure of the highly oriented seed layer. The compositionally homogeneous phase-change material layer and the highly oriented seed layer are located at least partially between the first and second electrodes.

[0008] In a further embodiment, a method for forming a phase-change memory cell includes the step of providing an initiation structure comprising a substrate, an insulating layer outside the substrate, and a first electrode embedded in the insulating layer. The outer end of the first electrode is locally flush with the outer surface of the insulating layer. Further steps include depositing a highly oriented crystal seed layer on the outer surface of the insulating layer and the outer end of the first electrode; epitaxially growing a compositionally homogeneous crystalline phase-change material layer on the highly oriented crystal seed layer; and depositing a top electrode material on the compositionally homogeneous crystalline phase-change material layer.

[0009] In a further embodiment, another method for forming a phase-change memory cell includes the step of providing an initiation structure comprising a substrate, an insulating layer outside the substrate, and a first electrode embedded in the insulating layer. The outer end of the first electrode is locally flush with the outer surface of the insulating layer. Further steps include depositing an amorphous phase-change material layer on the outer surface of the insulating layer and the outer end of the first electrode; depositing a highly oriented crystal seed layer on the outer surface of the amorphous phase-change material layer at a temperature below the crystallization temperature of the first amorphous phase-change material layer to create a resulting structure; and annealing the resulting structure at a temperature above the crystallization temperature of the first amorphous phase-change material layer to induce solid-phase crystallization of the amorphous phase-change material layer by template formation from the seeding layer.

[0010] In a further embodiment, another method for forming a phase-change memory cell includes the step of providing an initiation structure comprising a substrate, an insulating layer outside the substrate, and a first electrode embedded in the insulating layer. The outer end of the first electrode is locally flush with the outer surface of the insulating layer, and the insulating layer is amorphous. Further steps include preparing the outer surface of the amorphous insulating layer to cause orientation of a compositionally homogeneous crystalline phase-change material layer to be epitaxially grown thereafter; epitaxially growing the compositionally homogeneous crystalline phase-change material layer on the prepared outer surface of the amorphous insulating layer at a temperature such that the compositionally homogeneous crystalline phase-change material layer grows crystallinely; and depositing a top electrode material on the compositionally homogeneous crystalline phase-change material layer.

[0011] In a further embodiment, a hardware description language (HDL) design structure is encoded on a machine-readable data storage medium. The HDL design structure includes elements that, when processed by a computer-aided design system as described, generate a machine-executable representation of a phase-change memory cell and / or array.

[0012] As used herein, “facilitating” an action includes performing an action, making an action easier, assisting in the performance of an action, or causing an action to be performed. Therefore, for example, but not limited to, instructions executed on a single processor may facilitate an action performed by a semiconductor processing device by sending appropriate data or commands to cause an action to be performed or by assisting in the performance of an action. Even when an action is facilitated by means other than the performer performing the action, the action is still performed by an entity or combination of entities.

[0013] The methods disclosed herein can provide substantial beneficial technical effects. Some embodiments may not have these potential benefits, and these potential benefits are not necessarily required in all embodiments. As examples only, and not as an limitation, one or more embodiments may provide one or more of the following: • Phase-change memory with low RESET current (e.g., due to the presence of a van der Waals gap). ·R RESET / R SET Phase-change memory with a large window (i.e., the ratio of resistances in two different states, such as SET and RESET, is high, and the higher resistance (R) is used depending on the application) RESET The lower resistor R SET For example, more than 10 times, or preferably more than 100 times. • Phase change memory with higher programming endurance (i.e., a large number of SET-RESET cycles before the device fails, and depending on the application, the number of cycles before failure is, for example, at least 10) 9 be). • Phase-change memory with good memory capacity (for example, the programmed state is maintained for at least 10 years when the device is operated within a reasonable temperature range). • Phase-change memory with low resistive drift (due to its epitaxial structure, where, once a device is placed in a given resistive state, it maintains a resistance level with little or no change over the period for which the stored data needs to be retained. This is particularly useful when storing one or more bits using devices with intermediate states, or in analog artificial intelligence (AI) computation. • The use of epitaxial materials compared to polycrystalline materials results in less device variability.

[0014] These and other features and advantages will become apparent from the following detailed description of exemplary embodiments, which should be read in conjunction with the attached drawings. [Brief explanation of the drawing]

[0015] The following drawings are presented by way of example and not limitation, where like reference numerals (if used) indicate corresponding elements throughout several views.

[0016] [Figure 1] An embodiment of a phase change memory cell according to an aspect of the present invention is shown.

[0017] [Figure 2] An embodiment of FIG. 1 according to an aspect of the present invention is shown together with a PCM switching region.

[0018] [Figure 3] An embodiment of a phase change memory cell according to an aspect of the present invention is shown.

[0019] [Figure 4] An embodiment of a phase change memory cell according to an aspect of the present invention is shown.

[0020] [Figure 5] An embodiment of a phase change memory cell according to an aspect of the present invention is shown.

[0021] [Figure 6] An embodiment of a phase change memory cell according to an aspect of the present invention is shown.

[0022] [Figure 7] An embodiment of a phase change memory cell according to an aspect of the present invention is shown.

[0023] [Figure 8] An embodiment of a phase change memory cell according to an aspect of the present invention is shown.

[0024] [Figure 9] An embodiment of a phase change memory cell according to an aspect of the present invention is shown.

[0025] [Figure 10] Figures 10A to 10D show a model series of steps for manufacturing the phase-change memory cell described in the embodiment of Figure 3, according to one aspect of the present invention.

[0026] [Figure 11] Multiple embodiments of the present invention demonstrate epitaxial growth of PCM on a seed layer, including a van der Waals gap.

[0027] [Figure 12] Figures 12A and 12B show alternative seed layer locations according to several embodiments of the present invention.

[0028] [Figure 13] A crossbar array of PCM cells according to one aspect of the present invention is shown.

[0029] [Figure 14] A computing environment according to one embodiment of the present invention (for example, one for implementing a design process such as the design process shown in Figure 15) is shown.

[0030] [Figure 15] This is a flowchart of the design process used in the design, manufacturing, and / or testing of semiconductors.

[0031] Please understand that elements in the figures are shown for the sake of brevity and clarity. Common but well-understood elements that may be useful or necessary in commercially viable embodiments may be omitted so as not to interfere with the depiction of the shown embodiments. [Modes for carrying out the invention]

[0032] In this specification, the principles of the present invention are described in the context of exemplary embodiments. Also, it will be apparent to those skilled in the art that numerous modifications can be made to the disclosed embodiments within the scope of the claims based on the teachings herein. That is, no limitation or speculation is intended with respect to the embodiments shown and described herein.

[0033] One or more embodiments advantageously provide a PCM cell comprising a homogeneous single-crystal phase change material layer having a crystal plane aligned with the crystal plane of the seed layer. The single-crystal PCM is said to be templated from the seed layer such that the PCM layer mimics at least one aspect of the order provided by the seed layer. An exemplary phase change memory includes, for example, a homogeneous phase change material layer having an out-of-plane crystal axis aligned with the out-of-plane crystal axis of a crystalline seed layer. The seed layer is, for example, Ti x Te y or Sb x Te yThis may include the seed layer, which may be the first, last, or intermediate layer. One or more embodiments provide a single-crystal homogeneous phase-change material layer on a non-planar electrode substrate having an out-of-plane crystal axis perpendicular to the substrate. An exemplary method for forming a phase-change memory (PCM) includes the steps of preparing the surface (e.g., charging the substrate with Ar sputtering or an electron beam), followed by crystal deposition of the seed layer at a first optimized temperature, followed by crystal deposition of the phase-change material layer at a second optimized temperature (with the crystal structure aligned to the seed layer). For example, a TiTe2 seed layer can be deposited at a substrate temperature of 150°C to 250°C, and a GST225 PCM layer can be deposited at a temperature of 150°C to 250°C. In yet another example, both the TiTe2 layer and the GST225 layer are deposited at the same temperature (e.g., 200°C). For example, a lower electrode is formed embedded in an insulating material, a thin (0.25-5 nm) crystalline seed layer is deposited with the z-axis orientation of the crystal perpendicular to the substrate, a crystalline phase change material layer is deposited with the z-axis aligned with the z-axis of the seed layer, and the top electrode material is deposited. In another example, a first amorphous PCM layer is deposited; a seeding layer is deposited at a temperature below the crystallization temperature of the first amorphous PCM layer (where the seeding layer is a highly oriented crystalline layer); and annealing is performed at a temperature above the crystallization temperature of the first PCM layer to induce solid-phase crystallization of the first PCM layer from top to bottom by template formation from the seeding layer. Regarding the "highly oriented" crystalline layer, in reality, the seed layer (or subsequent PCM layer) is not a perfect single crystal, but a polycrystalline layer in which almost all of the polycrystals are oriented in the same direction. Furthermore, the polycrystals are usually very large. "Large" means that the polycrystal is several times the size of the device compared to the size of the device. Therefore, in one or more embodiments, the highly oriented seed layer is not a single crystal; rather, it has microcrystals, but all microcrystals are oriented substantially the same way in at least one dimension / axis. In two adjacent microcrystals, the atomic layers are parallel to the substrate, but these two microcrystals may rotate relative to each other, and as a result, the atomic layers may not necessarily be aligned with respect to other axes.In one or more embodiments, alignment along at least one direction is appropriate. The use of templates according to one or more embodiments may be particularly advantageous for line processing backends where access to crystalline Si(111) substrates, as required by some prior art methods, is unavailable. In other words, a “highly oriented” crystalline film is a layer composed of polycrystalline domains, all of which are aligned in close proximity to one another (in one or more directions). Experimentally, this can be observed using X-ray diffraction. If the film is polycrystalline and all domains (or microcrystals) are randomly oriented, most microcrystals will not match the diffraction conditions, and no diffraction peaks will be observed. However, in a highly oriented crystalline film, most microcrystals will match the diffraction conditions (in a specific beam orientation), and clear diffraction peaks will be observed. At the limit of perfect alignment of all microcrystals, the material approaches a single-crystal film. Note that there may be arrangements of microcrystals where all microcrystals have atomic planes parallel to the substrate surface, but each microcrystal is rotated in the plane at some random angle. In this case, diffraction from atomic planes parallel to the surface will show good crystallinity (strong diffraction peaks), but diffraction from planes with asymmetric diffraction patterns (for example, atomic planes at a certain angle to the surface) will be similar to that of random polycrystalline materials (no diffraction peaks).

[0034] Furthermore, the epitaxial process, which grows a homogeneous single-crystal layer, may be called "homoepitaxy," while the growth of a superlattice may be called "heteroepitaxy."

[0035] In some prior art devices, a Si(111) substrate is required as a seeding template for a homogeneous single-crystal phase transition layer; in contrast, one or more embodiments are substrate orientation independent, and at least to some extent, substrate material independent (it is unclear how much the epitaxy would change if the top surface of the substrate could not have high conductivity to retain charge, as charges deposited on the substrate surface (e.g., by Ar sputtering) help in the orientation of the seed layer). This is not a problem for PCM devices because the bottom electrodes are embedded in silicon nitride or silicon oxide, which acts as an insulator and retains charge well. In some prior art devices, superlattice structures are utilized, but in one or more embodiments, bulk homogeneous polycrystalline PCM materials are employed; for example, GST225 or other stoichiometric compositions, or Sb2Te3 or other stoichiometric compositions, optionally doped (examples of dopants: SiC, Si, SiO2, SiN). In one or more embodiments, the seed layer can be made to a maximum thickness of 5 nm and a minimum thickness of a single layer, minimizing the impact on electrical properties.

[0036] As an example, and not an exhaustive one, a typical configuration of a seed layer + homogeneous phase-change material for an exemplary PCM cell includes the following:

[0037] Seed layer: TiTe2 of 0.25~5nm / PCM layer: Sb2Te3 of 1~100nm

[0038] Seed layer: TiTe2 of 0.25~5nm / PCM layer: Ge2Sb2Te5 of 1~100nm

[0039] Seed layer: 0.25~5nm Sb2Te3 / PCM layer: 1~100nm Ge2Sb2Te5

[0040] First seed layer: TiTe2 of 0.25-5nm / Second seed layer: Sb2Te3 of 1-5nm / PCM layer: Ge2Sb2Te5 of 1-100nm

[0041] PCM layer: Ge2Sb2Te5 of 1-100nm / Seed layer: TiTe2 of 0.25-5nm (crystallization from top to bottom with a seeding layer on top of the PCM).

[0042] If necessary, in any of the above embodiments, a dopant (e.g., C, SiC, Si, SiN, Ta) may be added to the seed layer, the PCM layer, or both. x O y (N, O) may be included. Optionally, in any of the above embodiments, the stoichiometric composition in the seed layer, PCM layer, or both may be altered. The effect of doping on epitaxy will typically depend on the dopant used. For example, carbon is known to slow the crystallization of amorphous GST, but is likely to be incorporated during epitaxial growth. Oxygen may hinder epitaxy, as it may lead to the formation of an amorphous GST oxide layer (i.e., essentially negate the template effect). Since carbon and / or silicon are precisely substitutes for Ge, doping using these is now considered potentially useful.

[0043] Please note here, referring to Figure 1, that the embodiment includes an inner insulating layer 301A, a bottom electrode 303, a crystalline seed layer 305 (non-PCM in this case), a crystalline homogeneous PCM layer 307, a top electrode 309, and an outer insulating layer 301B. Below the inner insulating layer 301A, there may be, for example, an interconnection layer 397 and a silicon substrate 399 having a circuit constructed of transistors (for example, a metal-oxide semiconductor field effect transistor (MOSFET) as will be apparent to those skilled in the art based on the teachings herein). In the exemplary embodiment shown, the z axes of the crystalline PCM layer 307 and the crystalline seed layer 305 are aligned. In this embodiment, for example, a crystalline material 307 is grown on the seed layer 305 at a high temperature (e.g., 180-200°C). The PCM is epitaxially grown on the highly oriented seeding layer 305. In some cases, the growth temperature may be higher than the crystallization temperature of the PCM layer 307; however, this is not a requirement. In practice, the growth temperature can generally be lower than the crystallization temperature of the PCM. The crystallization temperature of the PCM is defined for the spontaneous crystallization of amorphous PCM, and in this case, since the PCM is epitaxially grown using a template, it is permissible, but not necessary, to use a growth temperature higher than the temperature mentioned above.

[0044] Note that all embodiments shown, including those in Figures 6 and 7, may have layers 397 and 399, but for illustrative purposes, these are shown only in Figure 1. In one or more embodiments, the process begins with layers 399, 397, 301A, and a lower electrode 303 flush with the uppermost layer of 301A. Next, layers 305, 307, and 309 are deposited as blanket layers, and a device stack is created from 305, 307, and 309 using patterning / lithography, with an insulator 301B deposited on both sides, which may generally be the same or different material compared to 301A (regions 301A and 301B are separated by dotted lines accordingly).

[0045] In one or more embodiments, a homogeneous crystalline material is epitaxially grown on a seed layer using a van der Waals gap without using / forming a multilayer or superlattice.

[0046] The seed layer 305 can be deposited at a sufficiently high temperature so that it is crystalline. Next, the wafer can be cooled, and then the PCM layer 307 can be deposited at a sufficiently low temperature (e.g., room temperature) so that the PCM layer 307 is amorphous. Next, the wafer can be annealed at a sufficiently high temperature (e.g., 200°C for GST225) to allow the PCM 307 layer to grow as a solid-state ordered crystal by template from the seed layer 305. The remaining fabrication steps remain the same.

[0047] Figure 2 shows an embodiment of Figure 1, in which a dome 311 of amorphous PCM material is formed. Note that the seed layer beneath region 311 has disappeared, but the seed / template layer 305 beneath the crystalline homogeneous PCM layer 307 remains. The dome and bottom electrode work together to form a "mushroom shape," with the bottom electrode acting as the "stem" of the mushroom and region 311 as the "dome" of the mushroom. The amorphous PCM dome can be recrystallized with a SET pulse using the surrounding crystalline PCM material as a template. In one or more embodiments, since material 307 is homogeneous, the same composition remains regardless of how much of the material melts after melting and recrystallization. In contrast, in prior art methods using multilayer / superlattice, when the first two layers melt during RESET, they mix together in a mixed material. In another RESET melt, the first three layers melt together to form a larger dome, which is thought to result in a different composition. Advantageously, in one or more embodiments of the present invention, the PCM material is homogeneous, and the composition of the PCM will not change upon resetting.

[0048] Regarding RESET, this operation typically involves applying a high current pulse to the device ("high" meaning providing enough energy to melt the PCM adjacent to the bottom electrode). The RESET pulse is rapidly quenched / shut down to force rapid cooling of the molten material, which then solidifies in the amorphous phase. If the current pulse weakens slowly (by having a long falling edge), the molten material will solidify in the crystalline phase, as it will have enough time to crystallize. Based on the teachings herein, those skilled in the art can determine the current and waveform required for a particular shape using known methods such as thermoelectric finite element analysis. The maximum current density is at the point where the bottom electrode 303 contacts the material 307. The material melts, and the dome 311 is formed. Line 312 represents the current density. When the pulse is plotted as a function of time, quenching means that the falling edge of the pulse drops abruptly. This abrupt drop causes the molten material to cool rapidly without crystallization. As a result, the bottom electrode (one of the contacts) is covered with a dome 311 of amorphous material (high resistance), blocking the current. One of the figure of merit (FOM) of a PCM device is to have the lowest possible reset current. One approach is to make the bottom electrode 303 as small as possible, as will be discussed elsewhere in this specification. Another approach is to use a doped PCM to which additives such as oxygen and / or nitrogen have been added. Additives typically "decorate" the particle boundaries between particles in the polycrystalline material. This has the effect of increasing the resistance of the material and lowering the reset current.

[0049] In one or more embodiments, when melting and recrystallization are performed using rapid quenching, a second low-intensity pulse can be applied to anneal the material above the crystallization temperature without melting it. Another approach employs a RESET pulse, but without using a sudden falling edge; rather, it cools slowly to recrystallize the PCM. In Figure 2, even if the material melts near the bottom electrode 303, the molten material treats the top of the remaining crystalline electrode 307 as a template and follows that template during recrystallization. Furthermore, with respect to "rapid" quenching, it must be fast enough so that the molten material solidifies in the amorphous phase. This varies depending on the PCM material used. For example, in the case of GST225, the falling edge of the RESET pulse is about a few nanoseconds. Furthermore, with respect to "low-intensity" pulses, it is defined as a pulse that will lead to crystallization of the PCM material. For example, in the case of GST225, it is typically a pulse with a long falling edge of tens of nanoseconds or more. In this case as well, based on the teachings herein, a person skilled in the art can determine the current and waveform required for a particular shape using known methods such as thermoelectric coupling finite element analysis.

[0050] Note that Figure 3 shows an embodiment including an inner insulating layer 301A and an outer insulating layer 301B, a bottom electrode 303, a crystalline seed layer 305 (non-PCM in this case), a crystalline homogeneous PCM layer 307, and a top electrode 309. In the exemplary embodiment shown, the z-axis of the crystalline PCM layer 307 and the crystalline seed layer 305 are aligned. In this embodiment, the seed layer 305 is located outside the PCM layer 307. Having the seed layer 305 on layer 307 has certain advantages. If the seed layer is located at the bottom between the bottom electrode 303 and layer 307, it may affect the contact between the bottom electrode and the PCM layer. In many cases, the seed layer itself is not PCM. It is desirable to have the bottom electrode in direct contact with the epitaxial PCM layer, as shown in Figure 3.

[0051] Please refer to Figures 10A to 10D. In Figure 10A, amorphous PCM 307A is deposited on the inner insulating layer 301A. For example, depositing PCM at room temperature yields amorphous PCM. Generally, to obtain amorphous PCM, the substrate temperature should be kept below the crystallization temperature of the PCM material. For example, in the case of GST225, the crystallization temperature is approximately 165°C. In Figure 10B, a highly oriented seeding layer 305 is deposited on the amorphous PCM 307A. In the annealing step in Figure 10C, solid-phase epitaxy is performed, meaning that PCM 307A crystallizes from the top, but note the crystalline PCM 307C and the remaining amorphous portion 307A. Once this process is complete, in Figure 10D, crystalline PCM 307C is obtained throughout, with the top electrode 309 on top. Optionally, a sputtering cleaning step may be used after the deposition of the amorphous PCM to clean off any oxides that may form while the temperature rises to the seeding layer deposition temperature. Furthermore, this sputtering cleaning may deposit charges within the PCM layer surface, which may be useful for the orientation of the seeding layer. Advantageously, the bottom electrode 303 is in direct contact with the PCM 307C, and no interface exists. The structure in Figure 10D is ready for immediate use, compared to the embodiment in Figure 1, which has a seed layer 305 at the bottom of the PCM 307 and requires cycling before use.

[0052] In one or more embodiments, the bottom electrode 303 is significantly smaller than the top electrode 309, which extends across the entire cell. In Figure 2, a dome 311 is formed at the bottom because this is where the current density is highest. The highest current density is directly above the bottom electrode 303. Generally, a smaller diameter for the bottom electrode 303 is better (higher current density means lower RESET current). The diameter of the bottom electrode 303 should usually be the smallest possible with a given technology (current technology has a bottom electrode diameter of about 30 nm; this will change (decrease) with advances in fabrication technology). Generally, in one or more embodiments, the diameter of the bottom electrode 303 is 30-40 nm (20 nm is considered better if possible under certain technology nodes and process conditions), and the diameter of the top electrode 309 is several hundred nm.

[0053] Figure 4 shows an embodiment that is generally similar to the embodiment in Figure 1, except that a double seed layer is employed, which includes a crystalline (non-PCM) seed layer 305 outside the inner insulating layer 301A, and a crystalline (PCM) seed layer 313 outside the crystalline (non-PCM) seed layer 305 and inside the PCM 307. Therefore, Figure 4 shows an embodiment in which a crystalline PCM seed layer follows the crystalline non-PCM seed layer.

[0054] Generally, the seeding material may be PCM, but is not necessarily limited to PCM. Sb2Te3, which is a PCM, is used as the seed layer in one or more exemplary embodiments that are not limited.

[0055] Figure 5 shows an embodiment in which a separate seed layer is not employed. Rather, the entire crystalline homogeneous PCM layer 307 grows as, for example, Sb2Te3. In this embodiment, the seeding layer is the PCM. In the exemplary embodiment of Figure 5, the surface on which layer 307 is deposited is amorphous (e.g., Si3N4 or SiO2) and therefore cannot function as a template. It should be noted that in certain prior art devices, the surface of a (crystalline) Si(111) substrate was used as a template for growing the PCM layer. It should also be noted that Sb2Te3 is not necessarily the best PCM for all applications; in our experiments with other configurations, TiTe2 was used as the seed layer (which is not a PCM and therefore cannot be used as layer 307 in the embodiment of Figure 5). In the example of Figure 5, layer 307 is a PCM with properties that allow it to function as a seeding layer, i.e., it grows as a highly oriented layer. In general, in embodiments employing a separate seed layer (i.e., other than Figures 5 and 7), the seed layer may be either a PCM or a non-PCM.

[0056] Figure 6 shows an embodiment in which the bottom electrode is part of a layer in the stack and the device is constructed on the side. Note the inner insulating layer 601A and the outer insulating layer 601B (the inner and outer layers may be the same or different material); the bottom electrode 603 having a portion 603L extending to the right laterally; the crystalline seed layer 613 (the seed layer 613 may be either PCM or non-PCM); the crystalline homogeneous PCM layer 607; and the top electrode 609. In the exemplary embodiment shown, the z-axis of the crystalline PCM layer 607 and the crystalline seed layer 605 are aligned. The embodiment in Figure 6 is useful, for example, to provide a very narrow bottom electrode in at least one dimension (controlled by deposition rather than lithography). To fabricate the embodiment in Figure 6, for example, start from the bottom electrode 603 and the inner insulator 601A to the dotted line 604 (and layers 397, 399). At this point, the surface indicated by the dotted line 604 will extend to the full width. Next, a thin (e.g., 5 nm) blanket layer 603L of conductor is deposited on the top of 601A, adding further insulators 601A up to the top surface shown in Figure 6 (at this point, the outermost surface between 601A and 601B will extend across the entire width). At this stage, there is a stack of 601A having a vertical contact 603 and an embedded thin contact layer 603L that coincides with the top of the contact and extends across the entire width. The stack is patterned into fin-like ridges running from left to right, and these fins are "cut" to create facets 606, on which layers 613, 607, and 609 are deposited. The structure perpendicular to the page is very narrow. The area of ​​the lateral projection 603L from the electrode 603 is equal to the product of the layer thickness (controlled by deposition) and the width of the ridge in the page (controlled by lithography). This allows for one-dimensional control of the electrode by deposition rather than lithography. The portion 603 can be created in the same manner as in Figure 1, but in this embodiment, the dimension of the projection 603L is controlled, so it can be made larger. The projection 603L can also extend to the left. The upper surface of 601A can be aligned with the bottom of layer 613 or recessed below it.

[0057] Figure 7 shows an embodiment similar to the embodiment in Figure 6, except that a separate seed layer is not used as in Figure 5. Rather, the entire crystalline homogeneous PCM layer 607 is grown as, for example, Sb2Te3. In this embodiment, the seeding layer is PCM. In the exemplary embodiment of Figure 7, the surface on which layer 607 is deposited is amorphous (e.g., Si3N4 or SiO2) and therefore cannot function as a template. In the example of Figure 7, layer 607 is a PCM with properties that function as a seeding layer, that is, it grows as a highly oriented layer. The remaining fabrication of the embodiment in Figure 7 may be the same as that of Figure 6.

[0058] Figure 8 shows an embodiment having a lateral electrode 309L. Note the inner insulating layer 301A and outer insulating layer 301B, bottom electrode 303, crystal seed layer 305, crystalline homogeneous PCM layer 307, and lateral electrode 309L. In the exemplary embodiment shown, the z-axis of the crystalline PCM layer 307 and the crystal seed layer 305 are aligned. For explanatory convenience and generality, only a single lateral electrode 309L is shown on the left. However, a lateral electrode can also be provided on the right side of the PCM layer 307. In practice, the PCM layer 307 can be patterned into a mesa structure, and contacts can be created against the sidewalls of the mesa. In one non-limiting example, if the PCM layer 307 is patterned in a disk shape (viewed from above), the contacts will be a ring surrounding the PCM mesa.

[0059] Figure 9 shows an embodiment having a transverse crystalline seed layer 305L. Note the inner insulating layer 301A and outer insulating layer 301B, bottom electrode 303, transverse crystalline seed layer 305L, crystalline homogeneous PCM layer 307L, and top electrode 309. In the exemplary embodiment shown, the z axes of the crystalline PCM layer 307L and the transverse crystalline seed layer 305L are aligned. To create this structure, first the PCM layer 307L is deposited as an amorphous film (for example, by depositing it at room temperature) (at this point, the electrode material 309 can also be deposited). For example, the PCM layer and electrode material are patterned (for example, into a square or rectangle when viewed from above) by reactive ion etching to obtain a mesa. Each mesa sidewall is cleaned (for example, by Ar sputtering) and the seed layer 305L is deposited. The seed layer can be deposited, for example, from the left, at an angle of 45 degrees, so that only the left sidewall (or the right side if angled from the right) is coated (the mesa prevents material deposition on the opposite sidewall). The wafer is then annealed to enable solid-phase epitaxy of the PCM layer 307 templated from the seed layer 305. If seed layers were present on both sides, the amorphous material would grow crystals from each side, resulting in contact at undesirable seams or boundaries. If growth from both sides is desirable, the bottom electrode can be offset to some extent from the center of the cell to avoid approaching the seams or boundaries.

[0060] Figure 11 illustrates a particular novel aspect of one or more embodiments. In one or more embodiments, a known phase-change material is used, but it is epitaxially grown on a seed layer. In one or more embodiments, PCM 307, 307L, and 607 are ordered crystalline materials rather than having many randomly oriented PCM microcrystals. The prior art “crystalline” phase-change materials are actually polycrystalline. Figure 11 shows Sb2Te3 epitaxially grown on a substrate (not shown) having a seed layer (not shown) containing atomic layers separated by a van der Waals gap 1101. By employing a nucleation / seed layer (in this specification, nucleation layer and seed layer are synonymous), an epitaxially grown PCM with a van der Waals gap 1101 is obtained. Therefore, while certain prior art methods require the substrate to be used as a template, in one or more embodiments, the substrate itself does not need to be used as a template; rather, a seeding layer on the substrate is used. In the example in Figure 11, the material grows epitaxially with covalent bonds, and after a certain number of atomic layers, it instead forms a "satisfied layer" that is held to the next layer by van der Waals forces rather than covalent bonds, resulting in a literal gap. We have found embodiments in which thermal and electrical resistance increases due to the formation of van der Waals interfaces / gaps. The location of the van der Waals gap may depend on the material composition. For example, in the case of Sb2Te3, this will occur every 5 atomic planes between the two Te planes. In the case of GST225, this will occur every 9 atomic planes between the Te planes, in this case as well. Therefore, generally, in one or more embodiments, van der Waals gaps occur between Te planes, and depending on the PCM composition, this can be between approximately 5 to 9 atomic planes.

[0061] If it is desirable to avoid the formation of epitaxial (crystalline) GSTs, deposition can be performed at room temperature. For example, 100 nm GST225 can be deposited on 2.6 nm TiTe2 at 25°C, but the GST will be amorphous. On the other hand, to form epitaxial (crystalline) GSTs, deposition can be performed at an optimized temperature. For example, 100 nm GST225 can be deposited on 2.6 nm TiTe2 at 200°C, but the GST will be epitaxial (crystalline), and advantageously, the reset current will be reduced. If necessary, for example, as shown in Figure 4, a second seed layer can be used and deposition can be performed at an optimized temperature. For example, 100 nm GST225 can be deposited on 2.6 nm TiTe2 with a 5 nm Sb2Te3 layer on top, at 180°C, but the GST will be epitaxial (crystalline). Therefore, one or more embodiments result in a reduction of the reset current without requiring an alternating layer / superlattice. It should be noted that in one or more embodiments, the SET resistance does not decrease, and the resistance increases due to the van der Waals gap. Furthermore, PCM devices with low SET resistance are undesirable because they require a higher current to reset.

[0062] Referring now to Figures 12A and 12B, in one or more embodiments, the seeding layer can be placed anywhere as long as it is in contact with the amorphous PCM. For example, it can be placed within the PCM layer (Figure 12A) or on its sidewall (Figure 12B). Note in Figure 12A the inner insulating layer 301A, bottom electrode 303, intermediate crystal seed layer 305M, and lower amorphous PCM layer 307A-1 and upper amorphous PCM layer 307A-2 (these will grow into a crystalline form using seed layer 305M as a template). Compare Figure 12B with Figure 9. Note in Figure 12B the inner insulating layer 301A, bottom electrode 303, lateral (on the sidewall) crystal seed layer 305L, and amorphous PCM layer 307A (this will grow into a crystalline form using seed layer 305L as a template).

[0063] In one or more embodiments, a highly oriented crystalline layer is employed, and it should be noted that the PCM uses this layer as a template. Optionally, in one or more embodiments, (111) oriented crystals are used.

[0064] Therefore, in one embodiment, the phase change memory includes a homogeneous phase change material layer having an out-of-plane crystal axis aligned with the out-of-plane crystal axis of the crystal seed layer. The seed layer is, for example, Ti x Te y Sb x Te y , or similar. In one or more embodiments, a single-crystal homogeneous phase-change material layer is provided on a non-planar electrode substrate having an out-of-plane crystal axis perpendicular to the substrate. In another embodiment, a method for forming a phase-change memory (PCM) includes the steps of charging the substrate by Ar sputtering, followed by crystal deposition of a seed layer at an optimized temperature, and then crystal deposition of the phase-change material layer at an optimized temperature. Based on the teachings herein, those skilled in the art can select an appropriate temperature depending on the material and whether amorphous or crystalline form is desired.

[0065] Please refer to Figure 13 here. View 1299 shows a phase-change memory array; only a 2x2 array is shown, but any suitable number of cells can be used. The appropriate word line 1279 selects which bits are to be read or written. The word line is connected to the gate of transistor 1277. The gate of the transistor provides an electrical switching function. The drain of the transistor is connected to one terminal of memory element 1275 (e.g., the PCM described in any of the disclosed embodiments), and the other terminal of the memory element is connected to the corresponding bit line 1273. The source of the switch (transistor) is connected to ground.

[0066] There are many ways to read a bit. For example, the bit line can be charged to a certain voltage and then kept in a floating state, and the switch opens when the word line is set to high, allowing current to flow from the bit line through the memory element to ground. If the memory element is in the RESET phase, the bit line will remain charged because little current flows due to the high resistance of the PCM. However, if the PCM is in the SET phase, the bit line will discharge due to the low resistance of the PCM, and the voltage on the bit line will approach zero. A sensing amplifier can be used to detect the voltage on the bit line and determine whether the read bit was "0" or "1".

[0067] To write a bit, a voltage is applied to the word line, and then the bit is selected by pulsing the bit line using a SET or RESET pulse.

[0068] Furthermore, to avoid accidental bit writing, read operations are usually performed at a low voltage; those skilled in the art can heuristically select a suitable voltage based on the teachings herein.

[0069] View 1297 shows a crossbar array for AI computation; a general structure of such an array using prior art memory cells can be found in the IBM research paper “Tutorial: Brain-inspired computing using phase-change memory devices” by Abu Sebastian, Manuel Le Gallo, Geoffrey W. Burr, Sangbum Kim, Matthew BrightSky, and Evangelos Eleftheriou, Journal of Applied Physics 124, no. 11 (2018 Sep 21), pages 111101-1 to 111101-1. A voltage is applied on input line 1206 and the currents from each PCM element 1202 (e.g., a PCM as described in any of the disclosed embodiments) are summed on output line 1210. The current in each element is V(j) × G(k,j), where G is the conductance of element (k,j). Conductance is the resistance of a 1 / R or 1 / PCM element.

[0070] Therefore, as a result, output line 1210 is the sum of the products of the input voltage and the conductance of the array elements. This multiply accumulate (MAC) is a very common operation in artificial neural network computation, so crossbar arrays can be used to accelerate AI computation. Transistor 1203 is used to prevent the read current from flowing through another bit in the SET phase to another output line. Suppressing unwanted current flow in unselected cells is called "sneak path" current.

[0071] The matrices and vectors generally suggest weightings, peripheral circuit configurations, etc., which are well known to those skilled in the art.

[0072] A large array of memory devices can be implemented on a single chip. Within the limits of the manufacturing process and design specifications, any large number of cells 1202 or 1275 can be employed. View 1297 is an example of an analog AI application (multiplying matrix A 1295 by x vector 1293 to obtain output vector b 1291). The matrices and vectors generally represent weightings, peripheral circuit configurations, and the like, which would be well known to those skilled in the art. A controller (e.g., a known digital circuit configuration) and a power supply 1289 are coupled to the array and peripheral circuits in a known manner. Crossbar arrays themselves are well known; taking into account the teachings herein, those skilled in the art can implement such arrays with appropriate peripheral circuit configurations, controllers, and power supplies using the PCM cells of the invention disclosed herein.

[0073] The manufacturing of semiconductor devices involves various steps in the device patterning process. For example, the manufacturing of a semiconductor chip may begin with multiple device patterns generated by, for example, CAD (computer-aided design), followed by the task of replicating these device patterns on a substrate. The replicating process may involve the use of various exposure techniques and various subtractive (etching) and / or additive (deposition) material processing procedures. For example, in the photolithography process, a layer of photoresist material is first applied to a substrate and then selectively exposed according to a predetermined device pattern or multiple patterns. In the photoresist, the portion exposed to light or other ionizing radiation (e.g., ultraviolet light, electron beam, X-rays, etc.) may undergo some changes in its solubility in a particular solution. Next, the photoresist is developed in a developer, thereby removing the unirradiated portion (in the case of negative resist) or the irradiated portion (in the case of positive resist) of the resist layer, thereby creating a photoresist pattern or photomask. The photoresist pattern or photomask can then be copied or transferred to the substrate beneath the photoresist pattern.

[0074] Numerous techniques are used by those skilled in the art to remove material at various stages in the formation of semiconductor structures. In this specification, these processes are collectively referred to as “etching.” For example, etching includes techniques such as wet etching, dry etching, chemical oxide removal (COR) etching, ion milling, and reactive ion etching (RIE), all of which are known techniques for removing selected material when forming semiconductor structures. Standard Clean 1 (SC1) includes strong bases, typically ammonium hydroxide, and hydrogen peroxide. SC2 includes strong acids such as hydrochloric acid and hydrogen peroxide. Those skilled in the art are well familiar with etching techniques and applications; therefore, a more detailed description of such processes is not provided herein.

[0075] While the overall fabrication method and the resulting structures are novel, conventional semiconductor fabrication techniques and tools may be used for certain individual processing steps required to implement the method. These techniques and tools will be well known to those skilled in the art, based on the teachings herein. Furthermore, one or more of the processing steps and tools used to fabricate semiconductor devices are also described in several readily available publications, including, for example, James D. Plummer et al., Silicon VLSI Technology: Fundamentals, Practice, and Modeling 1st Edition, Prentice Hall, 2001, and PH. Holloway et al., Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices, Cambridge University Press, 2008 (both incorporated herein by reference). Although several individual processing steps are described herein, it should be emphasized that these steps are illustrative and that those skilled in the art may be familiar with several equally suitable alternatives that are applicable.

[0076] Please understand that the various layers and / or regions shown in the attached diagram may not be depicted to scale. Furthermore, one or more semiconductor layers of a type commonly used in such integrated circuit devices may not be explicitly shown in the given diagram for the sake of simplicity. This does not imply that the unshown semiconductor layers are omitted in actual integrated circuit devices.

[0077] Based on the above discussion, it can be seen that, as a general rule, an exemplary phase-change memory cell includes (inner) insulating layers 301A, 601A; and first electrodes 303, 603 / 603L embedded in the (inner) insulating layers. The outer ends of the first electrodes are locally flush with the outer surface of the (inner) insulating layer (e.g., the top surface in Figure 1, the surface of the facet in Figure 6). Second electrodes 309, 609 are also included, which are larger than the first electrodes and spaced apart from them. Compositionally homogeneous crystalline phase-change material layers 307, 307L, 607; and highly oriented seed layers 305, 305 / 313, 613 are also included. The crystalline structure of the homogeneous phase-change material layers correlates with the crystalline structure of the highly oriented seed layers. The compositionally homogeneous phase-change material layers and the highly oriented seed layers are located at least partially between the first and second electrodes.

[0078] The crystalline structure of the PCM correlates with the seed layer in that knowing the seeding layer reveals the structure of the PCM layer. The PCM layer is templated from the seed layer. In one or more embodiments, there is alignment along at least one direction.

[0079] When used herein, a compositionally homogeneous layer has a uniform atomic concentration of the various elements that make up the film throughout the entire film. Experimentally, this can be verified using secondary-ion mass spectrometry (SIMS). In this method, an ion beam is used to sputter the film, and the mass of the sputtered elements is measured. This allows for obtaining a depth profile of the elemental concentration within the film. If the film has multiple layers of different compositions, for example, a prior art superlattice structure, SIMS will show changes in composition as the film is sputtered. On the other hand, in a homogeneous film, depth profiling will show a constant elemental composition.

[0080] In one or more embodiments, for example, in all exemplary embodiments other than those shown in Figures 5 and 7, the compositionally homogeneous phase-change material layer and the highly oriented seed layer are made of different materials.

[0081] Optionally, in any or all of the disclosed embodiments, the seed layer has an out-of-plane crystal axis, and the homogeneous phase-change material layer has an out-of-plane crystal axis aligned with the out-of-plane crystal axis of the seed layer. See the Z-axis description.

[0082] In one or more embodiments, for example, in all exemplary embodiments other than Figures 5 and 7, the seed layer is optional, Ti x Te y and Sb x Te y A selection can be made from the group consisting of the following:

[0083] Optionally, in any or all of the disclosed embodiments, the homogeneous phase-change material layer includes a van der Waals gap.

[0084] In one or more embodiments, for example, in all exemplary embodiments other than those shown in Figures 5 and 7, the homogeneous phase-change material layer and the seed layer each have a (111) crystal orientation.

[0085] Optionally, in any or all of the disclosed embodiments, the homogeneous phase change material is GST and Sb x Te y The seed layer and homogeneous phase change material are selected from the group consisting of the following. Optionally, in such embodiments, the seed layer and homogeneous phase change material are selected from the group consisting of the following:

[0086] A seed layer of TiTe2 with a thickness of 0.25-5 nm and a homogeneous crystalline phase-change material layer of Sb2Te3 with a thickness of 1-100 nm;

[0087] A seed layer of TiTe2 with a thickness of 0.25 to 5 nm and a homogeneous crystalline phase-change material layer of Ge2Sb2Te5 with a thickness of 1 to 100 nm; and

[0088] A seed layer of Sb2Te3 with a size of 0.25-5 nm and a homogeneous crystalline phase-change material layer of Ge2Sb2Te5 with a size of 1-100 nm.

[0089] For example, referring to the embodiment of Figure 1, in some cases the seed layer 305 is generally planar and located outside the (inner) insulating layer 301A; the homogeneous phase-change material layer 307 is generally planar and located outside the seed layer; and the second electrode 309 is generally planar and located outside the homogeneous phase-change material layer.

[0090] For example, referring to the embodiment in Figure 3, in some cases the homogeneous phase-change material layer 307 is generally planar and located outside the (inner) insulating layer 301A; the seed layer 305 is generally planar and located outside the homogeneous phase-change material layer; and the second electrode 309 is generally planar and located outside the seed layer.

[0091] For example, referring to the embodiment in Figure 4, in some cases the seed layer 305 includes a first seed layer of non-phase-change material, and further includes a second seed layer 313 of phase-change material. The first seed layer 305 is generally planar and located outside the (inner) insulating layer 301A; the second seed layer 313 is generally planar and located outside the first seed layer; the homogeneous phase-change material layer 307 is generally planar and located outside the second seed layer; and the second electrode 309 is generally planar and located outside the homogeneous phase-change material layer. Optionally, in such embodiments, the first seed layer includes TiTe2 of 0.25 to 5 nm, the second seed layer includes Sb2Te3 of 1 to 5 nm, and the homogeneous phase-change material layer includes Ge2Sb2Te5 of 1 to 100 nm.

[0092] For example, referring to the embodiment in Figure 6, the first electrode may in some cases have a generally vertical portion 603 and a horizontal (lateral) projection 603L; the (inner) insulating layer 601A has a stepped region (facet 606), and the horizontal projection of the first electrode extends to the surface of the stepped region. Furthermore, the seed layer 613 is located outside the (inner) insulating layer and is in contact with the horizontal projection 603L and the stepped region of the first electrode. The homogeneous phase-change material layer 607 is located outside the seed layer; and the second electrode 609 is located outside the homogeneous phase-change material layer.

[0093] For example, referring to the embodiment in Figure 6, in some cases the seed layer 305 is located outside the (inner) insulating layer 301A; the homogeneous phase-change material layer 307 is located outside the seed layer 305; and the second electrode 309L is located on at least one side of the homogeneous phase-change material layer and the seed layer.

[0094] For example, referring to the embodiment in Figure 6, in some cases the homogeneous phase-change material layer 307L is located outside the (inner) insulating layer 301A; the second electrode 309 is located outside the homogeneous phase-change material layer; and the seed layer 305L is located on a side (preferably only a single side) of the homogeneous phase-change material layer.

[0095] For example, referring to the embodiment in Figure 12A, in some cases the homogeneous phase-change material layer is located outside the (inner) insulating layer 301A; the second electrode 309 (not shown in Figure 12A; refer to any of the other embodiments such as Figures 1 and 3) is located outside the homogeneous phase-change material layer; and the seed layer 305M is located within the homogeneous phase-change material layer. Figure 12A shows the amorphous homogeneous phase-change material layers in 307A-1 and 307A-2 before crystallization.

[0096] In all of these embodiments, the second electrode is larger than the first electrode, in that the second electrode has a cross-sectional area at least six times that of the first electrode.

[0097] In another embodiment, referring to Figure 13, the phase-change memory array includes a plurality of horizontal lines 1206 or 1279; a plurality of vertical lines 1210 or 1273 intersecting the plurality of horizontal lines at a plurality of cell locations; and a plurality of phase-change memory cells 1202 or 1275 located at each of the plurality of cell locations. A plurality of transistors 1203, 1277 are associated with each of the plurality of phase-change memory cells. Each of the phase-change memory cells may conform to any of the embodiments disclosed herein. Optionally, a controller 1289 may be provided to control reading, writing, MAC calculation, etc.

[0098] In another embodiment, an exemplary method of operation includes the steps of providing array 1299 and using a controller to store logical 1s in a first subset of cells and logical 0s in a second subset of cells; and reading the stored logical 1s and 0s. Alternatively, an exemplary method of operation includes providing array 1297 and using a controller to perform MAC calculations.

[0099] In a further embodiment, an exemplary method for forming a phase-change memory cell includes the step of providing an initiation structure comprising a substrate, an insulating layer outside the substrate, and a first electrode embedded in the insulating layer. The outer edge of the first electrode is locally flush with the outer surface of the insulating layer. Further steps include depositing a highly oriented crystal seed layer on the outer surface of the insulating layer and the outer edge of the first electrode; epitaxially growing a compositionally homogeneous crystalline phase-change material layer on the highly oriented crystal seed layer; and depositing a top electrode material on the compositionally homogeneous crystalline phase-change material layer. In one or more embodiments, for example, a thin (0.25 to 5 nm) crystal seed layer is deposited with the z-axis orientation of the crystal perpendicular to the substrate, and a crystalline phase-change material layer is deposited with its z-axis aligned with the z-axis of the seed layer. In one or more embodiments, the substrate can be charged by Ar sputtering before crystal deposition of the seed layer.

[0100] In a further embodiment, another exemplary method for forming a phase-change memory cell includes the step of providing an initiation structure comprising a substrate, an insulating layer outside the substrate, and a first electrode embedded in the insulating layer. The outer edge of the first electrode is locally flush with the outer surface of the insulating layer. Further steps include: depositing an amorphous phase-change material layer on the outer surface of the insulating layer and the outer edge of the first electrode (e.g., at room temperature); depositing a highly oriented crystal seed layer on the outer surface of the amorphous phase-change material layer at a temperature below the crystallization temperature of the first amorphous phase-change material layer to create the resulting structure; and annealing the resulting structure at a temperature above the crystallization temperature of the first amorphous phase-change material layer to induce solid-phase crystallization of the amorphous phase-change material layer by template formation from the seeding layer. Optionally, a sputtering cleaning step may be used after the deposition of the amorphous PCM to clean oxides that may form while the temperature rises to the seeding layer deposition temperature. Furthermore, this sputtering cleaning process can deposit electric charge within the PCM layer surface, which may be helpful in aligning the seeding layer.

[0101] In a further embodiment, another exemplary method for forming a phase-change memory cell includes the step of providing an initiation structure comprising a substrate, an insulating layer outside the substrate, and a first electrode embedded in the insulating layer. The outer end of the first electrode is locally flush with the outer surface of the insulating layer, and the insulating layer is amorphous. Further steps include preparing the outer surface of the amorphous insulating layer to cause orientation of a compositionally homogeneous crystalline phase-change material layer to be epitaxially grown thereafter; epitaxially growing the compositionally homogeneous crystalline phase-change material layer on the prepared outer surface of the amorphous insulating layer at a temperature at which the compositionally homogeneous crystalline phase-change material layer grows crystallinely; and depositing a top electrode material on the compositionally homogeneous crystalline phase-change material layer. Thus, in one or more such “seed-layer-free” embodiments, (i) prepare an amorphous surface; and (ii) deposit the PCM at a temperature at which it grows crystallinely (e.g., 150°C to 250°C). Preparing an amorphous surface may involve, for example, selecting a PCM material that deposits charges within the surface of an amorphous layer and organizes them into a highly oriented structure during deposition. An example of such a PCM material is Sb2Te3.

[0102] Those skilled in the art will understand that the exemplary structures discussed above can be distributed in their raw form (i.e., a single wafer with multiple unpackaged chips), as bare dies, or in a packaged form, or incorporated as part of an intermediate or final product that benefits from phase-change memory cells in a phase-change memory array and similar structures having a crystal structure aligned to a seed layer.

[0103] Integrated circuits according to several aspects of the present invention, having a crystal structure aligned to a seed layer, such as phase-change memory cells in a phase-change memory array and the like, can be employed in essentially any application and / or electronic system where such would be beneficial. Those skilled in the art will be able to envision other implementations and applications of the embodiments disclosed herein, based on the teachings of this disclosure provided herein.

[0104] Now, referring to Figure 14, this figure shows a computing environment according to one embodiment of the present invention (for example, for implementing a design process like that shown in Figure 15).

[0105] Various aspects of this disclosure are illustrated by explanatory text, flowcharts, block diagrams of computer systems, and / or block diagrams of mechanical logic included in embodiments of computer program products (CPPs). With respect to any flowchart, depending on the technology involved, operations may be performed in a different order than those shown in a given flowchart. For example, again, depending on the technology involved, two operations shown in consecutive blocks of a flowchart may be performed in reverse order, as a single integrated step, simultaneously, or with at least partial time overlap.

[0106] Embodiments of a computer program product ("CPP Embodiment" or "CPP") are terms used in this disclosure to describe any set of one or more storage media ("mediums") that are collectively comprised of one or more storage devices that collectively contain machine-readable code corresponding to instructions and / or data for performing computer operations specified in a given CPP claim. "Storage device" is any tangible device capable of holding and storing instructions for use by a computer processor. Computer-readable storage media may, but are not limited to, electronic storage media, magnetic storage media, optical storage media, electromagnetic storage media, semiconductor storage media, mechanical storage media, or any preferred combination thereof. Some known types of storage devices, including these media, include diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices (such as pits / lands formed on the main surface of a punch card or disk), or any suitable combination of the foregoing. When the term "computer-readable storage medium" is used in this disclosure, it shall not be construed as storage in the form of a temporary signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides, optical pulses passing through optical fiber cables, electrical signals communicated through wires, and / or other transmission media.As those skilled in the art will understand, data is typically moved at several intermittent points during the normal operation of a storage device, such as during access, defragmentation, or garbage collection. However, since data is not temporary while it is stored, the above does not mean that the storage device is temporary.

[0107] The computing environment 100 includes an example of an environment for executing at least a portion of the computer code involved in carrying out the method of the present invention, such as a system 200 for controlling the design and / or fabrication of semiconductors (see Figure 15). In addition to block 200, the computing environment 100 includes, for example, a computer 101, a wide area network (WAN) 102, an end-user device (EUD) 103, a remote server 104, a public cloud 105, and a private cloud 106. In this embodiment, the computer 101 includes a processor set 110 (including a processing circuit configuration 120 and a cache 121), a communication fabric 111, volatile memory 112, persistent storage 113 (including an operating system 122 and the block 200 identified above), a peripheral device set 114 (including a user interface (UI) device set 123, storage 124, and an Internet of Things (IoT) sensor set 125), and a network module 115. The remote server 104 includes a remote database 130. The public cloud 105 includes a gateway 140, a cloud orchestration module 141, a host physical machine set 142, a virtual machine set 143, and a container set 144.

[0108] Computer 101 may take the form of a desktop computer, laptop computer, tablet computer, smartphone, smartwatch or other wearable computer, mainframe computer, quantum computer, or any other form of computer or mobile device currently known or to be developed in the future that is capable of executing programs, accessing networks, or querying databases such as remote database 130. As is well understood in the field of computer technology, and depending on the technology, the execution of a computer implementation method may be distributed among multiple computers and / or between multiple locations. On the other hand, in this presentation of the computing environment 100, in order to keep the presentation as concise as possible, the detailed discussion focuses on a single computer, specifically computer 101. Computer 101 may be located in the cloud, although it is not shown in the cloud in Figure 14. On the other hand, computer 101 is not required to be located in the cloud, except to any extent that can be definitively shown.

[0109] The processor set 110 includes one or more computer processors of any type currently known or to be developed in the future. The processing circuit configuration 120 may be distributed across multiple packages, for example, multiple interconnected integrated circuit chips. The processing circuit configuration 120 may implement multiple processor threads and / or multiple processor cores. The cache 121 is memory located within the processor chip package and is typically used for data or code that should be available for rapid access by threads or cores running on the processor set 110. The cache memory is typically configured in multiple levels, depending on its relative proximity to the processing circuit configuration. Alternatively, some or all of the cache for the processor set may be located "off-chip". In some computing environments, the processor set 110 may operate using qubits and be designed to perform quantum computing.

[0110] Computer-readable program instructions are typically loaded onto computer 101 and cause the processor set 110 of computer 101 to execute a series of operational steps, thereby realizing the computer implementation method. As a result, the instructions thus executed instantiate the methods specified in the flowcharts and / or descriptions of the computer implementation methods contained herein (collectively referred to as the "Methods of the Invention"). These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache 121 and other storage media discussed below. The program instructions and associated data are accessed by the processor set 110 to control and direct the execution of the Methods of the Invention. In computing environment 100, at least some of the instructions for executing the Methods of the Invention may be stored in blocks 200 within persistent storage 113.

[0111] The communication fabric 111 is a signal conduction path that enables various components of the computer 101 to communicate with one another. Typically, this fabric consists of switches and conductive paths such as buses, bridges, physical input / output ports, and similar components. Other types of signal communication paths, such as optical fiber communication paths and / or wireless communication paths, may be used.

[0112] The volatile memory 112 is any type of volatile memory that is currently known or may be developed in the future. Examples include dynamic random access memory (RAM) or static RAM. Typically, volatile memory 112 is characterized by random access, but this is not required unless explicitly stated. In computer 101, the volatile memory 112 is located in a single package and resides inside computer 101, but alternatively or additionally, the volatile memory may be distributed across multiple packages and / or located externally to computer 101.

[0113] The persistent storage 113 is any form of non-volatile storage for a computer, currently known or to be developed in the future. The non-volatility of this storage means that the stored data is maintained regardless of whether power is supplied to the computer 101 and / or directly to the persistent storage 113. The persistent storage 113 may be read-only memory (ROM), but typically at least a portion of the persistent storage allows for writing, deleting, and rewriting of data. Some well-known forms of persistent storage include magnetic disks and solid-state storage devices. The operating system 122 may take several forms, such as various known proprietary operating systems employing a kernel or open-source portable operating system interface type operating systems. The code contained in block 200 typically includes at least some computer code involved in performing the method of the present invention.

[0114] The peripheral device set 114 includes a set of peripheral devices for the computer 101. Data communication connections between the computer 101's peripheral devices and other components may be implemented in various ways, such as Bluetooth® connections, near-field communication (NFC) connections, connections made by cables (such as Universal Serial Bus (USB) type cables), insert-type connections (e.g., Secure Digital (SD) cards), connections made through local area communication networks, and even connections made through wide area networks such as the Internet. In various embodiments, the UI device set 123 may include components such as a display screen, speaker, microphone, wearable devices (such as goggles and smartwatches), keyboard, mouse, printer, touchpad, game controller, and haptic devices. Storage 124 is external storage such as an external hard drive, or insertable storage such as an SD card. Storage 124 may be persistent and / or volatile. In some embodiments, storage 124 may take the form of a quantum computing memory device for storing data in the form of qubits. In embodiments where computer 101 requires a large amount of storage (for example, when computer 101 locally stores and manages a large database), this storage may be provided by peripheral storage devices designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. The IoT sensor set 125 consists of sensors that can be used in an Internet of Things application. For example, one sensor may be a thermometer and another may be a motion detector.

[0115] The network module 115 is a collection of computer software, hardware, and firmware that enables computer 101 to communicate with other computers via the WAN 102. The network module 115 may include hardware such as a modem or Wi-Fi signal transceiver, software for packetizing and / or depacketizing data for communication network transmission, and / or web browser software for transmitting data over the internet. In some embodiments, the network control and network forwarding functions of the network module 115 are performed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing Software-Defined Networking (SDN)), the control and forwarding functions of the network module 115 are performed on physically separate devices, such that the control function manages several different network hardware devices. Computer-readable program instructions for performing the method of the present invention can typically be downloaded from an external computer or external storage device to computer 101 via a network adapter card or network interface included in the network module 115.

[0116] WAN102 is any wide area network (e.g., the Internet) that can transmit computer data over non-local distances using any currently known or future-developed technology for transmitting computer data. In some embodiments, WAN102 may be replaced and / or complemented by a local area network (LAN), such as a Wi-Fi network, designed to transmit data between devices located in a local area. WANs and / or LANs typically include computer hardware such as copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and edge servers.

[0117] The end-user device (EUD) 103 is any computer system used and controlled by an end-user (e.g., a customer of the company operating computer 101), and may take any of the forms discussed above in relation to computer 101. The EUD 103 typically receives useful and helpful data from the operation of computer 101. For example, in a hypothetical scenario where computer 101 is designed to provide recommendations to an end-user, these recommendations would typically be transmitted from computer 101's network module 115 to the EUD 103 via the WAN 102. Thus, the EUD 103 can display or otherwise present recommendations to the end-user. In some embodiments, the EUD 103 may be a client device such as a thin client, heavy client, mainframe computer, or desktop computer.

[0118] The remote server 104 is any computer system that provides at least some data and / or functionality to computer 101. The remote server 104 may be controlled and used by the same entity that operates computer 101. The remote server 104 represents a machine that collects and stores useful and helpful data for use by other computers, such as computer 101. For example, in a hypothetical case where computer 101 is designed and programmed to provide recommendations based on historical data, this historical data may be provided to computer 101 from the remote database 130 of the remote server 104.

[0119] The public cloud 105 is any computer system available for use by multiple entities, providing on-demand availability with respect to computer system resources and / or other computing capabilities, particularly data storage (cloud storage) and computing capabilities, without requiring direct and active management by the user. Cloud computing typically leverages resource sharing to achieve coherence and economies of scale. Direct and active management of the computing resources of the public cloud 105 is performed by the computer hardware and / or software of the cloud orchestration module 141. The computing resources provided by the public cloud 105 are typically implemented by virtual computing environments running on various computers that make up the computers of the host physical machine set 142, which is a universe of physical computers located within and / or available to the public cloud 105. The virtual computing environment (VCE) typically takes the form of virtual machines from the virtual machine set 143 and / or containers from the container set 144. These VCEs may be stored as images and may be transferred between hosts of various physical machines, either as images or after instantiation of the VCEs. The cloud orchestration module 141 manages the transfer and storage of images, deploys new VCE instances, and manages the active instantiation of VCE deployments. The gateway 140 is a collection of computer software, hardware, and firmware that enables the public cloud 105 to communicate through the WAN 102.

[0120] Here, some further explanation of virtualized computing environments (VCEs) is provided. A VCE can be stored as an "image." A new active instance of a VCE can be instantiated from an image. Two well-known types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to an operating system feature where the kernel allows for the existence of multiple isolated user-space instances called containers. These isolated user-space instances typically behave like actual computers in terms of the programs running within them. Computer programs running on a normal operating system can utilize all of that computer's resources, including connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, programs running inside a container can only use the contents of the container and the devices allocated to the container; this feature is known as containerization.

[0121] The private cloud 106 is similar to the public cloud 105, except that its computing resources are available only for use by a single enterprise. While the private cloud 106 is shown as being in communication with the WAN 102, in other embodiments, the private cloud may be completely isolated from the internet and accessible only via a local / private network. A hybrid cloud is a combination of multiple clouds of different types (e.g., private, community, or public cloud types), often implemented by different vendors. Each of the multiple clouds remains a separate, discrete entity, but the larger hybrid cloud architecture is bound together by standardized or proprietary technologies that enable orchestration, management, and / or data / application portability between the multiple configuration clouds. In this embodiment, both the public cloud 105 and the private cloud 106 are part of a larger hybrid cloud.

[0122] [Exemplary design processes used in the design, manufacturing, and / or testing of semiconductors]

[0123] In one or more embodiments, computer-aided semiconductor integrated circuit design simulation, testing, layout, and / or manufacturing are used. In this regard, Figure 15 shows a block diagram of an exemplary design flow 700 used, for example, for semiconductor IC logic design, simulation, testing, layout, and manufacturing. The design flow 700 includes processes, machines, and / or mechanisms for processing a design structure or device and generating a logically or otherwise functionally equivalent representation of the design structure and / or device, such as one that can be analyzed using the methods disclosed herein or similar methods. The design structure processed and / or generated by the design flow 700 may be encoded on a machine-readable storage medium so as to include data and / or instructions that, when executed on a data processing system or otherwise processed, generate a logically, structurally, mechanically, or otherwise functionally equivalent representation of a hardware component, circuit, device, or system. The machines include, but are not limited to, any machines used in IC design processes such as designing, manufacturing, or simulating circuits, components, devices, or systems. For example, the machine may include a lithography machine, a machine and / or equipment for generating a mask (e.g., an e-beam writer), a computer or equipment for simulating a design structure, any device used in a manufacturing or testing process, or any machine for programming a functionally equivalent representation of a design structure into any medium (e.g., a machine for programming a programmable gate array).

[0124] Design Flow 700 may vary depending on the type of representation being designed. For example, Design Flow 700 for building an application-specific IC (ASIC) may differ from Design Flow 700 for designing a standard component, or Design Flow 700 for instantiating a design on a programmable array such as a programmable gate array (PGA) or field programmable gate array (FPGA) provided by Altera® or Xilinx®.

[0125] Figure 15 preferably shows a plurality of such design structures, including an input design structure 720 processed by the design process 710. The design structure 720 may be a design structure for a logic simulation that is generated and processed by the design process 710 to produce a logically equivalent functional representation of a hardware device. When processed by the design process 710, the design structure 720 may additionally or alternatively comprise data and / or program instructions that generate a functional representation of the physical structure of the hardware device. Whether or not it represents functional and / or structural design features, the design structure 720 may be generated using electronic computer-aided design (ECAD), such as that implemented by a core developer / designer. Encoded on a gate array or storage medium or similar, the design structure 720 may be accessed and processed by one or more hardware and / or software modules within the design process 710 to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system. Therefore, the design structure 720 may comprise files or other data structures, including human- and / or machine-readable source code, compiled structures, and computer-executable code structures, which, when processed by a design or simulation data processing system, functionally simulate or otherwise represent a circuit or other level of hardware logic design. Such data structures may comprise hardware description language (HDL) design entities or other data structures that conform to and / or are compatible with lower-level HDL design languages ​​such as Verilog and VHDL, and / or higher-level design languages ​​such as C or C++.

[0126] The design process 710 preferably employs and incorporates hardware and / or software modules for synthesizing, translating, or otherwise processing functional equivalents of the design / simulation of components, circuits, devices, or logic structures to generate a netlist 780 which may include design structures such as design structures 720. The netlist 780 may comprise compiled or otherwise processed data structures representing, for example, lists of wires, discrete components, logic gates, control circuits, I / O devices, models, etc., describing connections to other elements and circuits in the design of an integrated circuit. The netlist 780 may be synthesized using an iterative process in which the netlist 780 is resynthesized once or more times depending on the design specifications and parameters of the device. As with other types of design structures described herein, the netlist 780 may be recorded on a machine-readable data storage medium or programmed into a programmable gate array. The medium may be a non-volatile storage medium such as a magnetic or optical disk drive, a programmable gate array, CompactFlash, or other flash memory. Additionally or alternatively, the medium may be system or cache memory, buffer space, or other suitable memory.

[0127] The design process 710 may include hardware and software modules for processing various types of input data structures, including a netlist 780. Such data structure types may, for example, reside within a library element 730 and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations for a given manufacturing technology (e.g., different technology nodes, 32nm, 45nm, 90nm, etc.). The data structure types may further include design specifications 740, characteristic data 750, verification data 760, design rules 770, and a test data file 785 which may include input test patterns, output test results, and other test information. The design process 710 may further include standard mechanical design processes, such as stress analysis, thermal analysis, simulation of mechanical events, and process simulation of operations such as molding, casting, and die-pressing. Those skilled in mechanical design will understand the range of possible mechanical design tools and applications used in the design process 710 without departing from the scope of the present invention. Design process 710 may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checks, placement, and routing operations.

[0128] The design process 710 employs and incorporates logic and physical design tools, such as an HDL compiler and a simulation model builder, to process the design structure 720 together with some or all of the illustrated supporting data structures, along with any further mechanical designs or data (if applicable), in order to generate a second design structure 790. The design structure 790 resides on a storage medium or on a programmable gate array in a data format used to exchange data for mechanical devices and structures (e.g., IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures). Similar to the design structure 720, the design structure 790 preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on a data storage medium and, when processed by an ECAD system, generate logically or otherwise functionally equivalent forms of one or more IC designs or similar. In one embodiment, the design structure 790 may comprise a compiled executable HDL simulation model that functionally simulates the device to be analyzed.

[0129] The design structure 790 may also employ a data format used for exchanging integrated circuit layout data and / or symbolic data formats (e.g., GDSII (GDS2), GL1, OASIS, map files, or any other preferred format for storing such design data structures). The design structure 790 may contain information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, metal levels, vias, geometry, data for routing through the manufacturing line, and any other data required by the manufacturer or other designer / developer to produce a device or structure as described herein (e.g., lib files). The design structure 790 may then proceed to stage 795, where, for example, the design structure 790 proceeds to tape-out, is released to manufacturing, released to a mask house, sent to another design company, and sent back to a customer, etc.

[0130] The examples of embodiments described herein are intended to provide a general understanding of various embodiments and are not intended to serve as a complete description of all elements and features of devices and systems that may use the circuits and techniques described herein. Many other embodiments will become apparent to those skilled in the art based on the teachings herein; other embodiments can be used, derived therefrom, and as a result, structural and logical substitutions and modifications can be made without departing from the scope of this disclosure. It should also be noted that in some alternative implementations, some of the steps of the exemplary method may be performed in an order other than that shown in the drawings. For example, two steps shown consecutively may actually be performed substantially simultaneously, or certain steps may be performed in reverse order depending on the functionality involved. The drawings are also reproductions only and are not drawn to scale. Therefore, this specification and the drawings should be considered illustrative rather than restrictive.

[0131] In this specification, for convenience only, embodiments are referred to individually and / or collectively as “embodiments,” but this is not intended to limit the scope of the application to any single embodiment or inventive concept when more than one embodiment or inventive concept is actually shown. Therefore, while specific embodiments have been illustrated and described in this specification, it should be understood that mechanisms achieving the same objective can be substituted for the specific embodiments shown; in other words, this disclosure is intended to cover all kinds of adaptations or variations of various embodiments. Combinations of the embodiments described herein, and other embodiments not specifically described herein, will become apparent to those skilled in the art in light of the teachings herein.

[0132] The technical terms used herein are intended to describe only specific embodiments and are not intended to limit them. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form unless otherwise explicitly indicated by the context. The terms “comprises” and / or “comprising,” where used herein, specify the presence of the described features, steps, actions, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, actions, elements, components, and / or groups thereof. Terms such as “bottom,” “top,” “up,” “up,” “below,” and “down” are used to indicate the relative positioning of elements or structures to each other, rather than relative height. Where a layer of a structure is described herein as being “up” another layer, it will be understood that there may or may not be intermediate elements or layers between the two specified layers. Where a layer is described as being “directly above” another layer, it indicates direct contact between the two layers. When used herein and in the appended claims, "approximately" means within plus or minus 10 percent.

[0133] Any means or step-plus-function elements in the following claims, corresponding structures, materials, actions, and equivalents are intended to include any structures, materials, or actions for performing a function in combination with other specifically claimed elements. While descriptions of various embodiments have been presented for illustrative and explanatory purposes, they are not intended to be exclusive or limitful to the disclosed forms. Many modifications and variations that do not deviate from this scope will be apparent to those skilled in the art. The embodiments have been selected and described to best illustrate the principle and practical application, and to enable those skilled in the art to understand various embodiments with various modifications suitable for specific intended uses.

[0134] The abstract is provided in accordance with 37 C. FR § 1.76(b), which requires an abstract that allows readers to quickly grasp the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the claims or their meaning. In addition, it is evident in the detailed description above that, for the purpose of simplifying the disclosure, various features are grouped into a single embodiment. This method of disclosure should not be interpreted as reflecting an intention that the claimed embodiments require more features than expressly described in each claim. Rather, as reflected in the attached claims, the claimed subject matter may consist of fewer features than all the features of a single embodiment combined. Therefore, the following claims are incorporated herein into the detailed description, and each claim stands alone as separately claimed subject matter.

[0135] Based on the teachings provided herein, those skilled in the art will be able to envision other implementations and applications of the methods and disclosed embodiments. While exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that exemplary embodiments are not limited to those exact embodiments, and that various other changes and modifications thereto can be made by those skilled in the art without departing from the scope of the appended claims.

Claims

1. Insulating layer; A first electrode is embedded in the insulating layer, wherein the outer end of the first electrode is locally flush with the outer surface of the insulating layer; A second electrode that is larger than the first electrode and spaced further apart from the first electrode; A compositionally homogeneous crystalline phase-changing material layer; and A highly oriented seed layer, where the crystal structure of the homogeneous phase-change material layer is correlated with the crystal structure of the highly oriented seed layer; Equipped with, Here, the compositionally homogeneous phase change material layer and the highly oriented seed layer are at least partially located between the first and second electrodes. Phase-change memory cell.

2. The phase change memory cell according to claim 1, wherein the compositionally homogeneous phase change material layer and the highly oriented seed layer are made of different materials.

3. The phase change memory cell according to claim 2, wherein the seed layer has an out-of-plane crystal axis, and the homogeneous phase change material layer has an out-of-plane crystal axis aligned with the out-of-plane crystal axis of the seed layer.

4. The aforementioned seed layer is Ti ｘ Te ｙ and Sb ｘ Te ｙ A phase-change memory cell according to claim 3, selected from the group consisting of the following:

5. The phase-change memory cell according to claim 3, wherein the homogeneous phase-change material layer has a van der Waals gap.

6. The phase change memory cell according to claim 3, wherein the homogeneous phase change material layer and the seed layer each have a crystalline orientation.

7. The homogeneous phase-change material is GST and Sb ｘ Te ｙ A phase-change memory cell according to claim 3, selected from the group consisting of the following:

8. The seed layer and the homogeneous phase change material are 0.25 to 5 nm of TiTe ２ for the seed layer and 1 to 100 nm of Sb ２ Te ３ for the homogeneous crystal phase change material layer; TiTe of 0.25 to 5 nm ２ The seed layer and Ge of 1 to 100 nm ２ Sb ２ Te ５ The homogeneous crystalline phase change material layer; and Sb 0.25-5 nm ２ Te ３ The seed layer and Ge of 1 to 100 nm ２ Sb ２ Te ５ The homogeneous crystalline phase change material layer A phase-change memory cell according to claim 7, selected from the group consisting of the following:

9. The seed layer is generally planar and located outside the insulating layer; The homogeneous phase-change material layer is generally planar and located outside the seed layer; and The second electrode is generally planar and located outside the homogeneous phase-change material layer. The phase-change memory cell according to claim 3.

10. The homogeneous phase-change material layer is generally planar and located outside the insulating layer; The seed layer is generally planar and located outside the homogeneous phase-change material layer; and The second electrode is generally planar and located outside the seed layer. The phase-change memory cell according to claim 3.

11. The seed layer has a first seed layer of non-phase change material and further has a second seed layer of phase change material, where, The first seed layer is generally planar and located outside the insulating layer; The second seed layer is generally planar and lies outside the first seed layer; The homogeneous phase-change material layer is generally planar and located outside the second seed layer; and The second electrode is generally planar and located outside the homogeneous phase-change material layer. The phase-change memory cell according to claim 3.

12. The first seed layer is a TiTe of 0.25 to 5 nm. ２ The second seed layer includes 1-5 nm Sb ２ Te ３ The homogeneous phase change material layer includes Ge with a wavelength of 1 to 100 nm. ２ Sb ２ Te ５ A phase change memory cell according to claim 11, having the features described above.

13. The first electrode generally has a vertical portion and a horizontal projection; The insulating layer has a stepped region, and the horizontal projection of the first electrode extends to the surface of the stepped region; The seed layer is located outside the insulating layer and is in contact with the horizontal protrusion and the stepped region of the first electrode; The homogeneous phase-change material layer is located outside the seed layer; and The second electrode is located outside the homogeneous phase-change material layer. The phase-change memory cell according to claim 3.

14. The seed layer is located outside the insulating layer; The homogeneous phase-change material layer is located outside the seed layer; and The second electrode is located on at least one side surface of the homogeneous phase-change material layer and the seed layer, The phase-change memory cell according to claim 3.

15. The homogeneous phase-change material layer is located outside the insulating layer; The second electrode is located outside the homogeneous phase-change material layer; and The seed layer is located on the side surface of the homogeneous phase change material layer. The phase-change memory cell according to claim 3.

16. The homogeneous phase-change material layer is located outside the substrate insulating layer; The second electrode is located outside the homogeneous phase-change material layer; and The seed layer is located within the homogeneous phase change material layer. The phase-change memory cell according to claim 3.

17. The phase change memory cell according to claim 3, wherein the second electrode is larger than the first electrode, in that the second electrode has a cross-sectional area at least six times that of the first electrode.

18. Multiple horizontal lines; Multiple vertical lines that intersect the aforementioned multiple horizontal lines at multiple cell positions; A plurality of phase change memory cells located at each of the aforementioned plurality of cell locations; and Multiple transistors associated with each of the aforementioned multiple phase-change memory cells; Equipped with, Here, each of the phase-change memory cells is Insulating layer; A first electrode is embedded in the insulating layer, wherein the outer end of the first electrode is locally flush with the outer surface of the insulating layer; A second electrode that is larger than the first electrode and spaced further apart from the first electrode; A compositionally homogeneous crystalline phase-changing material layer; and A highly oriented seed layer, where the crystal structure of the homogeneous phase-change material layer is correlated with the crystal structure of the highly oriented seed layer; It has, Here, the compositionally homogeneous phase change material layer and the highly oriented seed layer are at least partially located between the first and second electrodes. Phase-change memory array.

19. The phase-change memory array according to claim 18, wherein the compositionally homogeneous phase-change material layer and the highly oriented seed layer are made of different materials.

20. The phase-change memory array according to claim 19, wherein the seed layer includes out-of-plane crystal axes, and the homogeneous phase-change material layer includes out-of-plane crystal axes aligned with the out-of-plane crystal axes of the seed layer.

21. The phase-change memory array according to claim 20, wherein the homogeneous phase-change material layer includes a van der Waals gap.

22. The phase-change memory array according to claim 21, wherein the homogeneous phase-change material layer and the seed layer each include crystal orientation.

23. A step of providing an initial structure comprising a substrate, an insulating layer outside the substrate, and a first electrode embedded in the insulating layer, wherein the outer end of the first electrode is locally flush with the outer surface of the insulating layer; A step of depositing a highly oriented crystal seed layer on the outer surface of the insulating layer and on the outer end of the first electrode; The step of epitaxially growing a compositionally homogeneous crystalline phase change material layer on the aforementioned highly oriented crystalline seed layer; and The step of depositing the top electrode material onto the compositionally homogeneous crystalline phase-change material layer. A method for forming a phase-change memory cell comprising the above.

24. A step of providing an initial structure comprising a substrate, an insulating layer outside the substrate, and a first electrode embedded in the insulating layer, wherein the outer end of the first electrode is locally flush with the outer surface of the insulating layer; A step of depositing an amorphous phase-change material layer on the outer surface of the insulating layer and on the outer end of the first electrode; A step of depositing a highly oriented crystal seed layer on the outer surface of the amorphous phase-change material layer at a temperature lower than the crystallization temperature of the first amorphous phase-change material layer to create the resulting structure; and The step of annealing the resulting structure at a temperature above the crystallization temperature of the first amorphous phase-change material layer to induce solid-phase crystallization of the amorphous phase-change material layer by template formation from the seeding layer. A method for forming a phase-change memory cell comprising the above.

25. A step of providing an initial structure comprising a substrate, an insulating layer outside the substrate, and a first electrode embedded in the insulating layer, wherein the outer end of the first electrode is locally flush with the outer surface of the insulating layer, and the insulating layer is amorphous; A step of preparing the outer surface of the amorphous insulating layer and subsequently causing the orientation of a compositionally homogeneous crystalline phase-change material layer to be epitaxially grown; A step of epitaxially growing the compositionally homogeneous crystalline phase-change material layer on the prepared outer surface of the amorphous insulating layer at a temperature at which the compositionally homogeneous crystalline phase-change layer grows in a crystalline state; and The step of depositing the top electrode material onto the compositionally homogeneous crystalline phase-change material layer. A method for forming a phase-change memory cell comprising the above.

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