Multilayer transistor with metal vias

Abstract

A semiconductor structure including a stacked device structure is provided. The stacked device structure includes a first field-effect transistor including a first source / drain region, and a second field-effect transistor stacked vertically above the first field-effect transistor, wherein the second field-effect transistor includes a gate region having a second source / drain region and a first sidewall spacer. The stacked device structure further includes a front-facing source / drain contact located on a first portion of the sidewall and top surface of the second source / drain region, a first metal via connected to the front-facing source / drain contact and a first back-facing power line, and a second sidewall spacer located on a first portion of the first metal via. The first sidewall spacer comprises a first dielectric material, and the second sidewall spacer comprises a second dielectric material different from the first dielectric material.

Description

[Technical Field]

[0001] A field-effect transistor (FET) is a transistor having a source, gate, and drain, whose operation depends on the flow of carriers (electrons or holes) along a channel extending between the source and drain. The current through the channel between the source and drain can be controlled by a transverse electric field below the gate. FETs are widely used for switching, amplification, filtering, and other tasks. [Overview of the project]

[0002] Exemplary embodiments of the present invention include techniques for use in semiconductor manufacturing. In an exemplary embodiment, the semiconductor structure comprises a multilayer device structure including a first field-effect transistor having a first source / drain region, and a second field-effect transistor stacked vertically above the first field-effect transistor, wherein the second field-effect transistor comprises a gate region having a second source / drain region and a first sidewall spacer. The semiconductor structure further includes a front-facing source / drain contact located on the sidewall and a first portion of the top surface of the second source / drain region. The semiconductor structure further includes a first metal via connected to the front-facing source / drain contact and a first back-facing power line. The semiconductor structure further includes a second sidewall spacer located on a first portion of the first metal via. The first sidewall spacer comprises a first dielectric material, and the second sidewall spacer comprises a second dielectric material different from the first dielectric material.

[0003] Advantageously, the semiconductor structure of the exemplary embodiment allows for improved connectivity between the metal vias and the top source / drain region by utilizing different dielectric materials between the gate region sidewall spacers and the metal via sidewall spacers, with the stacked device structure having a front-facing source / drain contact on part of the sidewall and top surface of the top source / drain region, and having metal vias connected to the front-facing source / drain contact and back-facing power lines.

[0004] In one or more additional exemplary embodiments that can be combined with the preceding paragraphs, the semiconductor structure further comprises a bottom dielectric insulating layer located on a first portion of the bottom surface of the first source / drain region.

[0005] In one or more additional exemplary embodiments that can be combined with the preceding paragraphs, the bottom dielectric insulating layer comprises a third dielectric material different from the second dielectric material.

[0006] In one or more additional exemplary embodiments that can be combined with the preceding paragraphs, the second portion of the first metal via is located within an interlayer dielectric layer.

[0007] In one or more additional exemplary embodiments that can be combined with the preceding paragraphs, the semiconductor structure further includes a back-side metal contact located on a second portion of the bottom surface of the first source / drain region and connected to a second back-side power line.

[0008] In one or more additional exemplary embodiments that can be combined with the preceding paragraphs, the semiconductor structure further includes another stacked device structure adjacent to the stacked device structure, which includes a third field-effect transistor having a third source / drain region, and a fourth field-effect transistor stacked vertically above the third field-effect transistor. The fourth field-effect transistor has a fourth source / drain region. The other stacked device structure includes a back-side source / drain contact located in a second portion of the sidewall and bottom surface of the third source / drain region, and includes a second metal via connected to the back-side source / drain contact and the back-end-of-the-line layer.

[0009] In one or more additional exemplary embodiments that can be combined with the preceding paragraphs, the semiconductor structure further includes a back-side metal contact located on the bottom surface of the first source / drain region and connected to a second back-side power line.

[0010] In one or more additional exemplary embodiments that can be combined with the preceding paragraphs, the front-facing source / drain contacts are further positioned on a back-end-of-the-line layer.

[0011] In another exemplary embodiment, the semiconductor structure includes a first multilayer device structure including a first field-effect transistor arranged to include a first source / drain region, and a second field-effect transistor stacked vertically above the first field-effect transistor and including a second source / drain region. The first multilayer device further includes a front-facing source / drain contact located on the sidewall and first portion of the top surface of the second source / drain region, and a first metal via connected to the front-facing source / drain contact and a first back-facing power line. The semiconductor structure further includes a second multilayer device structure adjacent to the first multilayer device structure. The second multilayer device structure includes a third field-effect transistor including a third source / drain region, and a fourth field-effect transistor stacked vertically above the third field-effect transistor and including a fourth source / drain region. The second stacked device structure includes a first back-side source / drain contact located on the second portion of the sidewall and bottom surface of the third source / drain region, and further includes a second metal via connected to the first back-side source / drain contact and the back-end ob-the-line layer.

[0012] Advantageously, the semiconductor structure of the exemplary embodiment allows the first stacked device structure to have front source / drain contacts on the sidewalls and a portion of the top surface of the top source / drain region, and metal vias connected to the front source / drain contacts and back-side power lines, thereby enabling improved connectivity between the metal vias and the top source / drain region. Even more advantageously, the semiconductor structure of the exemplary embodiment may allow a second stacked device structure adjacent to the first stacked device structure to include back source / drain contacts on the sidewalls and a portion of the bottom surface of the bottom source / drain region, and metal vias connected to the back-side source / drain contacts and back-side ob-the-line layers, thereby enabling improved connectivity between the metal vias and the bottom source / drain region.

[0013] In one or more additional exemplary embodiments that can be combined with the preceding paragraphs, the back-side source / drain contacts are further located on an interlayer dielectric layer.

[0014] In one or more additional exemplary embodiments that can be combined with the preceding paragraphs, the bottom dielectric insulating layer is located on a second portion of the bottom surface of the third source / drain region, the first and second sidewall spacers are located on the opposing sidewalls of the first and second stacked device structures, and the dielectric fill is located between the first and second sidewall spacers.

[0015] In one or more additional exemplary embodiments that can be combined with the preceding paragraphs, the bottom dielectric insulating layer comprises a first dielectric material, and the first and second sidewall spacers comprise a second dielectric material different from the first dielectric material.

[0016] In one or more additional exemplary embodiments that can be combined with the preceding paragraphs, the dielectric fill includes a third dielectric material different from the first dielectric material and the second dielectric material.

[0017] In one or more additional exemplary embodiments that can be combined with the preceding paragraphs, the semiconductor structure further includes a second back-side source / drain contact located on the first source / drain region and connected to a second back-side power line.

[0018] In yet another exemplary embodiment, the semiconductor structure includes a first stacked transistor having a first nanosheet field-effect transistor disposed on a first bottom dielectric insulating layer and including a first gate structure, and a second nanosheet field-effect transistor device stacked above the first nanosheet field-effect transistor and including a second gate structure having a first sidewall spacer. The semiconductor structure further includes a third nanosheet field-effect transistor disposed on a second bottom dielectric insulating layer and including a third gate structure, and a second stacked transistor adjacent to the first stacked transistor, stacked above the third nanosheet field-effect transistor and including a fourth gate structure having a second sidewall spacer. The semiconductor structure further includes a third and a fourth sidewall spacer disposed on the opposing sidewalls of the first and second stacked transistors, and a first metal via disposed between the third and fourth sidewall spacers.

[0019] Advantageously, the semiconductor structure of the exemplary embodiment allows the stacked device structure to have improved connectivity between the metal vias and the top source / drain region and the bottom source / drain region by utilizing different dielectric materials between the first bottom dielectric insulating layer, the second bottom dielectric insulating layer, the first sidewall spacer and the second sidewall spacer, and the third sidewall spacer and the fourth sidewall spacer.

[0020] In one or more additional exemplary embodiments that can be combined with the preceding paragraphs, the first bottom dielectric insulating layer, the second bottom dielectric insulating layer, the first sidewall spacer, and the second sidewall spacer comprise a first dielectric material, and the third sidewall spacer and the fourth sidewall spacer comprise a second dielectric material different from the first dielectric material.

[0021] In one or more additional exemplary embodiments that can be combined with the foregoing paragraphs, the metal via is connected to the back-end-of-line layer and the backside power line.

[0022] In one or more additional exemplary embodiments that can be combined with the foregoing paragraphs, the front-side source / drain contact is disposed on sidewalls and a portion of the top surface of the source / drain region of the second nanosheet field-effect transistor; a second metal via is connected to the front-side source / drain contact and the first backside power line.

[0023] In one or more additional exemplary embodiments that can be combined with the foregoing paragraphs, the backside metal contact is disposed on the bottom surface of the source / drain region of the first nanosheet field-effect transistor and is connected to a second backside power line.

[0024] In one or more additional exemplary embodiments that can be combined with the foregoing paragraphs, the backside source / drain contact is disposed on sidewalls and a portion of the bottom surface of the source / drain region of the third nanosheet field-effect transistor; a second metal via is connected to the backside source / drain contact and the back-end-of-line layer.

[0025] These and other exemplary embodiments will be described or will become apparent in forms for carrying out the following invention, read in connection with the accompanying drawings.

Brief Description of the Drawings

[0026] Exemplary embodiments will be described in more detail below with reference to the accompanying drawings: <000009​​​​​​ Figure 1B is a cross-sectional view of the semiconductor structure as cut along the XX axis of Figure 1A during the first intermediate manufacturing stage, according to an exemplary embodiment.

[0029] [Figure 1-2] Figure 1C is a cross-sectional view of a semiconductor structure cut along the Y1-Y1 axis of Figure 1A during a first intermediate manufacturing stage, according to an exemplary embodiment.

[0030] Figure 1D is a cross-sectional view of a semiconductor structure cut along the Y2-Y2 axis of Figure 1A during a first intermediate manufacturing stage, according to an exemplary embodiment.

[0031] [Figure 2-1] Figure 2A is a cross-sectional view of the semiconductor structure in Figure 1A, cut along the XX axis, during a second intermediate manufacturing stage, according to an exemplary embodiment.

[0032] Figure 2B is a cross-sectional view of the semiconductor structure as cut along the Y1-Y1 axis of Figure 1A during a second intermediate manufacturing stage, according to an exemplary embodiment.

[0033] [Figure 2-2] Figure 2C is a cross-sectional view of the semiconductor structure as cut along the Y2-Y2 axis of Figure 1A during a second intermediate manufacturing stage, according to an exemplary embodiment.

[0034] [Figure 3-1] Figure 3A is a cross-sectional view of the semiconductor structure in Figure 1A, cut along the XX axis, during a third intermediate manufacturing stage, according to an exemplary embodiment.

[0035] Figure 3B is a cross-sectional view of the semiconductor structure as cut along the Y1-Y1 axis of Figure 1A during a third intermediate manufacturing stage, according to an exemplary embodiment.

[0036] [Figure 3-2]Figure 3C is a cross-sectional view of the semiconductor structure as cut along the Y2-Y2 axis of Figure 1A during a third intermediate manufacturing stage, according to an exemplary embodiment.

[0037] [Figure 4-1] Figure 4A is a cross-sectional view of the semiconductor structure in Figure 1A, cut along the XX axis, during the fourth intermediate manufacturing stage, according to an exemplary embodiment.

[0038] Figure 4B is a cross-sectional view of the semiconductor structure as cut along the Y1-Y1 axis of Figure 1A during the fourth intermediate manufacturing stage, according to an exemplary embodiment.

[0039] [Figure 4-2] Figure 4C is a cross-sectional view of the semiconductor structure as cut along the Y2-Y2 axis of Figure 1A during the fourth intermediate manufacturing stage, according to an exemplary embodiment.

[0040] [Figure 5-1] Figure 5A is a cross-sectional view of the semiconductor structure as cut along the XX axis of Figure 1A during the fifth intermediate manufacturing stage, according to an exemplary embodiment.

[0041] Figure 5B is a cross-sectional view of the semiconductor structure as cut along the Y1-Y1 axis of Figure 1A during the fifth intermediate manufacturing stage, according to an exemplary embodiment.

[0042] [Figure 5-2] Figure 5C is a cross-sectional view of the semiconductor structure as cut along the Y2-Y2 axis of Figure 1A during the fifth intermediate manufacturing stage, according to an exemplary embodiment.

[0043] [Figure 6-1] Figure 6A is a cross-sectional view of the semiconductor structure in Figure 1A, cut along the XX axis, during the sixth intermediate manufacturing stage, according to an exemplary embodiment.

[0044] Figure 6B is a cross-sectional view of the semiconductor structure as cut along the Y1-Y1 axis of Figure 1A during the sixth intermediate manufacturing step, according to an exemplary embodiment.

[0045] [Figure 6-2] Figure 6C is a cross-sectional view of the semiconductor structure as cut along the Y2-Y2 axis of Figure 1A during the sixth intermediate manufacturing step, according to an exemplary embodiment.

[0046] [Figure 7-1] Figure 7A is a cross-sectional view of the semiconductor structure as cut along the XX axis of Figure 1A during the seventh intermediate manufacturing step, according to an exemplary embodiment.

[0047] Figure 7B is a cross-sectional view of the semiconductor structure as cut along the Y1-Y1 axis of Figure 1A during the seventh intermediate manufacturing step, according to an exemplary embodiment.

[0048] [Figure 7-2] Figure 7C is a cross-sectional view of the semiconductor structure as cut along the Y2-Y2 axis of Figure 1A during the seventh intermediate manufacturing step, according to an exemplary embodiment.

[0049] [Figure 8-1] Figure 8A is a cross-sectional view of the semiconductor structure as cut along the XX axis of Figure 1A during the eighth intermediate manufacturing step, according to an exemplary embodiment.

[0050] Figure 8B is a cross-sectional view of the semiconductor structure as cut along the Y1-Y1 axis of Figure 1A during the eighth intermediate manufacturing step, according to an exemplary embodiment.

[0051] [Figure 8-2] Figure 8C is a cross-sectional view of the semiconductor structure as cut along the Y2-Y2 axis of Figure 1A during the eighth intermediate manufacturing step, according to an exemplary embodiment.

[0052] [Figure 9-1]Figure 9A is a cross-sectional view of the semiconductor structure as cut along the XX axis of Figure 1A during the ninth intermediate manufacturing step, according to an exemplary embodiment.

[0053] Figure 9B is a cross-sectional view of the semiconductor structure as cut along the Y1-Y1 axis of Figure 1A during the ninth intermediate manufacturing step, according to an exemplary embodiment.

[0054] [Figure 9-2] Figure 9C is a cross-sectional view of the semiconductor structure as cut along the Y2-Y2 axis of Figure 1A during the ninth intermediate manufacturing step, according to an exemplary embodiment.

[0055] [Figure 10-1] Figure 10A is a cross-sectional view of the semiconductor structure as cut along the XX axis of Figure 1A during the tenth intermediate manufacturing step, according to an exemplary embodiment.

[0056] Figure 10B is a cross-sectional view of the semiconductor structure as cut along the Y1-Y1 axis of Figure 1A during the tenth intermediate manufacturing step, according to an exemplary embodiment.

[0057] [Figure 10-2] Figure 10C is a cross-sectional view of the semiconductor structure as cut along the Y2-Y2 axis of Figure 1A during the tenth intermediate manufacturing step, according to an exemplary embodiment.

[0058] [Figure 11-1] Figure 11A is a cross-sectional view of the semiconductor structure as cut along the XX axis of Figure 1A during the 11th intermediate manufacturing step, according to an exemplary embodiment.

[0059] Figure 11B is a cross-sectional view of the semiconductor structure as cut along the Y1-Y1 axis of Figure 1A during the 11th intermediate manufacturing step, according to an exemplary embodiment.

[0060] [Figure 11-2]Figure 11C is a cross-sectional view of the semiconductor structure as cut along the Y2-Y2 axis of Figure 1A during the 11th intermediate manufacturing step, according to an exemplary embodiment.

[0061] [Figure 12-1] Figure 12A is a cross-sectional view of the semiconductor structure as cut along the XX axis of Figure 1A during the twelfth intermediate manufacturing step, according to an exemplary embodiment.

[0062] Figure 12B is a cross-sectional view of the semiconductor structure as cut along the Y1-Y1 axis of Figure 1A during the twelfth intermediate manufacturing step, according to an exemplary embodiment.

[0063] [Figure 12-2] Figure 12C is a cross-sectional view of the semiconductor structure as cut along the Y2-Y2 axis of Figure 1A during the twelfth intermediate manufacturing step, according to an exemplary embodiment.

[0064] [Figure 13-1] Figure 13A is a cross-sectional view of the semiconductor structure as cut along the XX axis of Figure 1A during the 13th intermediate manufacturing step, according to an exemplary embodiment.

[0065] Figure 13B is a cross-sectional view of the semiconductor structure as cut along the Y1-Y1 axis of Figure 1A during the 13th intermediate manufacturing step, according to an exemplary embodiment.

[0066] [Figure 13-2] Figure 13C is a cross-sectional view of the semiconductor structure as cut along the Y2-Y2 axis of Figure 1A during the 13th intermediate manufacturing step, according to an exemplary embodiment.

[0067] [Figure 14-1] Figure 14A is a cross-sectional view of the semiconductor structure as cut along the XX axis of Figure 1A during the 14th intermediate manufacturing step, according to an exemplary embodiment.

[0068] Figure 14B is a cross-sectional view of the semiconductor structure as cut along the Y1-Y1 axis of Figure 1A during the 14th intermediate manufacturing step, according to an exemplary embodiment.

[0069] [Figure 14-2] Figure 14C is a cross-sectional view of the semiconductor structure as cut along the Y2-Y2 axis of Figure 1A during the 14th intermediate manufacturing step, according to an exemplary embodiment.

[0070] [Figure 15-1] Figure 15A is a cross-sectional view of the semiconductor structure as cut along the XX axis of Figure 1A during the 15th intermediate manufacturing step, according to an exemplary embodiment.

[0071] Figure 15B is a cross-sectional view of the semiconductor structure as cut along the Y1-Y1 axis of Figure 1A during the 15th intermediate manufacturing step, according to an exemplary embodiment.

[0072] [Figure 15-2] Figure 15C is a cross-sectional view of the semiconductor structure as cut along the Y2-Y2 axis of Figure 1A during the 15th intermediate manufacturing step, according to an exemplary embodiment.

[0073] [Figure 16-1] Figure 16A is a cross-sectional view of the semiconductor structure as cut along the XX axis of Figure 1A during the 13th intermediate manufacturing step, according to an exemplary embodiment.

[0074] Figure 16B is a cross-sectional view of the semiconductor structure as cut along the Y1-Y1 axis of Figure 1A during the 16th intermediate manufacturing step, according to an exemplary embodiment.

[0075] [Figure 16-2] Figure 16C is a cross-sectional view of the semiconductor structure as cut along the Y2-Y2 axis of Figure 1A during the 16th intermediate manufacturing step, according to an exemplary embodiment.

[0076] [Figure 17-1]Figure 17A is a cross-sectional view of the semiconductor structure as cut along the XX axis of Figure 1A during the 17th intermediate manufacturing step, according to an exemplary embodiment.

[0077] Figure 17B is a cross-sectional view of the semiconductor structure as cut along the Y1-Y1 axis of Figure 1A during the 17th intermediate manufacturing step, according to an exemplary embodiment.

[0078] [Figure 17-2] Figure 17C is a cross-sectional view of the semiconductor structure as cut along the Y2-Y2 axis of Figure 1A during the 17th intermediate manufacturing step, according to an exemplary embodiment. [Modes for carrying out the invention]

[0079] Exemplary embodiments of the present invention may be described herein, along with exemplary apparatus, structures, and devices formed using exemplary methods for forming metal vias within a stacked device structure to prevent routing congestion and reduce process complexity. However, it will be understood that embodiments of the present invention are not limited to exemplary methods, apparatus, structures, and devices, but are rather more broadly applicable to other suitable methods, apparatus, structures, and devices.

[0080] Please understand that the various layers, structures, and regions shown in the attached drawings are schematic diagrams and not drawn to scale. Furthermore, for the sake of simplicity, one or more types of layers, structures, and regions commonly used to form semiconductor devices or structures may not be explicitly shown in the given drawings. This does not imply that layers, structures, and regions not explicitly shown are omitted from actual semiconductor structures.

[0081] Furthermore, the same or similar reference numerals are used throughout the drawings to indicate the same or similar features, elements, or structures, and therefore, detailed descriptions of the same or similar features, elements, or structures are not repeated for each of the drawings. Furthermore, as used herein, the terms “exemplary” and “illustrative” mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” or “illustrative” is not considered preferable or advantageous to other embodiments or designs.

[0082] Furthermore, it should be understood that the embodiments considered herein are not limited to the specific materials, features, and process steps shown and described herein. In particular, with respect to semiconductor process steps, it should be emphasized that the descriptions provided herein are not intended to encompass all process steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain process steps commonly used when forming semiconductor devices, such as wet cleaning and annealing steps, are intentionally omitted herein for the sake of brevity. It should be understood that the terms “about” or “substantially” used herein with respect to thickness, width, percentage, range, etc., mean that they are not exact but are close or approximate. For example, the terms “about” or “substantially” used herein suggest that there may be slight errors, such as 1% or less of the stated quantity.

[0083] References in this specification to “one embodiment” or “one embodiment” of the Principle and other variations thereof mean that the specific features, structures, properties, etc. described in relation to that embodiment are included in at least one embodiment of the Principle. Therefore, the phrases “in one embodiment” or “in one embodiment” and any other variations appearing in various places throughout this specification do not necessarily all refer to the same embodiment. The term “located on top” means that a first element, such as a first structure, is located on a second element, such as a second structure, and an intervening element, such as an interface structure or interface layer, may be located between the first and second elements. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected at the interface of the two elements without any intermediate conductive, insulating, or semiconductor layer.

[0084] The terms "first," "second," etc., may be used in this specification to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. Thus, the first element considered below may be referred to as the second element without deviating from the scope of this concept.

[0085] As used herein, “height” refers to the vertical size of an element (e.g., a layer, trench, hole, opening, etc.) in a cross-sectional view, measured from the bottom to the top of the element and / or relative to the surface on which the element is located. Conversely, “depth” refers to the vertical size of an element (e.g., a layer, trench, hole, opening, etc.) in a cross-sectional view, measured from the top to the bottom of the element. Terms such as “thick,” “thickness,” “thin,” or their derivatives may be used instead of “height” when explicitly stated.

[0086] As used herein, “width” or “length” refers to the size of an element in a drawing (e.g., a layer, trench, hole, opening, etc.) measured from one side to the opposite surface of that element. Terms such as “thick,” “thickness,” “thin,” or their derivatives may be used instead of “width” or “length” if explicitly stated.

[0087] In the IC chip manufacturing industry, there are three sections typically mentioned in IC chip construction: the front-end-of-line (FEOL), the back-end-of-line (BEOL), and the middle-of-line (MOL), which connects these two together. The FEOL consists of semiconductor devices, such as transistors; the BEOL consists of interconnects and wiring; and the MOL is the interconnect between the FEOL and BEOL, including materials to prevent the diffusion of BEOL metals into the FEOL devices. Thus, the exemplary embodiments described herein may focus on BEOL semiconductor processing and construction. The BEOL is the second part of IC manufacturing, where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, such as a metallization layer or multiple metallization layers. The BEOL includes contacts, insulating layers (dielectrics), metal levels, and junction sites for connecting the chip to the package. In the BEOL stage, contacts (pads), interconnect wires, vias, and dielectric structures are formed as part of the manufacturing process. For modern IC processes, more than 10 metal layers may be added within the BEOL.

[0088] The embodiments described below may be applicable to FEOL processing and structure, BEOL processing and structure, or both FEOL processing and structure and BEOL processing and structure. In particular, exemplary processing schemes may be illustrated using FEOL processing scenarios, but such methods may also be applicable to BEOL processing. Similarly, exemplary processing schemes may be illustrated using BEOL processing scenarios, but such methods may also be applicable to FEOL processing.

[0089] Current multilayer FETs utilize metal vias as electrical paths connecting the top source / drain region to the back-side interconnect of the wafer and the bottom source / drain region to the front-side BEOL interconnect. However, current metal vias do not adequately connect to the top and bottom source / drain regions, resulting in routing congestion and high resistance. Therefore, there is a need to form multilayer FETs that do not suffer from the above drawbacks. Accordingly, non-limiting exemplary embodiments described herein overcome the drawbacks discussed above by forming metal vias that connect to both the top and bottom source / drain regions of the multilayer FET, thereby improving routableness and resistance.

[0090] Referring to Figures 1A to 17C, Figure 1A shows a top view of the semiconductor structure 100. The first side section view in Figure 1B is obtained by cutting along line XX in the top view of Figure 1A, the second side section view in Figure 1C is obtained by cutting along line Y1-Y1 in the top view of Figure 1A, and the third side section view in Figure 1D is obtained by cutting along line Y2-Y2 in the top view of Figure 1A.

[0091] The semiconductor structure 100 represents a substrate 102. The substrate 102 can be formed from any suitable semiconductor structure, including but not limited to various silicon-containing materials, including silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), and multilayers thereof. Although silicon is the primary semiconductor material used in wafer manufacturing, alternative semiconductor materials, such as but not limited to germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), zinc selenide (ZnSe), etc., may be used as additional layers. In one exemplary embodiment, the substrate 102 is silicon.

[0092] The etching stop layer 104 is formed within the substrate 102. The etching stop layer 104 may include a buried oxide (BOX) layer, silicon germanium (SiGe), or another suitable material, such as a III-V semiconductor epitaxial layer.

[0093] The nanosheet stack is formed on top of the substrate 102, and the nanosheet stack includes sacrificial layers 106-1 and 106-2 (collectively sacrificial layer 106), sacrificial layers 108-1 and 108-2 (collectively sacrificial layer 108), and nanosheet channel layers 110-1 and 110-2 (collectively nanosheet channel layer 110).

[0094] Sacrificial layers 106 and 108 are exemplary formed from different sacrificial materials so that they can be selectively etched or otherwise removed from each other. In some embodiments, both sacrificial layers 106 and 108 are formed from SiGe, but with different proportions of Ge. For example, sacrificial layer 106 may have a relatively high proportion of Ge (e.g., 55% Ge), and sacrificial layer 108 may have a relatively low proportion of Ge (e.g., 25% Ge). In other embodiments, other combinations of different sacrificial materials may also be used.

[0095] The nanosheet channel layer 110 may be formed from Si or another suitable material (e.g., a material similar to that used with respect to the substrate 102). After nanosheet lamination patterning, shallow trench isolation (STI) regions 116 are formed. The STI regions 116 may be formed from a dielectric material, such as silicon dioxide (SiO2), silicon oxycarbide (SiOC), or silicon oxynitride (SiON).

[0096] The semiconductor structure 100 further exhibits a dummy gate 112 above the structure, along with a gate hard mask (HM) layer 114. The dummy gate 112 can be formed by blanket deposition of a dummy gate material (e.g., amorphous silicon (a-Si) or amorphous silicon germanium (a-SiGe) above a thin SiO2 or titanium nitride (TiN) layer, or another suitable material) and a gate HM layer 114 material (e.g., a multilayer of silicon nitride (SiN), SiN, and SiO2, or another suitable material), followed by lithography, thereby obtaining a patterned gate HM layer 114 and the underlying dummy gate 112.

[0097] Figures 2A to 2C illustrate the semiconductor structure 100 in the second intermediate manufacturing stage. In this stage, the bottom dielectric insulator (BDI) layer 118-1, the middle dielectric insulator (MDI) layer 118-2, the inner spacer 120, and the side wall spacer 122 are formed.

[0098] The BDI layer 118-1 and the MDI layer 118-2 (collectively, the dielectric insulating layer 118) can be formed from any suitable insulator or dielectric material, such as SiN, silicon boron carbon nitride (SiBCN), silicon oxycarbon nitride (SiOCN), etc. The BDI layer 118-1 is formed in the region previously occupied by the sacrificial layer 106-1, and the MDI layer 118-2 is formed in the region previously occupied by the sacrificial layer 106-2, and may have a similar size to the sacrificial layer.

[0099] The inner spacer 120 may be formed to fill a recessed space (for example, one brought about by recess etching before the removal of the sacrificial layer 108). The inner spacer 120 may be formed from silicon nitride (SiN) or another suitable material, such as SiBCN, silicon carbide (SiCO), SiOCN, etc.

[0100] The sidewall spacer 122 may be formed from a material similar to that of the BDI layer 118-1. In one embodiment, the sidewall spacer 122 is formed from the same insulating or dielectric material as the BDI layer 118-1, for example, SiN or SiBCN.

[0101] Figures 3A to 3C show the semiconductor structure 100 in the third intermediate manufacturing stage. In this stage, the opening is extended through the substrate 102 and the STI region 116 to form a sacrificial placeholder, as discussed below. The opening is first formed by depositing a mask layer 124 (e.g., an organic planarization layer (OPL) or spin-on-carbon (SOC)) onto the semiconductor structure 100 using any conventional deposition process such as spin-on coating, or any other suitable deposition process. Next, the mask layer 124 is patterned and then selectively etched, for example, using reactive ion etching (RIE), to form the opening.

[0102] Figures 4A to 4C show the semiconductor structure 100 in the fourth intermediate manufacturing stage. In this stage, the sacrificial placeholder 126, bottom source / drain region 128a, top source / drain region 128b, interlevel dielectric (ILD) layer 130, and replacement gate 132 create the first transistor 129-1 and the second transistor 129-2 within the stacked structure. The sacrificial placeholder 126 is formed below the bottom source / drain region 128a and is made of sacrificial material, such as SiGe, titanium oxide (TiO2). x ), aluminum oxide (AlO x ), silicon carbide (SiC), or a combination thereof may be formed from the above. The mask layer may be patterned above the structure and subsequently etched into the substrate 102 through the underlying layer. A sacrificial placeholder 126 may then be deposited, followed by epitaxial growth of the bottom source / drain region 128a, deposition and planarization of a portion of the ILD layer 130 between the bottom source / drain region 128a and the top source / drain region 128b, followed by epitaxial growth of the top source / drain region 128b and deposition and planarization of a portion of the ILD layer 130 above the top source / drain region 128b.

[0103] The bottom source / drain region 128a and the top source / drain region 128b may be formed using an epitaxial growth process. The bottom source / drain region 128a and the top source / drain region 128b may be suitably doped using, for example, ion implantation, gas phase doping, plasma doping, plasma permeation ion implantation, cluster doping, infusion doping, liquid phase doping, solid phase doping, etc. The n-type dopant may be selected from the group consisting of phosphorus (P), arsenic (As), and antimony (Sb), and the p-type dopant may be selected from the group consisting of boron (B), boron fluoride (BF2), gallium (Ga), indium (In), and thallium (Tl). In some embodiments, the epitaxy process includes in-situ doping (the dopant is incorporated into the epitaxy material during epitaxy).

[0104] Epitaxial materials can be grown from gaseous or liquid precursors. Epitaxial materials can be grown using vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), rapid thermal chemical vapor deposition (RTCVD), metal organic chemical vapor deposition (MOCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), low-pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD), or other suitable processes. Epitaxial silicon, silicon germanium (SiGe), germanium (Ge), and / or carbon-doped silicon (Si:C) can be doped in-situ during deposition by adding dopants such as n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium) depending on the type of transistor being formed. The dopant concentration in the source / drain can range from 1×10 19 cm -3 to 3×10 21 cm -3 or, preferably, from 2×10 20 cm -3 to 3×10 21 cm -3 and can be in the range of.

[0105] After the bottom source / drain region 128a, the top source / drain region 128b, and the ILD layer 130 are formed, poly-open chemical mechanical planarization (CMP) is performed to expose the dummy gate 112. The ILD layer 130 can be formed from any suitable insulating material such as SiO2, SiOC, or SiON. The dummy gate 112 and the sacrificial layer 108 are removed, and thereafter the replacement gate 132 is formed (for example, using a replacement HKMG treatment).

[0106] The substitution gate 132 includes a gate stack layer which may comprise a gate dielectric layer and a gate conductor layer. The gate dielectric layer may be formed from a high-k dielectric material. Examples of high-k materials, but not limited to, include metal oxides such as HfO2, hafnium silicon oxide (Hf-Si-O), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanate, barium titanate, strontium titanate, yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide, and lead zinc niobate. The high-k material may further include dopants such as lanthanum (La), aluminum (Al), and magnesium (Mg). The gate dielectric layer may have a uniform thickness in the range of 1 nm to 3 nm.

[0107] The gate conductor layer may include a metallic gate or a work function metal (WFM). WFMs for the gate conductor layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), combinations of Ti and Al alloys, or laminates containing a barrier layer (e.g., TiN, TaN, etc.) followed by one or more of the aforementioned WFM materials. It should be understood that various other materials may be used for the gate conductor layer as needed.

[0108] Figures 5A to 5C illustrate the semiconductor structure 100 in the fifth intermediate manufacturing stage. In this stage, a first opening is formed through a replacement gate 132, exposing the STI region 116 (see Figure 5B), and second and third openings are formed between adjacent bottom source / drain regions 128a and top source / drain regions 128b, exposing a sacrificial placeholder 126 and a portion of the STI region 116 with respect to the second opening, and the STI region 116 with respect to the third opening (see Figure 5C). The openings are formed by first depositing a mask layer 134 (e.g., OPL or spin-on carbon (SOC)) onto the semiconductor structure 100 using any conventional deposition process such as spin-on coating or any other suitable deposition process. Next, the mask layer 134 is patterned and then selectively etched, for example using RIE, to form the openings.

[0109] Figures 6A to 6C illustrate the semiconductor structure 100 in the sixth intermediate manufacturing stage. In this stage, sidewall spacers 136 and dielectric fill 138 are deposited in the opening, followed by a planarization process such as CMP. The sidewall spacers 136 and dielectric fill are deposited using any conventional deposition technique, such as physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD). In one embodiment, the sidewall spacers 136 and dielectric fill 138 are formed from a first dielectric material and a second dielectric material different from the first dielectric material. In one embodiment, the sidewall spacers 136 are formed from a dielectric material different from the dielectric materials of the BDI layer 118-1 and sidewall spacer 122. For example, the sidewall spacer 136 is formed from a dielectric material such as SiN, and the BDI layer 118-1 and sidewall spacer 122 are formed from a dielectric material such as SiCO or SiOCN. A suitable dielectric material for the dielectric fill 138 includes, for example, SiO2.

[0110] Figures 7A to 7C illustrate the semiconductor structure 100 in the seventh intermediate manufacturing stage. In this stage, a first opening 141a is formed through the dielectric fill 138, the STI region 116, and a portion of the substrate 102 between the replacement gate 132 (see Figure 7B), exposing the sidewall spacer 136 and the substrate 102 (see Figure 7B). Second and third openings 141b and 141c are formed through the dielectric fill 138 between adjacent bottom source / drain regions 128a and top source / drain regions 128b, exposing the sacrificial placeholder 126 and a portion of the STI region 116 with respect to the second opening 141b, and the substrate 102 with respect to the third opening 141c (see Figure 7C). The openings are first formed by depositing a mask layer 140 (e.g., OPL or spin-on carbon (SOC)) onto the semiconductor structure 100 using any conventional deposition process such as spin-on coating or any other suitable deposition process. Next, the mask layer 140 is patterned and then selectively etched, for example using RIE, to form the openings.

[0111] Figures 8A to 8C illustrate the semiconductor structure 100 in the eighth intermediate manufacturing stage. In this stage, middle-of-the-line (MOL) contact openings are formed, which include the formation of top source / drain contact openings 142a, 142b, 142c, 142d, and 142e, and bottom source / drain contact opening 142f. For example, in an exemplary embodiment, the top source / drain contact openings 142a, 142b, 142c, 142d, and 142e, and the bottom source / drain contact opening 142f may be formed by first depositing an additional mask layer 140 within the first, second, and third openings 141a, 141b, and 141c, and then using a conventional lithography and etching process, such as RIE, at least on the mask layer 140 to form the top source / drain contact openings 142a, 142b, 142c, 142d, and 142e, and the bottom source / drain contact opening 142f. As can be seen in Figure 8C, by using different materials for the sidewall spacers 122 and 136, the etching process can selectively remove the sidewall spacer 136 relative to the sidewall spacer 122, protecting the replacement gate 132 in the top source / drain contact opening 142a, while exposing the top surface and sidewalls of the respective top source / drain regions 128b in the top source / drain contact opening 142e.

[0112] Figures 9A to 9C illustrate the semiconductor structure 100 in the ninth intermediate manufacturing stage. In this stage, the top surface source / drain contacts 146a, 146b, 146c, and 146d, metal vias 148 and 154, gate contact 149, bottom source / drain contact 150, and MOL contact 152 are first formed. In an exemplary embodiment, high-conductance metal is deposited in the top source / drain contact openings 142a, 142b, 142c, 142d, and 142e, and the bottom source / drain contact opening 142f to form the respective top surface source / drain contacts 146a, 146b, 146c, and 146d, and the bottom source / drain contact 150. The top surface source / drain contact 146e is partially positioned on the sidewall and top surface of the top source / drain region 128b. Therefore, the top surface source / drain contact 146e is sometimes referred to as a partially wrapped-around top surface source / drain contact 146e. In addition, the metal via 148 may be formed by selectively removing the mask layer 140 between adjacent bottom source / drain regions 128a and top source / drain regions 128b (see Figure 9C), thereby forming an extended via, followed by the deposition of at least a high-conductance metal as discussed above.

[0113] For example, the metal via 148 may include, for example, a silicide liner, e.g., Ti, Ni, NiPt, followed by an adhesive metal liner, e.g., TiN, and a metal fill material, e.g., tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), molybdenum (Mo), or any other suitable conductive material. In various embodiments, the high-conductance metal may be deposited by ALD, CVD, PVD, and / or plating. The high-conductance metal may be planarized using a planarization process such as CMP. Other planarization processes may include grinding and polishing.

[0114] The gate contact 149, MOL contact 152, and metal via 154 are formed using conventional lithography and etching processes. For example, the gate contact 149 can be formed by using conventional lithography and etching processes at least in the ILD layer 130, followed by the deposition of a high-conductance metal as discussed above. The MOL contact 152 can be formed using conventional lithography and etching processes by selectively removing the dielectric fill 138 between the replacement gates 132 (see Figure 9B), followed by the deposition of a high-conductance metal as discussed above. In addition, the metal via 154 can be formed by selectively removing the mask layer 140 between adjacent bottom source / drain regions 128a and top source / drain regions 128b (see Figure 9C), forming an extended via, followed by the deposition of a high-conductance metal as discussed above. The metal via 154 will connect to the bottom source / drain contact 164d, as discussed below in relation to Figure 16C. The high-conductance metal may be planarized using a planarization process such as CMP. Other planarization processes may include grinding and polishing.

[0115] Next, a front-side back-of-line (BEOL) structure 156 is formed on the semiconductor structure 100, and subsequently, the structure (e.g., the front-side BEOL structure 156) is bonded to the carrier wafer 158. The front-side BEOL structure 156 includes various BEOL interconnect structures. The carrier wafer 158 may be formed from a material similar to that of the substrate 102 and may be formed above the front-side BEOL structure 156 using a wafer bonding process such as dielectric-dielectric bonding.

[0116] Figures 10A to 10C illustrate the semiconductor structure 100 in the tenth intermediate manufacturing stage. In this stage, portions of the substrate 102 may be selectively removed from the back side, for example, by using substrate grinding, CMP, and wet etching until the etching stop layer 104 is reached. This can be achieved, for example, by inverting the semiconductor structure 100 using the carrier wafer 158 so that the back side (i.e., the back surface) of the substrate 102 faces upward.

[0117] Figures 11A to 11C illustrate the semiconductor structure 100 in the 11th intermediate manufacturing stage. In this stage, the etching stop layer 104 is selectively removed, for example, by using wet etching, until the substrate 102 is reached. Next, the remaining portion of the substrate 102 is removed to expose the BDI layer 118-1, the STI region 116, the sacrificial placeholder 126, the metal via 148, and the MOL contact 152. The remaining portion of the substrate 102 may be removed using a selective etching process such as wet etching.

[0118] Figures 12A to 12C illustrate the semiconductor structure 100 in the twelfth intermediate manufacturing stage. At this stage, the back surface ILD layer 160 may be formed using the same material and process as the ILD layer 130. The material for the back surface ILD layer 160 may be initially overfilled and then planarized (e.g., using CMP).

[0119] Figures 13A to 13C illustrate the semiconductor structure 100 in the 13th intermediate manufacturing stage. In this stage, the sacrificial placeholder 126 is selectively removed using any preferred etching process that selectively removes the material of the sacrificial placeholder 126 from the rest of the structure to form openings 162a, 162b, 162c, 162d, and 162e. Preferred etching processes include, for example, wet etching.

[0120] Figures 14A to 14C illustrate the semiconductor structure 100 in the 14th intermediate manufacturing stage. In this stage, the exposed sidewall spacers 136 and ILD layer 130 within the opening 162d are selectively removed using an etching process such as RIE, exposing at least a portion of the sidewalls of the bottom source / drain regions 128a (see Figure 14C). As discussed above, by using different materials for the BDI layer 118-1 and the sidewall spacers 136, the etching process can selectively remove the sidewall spacers 136 relative to the BDI layer 118-1, protecting the replacement gate 132 within the opening 162c, while exposing the top and sidewalls of the respective bottom source / drain regions 128a within the opening 162d.

[0121] Figures 15A to 15C illustrate the semiconductor structure 100 in the 15th intermediate manufacturing stage. In this stage, a suitable conductive metal is then deposited in the openings 162a, 162b, 162c, 162d, and 162e, followed by CMP to remove any metal on the back surface ILD layer 160, thereby forming the bottom source / drain contacts 164a, 164b, 164c, 164d, and 164e. The bottom source / drain contact 164d is partially positioned on the sidewall and bottom surface of the bottom source / drain region 128a. Therefore, the bottom source / drain contact 164d may also be referred to as a partially wrapped-around back surface bottom source / drain contact 164d. The suitable conductive metal may be any of the metals discussed above.

[0122] Figures 16A to 16C illustrate the semiconductor structure 100 in the 16th intermediate manufacturing stage. In this stage, the selective recessing of the bottom source / drain contacts 164a and 164d is performed by first forming a mask layer 166 on top of the semiconductor structure 100. The mask layer 166 may be formed from the same material and process as the mask layer 124. Next, the mask layer 166 is patterned and then etched to form the bottom source / drain contacts 164a and 164d, for example using RIE, and openings are formed within the mask layer 166.

[0123] Figures 17A to 17C illustrate the semiconductor structure 100 in the 17th intermediate manufacturing step. In this step, an additional back-side ILD layer 160 is formed on the semiconductor structure 100, and thereafter, a back-side power rail 168 is formed by depositing a suitable conductive metal on the back-side ILD layer 160. The conductive metal may include, but is not limited to, tungsten, copper, aluminum, silver, gold, and alloys thereof.

[0124] A back-side ground (GND or Vss) rail 170 for providing a series of power supplies, and a back-side power (Vdd) rail 172 for providing supply voltage to the structure, are formed within the back-side ILD layer 160 by creating openings using a conventional lithography and etching process, such as RIE, followed by depositing a suitable conductive metal within the openings.

[0125] Next, the back-side power supply network 174 is formed above the semiconductor structure 100, which includes a back-side power rail 168, a ground (GND or Vss) rail 170, and a back-side power (Vdd) rail 172, and is based on creating a wiring scheme that is arranged on both sides of the device layer (front-end-of-line structure).

[0126] Semiconductor devices and methods for forming such semiconductor devices by the techniques described above can be employed in a variety of applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing embodiments of the present invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, mobile communication devices (e.g., mobile phones and smartphones), solid-state media storage devices, and functional circuit configurations. Systems and hardware incorporating semiconductor devices are intended as embodiments of the present invention. With regard to the teachings provided herein, those skilled in the art will be able to envision other implementations and applications of embodiments of the present invention.

[0127] In some embodiments, the techniques described above are used in relation to semiconductor devices that require, for example, CMOS, MOSFET, and / or FinFET, or that can otherwise utilize them. In non-limiting examples, semiconductor devices may include, but are not limited to, CMOS, MOSFET, and FinFET devices, and / or semiconductor devices that utilize CMOS, MOSFET, and / or FinFET techniques.

[0128] The various structures described above can be implemented in integrated circuits. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packaged form. In the latter case, the chips are mounted in a single chip package (e.g., a plastic carrier with leads attached to a motherboard or other higher-level carrier) or in a multi-chip package (e.g., a ceramic carrier with either or both surface interconnects or embedded interconnects). In either case, the chips are integrated together with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product containing an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products and central processing units with displays, keyboards, or other input devices.

[0129] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be comprehensive or limitless to the disclosed embodiments. Many modifications and variations will become apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best describe the principles, practical applications, or technical improvements to the technologies available on the market, or to enable other those skilled in the art to understand the embodiments disclosed herein.

[0130] In preferred embodiments of the present invention as described herein, a semiconductor structure is provided comprising: a first field-effect transistor including a first source / drain region; a second field-effect transistor stacked vertically above the first field-effect transistor, the second field-effect transistor including a second source / drain region; a front-facing source / drain contact located in a first portion of the sidewall and top surface of the second source / drain region; and a first metal via connected to the front-facing source / drain contact and a first back-side power line; and a second multilayer device structure adjacent to the first multilayer device structure, the second multilayer device structure comprising: a third field-effect transistor including a third source / drain region; a fourth field-effect transistor stacked vertically above the third field-effect transistor, the fourth field-effect transistor including a fourth source / drain region; a first back-side source / drain contact located in a second portion of the sidewall and bottom surface of the third source / drain region; and a second metal via connected to the first back-side source / drain contact and a back-side-of-the-line layer. Preferably, the first back-side source / drain contact is further disposed on an interlayer dielectric layer. Preferably, such a structure further comprises: a bottom dielectric insulating layer disposed on another portion of the bottom surface of the third source / drain region; first and second sidewall spacers disposed on opposing sidewalls of the first and second multilayer device structures; and a dielectric fill disposed between the first and second sidewall spacers. The bottom dielectric insulating layer may include a first dielectric material, and the first and second sidewall spacers include a second dielectric material different from the first dielectric material. The dielectric fill may include a third dielectric material different from the first and second dielectric materials. The structure may further comprise a second back-side source / drain contact disposed on the first source / drain region and connected to a second back-side power line.

[0131] In preferred embodiments of the present invention described herein, a first stacked transistor having a first nanosheet field-effect transistor disposed on a first bottom dielectric insulating layer, the first nanosheet field-effect transistor comprising a first gate structure; and a second nanosheet field-effect transistor device stacked above the first nanosheet field-effect transistor, the second nanosheet field-effect transistor device comprising a second gate structure having a first sidewall spacer; and a third nanosheet field-effect transistor disposed on a second bottom dielectric insulating layer, the third nanosheet field-effect transistor A semiconductor structure is provided comprising: a second stacked transistor adjacent to the first stacked transistor having a third gate structure; a fourth nanosheet field-effect transistor device stacked above the third nanosheet field-effect transistor, the fourth nanosheet field-effect transistor device having a fourth gate structure having a second sidewall spacer; a third sidewall spacer and a fourth sidewall spacer disposed on the opposing sidewalls of the first and second stacked transistors; and a first metal via disposed between the third and fourth sidewall spacers. Preferably, the first bottom dielectric insulating layer, the second bottom dielectric insulating layer, the first sidewall spacer and the second sidewall spacer each comprise a first dielectric material, and the third sidewall spacer and the fourth sidewall spacer each comprise a second dielectric material different from the first dielectric material. Preferably, the first metal via is connected to a back-end-of-the-line layer and a back-side power line. The structure may further comprise a front-facing source / drain contact located on a portion of the sidewall and top surface of the source / drain region of the second nanosheet field-effect transistor device; and a second metal via connected to the front-facing source / drain contact and a first back-facing power line. The structure may further comprise a back-facing metal contact located on the bottom surface of the source / drain region of the first nanosheet field-effect transistor and connected to a second back-facing power line.The structure may further comprise a back-side source / drain contact located on a portion of the sidewall and bottom surface of the source / drain region of the third nanosheet field-effect transistor; and a second metal via connected to the back-side source / drain contact and the back-end ob-the-line layer.

Claims

1. A semiconductor structure having a stacked device structure, wherein the stacked device structure is: A first field-effect transistor including a first source / drain region; A second field-effect transistor is stacked vertically above the first field-effect transistor, the second field-effect transistor including a second source / drain region and a gate region having a first sidewall spacer; Front-facing source / drain contacts located on the first portion of the side wall and top surface of the second source / drain region; The first metal via connected to the front source / drain contact and the first rear power line; and A second sidewall spacer positioned in the first portion of the first metal via; It has, The first sidewall spacer comprises a first dielectric material, and the second sidewall spacer comprises a second dielectric material different from the first dielectric material. Semiconductor structure.

2. The semiconductor structure according to claim 1, further comprising a bottom dielectric insulating layer disposed on a first portion of the bottom surface of the first source / drain region.

3. The semiconductor structure according to claim 2, wherein the bottom dielectric insulating layer includes a third dielectric material different from the second dielectric material.

4. The semiconductor structure according to claim 2, wherein the second portion of the first metal via is disposed within an interlayer dielectric layer.

5. The semiconductor structure according to claim 2, further comprising a back metal contact located on a second portion of the bottom surface of the first source / drain region and connected to a second back power line.

6. A third field-effect transistor including a third source / drain region; A fourth field-effect transistor is stacked vertically above the third field-effect transistor, the fourth field-effect transistor including a fourth source / drain region; The rear surface source / drain contacts located on the second portion of the side wall and bottom surface of the third source / drain region; and The second metal via is connected to the aforementioned backside source / drain contact and backside ob-the-line layer. Another stacked device structure adjacent to the stacked device structure having the above stacked device structure The semiconductor structure according to claim 1, further comprising:

7. The semiconductor structure according to claim 6, further comprising a back metal contact disposed on the bottom surface of the first source / drain region and connected to a second back power line.

8. The semiconductor structure according to claim 1, wherein the front-facing source / drain contacts are further disposed on a back-end-of-the-line layer.

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