Semiconductor backside isolation feature for merged epitaxy

Abstract

The semiconductor structure includes a front-end-of-line level containing multiple field-effect transistors. Each field-effect transistor includes source / drain regions located on both sides of the field-effect transistor. Shallow trench isolation regions located between adjacent field-effect transistors electrically separate the multiple field-effect transistors from each other. The shallow trench isolation regions have a tapered profile. A back-side isolation region is incorporated inside the shallow trench isolation region, cutting open the source / drain regions. The back-side isolation region has an inverse tapered profile.

Description

Background Art

[0001] The present invention generally relates to the field of semiconductor devices, and more particularly to powering of active devices.

[0002] Modern integrated circuits (ICs) are composed of transistors, capacitors, and other devices formed on a semiconductor substrate. On the substrate, these devices are initially separated from each other but are later interconnected to form functional circuits. A typical interconnect structure includes horizontal interconnects such as metal wires (wiring) and vertical interconnects such as vias and contacts. Power is provided to the integrated circuit through power rails within the metal layers of the integrated circuit. For example, a lower metal layer (M0 or M1) may include multiple metal wires such as VDD power rails and VSS power rails.

[0003] As the size of ICs continues to scale down, in order to alleviate design difficulties and enable technology scaling beyond the 5nm technology node, a backside power rail (BPR), that is, a power rail usually formed on the backside of the wafer under the transistor "fins", and backside power supply (the "backside" is below the transistor substrate) have been proposed. BPR technology liberates resources for high-density logic connections that limit modern processor performance, and by removing the overhead within the area occupied by the power rail, further scaling of standard logic cells becomes possible, enabling a thicker and lower-resistance power rail that allows for a smaller voltage (IR) drop. However, as scaling increases, it can become difficult to avoid the fusion of epitaxially grown structures in a narrow space ("epi merge"). Therefore, there is a need for improved process sequences and methods for forming backside interconnects with merged epitaxial features present.

Summary of the Invention

[0004] According to one embodiment of the present disclosure, the semiconductor structure comprises a front-end of line level having a plurality of field-effect transistors, each field-effect transistor having a shallow trench isolation region located between adjacent field-effect transistors to electrically separate the plurality of field-effect transistors from one another, the shallow trench isolation region having a tapered profile, and a back-side isolation region incorporated inside the shallow trench isolation region and cutting open the source / drain region, the back-side isolation region having an inverse tapered profile.

[0005] In one or more embodiments, the back-surface isolation region having the inverse tapered profile comprises an upper portion of the back-surface isolation region incorporated into the source / drain region, having a first limit dimension, and a lower portion of the back-surface isolation region incorporated into the shallow trench isolation region, having a second limit dimension, the second limit dimension being greater than the first limit dimension.

[0006] According to another embodiment of the present disclosure, a method for forming a semiconductor structure comprises the steps of: forming a front-end-of-line level including a plurality of field-effect transistors; forming shallow trench isolation regions between adjacent field-effect transistors to electrically separate the plurality of field-effect transistors from one another, each field-effect transistor including source / drain regions deposited on both sides of the field-effect transistor, the shallow trench isolation regions having a tapered profile; and forming a back-side isolation region incorporated inside the shallow trench isolation region and cutting open the source / drain regions, the back-side isolation region having an inverse tapered profile.

[0007] In one or more embodiments, the upper portion of the back surface isolation region is incorporated into the source / drain region and has a first limit dimension, and the lower portion of the back surface isolation region is incorporated into the shallow trench isolation region and has a second limit dimension, the second limit dimension being greater than the first limit dimension. [Brief explanation of the drawing]

[0008] The following detailed description is provided for illustrative purposes only and is not intended to limit the invention to thereon, and will be best understood in conjunction with the accompanying drawings.

[0009] [Figure 1] This is a top view of a semiconductor structure in an intermediate stage of a semiconductor manufacturing process, showing various cross-sectional views used to illustrate embodiments of the present disclosure.

[0010] [Figure 2-1] Figure 2A is a cross-sectional view of a semiconductor structure taken along line XX shown in Figure 1, after forming the front-end-of-line level, middle-of-line level, and back-end-of-line level according to one embodiment of the present disclosure and bonding the carrier wafer.

[0011] [Figure 2-2] Figure 2B is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1 shown in Figure 1.

[0012] Figure 2C is a cross-sectional view of the semiconductor structure taken along the line Y2-Y2 shown in Figure 1.

[0013] [Figure 3-1] Figure 3A is a cross-sectional view of a semiconductor structure taken along line XX shown in Figure 1, after the substrate has been removed, according to one embodiment of the present disclosure.

[0014] [Figure 3-2]FIG. 3B is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1 shown in FIG. 1.

[0015] FIG. 3C is a cross-sectional view of the semiconductor structure taken along the line Y2-Y2 shown in FIG. 1.

[0016] [Figure 4-1] FIG. 4A is a cross-sectional view of the semiconductor structure taken along the line X-X shown in FIG. 1, which is shown after removing the first sacrificial layer and recessing the remaining Si-containing areas according to an embodiment of the present disclosure.

[0017] [Figure 4-2] FIG. 4B is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1 shown in FIG. 1.

[0018] FIG. 4C is a cross-sectional view of the semiconductor structure taken along the line Y2-Y2 shown in FIG. 1.

[0019] [Figure 5-1] FIG. 5A is a cross-sectional view of the semiconductor structure taken along the line X-X shown in FIG. 1, which is shown after forming a dielectric cap according to an embodiment of the present disclosure.

[0020] [Figure 5-2] FIG. 5B is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1 shown in FIG. 1.

[0021] FIG. 5C is a cross-sectional view of the semiconductor structure taken along the line Y2-Y2 shown in FIG. 1.

[0022] [Figure 6-1] FIG. 6A is a cross-sectional view of the semiconductor structure taken along the line X-X shown in FIG. 1, which is shown after performing an etching process to form a self-aligned backside source / drain cut according to an embodiment of the present disclosure. <​​​ [Figure 6-2] FIG. 6B is a cross-sectional view of a semiconductor structure taken along line Y1-Y1 shown in FIG. 1.

[0024] FIG. 6C is a cross-sectional view of a semiconductor structure taken along line Y2-Y2 shown in FIG. 1.

[0025] [Figure 7-1] FIG. 7A is a cross-sectional view of semiconductor structure 100 taken along line X-X shown in FIG. 1, after forming a backside source / drain cut or isolation region according to an embodiment of the present disclosure.

[0026] [Figure 7-2] FIG. 7B is a cross-sectional view of a semiconductor structure taken along line Y1-Y1 shown in FIG. 1.

[0027] FIG. 7C is a cross-sectional view of a semiconductor structure taken along line Y2-Y2 shown in FIG. 1.

[0028] [Figure 8-1] FIG. 8A is a cross-sectional view of a semiconductor structure taken along line X-X shown in FIG. 1, after removing a dielectric cap and forming a backside interlayer dielectric according to an embodiment of the present disclosure.

[0029] [Figure 8-2] FIG. 8B is a cross-sectional view of a semiconductor structure taken along line Y1-Y1 shown in FIG. 1.

[0030] FIG. 8C is a cross-sectional view of a semiconductor structure taken along line Y2-Y2 shown in FIG. 1.

[0031] [Figure 9-1] FIG. 9A is a cross-sectional view of a semiconductor structure taken along line X-X shown in FIG. 1, after backside contact patterning according to an embodiment of the present disclosure.

[0032] [Figure 9-2] Figure 9B is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1 shown in Figure 1.

[0033] Figure 9C is a cross-sectional view of the semiconductor structure taken along the line Y2-Y2 shown in Figure 1.

[0034] [Figure 10-1] Figure 10A is a cross-sectional view of a semiconductor structure taken along line XX shown in Figure 1, after selective etching of the back-side interlevel dielectric according to one embodiment of the present disclosure.

[0035] [Figure 10-2] Figure 10B is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1 shown in Figure 1.

[0036] Figure 10C is a cross-sectional view of the semiconductor structure taken along the line Y2-Y2 shown in Figure 1.

[0037] [Figure 11-1] Figure 11A is a cross-sectional view of a semiconductor structure taken along line XX shown in Figure 1, after selective removal of the placeholder layer, according to one embodiment of the present disclosure.

[0038] [Figure 11-2] Figure 11B is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1 shown in Figure 1.

[0039] Figure 11C is a cross-sectional view of the semiconductor structure taken along the line Y2-Y2 shown in Figure 1.

[0040] [Figure 12-1] Figure 12A is a cross-sectional view of a semiconductor structure taken along line XX shown in Figure 1, after back-side contact metallization, according to one embodiment of the present disclosure.

[0041] [Figure 12-2] Figure 12B is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1 shown in Figure 1.

[0042] Figure 12C is a cross-sectional view of the semiconductor structure taken along the line Y2-Y2 shown in Figure 1.

[0043] [Figure 13-1] Figure 13A is a cross-sectional view of a semiconductor structure taken along line XX shown in Figure 1, after back-side power rail patterning and metallization have been performed according to one embodiment of the present disclosure to form a back-side power supply network.

[0044] [Figure 13-2] Figure 13B is a cross-sectional view of the semiconductor structure taken along the line Y1-Y1 shown in Figure 1.

[0045] Figure 13C is a cross-sectional view of the semiconductor structure taken along the line Y2-Y2 shown in Figure 1.

[0046] The drawings are not necessarily to scale. The drawings are for illustrative purposes only and are not intended to depict the specific parameters of the invention. The drawings are intended to show only typical embodiments of the invention. In the drawings, similar numbering indicates similar elements. [Modes for carrying out the invention]

[0047] Detailed embodiments of the claimed structure and method are disclosed herein; however, it should be understood that the disclosed embodiments are merely illustrative examples of the claimed structure and method, which may be embodied in various forms. Nevertheless, the present invention may be embodied in many different forms and should not be construed as being limited to the exemplary embodiments described herein. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0048] Hereafter, for explanatory purposes, terms such as “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives shall refer to the structures and methods disclosed as oriented in the drawings. Terms such as “on top of,” “on the top of,” “top of,” “positioned on top of,” or “positioned on the top of” mean that a first element, such as a first structure, is located on a second element, such as a second structure, and an intervening element, such as an interface structure, may be located between the first and second elements. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating, or semiconductor layer at the interface between the two elements.

[0049] To avoid ambiguity in the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations known in the art may be combined with each other for presentation and illustrative purposes, and in some cases may not be described in detail. In other cases, some processing steps or operations known in the art may not be described at all. It should be understood that the following description focuses rather on the specific features or elements of various embodiments of the present invention.

[0050] The disclosed embodiments include a detailed description of exemplary nanosheet FET architectures having silicon and silicon-germanium nanosheets, but it should be understood that implementations of the teachings described herein are not limited to the specific FET architectures described herein. Rather, embodiments of the present invention can be implemented in conjunction with any other type of FET device that is currently known or will be developed later.

[0051] As transistor dimensions continue to scale down, fusion of the source and drain epitaxial features of adjacent FET transistors becomes increasingly difficult to avoid. However, in some cases, if fusion is avoided, the separation of the source and drain epitaxial features may be insufficient, resulting in undesirable parasitic capacitance between the lateral sidewalls of adjacent source and drain epitaxial features. Therefore, source and drain epitaxial features may be intentionally formed to merge, anticipating that the merged features will be separated in subsequent processing stages.

[0052] Accordingly, embodiments of the present disclosure provide a method for forming a semiconductor structure in which merged epitaxial features are separated by self-aligning source / drain isolation regions formed using a back-side process. In the embodiments described below, the self-aligning back-side dielectric features (i.e., back-side isolation regions) electrically isolate the source / drain regions by cutting through the source / drain regions and a shallow trench isolation region located between two adjacent field-effect transistors. In one or more embodiments, the self-aligning back-side isolation regions have a first limiting dimension (CD1) near the upper source / drain epi and gate regions that is substantially smaller than a second limiting dimension (CD2) located near the lower portion of the shallow trench isolation region. In one or more embodiments, the self-aligning back-side isolation regions are at least partially in contact with a gate cut within the gate region of the semiconductor structure. Preferably, the back side of at least one source / drain epi region is electrically connected to a self-aligning contact on the back side, while the back side of another source / drain region, electrically connected to a middle-of-line contact, is in contact with a placeholder layer.

[0053] Embodiments of this disclosure utilize tapered shallow trench isolation regions to implement self-aligning backside source / drain cuts, where the source / drain cuts have different limit dimensions in the lower and upper regions. Cell height continues to scale, and the space between FETs becomes denser. The smaller upper limit dimension of the source / drain cuts occupies less space, addressing this concern. A placeholder everywhere approach is used in conjunction with EUV patterning to form a placeholder layer. The advantages of the placeholder everywhere approach include ensuring uniform epitaxial growth of the source / drain regions and placeholder layer across different FETs.

[0054] Embodiments that can form a semiconductor structure having a backside source / drain isolation region will be described in detail below with reference to the attached drawings Figures 1 to 13C.

[0055] Referring here to Figure 1, a top view of a semiconductor structure 100 at an intermediate stage in a semiconductor manufacturing process according to one embodiment of the present disclosure. In particular, Figure 1 shows various cross-sectional views of the semiconductor structure 100 that will be used to illustrate embodiments of the present disclosure. The cross-sectional views are taken along lines XX, Y1-Y1, and Y2-Y2. As shown in the figure, line XX represents a cut along the nanosheet fin structure or nanosheet fin region 20 of the semiconductor structure 100, line Y1-Y1 represents a cut across the nanosheet fin structure or nanosheet fin region 20, and line Y2-Y2 represents a cut along the gate structure or gate region 24 of the semiconductor structure 100. Not intended to be limiting, and for illustrative purposes only, Figure 1 is a simplified version of the semiconductor structure 100 and may not include detailed features of a particular manufacturing stage.

[0056] Referring to Figures 2A to 2C, the cross-sectional views of the semiconductor structure 100 after the front-end-of-line (FEOL) level 30, middle-of-line (MOL) level 32, and back-end-of-line (BEOL) level 240 have been completed and the carrier wafer has been bonded are shown. In this embodiment, Figure 2A is a cross-sectional view of the semiconductor structure 100 taken along line XX shown in Figure 1, Figure 2B is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1 shown in Figure 1, and Figure 2C is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2 shown in Figure 1.

[0057] As is known to those skilled in the art, modern semiconductor device fabrication processes allow for the fabrication of numerous semiconductor devices, such as field-effect transistors (FETs), on a single wafer. Several non-planar device architectures, including nanosheet FETs, offer higher device density and enhanced performance compared to planar devices. In nanosheet FETs, in contrast to conventional FETs, the gate stack wraps around the entire outer periphery of each nanosheet, thereby enabling more complete depletion within the channel region and reducing short-channel effects. Furthermore, the wrap-around gate structure used in nanosheet devices allows for better control of leakage current within the active region, even when the drive current increases.

[0058] Nanosheet FETs often contain thin, alternating layers (nanosheets) of different semiconductor materials arranged in a stack. Typically, the nanosheets are patterned to form nanosheet fins. Once the nanosheet fins are patterned, a gate stack is formed on the channel region of the nanosheet fins, and the source / drain region is formed adjacent to the gate stack. In some devices, once the gate stack or source / drain region is formed, an etching process is performed to selectively remove the nanosheet layer, which is one of the dissimilar materials, from the fins. The etching process results in undercutting and suspension of the nanosheet fin layer, forming a nanosheet or nanowire. Nanosheets or nanowires can be used to form gate-all-around devices.

[0059] According to one embodiment, known semiconductor fabrication operations are used to form the semiconductor structure 100 shown in Figures 2A to 2C. Therefore, conventional techniques for fabricating semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Furthermore, various tasks and process steps described herein can be incorporated into more comprehensive procedures or processes having additional steps or functions not described in detail herein. In particular, various steps in the fabrication of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional steps are only briefly mentioned herein or completely omitted without providing details of well-known processes.

[0060] In the embodiments shown, the semiconductor structure 100 includes a substrate 102, a first sacrificial layer 104 positioned on the substrate 102, and a first semiconductor layer 106 deposited on the first sacrificial layer 104. According to one embodiment, the first sacrificial layer 104 and the first semiconductor layer 106 are stacked vertically on top of each other in a direction perpendicular to the substrate 102, as shown in the figure.

[0061] For example, the substrate 102 may be a bulk substrate made from any of several known semiconductor materials, such as silicon, germanium, silicon-germanium alloys, and compound (e.g., III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide, or indium gallium phosphide. Typically, the substrate 102 may be about several hundred microns thick, but is not limited. In other embodiments, the substrate 102 may be a semiconductor with layers such as a silicon-on-insulator or SiGe-on-insulator, where an embedded insulator layer separates the base substrate from the upper semiconductor layer.

[0062] The first sacrificial layer 104 may be formed on the substrate 102 using an epitaxial growth process. For example, in the embodiments described, the first sacrificial layer 104 is formed by epitaxially growing a layer of SiGe having a germanium concentration ranging from about 15 atomic percent to about 35 atomic percent. In some embodiments, the first sacrificial layer 104 may be made of epitaxially grown SiGe having a germanium concentration of about 30 atomic percent. In one or more embodiments, the first sacrificial layer 104 may function as an etching stop layer during subsequent substrate removal. Similarly, the first semiconductor layer 106 is formed by epitaxially growing a Si layer to a thickness ranging from about 30 nm to about 250 nm, although other thicknesses are included in the range intended for the present invention. In some embodiments, the first sacrificial layer 104 may contain SiO2. In these embodiments, the combined structure formed by the substrate 102, the first sacrificial layer 104, and the first semiconductor layer 106 may be an SOI wafer in which the first sacrificial layer 104 is a buried oxide (BOX) having a thickness ranging from about 20 nm to about 100 nm and in between. As used herein, the term sacrificial means a layer or other structure (or part thereof) that is removed before the final device is completed.

[0063] Generally, the first sacrificial layer 104 and the first semiconductor layer 106 can be formed by epitaxial growth using the substrate 102 as a seed layer. Terms such as “epitaxial growth and / or deposition” and “epitaxially formed and / or grown” refer to the growth of one semiconductor material on a deposition surface of another semiconductor material, where the grown semiconductor material has the same or substantially similar crystalline properties as the semiconductor material on the deposition surface. In the epitaxial deposition process, the chemical reactants provided by the source gas are controlled and system parameters are set so that the atoms to be deposited have enough energy to reach the deposition surface of the semiconductor substrate and orient themselves to match the crystalline structure of the atoms on the deposition surface. Thus, the epitaxial semiconductor material has the same or substantially similar crystalline properties as the deposition surface on which it is formed. For example, an epitaxial semiconductor material deposited on a {100} crystal surface will adopt a {100} orientation. In some embodiments, the epitaxial growth and / or deposition process is selective for formation on semiconductor surfaces and does not deposit material on dielectric surfaces such as silicon dioxide or silicon nitride surfaces.

[0064] Non-limiting examples of various epitaxial growth processes include rapid thermochemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), metal-organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), limited-reaction-process CVD (LRPCVD), and molecular beam epitaxy (MBE). Temperatures for epitaxial deposition processes can range from 500°C to 900°C. Higher temperatures generally result in faster deposition, but faster deposition can lead to crystal defects and film cracks.

[0065] A number of different precursors can be used for the epitaxial growth of the first sacrificial layer 104 and the first semiconductor layer 106. In some embodiments, the gas source for depositing the epitaxial semiconductor material includes a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, the epitaxial silicon layer may be deposited from a silicon gas source that includes, but is not limited to, silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. The epitaxial germanium layer may be deposited from a germanium gas source that includes, but is not limited to, german, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. Combinations of these gas sources can be used to form an epitaxial silicon-germanium alloy layer. Carrier gases such as hydrogen, helium, and argon can be used.

[0066] The semiconductor structure 100 further includes a plurality of field-effect transistors (FETs) or nanostructured devices 36 formed on a first semiconductor layer 106. According to one embodiment, the nanostructured device 36 may include gate-all-around (GAA) devices. In some embodiments, the nanostructured device 36 may include at least one of NFET devices or PFET devices. In some embodiments, the nanostructured device 36 may include only NFET devices. In yet another embodiment, the nanostructured device 36 may include only PFET devices.

[0067] Each of the nanostructured devices 36 includes a semiconductor channel layer 112. In the nanostructured device 36 shown in Figure 2A, the semiconductor channel layer 112 is abutted laterally by a source / drain region 208 and surrounded by a gate structure 210. The gate structure 210 controls the flow of current through the semiconductor channel layer 112 based on the voltage applied to the gate structure 210 and the source / drain region 208.

[0068] While other thicknesses fall within the range intended for this invention, in the shown embodiments, the semiconductor channel layer 112 is formed by epitaxially growing a Si layer to a thickness varying from about 6 nm to about 12 nm. In other embodiments, the semiconductor channel layer 112 may include silicon germanium, silicon carbide, silicon phosphide, or another suitable semiconductor material. In embodiments where the nanostructured device 36 is an NFET device, the source / drain region 208 may include, for example, phosphorus-doped silicon (Si:P), or another suitable material. In embodiments where the nanostructured device 36 is a PFET device, the source / drain region 208 may include, for example, silicon germanium (SiGe), or another suitable material.

[0069] The gate structure 210 (i.e., replacement gate) is deposited on and between the semiconductor channel layers 112. The gate structure 210 includes a gate dielectric, such as hafnium oxide (HfO2), zirconium dioxide (ZrO2), aluminum hafnium oxide (HfAlOx), lanthanum hafnium oxide (HfLaOx), and one or more work function metals, including but not limited to titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), and aluminum titanium carbide (TiAlC), and a conductive metal, such as aluminum (Al), tungsten (W), or cobalt (Co). The gate structure 210 surrounds the semiconductor channel layers 112. In some embodiments, a gate cap (not shown) may be formed on the gate structure 210.

[0070] The nanostructured device 36 also includes a gate spacer 212 deposited on the sidewall of the gate structure 210, and an inner spacer 214 deposited between the semiconductor channel layers 112. The gate spacer 212 and the inner spacer 214 may include dielectric materials, such as low-k materials like SiOCN, SiON, SiN, or SiOC.

[0071] In one or more embodiments, a spacer material deposited between the lower surface of the nanostructured device 36 and the first semiconductor layer 106 may be called the lower dielectric isolation layer 110. In some embodiments, the lower dielectric isolation layer 110 and the gate spacer 212 may be composed of different materials.

[0072] It should be noted that in one or more embodiments, a gate-cutting process may be performed on the semiconductor structure 100 to isolate gate structures 210 corresponding to different CMOS cells. As shown in Figure 2C, during the process, the gate-cutting region 216 is formed either before or after the replacement metal gate (RMG) and then filled with a dielectric such as SiO2, SiN, SiBCN, SiOCN, SiOC, SiC, and the like.

[0073] The semiconductor structure 100 further includes an interlevel dielectric layer 220 deposited on a nanostructure device 36. The interlevel dielectric layer 220 covers the uppermost surface of a source / drain region 208 located between adjacent nanostructure devices 36 and surrounds a plurality of conductive structures or metal contacts 230. The interlevel dielectric layer 220 fills voids and electrically isolates the active region within the semiconductor structure 100. The interlevel dielectric layer 220 can be formed by conformal deposition (e.g., CVD) of a dielectric material. Non-limiting examples of dielectric materials for forming the interlevel dielectric layer 220 may include silicon oxide, silicon nitride, silicon hydride carbon oxide, silicon-based low-k dielectrics, fluid oxides, porous dielectrics, or organic dielectrics including porous organic dielectrics.

[0074] According to one embodiment, a metal contact 230 is formed within a semiconductor structure 100 to electrically connect a FEOL device (i.e., a nanostructured device 36) to a subsequently formed metal level. The process for forming the metal contact 230 is standard and well known in the art. Typically, the process involves forming a trench (not shown) within an interlevel dielectric layer 220, and subsequently filling the trench with a conductive material or a combination of conductive materials to form the metal contact 230. In one or more embodiments, the conductive material filling the metal contact 230 may include a silicide liner (e.g., titanium (Ti), nickel (Ni), nickel-platinum (NiPt) alloy), a metal-bonding liner (e.g., titanium nitride (TiN)), and a conductive metal (e.g., aluminum (Al), tungsten (W), copper (Co), ruthenium (Ru), or any combination thereof).

[0075] The conductive material can be deposited by a suitable deposition process, such as CVD, PECVD, PVD, plating, thermal or electron beam deposition, or sputtering. A planarization process, such as CMP, is performed to remove any conductive material from the upper surface of the semiconductor structure 100. In the example shown, the metal contact 230 includes a source / drain contact extending to the uppermost surface of the source / drain region 208, and a gate contact leading to the gate structure 210.

[0076] According to one embodiment, the semiconductor structure 100 further includes a placeholder layer 202 formed inside the first semiconductor layer 106 and deposited between adjacent nanostructure devices 36. The placeholder layer 202 is formed beneath each of the source / drain regions 208 (i.e., a method of placing placeholders throughout). In one or more embodiments, the placeholder layer 202 can be formed inside the first semiconductor layer 106 using EUV lithography followed by the deposition of placeholder material. The placeholder layer 202 functions as a placeholder for the subsequently formed backside metal contacts, as suggested by its name. The material forming the placeholder layer 202 may include, for example, SiGe, AlOx, TiOx, and the like. In some embodiments, the upper surface of the placeholder layer 202 may be coplanar with the upper surface of the lower dielectric isolation layer 110. In other embodiments, a buffer layer 108, typically made of silicon (Si), may be formed between the source / drain region 208 and the underlying placeholder layer 202. In these embodiments, as shown in Figure 2A, the upper surface of the buffer layer 108 is coplanar with the upper surface of the lower dielectric isolation layer 110. The buffer layer 108 ensures that the source / drain region 208 (e.g., PFET source / drain SiGe epitaxy) is separated from the placeholder layer 202 (SiGe) epitaxy.

[0077] The semiconductor structure 100 further includes a shallow trench isolation (STI) region 120 surrounded by an STI liner 126. Methods for forming the STI region 120 and the STI liner 126 are standard and well known in the art and typically involve depositing an insulating material to substantially fill a number of trenches (not shown) created after a processing step of removing a portion of a first semiconductor layer 106 located between adjacent nanostructure devices 36 from the semiconductor structure 100. According to one embodiment, the STI region 120 and the STI liner 126 electrically isolate the nanostructure devices 36 from each other. The STI region 120 and the STI liner 126 can be formed, for example, by CVD of a dielectric material. Non-limiting examples of dielectric materials for forming the STI region 120 include silicon oxide, silicon nitride, silicon hydride carbon oxide, silicon-based low-k dielectrics, fluid oxides, porous dielectrics, or organic dielectrics including porous organic dielectrics. In one or more embodiments, the STI liner 126 may include a nitride material. In another embodiment, the STI liner 126 may include an oxidizing material. In yet another embodiment, the STI liner 126 may include a two-layer STI liner comprising a nitride liner and an underlying oxidizing liner.

[0078] In the proposed embodiment, it should be noted that the STI region 120 is formed in a tapered profile as shown in Figures 5B to 5C. As will be described in detail below, the tapered STI region 120 makes it possible to form a self-aligning back surface isolation region within the semiconductor structure 100.

[0079] In the embodiments shown, the semiconductor structure 100 further includes a BEOL interconnection level 240, which is formed on top of the FEOL device level 30 and electrically connected to it. As may be known to those skilled in the art, though not shown in the figures, the BEOL interconnection level 240 typically includes contacts, an insulating layer (dielectric), a metal level, and junctions for chip-to-package connections. As mentioned above, the various stages in the manufacture of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional stages will be only briefly mentioned herein or completely omitted without providing details of well-known processes.

[0080] According to one embodiment, after forming the BEOL interconnection level 240, the semiconductor structure 100 (i.e., the semiconductor wafer) is bonded to a carrier wafer (or auxiliary substrate) 250. The carrier wafer 250 can function as a reinforcing substrate to provide mechanical strength during processing (e.g., thinning) of the semiconductor wafer. The process of bonding the semiconductor wafer to the carrier wafer 250 can be achieved by conventional wafer bonding processes such as dielectric-to-dielectric bonding or Cu-to-Cu bonding.

[0081] Therefore, the carrier wafer 250 may include a silicon oxide layer or a SiCN layer, or any other layer applicable to direct bonding techniques used in current-level packaging techniques. Bonding of the device wafer to the carrier wafer 250 is performed by such known direct bonding techniques, thus obtaining the assemblies shown in Figures 2A to 2C. Although not shown in the figures, after bonding the device wafer to the carrier wafer 250, the wafer is inverted.

[0082] Referring now to Figures 3A to 3C, cross-sectional views of the semiconductor structure 100 after the substrate 102 (Figures 2A to 2C) has been removed, according to one embodiment of the present disclosure. In this embodiment, Figure 3A is a cross-sectional view of the semiconductor structure 100 taken along line XX shown in Figure 1, Figure 3B is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1 shown in Figure 1, and Figure 3C is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2 shown in Figure 1.

[0083] In the embodiments shown, after inverting the wafer (not shown), the substrate 102 (Figures 2A-2C) can be removed using a selective etching process, including conventional grinding, CMP, and wet or dry etching techniques. In one or more embodiments, the grinding process is carried out until the substrate 102 is substantially removed from the semiconductor structure 100, leaving only a few microns of Si. A further optional CMP process can then be used to reduce thickness variations, and finally, a highly selective Si etching process is used to selectively remove the remaining substrate 102 from the semiconductor structure 100 to a first sacrificial layer 104. In the embodiments shown, the first sacrificial layer 104 acts as an etching stop during the highly selective Si removal process to prevent excessive Si etching that could damage the gate structure 210 and source / drain region 208.

[0084] Referring now to Figures 4A to 4C, cross-sectional views of the semiconductor structure 100 after removing the first sacrificial layer 104 and creating a recess for the remaining Si-containing area (i.e., the first semiconductor layer 106) are shown according to one embodiment of the present disclosure. In this embodiment, Figure 4A is a cross-sectional view of the semiconductor structure 100 taken along line XX shown in Figure 1, Figure 4B is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1 shown in Figure 1, and Figure 4C is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2 shown in Figure 1.

[0085] The first sacrificial layer 104 (Figures 3A-3C) can be selectively removed from the first semiconductor layer 106 using any suitable etching technique. In embodiments where the first sacrificial layer 104 (Figures 3A-3C) is made of SiGe, the first sacrificial layer 104 can be removed using hot SC1 or dry HCl etching. In embodiments where the first sacrificial layer 104 (Figures 3A-3C) is made of SiO2, the first sacrificial layer 104 can be removed from the semiconductor structure 100 using DHF wet cleaning.

[0086] In one or more embodiments, a highly selective Si etching process can be performed following the removal of the first sacrificial layer 104 to create a recess in the first semiconductor layer 106 without damaging the STI liner 126 and STI region 120. As shown in Figures 4B to 4C, selective recessing of the first semiconductor layer 106 exposes the lowest portion of the STI liner 126 opposite the uppermost portion of the STI liner 126 / STI region 120 that is in contact with the gate structure 210, as can be observed in Figure 4C.

[0087] Referring now to Figures 5A to 5C, cross-sectional views of the semiconductor structure 100 after the dielectric cap 502 has been formed according to one embodiment of the present disclosure are shown. In this embodiment, Figure 5A is a cross-sectional view of the semiconductor structure 100 taken along line XX shown in Figure 1, Figure 5B is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1 shown in Figure 1, and Figure 5C is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2 shown in Figure 1.

[0088] In this embodiment, a dielectric material (e.g., SiC) can be deposited on the exposed portions of the recessed first semiconductor layer 106 and STI liner 126 using any known deposition process to form a dielectric cap 502. After depositing the dielectric material, chemical mechanical polishing (CMP) can be performed down to the STI liner 126 to remove excess material and polish the upper surface of the semiconductor structure 100. Thus, after CMP, the exposed surfaces of the dielectric cap 502 and STI liner 126 become substantially flat or coplanar.

[0089] Referring now to Figures 6A to 6C, cross-sectional views of the semiconductor structure 100 after an etching process to form a self-aligning backside source / drain cut according to one embodiment of the present disclosure are shown. In this embodiment, Figure 6A is a cross-sectional view of the semiconductor structure 100 taken along line XX shown in Figure 1, Figure 6B is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1 shown in Figure 1, and Figure 6C is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2 shown in Figure 1.

[0090] In the embodiment shown, a back surface opening 620 is formed inside the semiconductor structure 100 by performing a two-step etching process. For example, in this embodiment, the first step includes performing a first etching process up to the back surface region of the gate structure 210 and gate cut region 216, as shown in Figure 6C. The first etching process includes, for example, a plasma etching process using a C4F8 chemical reaction.

[0091] Referring further to Figures 6A to 6C, the second step of the two-step etching process used to form the back surface opening 620 includes performing a selective second etching process on the gate structure 210 and the gate cut region 216. The second etching process includes, for example, a plasma etching process using an SF6 / CH2F2 or SF6 / O2 chemical reaction.

[0092] By performing a second etching process, the back opening 620 is selectively extended through the source / drain region 208. More specifically, as shown in Figure 6B, the back opening 620 cuts open adjacent source / drain regions 208 (i.e., the source / drain regions 208 of two consecutive nanostructured devices 36) to create a space between these regions, providing a self-aligning back source / drain cut. In one or more embodiments, the second etching process may be performed until the back opening 620 reaches the interlevel dielectric layer 220.

[0093] Therefore, in the embodiment shown, the back opening 620 is formed by selectively etching a portion of the STI region 120, a portion of the STI liner 126, and the merged portion of adjacent source / drain regions 208. Note that the tapered STI region 120 makes it possible to form the back opening 620 with an inverse (or negative) tapered etching profile that narrows in the direction toward the interlevel dielectric layer 220.

[0094] Referring now to Figures 7A to 7C, cross-sectional views of the semiconductor structure 100 after the formation of a back-side source / drain cut or isolation region 750 according to one embodiment of the present disclosure are shown. In this embodiment, Figure 7A is a cross-sectional view of the semiconductor structure 100 taken along line XX shown in Figure 1, Figure 7B is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1 shown in Figure 1, and Figure 7C is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2 shown in Figure 1.

[0095] In this embodiment, a dielectric material can be deposited inside the back opening 620 (Figures 6A-6B) to form a back source / drain isolation region 750 between the source / drain regions 208. In an exemplary embodiment, the dielectric material may include silicon nitride and may be deposited using a conformal deposition process (e.g., CVD). The dielectric material fills the narrowing portion of the back opening 620 (Figures 6A-6B) that extends toward the interlevel dielectric layer 220.

[0096] As shown in Figure 7B, the back-side source / drain isolation region 750 may include an upper portion having a first limit dimension (CD1) and a lower portion having a second limit dimension (CD2), where CD2 is greater than CD1 (CD2 > CD1). This results from the back-side opening 620 (Figures 6A-6C) having an inverse tapered profile, as described above. Thus, the back-side source / drain isolation region 750 has tapered sidewalls formed at an angle that narrows toward the interlevel dielectric layer 220. The back-side source / drain isolation region 750 electrically isolates the adjacent (merged) source / drain region 208.

[0097] Referring now to Figures 8A to 8C, cross-sectional views of the semiconductor structure 100 after removing the dielectric cap 502 and forming the backside interlayer dielectric (BILD) 820 according to one embodiment of the present disclosure are shown. In this embodiment, Figure 8A is a cross-sectional view of the semiconductor structure 100 taken along line XX shown in Figure 1, Figure 8B is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1 shown in Figure 1, and Figure 8C is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2 shown in Figure 1.

[0098] According to one embodiment, dielectric caps 502 (Figures 7A-7C) can be removed from the semiconductor structure 100 using any suitable etching technique. For example, dielectric caps 502 can be removed using a plasma etching process based on a Cl-Br chemical reaction.

[0099] After removing the dielectric cap 502 (Figures 7A-7C), the BILD820 can be formed using standard methods and materials, such as those used to form the interlevel dielectric layer 220 described above with reference to Figures 2A-2C. The BILD820 is deposited on and in direct contact with the placeholder layer 202, the STI liner 126, the lower dielectric isolation layer 110, and the back surface source / drain isolation region 750. In one exemplary embodiment, the thickness of the BILD820 may vary between approximately 40 nm and approximately 300 nm, and in between. In one or more embodiments, after forming the BILD820, a planarization process (e.g., CMP) can be performed on the semiconductor structure 100.

[0100] Referring now to Figures 9A to 9C, cross-sectional views of the semiconductor structure 100 after back surface contact patterning are shown according to one embodiment of the present disclosure. In this embodiment, Figure 9A is a cross-sectional view of the semiconductor structure 100 taken along line XX shown in Figure 1, Figure 9B is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1 shown in Figure 1, and Figure 9C is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2 shown in Figure 1.

[0101] According to one embodiment, an organic planarization layer (OPL), or simply a planarization layer 910, can be deposited on the semiconductor structure 100. The planarization layer 910 can be made of any organic planarization material capable of effectively preventing damage to the underlying layer during a subsequent etching process. The planarization layer 910 may, but is not limited to, include an organic polymer containing C, H, and N. In one embodiment, silicon (Si) may not be present in the organic planarization material. In another embodiment, Si and fluorine (F) may not be present in the organic planarization material. As defined herein, if the level of a certain atomic element in a material is at or below a trace level detectable by analytical methods available in the art, then that atomic element is not present in the material. Non-limiting examples of organic planarization materials for forming the planarization layer 910 may include JSR HM8006, JSR HM8014, AZ UM10M2, Shin Etsu ODL 102, or other similar commercially available materials. The planarization layer 910 can be deposited, for example, by spin coating.

[0102] Continuing to refer to Figures 9A to 9C, a lithography process and a subsequent etching process are performed on the semiconductor structure 100 to etch the planarization layer 910 to form the opening 950 shown in the figure. In some embodiments, etching of the planarization layer 910 may be performed by an OPL RIE including, for example, trace point detection. In one or more embodiments, the location of the opening 950 may be selected based on a desired location of a subsequent backside metal contact.

[0103] Referring now to Figures 10A to 10C, cross-sectional views of the semiconductor structure 100 after selective etching of BILD820 according to one embodiment of the present disclosure are shown. In this embodiment, Figure 10A is a cross-sectional view of the semiconductor structure 100 taken along line XX shown in Figure 1, Figure 10B is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1 shown in Figure 1, and Figure 10C is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2 shown in Figure 1.

[0104] After patterning the planarization layer 910, an etching process can be performed on the semiconductor structure 100 to selectively remove portions of BILD 820 from the placeholder layer 202, the STI liner 126, and the back-side source / drain isolation region 750. In one exemplary embodiment, a plasma etching process using a C4F4 chemical reaction can be performed on the semiconductor structure 100 to remove BILD 820. As shown in the figure, etching BILD 820 enlarges the size of the opening 950, exposing portions of one or more placeholder layers 202. Note that the selectivity between BILD 820 and the STI liner 126 and the back-side source / drain isolation region 750 results in a self-aligning etching process that facilitates the formation of back-side contacts.

[0105] Referring now to Figures 11A to 11C, cross-sectional views of the semiconductor structure 100 after selective removal of the placeholder layer 202 according to one embodiment of the present disclosure are shown. In this embodiment, Figure 11A is a cross-sectional view of the semiconductor structure 100 taken along line XX shown in Figure 1, Figure 11B is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1 shown in Figure 1, and Figure 11C is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2 shown in Figure 1.

[0106] In the embodiments shown, the placeholder layer 202 exposed by the opening 950 can be removed from the semiconductor structure 100. Exemplary techniques suitable for selectively removing the placeholder layer 202 from the semiconductor structure 100 may include, but are not limited to, dry HCl etching that can minimize or eliminate damage to the underlying layers.

[0107] As shown in Figures 1A to 11B, after the placeholder layer 202 is removed, one or more of the source / drain regions 208 are exposed by the opening 950 (i.e., back surface contact vias). More specifically, the area of ​​one or more source / drain regions 208 exposed by the opening 950 corresponds to the first (lower) surface of the source / drain region 208, opposite the second (upper) surface of the source / drain region 208 that is in contact with the interlevel dielectric layer 220. A portion of BILD 820 remains on top of the lower dielectric isolation layer 110 in the gate region 24 (Figure 1) of the semiconductor structure 100 shown in Figure 11C.

[0108] As can be observed in the figure, the opening 950 exposes the first surface of at least one source / drain region 208 adjacent to at least one other source / drain region 208 that is electrically in contact with the metal contact 230. It should be noted that the location of the opening 950 shown is for illustrative purposes only, and it should be understood that a different location may be selected based on design requirements.

[0109] Alternatively, or additionally, a via gauging process may be performed on the semiconductor structure 100 to reinforce the interfaces between the openings 950 (i.e., back surface contact vias) and subsequently to form a back surface metal layer.

[0110] Referring now to Figures 12A to 12C, cross-sectional views of the semiconductor structure 100 after back-side contact metallization according to one embodiment of the present disclosure are shown. In this embodiment, Figure 12A is a cross-sectional view of the semiconductor structure 100 taken along line XX shown in Figure 1, Figure 12B is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1 shown in Figure 1, and Figure 12C is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2 shown in Figure 1.

[0111] According to one embodiment, a back metal is deposited within the semiconductor structure 100 to substantially fill the opening 950 (Figures 11A to 11C), thereby forming a back metal contact 1210 to one or more source / drain regions 208. In one or more embodiments, the back metal contact 1210 may be formed between adjacent source / drain regions 208 located within the NFET region or PFET region of the semiconductor structure 100. In the shown embodiment, the back metal contact 1210 is formed to be in direct contact with the first (lower) surface of one or more source / drain regions 208.

[0112] Referring now to Figures 13A to 13C, cross-sectional views of the semiconductor structure 100 after backside power rail patterning and metallization have been performed according to one embodiment of the present disclosure to form a backside power delivery network (BSPDN). In this embodiment, Figure 13A is a cross-sectional view of the semiconductor structure 100 taken along line XX shown in Figure 1, Figure 13B is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1 shown in Figure 1, and Figure 13C is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2 shown in Figure 1.

[0113] In the embodiments shown, the back-side power rail (BPR) 1320 is formed inside a BILD layer which is substantially similar to BILD 820. For simplicity, the newly deposited BILD layer is still referred to as BILD 820. The process for forming the BPR 1320 includes patterning the back-side power rail trench (not shown) within the BILD 820 by, for example, conventional lithography and reactive ion etching. In the example shown, the back-side power rail trench (not shown) is etched until it reaches the top surface of the back-side contact 1210. In some embodiments, the aspect ratio of the back-side power rail trench (not shown) can be about 0.5 to 5.0.

[0114] To form the BPR1320, a back-side power rail trench (not shown) can be filled with a conductive metal. The choice of metallization for the back-side power rail is based on where in the integration flow the rail is formed and metallized. In the embodiments shown, the BPR1320 is formed on the back surface of the semiconductor structure 100. In such cases, the BPR1320 may be formed by depositing layers of, for example, ruthenium (Ru) or Cu. In other embodiments, the conductive metal forming the BPR1320 may include Co, W, Al, and the like. According to one embodiment, the back-side BPR1320 is electrically connected to one or more back-side contacts 1210 to supply power to a device (e.g., a field-effect transistor) in FEOL level 30 (Figures 2A-2C).

[0115] In embodiments where the semiconductor structure 100 includes a PFET device, the BPR1320 may include a VDD rail incorporated within the PFET region of the semiconductor structure 100, electrically connected to the (P-type) source / drain region 208 through a back-side contact 1210 (located between adjacent P-type source / drain regions 208). In embodiments where the semiconductor structure 100 includes an NFET device, the BPR1320 may include a VSS rail incorporated within the NFET region of the semiconductor structure 100, electrically connected to the N-type source / drain region 208 through a back-side contact 1210 (located between adjacent N-type source / drain regions 208).

[0116] Note that the source / drain regions 208 wired to the BPR1320 are not connected to the BEOL interconnection level 240. More specifically, as shown in the figure, at least one BPR1320 is electrically connected to the source / drain region 208 of a transistor or nanostructure device 36 through at least one back-side contact 1210, and a back-side source / drain isolation region 750 electrically separates adjacent source / drain regions 208.

[0117] Continuing to refer to Figures 13A to 13C, the structure of the BSPDN1340 can be constructed according to known techniques. Depending on the exact function of the transistor configuration, multiple source / drain regions 208 can be connected to the back power and ground via back contacts 1210.

[0118] It should be noted that the BEOL interconnect level 240 in the semiconductor structure 100 manufactured according to the disclosed technology is separated from the BSPDN 1340, thereby increasing the routing resources within the semiconductor structure 100 for signal routing within the BEOL interconnect level 240.

[0119] Accordingly, according to the proposed embodiment, the semiconductor structure includes a front-end-of-line level having a plurality of field-effect transistors. Each field-effect transistor includes source / drain regions deposited on both sides of the field-effect transistor. A shallow trench isolation region is positioned between adjacent field-effect transistors to electrically separate the plurality of field-effect transistors from one another. The shallow trench isolation region has a tapered or positive profile. A back-side isolation region is incorporated inside the shallow trench isolation region and cuts open the previously merged source / drain regions, electrically separating the source / drain regions from one another. The back-side isolation region has an inverse or negative tapered profile. Preferably, the back-side isolation region has an upper portion incorporated inside the source / drain region having a first limiting dimension, and a lower portion incorporated inside the shallow trench isolation region having a second limiting dimension, the second limiting dimension being greater than the first limiting dimension of the back-side isolation region.

[0120] In one or more embodiments, the shallow trench isolation region further includes a shallow trench isolation liner surrounding the lower opposing side walls of the shallow trench isolation region. The shallow trench isolation liner is at least partially in contact with the lower portion of the back surface isolation region.

[0121] The semiconductor structure further includes an interlevel dielectric layer deposited on top of a field-effect transistor, and a back-side interlevel dielectric provided beneath the field-effect transistor. Metal contacts are formed within the interlevel dielectric layer to electrically connect a first surface of at least one source / drain region to the back-side ob-line level. In a preferred embodiment, a placeholder layer is formed within the back-side interlevel dielectric and in contact with a second surface of at least one source / drain region, opposite the first surface of at least one source / drain region. Back-side metal contacts are formed within the back-side interlevel dielectric layer to electrically connect a second surface of at least another source / drain region to the back-side power rail. The first surface of at least another source / drain region is in contact with the interlevel dielectric layer.

[0122] The semiconductor structure further includes a carrier wafer positioned above the back-end obline level, and a back-side power supply network deposited on back-side power rails.

[0123] In one or more embodiments, each of the field-effect transistors includes a gate structure positioned on and surrounding a plurality of channel layers, the gate structure of a field-effect transistor being electrically isolated from the gate structure of an adjacent field-effect transistor by a gate-cut isolation region. Preferably, as shown in Figure 13C, the back-side isolation region is in contact with the gate-cut isolation region within the gate region of the semiconductor structure.

[0124] According to the proposed embodiment, a method for forming a semiconductor structure includes the steps of forming a front-end-of-line level including a plurality of field-effect transistors, each field-effect transistor including source / drain regions deposited on both sides of the field-effect transistor, forming shallow trench isolation regions between adjacent field-effect transistors to electrically separate the plurality of field-effect transistors from one another, the shallow trench isolation regions having a tapered profile, and forming a back-side isolation region incorporated inside the shallow trench isolation region and cutting open the source / drain region, the back-side isolation region having an inverse tapered profile. The method further includes forming a placeholder layer in contact with a second surface of the source / drain region, opposite a first surface of the source / drain region. The placeholder layer is formed inside the first semiconductor layer. Preferably, metal contacts are formed inside an interlevel dielectric layer deposited on top of the field-effect transistors to electrically connect the first surface of at least one source / drain region to the back-end-of-line level, and a carrier wafer is formed on top of the back-end-of-line level. In one embodiment, each field-effect transistor includes a gate structure deposited on and surrounding multiple channel layers. The gate structure of a field-effect transistor is electrically isolated from the gate structure of an adjacent field-effect transistor by a gate-cut isolation region.

[0125] In one or more embodiments, the step of forming a shallow trench isolation region further includes the step of forming a shallow trench isolation liner that surrounds the lower opposing side walls of the shallow trench isolation region.

[0126] The method further includes the step of forming an etching stop sacrificial layer between the first semiconductor layer and the substrate.

[0127] In one or more embodiments, the step of forming a backside isolation region further includes removing a substrate and an etching stop layer from the semiconductor structure, recessing a first semiconductor layer to expose a shallow trench isolation liner, and forming a dielectric cap on the recessed first semiconductor layer, wherein the upper surface of the dielectric cap is coplanar with the upper surface of the shallow trench isolation liner. The method further includes performing a first etching process until the surface of the gate structure is reached, the first etching process exposing the gate structure and a portion of the gate cut, and performing a second etching process to cut open the source / drain region.

[0128] The method further includes the steps of: depositing dielectric filling material in recesses formed after a first etching process and a second etching process; forming a back-side interlevel dielectric; performing a patterning process on the back-side interlevel dielectric; selectively removing a placeholder layer from source / drain regions not electrically connected to metal contacts; depositing a conductive material inside the patterned back-side interlevel dielectric to form back-side metal contacts; forming back-side power rails to the back-side metal contacts; and forming a back-side power supply network on the back-side power rails.

[0129] Preferably, the back-side isolation region includes an upper portion having a first limit dimension and incorporated into the source / drain region, and a lower portion having a second limit dimension greater than the first limit dimension and incorporated into the shallow trench isolation region. According to one embodiment, the back-side isolation region is in contact with the gate cut isolation region within the gate region of the semiconductor structure.

[0130] The methods described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packaged form. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads fixed to a motherboard or other higher-level carrier) or multi-chip packages (e.g., ceramic carriers with either or both surface interconnects or embedded interconnects). In either case, the chips are then integrated together with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product containing integrated circuit chips, ranging from toys and other low-cost applications to displays, keyboards or other input devices, and advanced computer products with central processors.

[0131] The terminology used herein is intended solely to describe specific embodiments and is not intended to limit the disclosure. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form unless otherwise explicitly stated in the context. It will be further understood that the terms “comprise” and / or “comprising,” where used herein, specify the presence of the described feature, integer, stage, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integers, stages, operations, elements, components, and / or groups thereof. “Optional” or “optionally” means that the event or situation described thereafter may or may not occur, and the description includes both instances in which the event occurs and instances in which it does not.

[0132] Spatially relative terms such as “inside,” “outside,” “down,” “below,” “underside,” “up,” “top,” “bottom,” and similar terms may be used herein to describe the relationship of one element or feature shown in a figure to another element or feature, for the sake of simplicity of explanation. Spatially relative terms may be intended to encompass different orientations of the device during use or operation, in addition to the orientation shown in the figure. For example, if the device in the figure is turned over, an element described as “below” or “below” another element or feature will be oriented “above” that other element or feature. Thus, the exemplary term “down” may encompass both upward and downward orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0133] Where used herein and throughout the claims, the word "approximate" can be applied to modify any quantitative expression that may vary acceptablely without altering its fundamental function. Therefore, values ​​modified by one or more terms such as "about," "approximately," and "substantially" should not be limited to the exact value specified. In at least some cases, the word "approximate" may correspond to the precision of the instrument used to measure the value. Herein, and throughout the specification and claims, limitations on ranges may be combined and / or interchangeable, and such ranges are specified and, unless otherwise indicated by context or wording, include all subranges contained therein. "About," as applied to a particular value within a range, may apply to both values ​​and, unless otherwise dependent on the precision of the instrument used to measure the value, may indicate + / - 10% of the stated value.

[0134] The descriptions of various embodiments of the present invention have been presented for illustrative purposes only and are not intended to be exhaustive or to limit the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best describe the principles of the embodiments, their practical applications, or any technological improvements over the technology available on the market, or to enable other those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A front-end-of-line level having multiple field-effect transistors, each field-effect transistor including source / drain regions located on both sides of the field-effect transistor; A shallow trench isolation region is positioned between adjacent field-effect transistors to electrically separate the plurality of field-effect transistors from one another, the shallow trench isolation region having a tapered profile; and A back-side isolation region is incorporated inside the shallow trench isolation region and cuts open the source / drain region, and the back-side isolation region has an inverse tapered profile. A semiconductor structure comprising the features described above.

2. The aforementioned back surface separation region having an inverse tapered profile is The upper portion of the back surface separation region incorporated inside the source / drain region having a first limit dimension; and A lower portion of the back surface isolation region incorporated within the shallow trench isolation region, having a second limit dimension, wherein the second limit dimension is larger than the first limit dimension. A semiconductor structure according to claim 1, having the following characteristics.

3. Shallow trench isolation liner surrounding the lower opposing side walls of the shallow trench isolation region The semiconductor structure according to claim 1, further comprising:

4. The semiconductor structure according to claim 3, wherein the shallow trench isolation liner is in at least partial contact with the lower portion of the back surface isolation region.

5. An interlevel dielectric layer deposited on the field-effect transistor; and The back surface level dielectric provided below the field-effect transistor The semiconductor structure according to claim 1, further comprising:

6. A metal contact inside the interlevel dielectric layer, the metal contact electrically connects the first surface of at least one source / drain region to the back-end obline level. The semiconductor structure according to claim 5, further comprising:

7. The placeholder layer is located inside the interlevel dielectric on the back surface, and the placeholder layer is located on a second surface of the at least one source / drain region, opposite to the first surface of the at least one source / drain region. The semiconductor structure according to claim 6, further comprising:

8. The back metal contacts within the back interlevel dielectric layer electrically connect the second surface of at least another source / drain region to the back power rail, where the first surface of the at least another source / drain region is in contact with the interlevel dielectric layer. The semiconductor structure according to claim 5, further comprising:

9. Carrier wafer positioned above the aforementioned back-end obline level The semiconductor structure according to claim 6, further comprising:

10. Rear power supply network stacked on the aforementioned rear power rail The semiconductor structure according to claim 8, further comprising:

11. Each of the field-effect transistors is A gate structure positioned above and surrounding multiple channel layers, wherein the gate structure of a field-effect transistor is electrically isolated from the gate structure of an adjacent field-effect transistor by a gate-cut isolation region. The semiconductor structure according to claim 1, further comprising:

12. The semiconductor structure according to claim 11, wherein the back surface isolation region is in contact with the gate cut isolation region within the gate region of the semiconductor structure.

13. In the step of forming a front-end-of-line level including multiple field-effect transistors, each field-effect transistor includes source / drain regions deposited on both sides of the field-effect transistor; The step of forming shallow trench isolation regions between adjacent field-effect transistors in order to electrically separate the plurality of field-effect transistors from one another, wherein the shallow trench isolation regions have a tapered profile; and The step of forming a back-side isolation region that is incorporated inside the shallow trench isolation region and cuts open the source / drain region, wherein the back-side isolation region has an inverse tapered profile. A method for forming a semiconductor structure comprising the following features.

14. The step of forming a placeholder layer that is in contact with a second surface of the source / drain region and is opposite to a first surface of the source / drain region, wherein the placeholder layer is formed inside the first semiconductor layer; The step of forming a metal contact inside an interlevel dielectric layer deposited on the field-effect transistor, wherein the metal contact electrically connects the first surface of at least one source / drain region to the back-end obline level. The method according to claim 13, further comprising:

15. The step of forming a carrier wafer on the back-end obline level. The method according to claim 14, further comprising:

16. In the step of forming an etching stop sacrificial layer on the first semiconductor layer, the etching stop layer is positioned on the substrate. The method according to claim 14, further comprising:

17. The method according to claim 13, wherein each field-effect transistor includes a gate structure deposited on and surrounding a plurality of channel layers, wherein the gate structure of the field-effect transistor is electrically isolated from the gate structure of an adjacent field-effect transistor by a gate-cut isolation region.

18. The step of forming the shallow trench isolation region is as follows: The step of forming a shallow trench isolation liner that surrounds the lower opposing side walls of the shallow trench isolation region. The method according to claim 13, further comprising the above.

19. The step of forming the aforementioned back surface separation region is, A step of removing the substrate and the etching stop layer; The step of creating a recess in the first semiconductor layer to expose the shallow trench isolation liner; and In the step of forming a dielectric cap on the recessed first semiconductor layer, the upper surface of the dielectric cap is coplanar with the upper surface of the shallow trench isolation liner. The method according to claim 16, further comprising:

20. A step of performing a first etching process until it reaches the surface of the gate structure, the first etching process exposing the gate structure and a portion of the gate cut; and A second etching process is performed to cut open the source / drain region. The method according to claim 19, further comprising:

21. A step of depositing dielectric filling material in the recessed portion formed after the first etching process and the second etching process; and Step of forming the interlevel dielectric on the back surface. The method according to claim 20, further comprising:

22. The step of performing a patterning process on the aforementioned back surface level dielectric; and A step of selectively removing the placeholder layer from source / drain regions that are not electrically connected to the metal contacts. The method according to claim 21, further comprising:

23. A step of depositing a conductive material inside the patterned back-side interlevel dielectric to form a back-side metal contact; The step of forming a back-side power rail to the back-side metal contact; and The step of forming a rear power supply network on the rear power rail. The method according to claim 22, further comprising:

24. The method according to claim 13, wherein the upper portion of the back surface isolation region is incorporated into the source / drain region and has a first limit dimension, and the lower portion of the back surface isolation region is incorporated into the shallow trench isolation region and has a second limit dimension, the second limit dimension being greater than the first limit dimension.

25. The method according to claim 17, wherein the back surface isolation region is in contact with the gate cut isolation region within the gate region of the semiconductor structure.

Images