Doubling region configuration for enhancing near-infrared sensitivity in silicon CMOS single-photon avalanche diodes

Abstract

Disclosed is a near-infrared sensitive substrate-non-isolated silicon single-photon avalanche diode comprising a p-well layer (101) and a high-voltage n-well (102), wherein the p-well layer and the high-voltage n-well layer are arranged opposite each other to form a main junction (100) defining an active region (104), the p-well layer includes doping according to a doping concentration distribution, the p-well layer is configured to have a first double peak corresponding to each p-type doped region in its doping concentration distribution throughout the p-well layer in the active region, the high-voltage n-well is configured to have a second double peak corresponding to each n-type doped region configured to achieve an npnp-type device junction profile, thereby further lightly doping the p-well layer to obtain a broad depletion region, i.e., at least 1 μm in size, and the high-voltage n-well layer is further configured to extend beyond the p-well layer to form a guard ring (103) around the active region.

Description

Technical Field

[0001] The present invention relates to single photon avalanche diodes, more precisely, to address the low photon detection probability exhibited at near-infrared (NIR) wavelengths while utilizing standard silicon (Si) CMOS technology and the high excess bias requirements in a wide depletion (active) region approach.

Background Art

[0002] Applications such as light detection and ranging (LiDAR), optical tomography, and optical fiber communication require high-sensitivity light detection in the near-infrared (NIR) [1]-[3]. Therefore, further efforts are being directed towards improving the NIR efficiency in solid-state photodetectors. In this category of detectors, single photon avalanche diodes (SPADs) exhibit photon counting capabilities and low jitter in a compact and generally low-cost format. To enhance sensitivity in the NIR, wider depletion regions have been investigated to enable the collection of NIR photons deeply absorbed in silicon [4]-

[11] . There are two main issues with the wide depletion region approach. First, as the dimensions of smaller nodes decrease, the doping concentration tends to increase, making it more difficult to create SPADs with wide depletion regions while scaling down CMOS technology nodes. Second, the magnitude of the electric field is relatively smaller in wide depletion regions and linearly decays from the avalanche multiplication region towards the edge of the depletion zone. Therefore, wide depletion devices require a high excess bias voltage (about 10V) to increase the electric field magnitude and avalanche triggering probability. However, the required high excess bias voltage can complicate the design of pixel circuits when the excess bias exceeds the allowed rail-to-rail voltage range in digital circuits.

Summary of the Invention

[0003] The present invention provides a near-infrared sensitive substrate-non-isolated silicon single-photon avalanche diode comprising a p-well layer and a high-voltage n-well, configured such that the p-well layer and the high-voltage n-well layer are arranged opposite each other to form a main junction defining an active region, the p-well layer includes doping according to a doping concentration distribution, the p-well layer is configured to have a first double peak corresponding to each p-type doped region in its doping concentration distribution throughout the p-well layer in the active region, the high-voltage n-well is configured to have a second double peak corresponding to each n-type doped region configured to achieve an npnp-type device junction profile, thereby further lightly doping the p-well layer to obtain a wide depletion region, i.e., at least 1 μm in size, and the high-voltage n-well layer is further configured to extend beyond the p-well layer to form a guard ring around the active region.

[0004] In a preferred embodiment, the npnp-type device junction profile is further configured to have a well-designed doping concentration and depth such that a broad depletion region confines two separate multiplication regions, one of the n-type doped regions is sandwiched between the p-type doped regions, and the electric field between the two pn junctions never reaches zero.

[0005] The present invention will be better understood by referring to a detailed description and drawings of preferred embodiments of the present invention. [Brief explanation of the drawing]

[0006] [Figure 1] This figure shows a cross-section of an exemplary embodiment of the device according to the present invention. [Figure 2a] This figure shows the electric field profile of an exemplary embodiment of the device according to the present invention having a doubly multiplying region. [Figure 2b] This figure shows the electric field profile of a SPAD with a wide depletion region. [Figure 2c] This figure shows a graph comparing the electric fields, which indicate the magnitude of the electric field at the center of each device along the y-axis. [Figure 2d] This diagram shows a schematic cross-section of a SPAD with a wide depletion region, where the white lines on the electric field profile correspond to the boundaries of the depletion region. [Figure 3a] This figure shows the IV measurement results of SPAD at room temperature under ambient light. [Figure 3b] This figure shows the device's light emission test at excessive bias voltages of 3V and 5V. [Figure 4] This figure shows a graph of the DCR characteristic evaluation of the device according to the present invention with respect to the over-bias voltage from five different dies. [Figure 5] This figure shows an inter-arrival avalanche timing histogram with exponential fitting and afterpulsing probability at an over-bias voltage of 5.5V. [Figure 6] This figure shows a graph of the PDP measurement results of the device according to the present invention at an over-bias voltage of 1V to 5.5V. [Figure 7] This figure shows the timing jitter histogram of the device according to the present invention, obtained for an over-bias voltage of 5.5V at 850nm. [Figure 8a] This figure shows a graph illustrating the peak PDP versus DCR per unit area. [Figure 8b] This figure shows a graph comparing PDP versus over-bias voltage at 850nm for prior art FSI SPADs manufactured at the same and other CMOS technology nodes. [Figure 9] This figure shows a graph of the obtained doping profile (NPNP) at doping concentrations expressed over a certain depth. [Figure 10a] This figure shows photon absorption at longer wavelengths using a single multiplication region, and the avalanche multiplication process in a broad depletion SPAD. [Figure 10b] This figure shows photon absorption at longer wavelengths using the doubling region, and the avalanche multiplication process in a broad depletion SPAD. [Figure 11] (a) A figure showing the avalanche yield probability of electron-holes in an exemplary embodiment of a device according to the present invention using a doubling region method, and (b) A figure showing the avalanche yield probability of electron-holes in a broad depletion region SPAD of reference. [Figure 11c] This figure shows the avalanche yield probability values ​​at the center of each device along the y-axis. [Modes for carrying out the invention]

[0007] The same reference is used throughout the figure to refer to the same or similar features.

[0008] This invention proposes a SPAD device that addresses the low NIR sensitivity and high over-bias requirements in the broad depletion region approach used in the design of Si CMOS SPADs. This invention demonstrates that higher NIR sensitivity at lower over-bias voltages than in prior art devices (see the "Background Art" section and Figure 8) can be achieved through total avalanche breakdown or triggering probability enhancement in the depletion region. To enable the increase of avalanche triggering probability, extensive numerical simulations were performed on Technology Computer Aided Design (TCAD) enabling the design of a dual-peak electric field profile configured in the same depletion region, where each peak corresponds to a separate multiplication region, and the region obtained by this method is therefore referred to as a dual-multiplication region configuration. A dual-multiplication region comprises two separate multiplication regions. Thanks to these two separate multiplication regions, both photogenerated electrons and holes inside the depletion region can undergo avalanche multiplication. Furthermore, photogenerated carriers created in the neutral substrate but diffusing into the depletion region have more opportunities to trigger an avalanche due to the two separate multiplication regions. The acquired dual multiplication region configuration is in contrast to broad depletion and NIR-enhanced SPADs of prior art designs where the device has only one multiplication region and the electric field magnitude remains low in the remaining depletion region. Due to this electric field engineering and substrate-non-isolated device design, the NIR PDP increases at lower over-bias voltages without sacrificing sensitivity in the visible spectrum. The maximum achievable NIR PDP is also enhanced if the pixel circuitry allows for increases at over-bias voltages. The device was fabricated at the 110nm CIS technology node and has an active region with a diameter of 10μm.

[0009] Device design and TCAD simulation Referring to Figure 1, a cross-section of an exemplary embodiment of a device according to the present invention is shown, where the semiconductor used may be silicon. To create two multiplication regions confined within the same depletion region that enhance the avalanche triggering probability of carriers, a main junction 100 of a technology-specific p-well layer 101 / high-voltage n-well 102 is utilized corresponding to an active region 104, where the p-well layer 101 has a doping concentration distribution (not shown in Figure 1) and a first dual peak in the doping concentration distribution throughout the p-well layer 101 (the first dual peak 900 is shown in Figure 9). Thanks to these first dual peaks 900 in the p-well layer 101 (as shown in Figure 9 with a second dual peak 901 in the high-voltage n-well and the first dual peak 900 in the p-well), an npnp-type doping profile is achieved, which should form two distinct depletion and multiplication regions. However, because the n-type doped region sandwiched between the p-type doped regions (this region corresponds to the second peak in the high-voltage n-well layer as shown in Figure 9) is sufficiently short, these two depletion regions are merged. Furthermore, the high-voltage n-well layer 102 is extended to form a guard ring 103 around the main junction 100, preventing the device from suffering premature edge breakdown. The high voltage to the device is applied between the anode electrode and the N+ cathode electrode 107 of the P+ 106 / high-voltage p-well 105.

[0010] Doubling centers in a single large depletion region The electric field inside the SPAD is engineered through the doping profile shown in FIG. 9. In this configuration, the total doping concentration varies like n-p-n-p, which should form two p-n junctions and depletion regions in fact. The first intersection between the n layer and the p layer should correspond to the first junction, and the third intersection should create the second junction. However, when the n-type doping exceeds the p-type doping, the electric field is expected to decay. If the second junction is located before the electric field reaches zero, then two depletion regions with separate multiplication regions should merge to form only one depletion region. This can be achieved if the n-type doping and the depth in the middle are appropriate so that the electric field does not become zero before the second junction. Thus, it is possible that the second multiplication region in the same depletion zone can be achieved through this second peak in the doping layer 101. Having the second peak in the layer 101 that exceeds the n-type doping thus requires achieving the second multiplication region. Therefore, a double peak is expected in the resulting electric field profile of the device, and each peak in the double peak basically corresponds to a separate avalanche multiplication region, and this method is named the double multiplication region. This is in contrast to the design of any wide depletion region SPAD with a single multiplication region. By inserting the second multiplication region into the same depletion region, the avalanche triggering probability, and thus the NIR sensitivity, is significantly enhanced even at a lower excess bias voltage.

[0011] As already described above, the material for creating the device is silicon, and the technology is a 110 nm CMOS image sensor (CIS). The high voltage may be, for example, about 3.3V.

[0012] Values of various exemplary sizes for the device include 10 μm for the diameter of the active junction in FIG. 1 and 16 μm for the left P+ region 106 to the right P+ region 106 (when reading FIG. 1, left and right correspond to the left hand direction and the right hand direction).

[0013] The width of the depletion region may be, for example, 1 μm.

[0014] Electric field and avalanche yield probability The electric field simulation of the device from Figure 1 is shown in Figure 2. The simulation was performed on the TCAD numerical tool. Doping profiles of the layers used in the cross-section of Figure 1 (not shown in Figure 1 or Figure 2) were imported into the simulation environment. An example of a doping profile is shown in Figure 9, encompassing a graph of doping concentration as a function of depth, with curves labeled “double-peak p-well” and “high-voltage n-well”. The coupled Poisson equation and the photon-hole drift-diffusion equation were then solved to calculate the magnitude of the electric field under various voltages. As shown in Figure 2(a), in addition to the first electric field peak indicated by the first tone 200, a second peak appears in the field profile of the proposed device at an overbias of 1V, indicated by the second tone 201. Variations in the electric field at overbias voltages from 1V to 5V are also given, where the second peak becomes more apparent along with its clear first tone 200. Furthermore, Figure 2(b) provides the magnitude of the electric field at the center of the device in Figure 1 along the y-axis for over-biases from 1V to 5V. This shows that the electric field profile actually has two peaks 202 and 203 (see Figure 2(c)) whose boundary is confined within a single depletion region indicated by arrow 204 in Figure 2(b). Each peak 202 and 203 is the critical avalanche breakdown electric field in silicon, 3 × 10⁻⁶. 5Above V / cm and corresponding to different multiplication regions. Therefore, the second peak 203 behaves as a second multiplication center for carriers, which is a new concept for SPAD design and can be utilized in any CMOS technology. Thus, the electric field simulation proves that the two multiplication regions are inserted within two wide depletion regions. The second multiplication region does not currently exist in other designed SPADs, and an example is simulated with its electric field profile 205 shown in FIGS. 2(b) and 2(c), which shows that only one peak corresponding to only one multiplication region exists in these devices. The cross-section of this exemplary SPAD is provided in FIG. 2(d) adapted from reference [6] and has a depletion region width similar to the proposed device designed using the double multiplication region method. The depletion widths of both devices are indicated by arrow 204 in FIGS. 2(a) and 2(b).

[0015] One advantage of the electric field profile of this new SPAD with two separated multiplication regions in a wide depletion region is that the total avalanche triggering probability of photo-generated carriers is increased, thus enhancing the NIR sensitivity of the device and reaching a high NIR PDP at a relatively lower excess bias voltage. This advantage is conceptualized in FIG. 10. FIG. 10(a) represents a SPAD 1000 with a wide depletion region having one multiplication region 1001. As shown in this scheme, when a hole pair 1002 is generated in the middle of the depletion region 1003 upon absorption of a photon 1004, only the photo-generated electron (e - ) 1002 can trigger an avalanche, while the hole (h + ) proceeds to the substrate. Furthermore, the photo-generated electron 1005 created in the neutral substrate of the depletion region 1003 and diffusing into the depletion has only one chance to trigger an avalanche due to one multiplication region 1001. On the other hand, FIG. 10(b) shows a device designed using the double multiplication region method. This is due to the insertion of the second multiplication region 1007, so that the photo-generated hole (h +)1006 can also trigger an avalanche. Furthermore, photogenerated electrons diffusing from the substrate can have up to two more opportunities to trigger an avalanche. Thus, it is guaranteed that the total avalanche yield probability and the NIR PDP of the SPAD can be boosted using the doubling region method. This concept is also valid for carriers generated thermally or via tunneling, which would be undesirable as it would increase the noise of the SPAD.

[0016] To prove the claim of enhanced avalanche yield probability expected using the double-multiplier region method, the yield probabilities of the proposed device with two multiplier regions and the same exemplary broad-depletion-region device with one multiplier region are simulated and given in Figures 11(a) and 11(b), respectively. The total avalanche triggering probability obtained for the broad-depletion-region SPAD example is 33% in the middle of the device, while it reaches 77% in the proposed SPAD thanks to the presence of the second multiplier region, as can be observed from Figure 11(c). Furthermore, if absorption outside the depletion region, which is likely to occur at NIR wavelengths, is considered, photogenerated electrons diffusing into the depletion region have a 1.2 times greater chance of triggering an avalanche, as can be calculated from the edge of the depletion region. Thus, operating the double-multiplier region device at lower over-bias voltages is possible to achieve NIR PDP similar to or higher than that in conventional broad-depletion-region SPADs with only one multiplier region.

[0017] Characteristic evaluation results IV measurement and luminescence test Figure 3(a) shows the IV characteristics of the device from Figure 1 at room temperature under ambient light. The breakdown voltage, indicated by a sharp increase in current, occurs at 29.8V. To ensure that the device does not suffer premature edge breakdown, luminescence tests were performed at over-bias voltages of 3V and 5V. Figure 3(b) shows that in the proposed device, the edge breakdown effect is absent thanks to the guard ring structure implemented in the design. These results demonstrate that the device functions properly in Geiger mode.

[0018] DCR measurement DCR measurements were obtained using an externally connected 660 kΩ resistor to quench and recharge the SPAD. The same SPAD was measured from different dies to collect statistics on noise. Figure 4 shows the DCR measurement results for five devices with respect to over-bias voltage. According to this graph, device 3 was selected as the reference because it corresponds to the median in the noise measurement results. The DCR of this device changes from 8 cps at an over-bias of 1 V to 295 cps at an over-bias of 5.5 V at room temperature. Therefore, the DCR per unit area at an over-bias of 5.5 V is 3.7 cps / μm 2 The results of the characterization of device 3 are presented below.

[0019] Afterpulsing possibility measurement The afterpulsing histogram of the device was acquired using the inter-avalanche time method. A high-speed digital oscilloscope (Tele-dyne LeCroy WavePro 760Zi-A) was used to measure the time interval between pulses. The afterpulsing histogram acquired under dim light is shown in Figure 5. Histogram 500 corresponds to the measured inter-arrival time histogram of pulses, and curve 501 is the fitting curve. Since the SPAD was passively quenched and recharged through an external resistor, the dead time of the SPAD was approximately 7 μs. The afterpulsing probability of the device was 5.4% under an overbias of 5.5V, which is calculated as the ratio of the range between the measured curve and the fitted curve to the range below the fitted curve. Thus, this low afterpulsing probability indicates that defect concentration in the manufactured device is expected to be similarly low.

[0020] Photon detection probability measurement The device's PDP was measured via a monochromator setup in which a xenon lamp emitted broadband light and a monochromator selected each wavelength through a diffraction grating. An integrating sphere was then used to provide spatially uniform light on the SPAD, and a calibrated reference detector was used to accurately assess the colliding photon count. Under this configuration, the device's measured PDP was acquired at over-bias voltages from 1V to 5.5V, as shown in Figure 6. Peak PDP actually occurs at two different wavelengths, 450nm and 500nm, as is more evident at 5.5V. This is thought to be related to the nature of the two peaks in the device's electric field profile, which form two multiplication regions most favorable for detection at these wavelengths. At an over-bias voltage of 4V and a wavelength of 500nm, the device has a PDP of 50%, and at an over-bias voltage of 5.5V, the PDP at 500nm reaches 78%. Furthermore, the device's NIR sensitivity is also enhanced thanks to a second multiplication region inserted within a broad depletion region, keeping the substrate non-isolated from the junction. At 850nm, the SPAD exhibits 13% and 25.5% PDP, respectively, only at over-bias voltages of 4V and 5.5V.

[0021] Jitter measurement Time-correlated single-photon counting (TCSPC) technique was employed to measure timing jitter. The device was illuminated with an 850 nm pulsed laser (ALS GmbH) operating at 100 kHz, and the incident power was reduced to a single-photon regime using an absorption-type attenuation filter. The same high-speed digital oscilloscope was used to detect the time difference between the laser clock signal and the positive edge of each avalanche pulse. The jitter histogram obtained at 850 nm with an overbias of 5.5 V is provided in Figure 7. Jitter was calculated as full width at half maximum (FWHM), which is 240 ps at an overbias voltage of 5.5 V. Two peaks were observed in the timing jitter because many of the diffused carriers from the substrate reached the depletion region due to the non-insulating structure of the substrate. The smaller peak represents the contribution of carriers generated in the depletion region, and the other peak represents the contribution of diffused carriers.

[0022] Comparison with prior art In Figure 8, the best-performing front-side-illuminated (FSI) CMOS SPAD with broad depletion and enhanced sensitivity in NIR is selected and compared to Device 3 described herein. Figure 8(a) shows the peak PDP achieved using these SPADs for normalized DCR with an active region. As can be seen, Device 3 achieves the highest PDP reported to date among these FSI broad depletion region SPADs. The noise of Device 3 with respect to DCR per unit area is also consistent with most of the prior art SPADs. Figure 8(b) shows a comparison of PDPs at a wavelength of 850 nm with respect to over-bias voltage. This shows that Device 3 effectively eliminates the high over-bias required in broad depletion devices due to the insertion of a second multiplication region within the same broad depletion region in this function which increases the total avalanche triggering probability. Figure 8(b) also shows that Device 3 achieves one of the highest PDPs in NIR.

[0023] conclusion A novel technique, referred to as the double multiplication region, has been proposed to achieve high NIR PDP in SPADs with a wide depletion region at relatively lower over-bias voltages. In contrast to conventional wide depletion devices that have only one multiplication region, this technique aims to insert a second multiplication region. As shown in the avalanche yield probability simulations in TCAD in Figures 11(a) to 11(c), the second multiplication region significantly increases the triggering probability. The reason for this increase is also explained in Figures 10(a) to 10(b). To achieve the second multiplication region, a double-peak p-well was used in conjunction with a high-voltage n-well layer. Here, the two peaks produce two pn junctions and, consequently, two multiplication regions. Between these two peaks, as shown in Figure 9, n-type doping exceeds p-type doping, causing electric field attenuation and separating the two distinct multiplication regions. Characterization results for this device show that high NIR PDP was indeed achieved at an over-bias voltage of 5.5V, reaching 25.5% at 850nm while maintaining noise at an acceptable level of 295cps. The high NIR PDP was achieved thanks to the SPAD structure, which has a wide depletion region on the substrate and a higher yield probability for carriers. Reducing the need for high over-bias voltages was addressed by the enhanced avalanche triggering probability at a given over-bias. However, the SPAD jitter degraded to 236ps due to diffused carriers detected from the substrate.

[0024] Reference material [1] K. Morimoto, A. Ardelean, M.-L. Wu, ACUlku, IMAntolovic, C. Bruschini, and E. Charbon, eds., “Megapixel time-gated spad image sensor for 2d and 3d imaging applications,” Optica, vol.7, no.4, pages 346–354, 2020. [2] Edited by J.M.Pavia, M.Scandini, S.Lindner, M.Wolf, and E.Charbon, "A1×400 backside-illuminated spad sensor with 49.7ps resolution, 30pj / sample tdcs fabricated in 3d cmos technology for near-infrared optical tomography", IEEE Journal of Solid-State Circuits, vol.50, no.10, pp. 2406 - 2418, 2015. [3] Edited by M.T.Rakher, L.Ma, O.Slattery, X.Tang, and K.Srini - vasan, "Quantum transduction of telecommunications-band single photons from a quantum dot by frequency upconversion", Nature Photonics, vol.4, no.11, pp. 786 - 791, 2010. [4] Edited by M.Moreno - Garcia, H.Xu, L.Gasparini, and M.Peren - zoni, "Low - noise single photon avalanche diodes in a 110nm cis technology", in 2018 48th European Solid - State Device Research Conference (ESSDERC). IEEE, 2018, pp. 94 - 97. [5] Edited by I.Vornicu, J.M.Lopez - Martinez, F.N.Bandi, R.C.Galan, and A.Rodriguez - Vazquez, "Design of high - efficiency spads for lidar applications in 110nm cis technology", IEEE Sensors Journal, vol.21, no.4, pp. 4776 - 4785, 2020. [6] Edited by E.A. Webster, L.A. Grant, and R.K. Henderson, "A high-performance single-photon avalanche diode in 130-nm cmos imaging technology", IEEE Electron Device Letters, vol. 33, no. 11, pp. 1589 - 1591, 2012. [7] Edited by M. Sanzaro, P. Gattari, F. Villa, A. Tosi, G. Croce, and F. Zappa, "Single-photon avalanche diodes in a 0.16μm bcd technology with sharp timing response and red-enhanced sensitivity", IEEE Journal of Selected Topics in Quantum Electronics, vol. 24, no. 2, pp. 1 - 9, 2017. [8] Edited by F. Gramuglia, P. Keshavarzian, E. Kizilkan, C. Bruschini, S.S. Tan, M. Tng, E. Quek, M.-J. Lee, and E. Charbon, "Engineering breakdown probability profile for pdp and dcr optimization in a spad fabricated in a standard 55nm bcd process", IEEE Journal of Selected Topics in Quantum Electronics, vol. 28, no. 2:Optical Detectors, pp. 1 - 10, 2021. [9] Edited by M. Ghioni, A. Gulinatti, I. Rech, F. Zappa, and S. Cova, "Progress in silicon single-photon avalanche diodes", IEEE Journal of selected topics in quantum electronics, vol. 13, no. 4, pp. 852 - 862, 2007.

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Claims

1. p-well layer (101), High voltage n-well (102) Equipped with, The p-well layer (101) and the high-voltage n-well layer (102) are arranged facing each other to form a main junction (100) that defines an active region (104). The p-well layer (101) contains doping according to the doping concentration distribution, The p-well layer (101) is configured to have a first dual peak (900) corresponding to each p-type doped region in its doping concentration distribution throughout the p-well layer in the active region (104), and the high-voltage n-well (102) is configured to have a second dual peak (901) corresponding to each n-type doped region configured to achieve an n-p-n-p type device junction profile. This further dops the p-well layer lightly, resulting in a configuration that obtains a wide depletion region, i.e., one with an area of ​​at least 1 μm. The high-voltage n-well layer (102) is further configured to extend beyond the p-well layer (101) to form a guard ring (103) around the active region (104). A non-isolated silicon single-photon avalanche diode with enhanced near-infrared sensitivity.

2. The aforementioned n-p-n-p type device bonding profile is The aforementioned large depletion region confines two separate multiplication regions, The near-infrared sensitive substrate-non-isolated silicon single-photon avalanche diode according to claim 1, further configured such that one of the n-type doped regions is sandwiched between the p-type doped regions and has a well-designed doping concentration and depth such that the electric field between the two p-n junctions never reaches zero.

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