Apparatus and method for dissipating heat near diamond through an engineered intermediate layer

Abstract

[Solution] In a particular example, the method and semiconductor structure are directed to a device such as a semiconductor device, comprising a substrate material that tends to accumulate or generate heat due to nearby electrical conductivity, a diamond material for diffusing and transferring heat from the substrate material, and an intermediate layer material disposed between the substrate material and the diamond material. The intermediate layer material has a thermal boundary resistance (TBR) and is characterized by having a cross-sectional thinness index of the intermediate layer material, the upper limit of which is designed by material deposition technique to mitigate phonon transport losses in order to achieve a target or corresponding TBR associated with the intermediate layer material.

Description

[Technical Field]

[0001] Aspects of this disclosure relate to the field of use and manufacture of devices for heat dissipation via diamond, and can be exemplified by the use of diamond grown around high-speed switching and high-power signal amplification semiconductor devices. [Background technology]

[0002] To facilitate the discussion, using one such technical type, it is recognized that the presence of highly localized electric fields within a transistor creates high-temperature spots, which reduce carrier mobility, resulting in decreased current and degraded performance. Further increasing the operating voltage for high-power applications causes temperature spikes, leading to premature failure of the device. Precisely designed and implemented device-level thermal management strategies can reduce channel / junction temperatures in high-power, high-frequency transistors such as GaN RF HEMTs, InP HBTs, and Ga2O3 power transistors, improving the lifespan and operating characteristics of such transistors. [Overview of the Initiative] [Problems that the invention aims to solve]

[0003] Diamond is an excellent thermal material with a high thermal conductivity (TC) of 500-2200 W / m / K, and can be integrated as close as 1 nm to the channel / junction of the device. Furthermore, the thermal boundary resistance (TBR) between the diamond and the (transistor) channel can be reduced to ~3 m 2 This has been used to reduce the K / GW ratio. In RF equipment in particular, while the majority of heat transport is carried out by ballistic transport, it is becoming increasingly difficult to dissipate heat from channels / junctions. Therefore, heat spreaders such as diamonds are integrated as close as possible to the source while providing high in-plane and out-of-plane TC without compromising equipment performance.

[0004] In addition to RF transistors and power transistors, there is also an increasing demand for device-level thermal management in Si technology. In order to operate high-power integrated circuits (ICs), including 3D integrated circuits for faster and higher-power computing, reliably without overheating, depending on specific applications and / or design implementations, it may be important to incorporate a heat spreader in the back-end-of-line (BEoL) process. Although recently developed heat sink technologies, such as porous copper, can provide a heat removal capacity of 10 6 W / m 2 / K, heat transport from hot spots through BEoL wiring in a 3D material stack is still a very significant issue in the current selection of inter-layer dielectric (ILD) materials. As 3D ICs stack more layers and heat sinks are improved, these thermally resistive materials will ultimately have a greater impact on the junction temperature than the heat sink. Here too, polycrystalline diamond, which has a relatively high TC, can replace some of the existing ultra-low-κ ILD (which has a very low TC of 0.2 W / m / K) to conduct heat laterally to thermal vias or can be added to the power supply network in a flip-chip structure to reduce the overall thermal resistance to the heat sink.

[0005] Therefore, the exemplary aspects of the present disclosure are directed to these and other issues related to heat removal inside and around heat generating devices, including but not limited to those described above.

Means for Solving the Problems

[0006] The various examples / embodiments presented by this disclosure are directed to problems such as those described above and other problems that may become apparent from the following disclosure. For example, some of these disclosed aspects are directed to methods and apparatuses for using diamond in the vicinity of hot spots in high-power / high-speed switching transistor technology. Other aspects are directed to overcoming the conventionally used technologies as described above by a carefully designed intermediate layer material characterized by having a thermal boundary resistance (TBR) and a cross-sectional dimension between a diamond material for heat diffusion and a substrate material that exhibits a high temperature such as a channel / junction.

[0007] In one specific example, the method and semiconductor structure are directed to an apparatus such as a semiconductor device that includes a substrate material that is prone to heat accumulation or generation due to nearby electrical conductivity, a diamond material that diffuses and transfers heat from the substrate material, and an intermediate layer material disposed between the substrate material and the diamond material. The intermediate layer material has a TBR and is characterized by having a cross-sectional thickness index of the intermediate layer material whose upper limit is designed by a material deposition technique to mitigate phonon transport loss in order to achieve a targeted or corresponding TBR associated with the intermediate layer material.

[0008] In some other examples, which may also be based on the aspects described above, the method and semiconductor structure are directed such that the interlayer material is characterized by at least one smooth transition in the material phase to suit one or more phonon-related parameters (phonon group velocity, phonon frequency, and phonon mode) on opposite sides of the interlayer material, and / or the substrate material includes a carbon diffusion region along the side of the substrate material facing the diamond material, and the carbon diffusion region has a cross-section characterized by a thickness parameter in the range of about 1 nm to about 10 nm. In some other examples, which may further be based on the aspects described above, the method and semiconductor structure are directed such that the interlayer material is characterized as a dielectric containing SiC or AlC, and / or the interlayer material is formed by material deposition techniques and includes a crystalline or amorphous dielectric portion.

[0009] The above description is not intended to describe any aspect of this disclosure, any individual embodiment, or any embodiment. The following drawings and detailed description are also illustrative of various embodiments. [Brief explanation of the drawing]

[0010] Various exemplary embodiments, including experimental examples, can be better understood by considering the following detailed description in accordance with this disclosure in conjunction with the accompanying drawings. [Figure 1] This is a cross-sectional view of a diamond on a substrate, comprising an intermediate layer (e.g., including a transition layer) of a suitable dielectric material, in accordance with certain exemplary aspects of the present disclosure. [Figure 2A-2B] A set of cross-sectional views of an exemplary switching device's thermal generation profile, illustrating how the thermal penetration depth changes with respect to the frequency of the device's operation, in accordance with certain exemplary aspects of the present disclosure, where the cross-sectional view in Figure 2A shows heating in the low-frequency range and the cross-sectional view in Figure 2B shows heating in the high-frequency range. [Figure 3A-1.3A-2.3B-1.3B-2.3B-3] A set of cross-sectional views in accordance with certain exemplary aspects of the present disclosure. [Figure 4] This is a process flow diagram for controllingly fabricating and characterizing nanometer-thick thin films according to certain exemplary aspects of the present disclosure. [Figures 5A-5C] This is a set of TEM images showing the realization of a designed intermediate layer in accordance with certain exemplary aspects of the present disclosure. [Figure 6] This is a TEM image of an exemplary experimental setup, highlighting the C / Si interface after ion beam exposure, in accordance with certain exemplary aspects of this disclosure. [Figures 7A-7B] A set of figures characterizing the thermal behavior of an exemplary experimental apparatus with a specific experimental interlayer, in accordance with certain exemplary aspects of the present disclosure, where Figure 7A shows a graph of different thermal boundary resistances against diamond thickness, and Figure 7B shows the EELS characterization of the interlayer. [Figures 8A-8C] This is a set of images showing EELS analysis with cross-sectional views of different experimental specimens, each shown in the figure, in accordance with certain exemplary aspects of this disclosure. [Figure 9] This is a graph showing the thermal boundary resistance against the intermediate layer thickness associated with different experimental samples, in accordance with certain exemplary aspects of this disclosure. [Figure 10] This graph shows electrothermal simulations of GaN HEMTs for three cases, following specific exemplary aspects of this disclosure. [Figure 11] This is an example of a layered system in accordance with certain exemplary aspects of the present disclosure. [Figure 12] The graphs, following certain exemplary aspects of this disclosure, show simulation results for steep interfaces between diamond / Si, SiC / Si, and diamond / SiC (shown with an intermediate layer thickness of 0 nm for illustrative purposes). [Figures 13A-13B] Figures 13A and 13B show a Si integrated circuit ("IC") and a GaN power amplifier IC, respectively, according to certain exemplary aspects of the present disclosure. [Figures 14A-14B] These are TEM images of diamonds grown on substrates that have undergone different treatments, in accordance with certain exemplary aspects of the present disclosure. [Figure 15] This is a graph of TBR against intermediate thickness, according to certain exemplary aspects of the present disclosure. [Modes for carrying out the invention]

[0011] The various embodiments described herein are subject to modification and alternative forms, the aspects of which are shown in the drawings as examples and described in detail below. However, it should be understood that this disclosure is not intended to limit to the specific embodiments described. Rather, the intent of this disclosure is to encompass all modifications, equivalents, and alternative forms that fall within the scope of this disclosure, including the aspects defined in the claims. Furthermore, the term “example” used throughout this application is for illustrative purposes only and is not intended to limit.

[0012] Aspects of this disclosure are considered applicable to a wide variety of different types of devices, systems, and methods, including devices characterized at least in part by a diamond material for diffusing and transferring heat from heat or hot spots in a substrate material through a designed thin interlayer material placed between the substrate material and the diamond material. While this disclosure is not necessarily limited to such aspects, understanding the specific examples in the following description can be gained from descriptions in such specific contexts.

[0013] Accordingly, the following description includes various specific details to illustrate the specific examples presented herein. However, it should be apparent to those skilled in the art that one or more other examples and / or variations thereof can be implemented without all of the specific details shown below. In other cases, well-known features are not described in detail so as not to obscure the description of the examples herein. For the sake of illustration, the same meaning and / or the same reference numeral may be used in different drawings to refer to the same element or an additional example of the same element. Also, while aspects and features may be described in individual drawings in some cases, it will be understood that features of one drawing or embodiment can be combined with features of another drawing or embodiment, even if the combination is not explicitly shown or described as such.

[0014] Illustrative aspects of the disclosure relate to devices such as semiconductor devices or other heat generation / collection structures, and to heat dissipation by using a carefully designed intermediate layer or interface layer between the structure or substrate material and the diamond material. The intermediate layer material is characterized by having a thermal boundary resistance (TBR) and a cross-sectional thinness index of the intermediate layer material, whose upper limit is designed by material deposition techniques to mitigate phonon transport losses in order to achieve a target or corresponding TBR associated with the intermediate layer material.

[0015] In accordance with the aspects described above, any apparatus or method of such manufacture may include aspects presented and claimed in U.S. Provisional Application No. 63 / 471,822 (STFD.455P1 S23-225), which includes Appendices A-E of the application filed 8 June 2023, to which priority is claimed. To the extent permitted, such subject matter is incorporated herein by reference in whole, and further incorporated to the extent that additional aspects and examples (e.g., experimental examples and more detailed embodiments) which may be useful for supplementation and / or clarification.

[0016] In accordance with the specific aspects and applications of the exemplary embodiments of this disclosure, Figure 1 is a cross-sectional view of an apparatus having a dielectric interlayer between a diamond and a substrate. In this example, the substrate is indicated as “X substrate” and may include, but is not limited to, any of a variety of different exemplary types of semiconductor materials. For example, in Figure 1, the X substrate may include, or be based on, any one or a combination thereof of Si, SiC, GaAs, GaN, InP, and β-Ga2O3. The dielectric interlayer in Figure 1 may optionally have a carbon-diffused transition layer (e.g., SiC or Al4C3) shown along the top surface of the dielectric interlayer and immediately adjacent to the diamond.

[0017] The use of such dielectric interlayers has been experimentally demonstrated to be particularly important as a thermal management strategy for reducing channel / junction temperatures in high-power and high-frequency transistors such as GaN RF HEMTs, InP HBTs, and Ga2O3 power transistors. Proper thermal management in this manner has been shown to extend transistor life and shift the point of failure to higher power and frequency sides. Furthermore, in connection with experimental efforts leading to this disclosure, the use of such dielectric interlayers has been experimentally demonstrated to be particularly important for maintaining high current levels by increasing the heat transfer coefficient from the channel to the heat spreader material. In such experimental efforts, diamond is used as the thermal material (e.g., having a high TC of 500-2200 W / m / K) and is integrated as close as 1 nm to the channel / junction, and the thermal boundary resistance (TBR) between the diamond and the channel is ~3 m 2 It has been reduced to less than k / gW.

[0018] Figures 2A and 2B are useful for understanding how frequency affects thermal penetration depth, which changes based on the frequency of the operating device. Figure 2A shows low-frequency heating with a hot spot in the center extending to the dotted line, and the region outside the dotted line shows thermal diffusion via passivation. In contrast, Figure 2B shows high-frequency heating, where the central portion is reduced to show a hot spot, which spreads outward and covers the region demarcated by a dotted line with a smaller perimeter (and again the region outside the dotted line shows thermal diffusion via passivation). In high-power and / or high-frequency transistors as shown in Figure 2B, heat generation at the channel / junction at higher frequencies is due to diffuse phonon transport. Through TIFF2026521474000002.tif2143), the thermal penetration depth is significantly reduced, resulting in more localized hot spots. Therefore, the exemplary thermal management strategy shown in Figure 1 is particularly advantageous in RF equipment that often uses high-power and / or high-frequency transistors, given the difficulty in dissipating heat from channels / junctions. In some more specific examples relating to this disclosure, it is therefore preferable that the heat spreader (diamond material) be integrated as close as possible to the hot spot without impairing equipment performance, while providing high in-plane and out-of-plane TC.

[0019] Whether it is an RF device, a power transistor, or another type of heat-generating structure such as Si technology, the device-level thermal management according to this disclosure is advantageous in reducing the thermal boundary resistance between the diamond and the hot spots of the underlying material (e.g., the channel / junction of the device). As illustrated above, by using a carefully designed interlayer, a suitable buffer is provided as an interface, i.e., an interface layer, to mitigate or minimize the differences in phonon frequency and group velocity between the two materials, thereby reducing TBR. According to the examples of this disclosure, the interface is designed to provide low-loss diffusive or ballistic phonon transport at the interface, depending on the heating frequency.

[0020] In several experiments toward this objective, it was unexpectedly discovered that epitaxially steep and nearly / substantially perfect interfaces can be realized between diamond and one or more other semiconductors (e.g., Si, GaN, InP, and β-Ga2O3), despite the extreme difficulty in obtaining such results due to lattice mismatch between the two materials. Transmission electron microscopy (TEM), electron energy loss spectroscopy (EELS), and Raman spectroscopy were used to confirm the interface analysis. Designing the interface via the intermediate layer material exemplified in the examples disclosed above is a crucial step in the efficient thermal management relating to this disclosure. More specifically, and according to the specific examples of this disclosure, interface design with temperature control is carried out to minimize, or at least substantially reduce, phonon transport losses at the interface in order to obtain a lower or target TBR. This intermediate layer material is designed using material deposition for specific lower levels (e.g., minimum or target) of TBR and for an appropriate degree of treatment (e.g., smoothing or etching) of the upper portion / surface of the deposited material, along with its chemical properties and thickness. In this way, the intermediate layer material is designed for a specific TBR and thickness of the intermediate layer material, spanning between the substrate material and the diamond material. As a result of this design, the thickness of the intermediate layer material is set within a range (including, but not limited to, 1 nm to 20 nm, 20 nm to 50 nm, etc.), the upper limit of which is controlled by a design process related to the material deposition technique for setting the thickness dimension, thereby mitigating the degree (or all of it) of phonon transport loss in order to achieve the target or corresponding TBR associated with the intermediate layer material. For example, considering Si technology, the large difference in phonon group velocities between Si (5000 to 8100 m / s) and diamond (14400 to 18700 m / s) increases phonon transport loss by reflecting most of the phonons. By using such an efficient thermal management strategy as illustrated herein, as in the example of this disclosure, this increased phonon transport loss, which is associated with lattice mismatch between the two materials, is overcome.

[0021] As shown in Figures 3A-1 and 3A-2, and Figures 3B-1, 3B-2, and 3B-3, interface design can be carried out during manufacturing by adding a buffer layer, such as SiC, with a phonon group velocity greater than that of Si (7200-12000 m / s), to the interface (upper surface of the intermediate layer) to form a smoother transition between phonon properties. In one exemplary experiment relating to this disclosure, carbon is diffused into the Si substrate during diamond growth to form an intermediate layer (or buffer), creating a thin layer of SiC (e.g., one to several atomic layers), which improves the C-Si bond strength and provides a smooth transition in the material phase to match one or more phonon-related parameters (phonon group velocity, phonon frequency, and phonon mode) on both sides (Figures 3A-1 and 3A-2). In GaN material systems, a thin SiN layer is combined with the SiC interface layer. x The layer functions as a phonon buffer layer between diamond and GaN (Figures 3B-1, 3B-2, and 3B-3). By using a suitable intermediate layer as a phonon transport buffer layer, diamond has been shown to be growable on a wide variety of semiconductor materials, including but not limited to Si, SiC, GaAs, GaN, InP, and β-Ga2O3. This intermediate layer also acts as a stress relaxation layer due to lattice and thermal expansion coefficient (CTE) mismatch, enhancing adhesion. More specifically, Figures 3A-1 and 3A-2 show cross-sectional views including exemplary diamond / Si interfaces where carbon interdiffuses to form SiC on one side (e.g., the top side) of a Si and SiO2 / Si substrate, respectively, while Figures 3B-1, 3B-2, and 3B-3 show SiN for low-loss phonon transport, respectively. x This shows a diamond / GaN interface formed by the interdiffusion of carbon atoms: SiC on GaN and Al4C3 on AlN / GaN.

[0022] In relation to the specific experimental examples relating to this disclosure, different processes and / or techniques (so-called “intermediate layer design aspects”) may be used individually or in combination to design the exemplary intermediate layer as described above. Figures 4, 5, and 6 are used to illustrate four examples of design aspects for fabricating such exemplary intermediate layers, which are as follows: (i) Amorphous and crystalline dielectric deposition, (ii) Nanocrystallization and amorphous formation of interfaces using high-energy ion beams, (iii) Crystallization of the interface using high-temperature vacuum annealing, (iv) Carbon diffusion during diamond growth. Another design aspect, which can be combined with one or more of the above aspects, is the crystallization of the intermediate material during the growth of the diamond material.

[0023] The first exemplary design aspect is referred to as amorphous and crystalline dielectric deposition. In this aspect, a combination of deposition techniques such as ALD, MOCVD, PECVD, LPCVD, and / or sputtering is used to deposit SiO2, SiN on semiconductors (as substrates) including Si, GaN, InP, and β-Ga2O3. x Dielectrics containing SiC, Al2C3, and AlN are deposited. Dielectric layers with thicknesses ranging from 1 nm to 20 nm (or greater than 20 nm) are formed by the aspects or processes described below in relation to Figure 4. The temperature used for depositing the intermediate layer can vary from ambient temperature (or room temperature) to 900°C. The thickness of the dielectric can be measured using ellipsometry after deposition. The final thickness of the intermediate layer can be measured using TEM after diamond growth, as shown in Figure 5.

[0024] Figure 4 is a process flow diagram for controllingly fabricating and characterizing nanometer-thick thin films to provide an intermediate layer material, according to certain exemplary aspects of this disclosure. The four blocks (and corresponding steps) shown in Figure 4, from left to right, include the deposition of an intermediate layer (e.g., PECVD, LPCVD, MOCVD, and / or ALD) and subsequent etching (e.g., dry etching) as necessary to establish or set the desired intermediate layer thickness. These deposition and etching steps may be repeated as appropriate, and predetermined thickness measurements may be performed as necessary (e.g., thickness measurement by ellipsometry using the Cauchy model on a transparent film) to confirm the desired TBR and / or thickness. The next step shown in Figure 4 includes the growth of polycrystalline diamond, optionally followed by TEM characterization to confirm that the diamond is properly formed on the intermediate layer. As shown on the far left of Figure 4, in the PECVD and LPCVD methods, the film is carefully etched and measured to achieve nanometer-scale control, while in the MOCVD and ALD methods, the film can be deposited with nanometer-scale control.

[0025] Figures 5A, 5B, and 5C are a set of TEM images showing the realization of a designed intermediate layer, displaying the cross-section of each sample to illustrate different amorphous intermediate layer thicknesses achievable according to certain exemplary aspects of this disclosure. Figure 5A is a TEM image of an SiO2 amorphous intermediate layer with a cross-sectional thickness in the range of 2 nm to 4 nm, and Figure 5BA shows a TEM image of another example of an SiO2 amorphous intermediate layer with a cross-sectional thickness in the range of 10 nm to 15 nm. Figure 5C is a TEM image of an SiO2 amorphous intermediate layer with a cross-sectional thickness in the range of 5 nm, or 3 nm to 5 nm (e.g., about 4 nm).

[0026] A second exemplary design aspect relates to the nanocrystallization and amorphous formation of interfaces using high-energy ion beams. In line with the exemplary methods of this disclosure, the ion source is used in the range of 100 eV to 10 keV. By using this aspect or method, a thin interface layer can be formed between diamond and the semiconductor beneath it. If a thin interlayer is designed to function as a phonon buffer layer between the two materials to reduce TBR, the thickness of the interlayer can vary, for example, in one experimental effort, ranging from a few nanometers to less than 10 nanometers at the lower limit and several hundred nanometers at the upper limit.

[0027] The next of these exemplary design aspects is interface crystallization using high-temperature vacuum annealing. In this aspect or method, high-temperature annealing of 800–1800°C is used to crystallize the amorphous interlayer deposited using the first exemplary design aspect or method described above. It has been shown that crystallization of the interlayer with higher TC can further reduce TBR, as shown by the black dots in Figure 9.

[0028] The last of these exemplary design aspects concerns the diffusion of carbon during diamond growth. In line with the exemplary methodology and related aspects of this disclosure described above, the hydrogen plasma density is controlled within the chamber (used for diamond growth) to diffuse carbon into the substrate to a depth of 1 nm to 10 nm. The temperature of the carbon diffusion process varies in the range of 300°C to 1100°C, depending on the substrate and the target depth. This process allows a portion of the interface to be (SiO2, SiN at the interface). x It is converted to SiC (if Si is present) or to Al4C3 (if AlN or Al2O3 is present at the interface).

[0029] Figure 6 is a TEM image of an exemplary experimental setup highlighting the C / Si interface after ion beam exposure, in accordance with certain exemplary aspects of this disclosure.

[0030] Figures 7A and 7B are a set of figures characterizing the thermal behavior of an exemplary experimental apparatus with a specific experimental intermediate layer, in accordance with certain exemplary aspects of the present disclosure. Figure 7A shows a graph of different thermal boundary resistances with respect to diamond thickness, where the dashed line ("DMM TBR") indicates the level relevant to diffusion mismatch (DMM) prediction. Figure 7B shows the EELS characterization of a C / SiN / GaN interface or intermediate layer where C has diffused into SiN to form a SiC transition layer. The insets correspond to the EELS edge strength of diamond. The first (left) image is a magnified view of the SiL2,3 edge, showing a representative example where Si atoms are maximal at the yellow-indicated location (corresponding to the brighter central region above and slightly below the SiN-GaN interface); the next (center) image is a magnified view of the CK edge, showing a representative example where carbon atoms are maximal at the yellow-indicated location (corresponding to the upper region of the inset well above the SiN-GaN interface); and the far right image is a magnified view of the NK edge, showing a representative example where nitrogen atoms are maximal at the yellow-indicated location (corresponding to the brighter central region above and below the SiN-GaN interface).

[0031] Figures 8A, 8B, and 8C are a set of three images showing EELS analysis with cross-sectional views of three different experimental specimens, each shown according to specific exemplary aspects of the present disclosure. As shown in these images, EELS imaging allows for the identification of the precise thickness of SiO2 based on the detection of oxygen, and also allows observation of slight diffusion of C into the SiO2. Figure 8A corresponds to one such specimen showing a TEM image at the interface between diamond, SiO2, and Si; Figure 8B corresponds to a second specimen showing a two-dimensional EELS mapping of the carbon atom distribution at the interface; and Figure 8C corresponds to a third specimen showing a two-dimensional EELS mapping of the oxygen atom distribution at the interface.

[0032] FIG. 9 is a graph showing the thermal boundary resistance against the intermediate layer thickness associated with different experimental samples, according to certain exemplary aspects of the present disclosure. As shown in the legend of the graph of FIG. 9, these experimental samples include, as diamond-intermediate layer-substrate materials, S / SiO2 / Si, C / Si3N4 / GaN, C / None / 4H-SiC, and C / a-SiC / Si. All samples were prepared and fabricated at Stanford.

[0033] As shown for each item plotted on the graph, reducing the thickness of the intermediate layer results in a decrease in the TBR between diamond and any semiconductor, and by crystallizing the intermediate layer, a minimum possible TBR of 1 m 2 K / GW was obtained between diamond and SiC. In some examples, by controlling the thickness (i.e., limiting the thickness) of the intermediate layer material using at least one of amorphous dielectric deposition and crystalline dielectric deposition, the TBR can be achieved to be 3 or less, and depending on the material stack, the TBR may exceed 3. For example, when forming the thickness of the intermediate layer material using at least one of amorphous dielectric deposition and crystalline dielectric deposition, such a design can be implemented by controlling the thickness to achieve its upper limit so that the phonon transport loss is mitigated for the targeted or corresponding TBR, which can be associated with or set as a function of the thickness and / or material composition of the intermediate layer material. In such cases, and depending on the thickness and / or such configuration (e.g., the material composition and / or lamination of the layers designed to form the intermediate layer), the TBR can be set to be 3 or less, or exceed 3. Note: Unless otherwise specified, the measurement unit used to characterize the TBR is m 2 K / GW.

[0034] Furthermore, according to this disclosure, by using such manufacturing methodologies, various semiconductor structures and / or devices can be characterized as including deposited and / or etched materials (after manufacturing or during the partial manufacturing process), that is, in the case of deposition (in contrast to diffusion which shows a gentle profile, such as carbon diffusion in Figures 3A-1 and 3A-2), different chemical compositions of the material exist and transitions between these chemical compositions can be clearly observed by TEM imaging or other (e.g., chemical) analysis, and in the case of etching (e.g., dry etching), an etched surface showing a degree of roughness or smoothness can be observed depending on the type of etching chemistry used. Further related experimental efforts and / or additional, more detailed examples.

[0035] Further information regarding various aspects of this disclosure (e.g., exemplary structures, layered materials, dimensions, steep and non-steep comparisons, measurements related to TBR and layer thickness (or thinness), heat transport efficiency, phonon-related overlap and / or transport losses, etc.) can be found in the experimental studies described below. It is understood that the aspects, features, etc., in these experimental studies can be combined with features in other figures or exemplary embodiments (related to the discussions below or above), even if such combinations are not explicitly shown or described as such, and each such combination may be considered a combinatorial aspect of this disclosure. Supporting this disclosure, experimental efforts and / or additional, more detailed examples have been successfully implemented and relate to the aspects (and other aspects) of this disclosure as described above, and will be further detailed and supported in connection with the following description.

[0036] Some of these aspects, experimental approaches, and / or additional, more detailed examples will be presented in the following explanation. Results obtained in connection with this work show that precise intermediate layer design of less than 4 nm can achieve TBR below the diffusion mismatch (DMM) theory, i.e., 2.13 nm. 2This demonstrates that the temperature can be reduced to K / GW. Part of this work involved using Si substrates with SiC developed using GaN material technology. Experimentally, the SiC deposition was precisely controlled to achieve a 4-8 nm intermediate layer deposited on the Si. Diamond was grown, and the resulting TBR was evaluated using multiple thermoreflectance testbeds. These experimental and simulation results provide an example of a practical and predictive platform for thermal design.

[0037] In relation to some experimental and simulation efforts, Figure 10 shows the peak channel temperature (K) as a function of power density (W / mm) in electrothermal simulations of broadband N-polarity GaN HEMTs (high electron mobility transistors), including three cases: a control HEMT without diamond, a HEMT with single-crystal diamond as the substrate, and a HEMPT with a 2-micrometer all-around PC diamond on top. Lowering the TBR between the channel and the diamond heat spreader can reduce the peak channel temperature, enabling reliable performance at higher power densities. Simulations show that a device operating at 15 W / mm requires a TBR of 10 m 2 In the case of 2, the channel temperature decreases by 80K compared to the case of K / GW. The conventional approach of overlaying diamond onto the thermoreflectance data of GaN HEMT is shown superimposed on this plot, and within the reasonable range of the model (TBR is 2-5m) 2 It is located at K / GW.

[0038] A model for predicting TBR between diamond and Si using different steep interfaces and interlayers was developed to understand the lower limit of TBR due to interlayer design. As shown in Figure 11, heat transport in a layered system of Si and diamond was simulated based on molecular dynamics. More specifically, Figure 11 shows an exemplary layered system with a heat source on Si, a heat sink on diamond, and a constant heat flux passing through the entire system. This approach has three stages: equilibrium, transient, and steady state. Finally, the temperature gradient becomes time-invariant, and the total thermal resistance of the system is calculated based on Fourier's law of heat conduction.

[0039] To evaluate the actual TBR of the interface, the bulk component of the thermal resistance was calculated separately and subtracted from the total thermal resistance. Interatomic interactions were described based on the Tersoff potential (Erhart, P. et al., Physical Review B 71 3 (2005): 035211), and all simulations were performed using the Large-Scale Atomic / Molecular Parallel Simulator (LAMMPS). Among the three different steep interface models (diamond / Si, diamond / SiC, and SiC / Si), the diamond / SiC interface was found to have good phonon density of states matching, resulting in a 0.89 m 2 The lowest simulated TBR was observed at K / GW, and the SiC / Si ratio also showed relatively low values. As experimentally demonstrated by these efforts, the calculated phonon density of states (PDOS) of the bulk phase (based on the Tersoff potential) indicates that phonons across the entire frequency range (0 to 1500 1 / cm) can be effectively transported on a-SiC films with a thickness of less than 3 nm for amorphous SiC PMFPs. In specific cases, when the interlayer material was SiC and the interlayer was deposited by PECVD, the interlayer thickness was measured to be ~4-7 nm, and when the interlayer material was SiC / a-SiO2 and the interlayer was deposited by C-diffusion ALD, the interlayer thickness was measured to be ~3 nm.

[0040] In contrast, as shown in Figure 12, the direct diamond-Si interface is 5.01m 2 The TBR for K / GW is shown, and the predicted value of 2.86–3.15m is calculated by a DMM assuming random elastic scattering at the interface. 2 The TBR was slightly higher than that of K / GW. This higher TBR indicates that thermal transport is not optimal when no intermediate layer is considered for diamond in Si technology. Therefore, it was shown that by inserting a very thin amorphous SiC intermediate layer (less than 4 nm), the TBR between diamond and Si becomes smaller than in the case of a steep interface. Furthermore, it was observed that the TBR increases with increasing the thickness of the a-SiC intermediate layer, which is expected to be due to the increased possibility of phonon scattering. Nevertheless, it was shown that by having a sufficiently thin a-SiC intermediate layer, the TBR can be reduced significantly by more than 50%, and even below the DMM theoretical limit. See, for example, Figure 12. This is thought to be due to the fact that, as explained above in relation to PMFP of amorphous SiC, when it is thinner than PMFP, phonon mode matching and phonon tunneling through the thin amorphous intermediate layer are improved, and phonons across the entire frequency range are efficiently transported on the a-SiC film with a thickness of less than 3 nm.

[0041] In relation to the deposition and control of the intermediate layer, and to support the predicted TBR obtained by the model, intermediate layers of varying crystallinity and thickness were deposited on a Si substrate, and diamond growth was performed. SiO2 was deposited by atomic layer deposition (ALD), and SiC was deposited by plasma-enhanced chemical vapor deposition (PECVD). In a specific example of this PECVD deposition, a thickness of less than 10 nm could not be achieved. Therefore, a thicker intermediate layer was deposited first, and then precisely etched to less than 10 nm by RIE. The thickness of the intermediate layer was measured by ellipsometry before diamond growth and by TEM after diamond growth. Large-grained, isotropic PC diamonds grown by MPCVD are easily recognizable when observed through TEM images.

[0042] The results obtained from related experiments will be explained immediately below. The average TBR of diamond / SiC / Si structures with a deposited SiC interlayer (~5nm) is 3.3m 2 The measured K / GW and low TBR support the hypothesis that SiC is the primary buffer material. Furthermore, the extremely low diamond / SiC TBR of 1.0m was measured between diamond and crystalline 4H-SiC. 2 The K / GW values ​​below the specified value are in close agreement with the simulation, supporting the advantage of SiC in efficient phonon transport with diamond. On the other hand, in simulations using a purely amorphous SiC interlayer, the TBR of diamond / a-SiC / Si was 5.09~6.68m when the thickness was approximately 5nm. 2The predicted K / GW range is greater than the experimentally observed value. HAADF TEM analysis revealed that diamond growth causes the deposited a-SiC to crystallize, forming SiC nanocrystals within the intermediate layer. As simulations show, TBR can be further reduced by designing the crystallinity of SiC. Therefore, it is predicted that TBR can be further reduced by annealing before or during high-temperature diamond growth, thereby increasing the crystallinity of the intermediate layer, which is normally amorphous during deposition. EELS analysis of these structures revealed the non-steep nature of the interface, which contributes to the smooth transition of phonon modes across the interface. Core loss spectra showed that the C_K edge sampled toward the Si substrate gradually disappears, and the Si_L2,3 edge gradually appears. Furthermore, to distinguish the intermediate layer from the PC diamond and substrate, C and Si standards were obtained in different layers, showing that the bonding to SiC gradually transitions from either side of the interface. For example, in a layered configuration where PC diamond is on C (edge ​​standard from PC diamond), C (edge ​​standard from SiC interlayer), Si (edge ​​standard from SiC interlayer), and Si (edge ​​standard from substrate), the buffer SiC layer (1-2 nm, or interlayer) provides smooth transitions from diamond to SiC, and between the phonon properties of diamond, the interlayer, and the substrate material, thereby reducing the probability of phonon reflection and scattering. Furthermore, in a sample using deposited SiO2, a standard dielectric in Si technology, the TBR of diamond / SiC / SiO2 / Si is 4.46 nm when there is a 3 nm SiC / SiO2 interlayer. 2 The K / GW ratio was low. EELS analysis of the interface revealed slight carbon diffusion (~2 nm) into the SiO2 layer, confirming the formation of a thin interface SiC layer (e.g., SiN x(This is similar to what has already been observed and described herein in relation to GaN). The TBR of diamond / SiC / SiO2 / Si was higher than that of diamond / SiC / Si, but in the case of diamond on Si without any intermediate layer design (TBR of diamond / Si = 7.2 ± 0.8 m 2 It was lower than (K / GW). With respect to limited exemplary embodiments aimed at minimizing or setting such particularly low TBRs, these experimental results show very low, and possibly the lowest TBR values ​​to date reported, and further demonstrate that such low experimental TBRs for diamond are achievable in Si and GaN. This highlights the advantages of the interlayer design, achieved across different interlayer materials, 5m 2 A relatively low TBR of less than K / GW was first obtained in certain conventional diamond experiments containing GaN at 3.1 ± 0.7 m. 2 Following the K / GW TBR value, it was confirmed that the results were reproducible.

[0043] Therefore, the effect of the intermediate layer on enabling efficient heat transport was first modeled and then experimentally demonstrated. This involved incorporating a SiC intermediate layer before diamond growth, or using SiC, SiN x By incorporating carbon through interdiffusion (1-2 nm) into SiO2, the TBR measured between diamond and the substrate was reduced. This study showed that fine-tuning of the intermediate layer facilitated smooth transitions between phonon modes and DOS overlap, resulting in record low TBRs for phonon transport from Si and GaN to the diamond heat spreader (TBR = 1.89 ± 0.18 for diamond / SiC / Si, TBR = 4.46 ± 0.99 for diamond / SiC / SiO / Si, and TBR = 4.46 ± 0.99 for diamond / SiC / SiN x TBR of GaN = 3.1 ± 0.7 m 2It became clear that a K / GW) could be achieved. Furthermore, the crystallization of a-SiC at the interface during diamond growth was lower than predicted by simulations, and the TBR (1m) of the epitaxial interface between diamond and 4H-SiC was also found to be lower. 2 These were considered to be the factors behind the record-low TBR values, which were extremely close to less than K / GW. These experiments can be directly applied to implementations, including, but not limited to, Si, GaN RF, and thermal engineering applications of various RF power amplifier (PA) technologies.

[0044] Figures 13A and 13B illustrate Si ICs and GaN-PA ICs (which can be used in RF transistors, etc.), demonstrating that device-level thermal control is possible by replacing the passivation layer with single-crystal or polycrystalline diamond (due to its excellent thermal conductivity of 300-2200 W / m / K). In Si ICs, diamond can be incorporated as a heat spreader in the back-end-of-line (BEOL) and, when used with an intermediate layer material (shown in the previous figure but not in Figures 13A and 13B), enables virtually lossless phonon transitions through interfaces such as GaN-diamond and Si-diamond.

[0045] In relation to the use of intermediate layers in IC-related structures, examples of this disclosure show that low-temperature (below 400°C) CVD growth allows polycrystalline diamond to be incorporated near hot spots in the channels / junctions of the device, and heat can be diffused to the heat sink via various (diffusive or ballistic) phonon transport mechanisms. Achieving a perfect interface (epitaxial covalent bond) between diamond and other semiconductors such as Si, GaN, InP, and β-Ga2O3 is extremely difficult due to mismatches in lattice and coefficient of thermal expansion (CTE), thus requiring interface design between these semiconductors and diamond. Forming a thin intermediate layer between the two materials can serve two main purposes. Firstly, in certain materials such as GaN, an intermediate layer is necessary to mitigate the mismatch in lattice and coefficient of thermal expansion (CTE) between diamond and GaN. It acts as a stress-relaxing layer to improve diamond adhesion and also as a protective layer (against H plasma) for the semiconductor surface during diamond growth. Secondly, the intermediate layer plays a crucial role in heat transport. As mentioned above, the third is a combination of diamond (which has high thermal conductivity) and designing a structure for effective TBR between the diamond and the channel / joint material of the device.

[0046] Some of these aspects, experimental approaches, and / or additional, more detailed examples are described below.

[0047] In specific related experimental efforts relating to this disclosure, it has been found that phonon loss at the interface can be optimized or minimized (for lower TBR), and that this requires precise interface design accompanied by careful deposition and / or material removal efforts such as etching. In perfectly smooth and steep interfaces (acoustic mismatch (AMM) theory), the frequency and wavenumber of the k-vector must be identical for phonons to transmit seamlessly across the interface. In practice, under non-cryogenic conditions, interfaces are relatively rough, and the diffuse mismatch (DMM) model is more appropriate. Here, phonons are assumed to diffusely scatter at the interface and have no mode memory. Therefore, the overlap of phonon density of states (PDOS) is proportional to the ease with which phonons move across the interface. Between Si or GaN and diamond, the PDOS does not overlap sufficiently over higher frequency ranges. Therefore, it is necessary to add a phonon bridge between the two materials. The use of amorphous intermediates results in phonon mode mixing, which modifies the initial phonon modes from Si or GaN, potentially leading to better matching than that of diamond, thus enabling more efficient phonon transport across the interface. Amorphous intermediates result in significant phonon mode conversions, such as longitudinal acoustic (LA) to transverse acoustic (TA) conversion, TA to LA conversion, and LA to transverse optical (TO) conversion. These conversions in amorphous materials, where phonon modes are not clearly defined, help transport phonons from one material to the other with less loss. This conversion is due to the strong anharmonicity of the interatomic potentials, which results in the mixing of different phonon modes. SiC provides a larger PDOS overlap between Si and diamond, allowing a larger proportion of phonons to cross the interface due to phonon mode mixing in the amorphous intermediate.Compared to a-Si, which does not provide sufficient PDOS overlap between diamond and Si, a-SiC can form a more efficient phonon bridge, and SiO2 overlaps with both Si and diamond, which is beneficial to certain exemplary embodiments of this disclosure. For example, regarding phonon bridging between diamond and GaN, experiments leading to this disclosure have shown that for certain combinations, SiN... x 3.1m 2 K / GW TBR, and possibly 3m 2 It has been shown that it can provide a TBR slightly below K / GW. SiN x This not only expands the frequency overlap but also improves the adhesion of diamond to the surface through SiC formation during diamond growth (SiC formation was also observed in the SiO2 intermediate layer). SiN x In addition, a-SiC can also form a phonon bridge between diamond and GaN due to its frequency overlap of 20-30 THz.

[0048] In the case of the GaN / diamond interface, despite the PDOS overlap between 20 and 30 THz, weak van der Waals coupling degrades phonon transitions because H plasma damage and large CTE mismatches create nanoscale voids and delamination. Regarding phonon bridging between diamond and GaN, the approach of this disclosure enables SiN for a given combination. x 3.1m 2 It has been shown that it can provide a record low TBR of K / GW. SiN x This not only expands the frequency overlap but also improves the adhesion of diamond to the surface through SiC formation during diamond growth (SiC formation was also observed in the SiO2 intermediate layer). SiN x In addition, a-SiC can also form a phonon bridge between diamond and GaN due to its frequency overlap of 20-30 THz.

[0049] To elucidate the interface between diamond and different intermediate layers and substrates, extensive TEM (transmission electron microscopy) imaging and EELS (electron energy loss spectroscopy) analysis were performed. First, when polycrystalline diamond was grown directly on a Si substrate without a designed intermediate layer, the presence of a native oxide film, measured as ~1.4 nm by ellipsometry, was shown to improve diamond nucleation and growth by potentially reducing the penetration of hydrogen generated within the diamond growth chamber into the substrate, as shown in Figure 14B. In contrast, when the native oxide film was removed by HF etching before diamond seeding, TEM images indicated significant etching damage on the Si substrate during diamond growth (Figure 14A). Furthermore, the final average diamond thickness after growth was only 0.3–0.5 μm, which was smaller than the 1.5–1.8 μm thickness achieved using the same growth conditions on a Si substrate with a native oxide film. These results, considering the seeding and growth parameters used in such experiments, confirm that the intermediate layer plays a crucial role in heterogeneous diamond growth and substrate protection. It should also be noted that varying the growth pretreatment, plasma parameters, and CH4 ratio can also play a role in interface roughness and SiO2 etching during diamond growth.

[0050] More specifically, Figure 14A is a TEM image of polycrystalline diamond grown on an HF-treated Si substrate from which the native oxide film has been removed. Figure 14B is a TEM image of polycrystalline diamond grown on a Si substrate with the native oxide film present, under the same growth conditions as Figure 14A. In addition to the native SiO2, four different thicknesses of ALD SiO2 were deposited as an intermediate layer before diamond growth. The thickness of the SiO2 was measured by TEM after growth, and its thickness was varied in the range of 3 to 12.5 nm. The detailed EELS profile of the interface of the sample with 3 nm of SiO2 (Figure 14A) reveals the non-steep nature of the interface, confirms carbon diffusion into the SiO2 layer, and indicates the formation of a SiC buffer layer between the diamond and SiO2. By using the core loss EELS spectrum summed across a rectangular region, we can identify regions useful for analyzing the chemical composition of each material layer (from the upper diamond region, through the upper and lower intermediate layer regions, to the lower Si substrate region). In these regions, C and O are detected, with a prominent carbon peak (~285 eV) observed (the intensity decreases as we move from diamond through the lower intermediate layer region towards silicon). Additionally, an oxygen peak is detectable from the intermediate layer region, confirming the presence of both elements in the intermediate layer. Finally, in the bottommost region, as expected in a Si substrate, neither the carbon nor oxygen peaks are present. The absence of Si and oxygen in the second region may be due to the diffusion of carbon and hydrogen into the amorphous layer, and the removal of Si and oxygen after reaction with hydrogen radicals. In such experiments, this interdiffused carbon combines with Si, forming an interfacial SiC layer (2-3 nm) between diamond and SiO2. The interdiffusion of carbon, as demonstrated by the efforts of this disclosure, provides a smooth transition between the phonon properties of the diamond, the intermediate layer, and the substrate material, and thus reduces the probability of phonon loss (reflection / scattering) as described above.

[0051] When HDPCVD SiC was used as the intermediate layer, TEM images showed partial crystallization of the SiC during diamond growth (fringes were observed at the interface). Fast Fourier Transform (FFT) analysis confirmed the presence of SiC nanocrystals in the intermediate layer based on identified diffraction spots. The amorphous nature of the SiC deposited before diamond growth was verified using a similar technique that showed the absence of diffraction spots in the SiC. Therefore, it is inferred that crystallization occurred during diamond growth due to the atomic hydrogen plasma in the chamber and the relatively high temperature conditions (500-600°C).

[0052] Similar to the SiO2 intermediate layer sample, EELS analysis revealed that the diamond / SiC / Si interface has a stepwise and smooth compositional transition. The core loss spectrum showed that the C_K edge sampled toward the Si substrate gradually disappeared, and Si_L 2,3 This indicates the gradual emergence of edges. Furthermore, the shift of the Si peak in the intermediate layer from 102 eV to 105 eV suggests the formation of SiC in certain segments, though not all segments.

[0053] In experiments concerning the diamond / SiC / GaN interface, due to the relatively low growth temperature (450-500°C), most of the interface remained amorphous. Furthermore, from the EELS data, the presence of carbon overlaps with that of Si, which is expected from the SiC interlayer, but also from diffusion from diamond. On the opposite side of the interface, Ga and N overlap with Si originating from the interlayer. Therefore, over the ~6 nm portion forming the interface and buffer layer, there is a clear mixing of different elements present in the diamond, interlayer, and GaN substrate.

[0054] Figure 15 presents a summary based on graphs of measured TBRs for diamond-Si, diamond-GaN, and diamond-SiC using different intermediate dielectrics, according to the examples of this disclosure. Details of each material system are broken down below.

[0055] For diamond / 4H-SiC, due to the phonon frequency overlap between diamond and 4H-SiC, phonons are transported between the two materials primarily unhindered, maintaining their modes. SiC has a high defect density near the interface and a narrow band with a different crystalline structure in the upper part (~1.5 nm). FFT and stacked array (ABC) show a thin band of 3C-SiC (less than 1.5 nm) in several regions of the surface. Crystalline cubic diamond forms directly at the interface on 3C-SiC with little to no indication of any amorphous phase between them. This steep interface provides a stable single CC coupling that can reduce the probability of phonon loss across the interface with minimal reflection. TBR of diamond / 3C-SiC / 4H-SiC is performed using the TTR method at ~1 nm 2 It was measured as K / GW. This is 0.39 m (which appears to be the previously reported value). 2 K / GW and 0.89m 2 This experimental value is the closest to the MD simulation value for K / GW.

[0056] For diamond / Si, two different intermediate layers, SiO2 and a-SiC, were used on the Si substrate. By reducing the thickness of the SiO2, a 3nm SiO2 intermediate layer was used to reduce TBR, and 5nm 2 A TBR of less than K / GW was obtained. This has been previously reported to be because, especially in the case of low thermal conductivity materials such as SiO2 (TC: ~1 W / m / K), a thicker interlayer contributes to thermal resistance due to a higher scattering probability. However, the TBR obtained as a result was approximately 7 m 2 This is lower than that of direct diamond-Si TBR, which is measured as K / GW. Therefore, the importance of a non-steep phonon-mixed intermediate layer for phonon propagation across the diamond / Si interface is confirmed in line with the aspects of this disclosure. Furthermore, at thicknesses of less than 3 nm, phonon tunneling through an amorphous intermediate layer appears to be an important phenomenon contributing to improved phonon transport.

[0057] Notably, when a-SiC was used as an intermediate dielectric between diamond and Si, samples with thinner intermediate layers did not necessarily exhibit lower TBRs, as was the case with SiO2. TEM analysis of the interface revealed that a-SiC partially crystallized during diamond growth, and its atomic structure rearranged to form a thin 3C-SiC layer. This rearrangement of the SiC atomic structure may occur throughout the high-temperature diamond growth process or during the early stages of nucleation; however, further investigation is needed to fully understand SiC crystallization and its contribution to phonon mode mixing. The thinner SiC intermediate layer (2.6 nm) crystallized completely, with no a-SiC remaining, while the thicker layer (7.2 nm) partially crystallized, with 2-3 nm of a-SiC remaining. It is thought that the remaining a-SiC enables phonon mode mixing between diamond and Si, promoting phonon propagation across the interface. Therefore, the thicker SiC intermediate layer, 1.89 nm between diamond and Si... 2 This resulted in an average TBR of K / GW (for example, another clearly lower value compared to those reported to date).

[0058] In one example, direct diamond CVD growth on GaN is ~20m 2 This resulted in a minimum TBR of K / GW. This large value is attributed to the weak van der Waals coupling between diamond and GaN, and the lack of phonon frequency overlap between the two materials. As shown in Figure 15, SiN between diamond and GaN. x Furthermore, by reducing the thickness of the SiC, a lower TBR was obtained. In this particular study, PECVD and MOCVD SiN x However, it is used to form an intermediate layer between diamond and GaN. To minimize the TBR of diamond-GaN, ultrathin SiN less than 3 nm is used (to enable phonon tunneling). x PECVD SiN is required. x Due to H2 plasma exposure, it was completely damaged during diamond growth and removed by etching. On the other hand, MOCVD SiN xOnly 1 nm was etched during growth, but the remaining intermediate layer survived the growth process and protected the interface. Diamond / SiN x TBR of GaN is measured by TEM. x With an intermediate layer (~1 nm) and an interdiffused SiC layer of ~1 nm measured by EELS, 3.1 m 2 The minimum value of K / GW is reached, which is closely consistent with DMM theory. On the other hand, SiN x It forms a strong bond with GaN, and carbon diffusion during diamond growth occurs on the other side, SiN x This results in the conversion of the SiC layer to SiC. The newly formed SiC layer establishes a strong covalent bond (CC single bond) with the diamond, improving adhesion while allowing a stepwise change in stoichiometry along the interface. This stepwise material transition not only mitigates the coefficient of thermal expansion (CTE) mismatch between diamond and GaN, but more importantly, it facilitates phonon transport across the interface by providing phonon frequency overlap and phonon mode conversion with both diamond and GaN, resulting in a lower TBR.

[0059] SiN x The thin SiC layer formed during diamond growth due to carbon diffusion then motivated the use of SiC as an intermediate layer before growth. Unlike the diamond / SiC / Si material system, the SiC between diamond and GaN did not crystallize and remained amorphous throughout growth. As a result, the TBR decreased with decreasing a-SiC thickness, and 5m 2 The value reaches less than K / GW. In connection with such experimental efforts relating to this disclosure, a-SiC(SiN x It has also been shown that (similarly) this can provide a low thermal resistance interface between diamond and GaN.

[0060] Furthermore, this disclosure demonstrates that TBRs can have a significant impact on channel / junction temperatures in such ICs, including so-called three-dimensional (3D) ICs. It has been reported that ultra-high-density 3D ICs with a horizontal pitch of 100 nm between vertical vias can achieve a 1000-fold gain in energy-delay product compared to those constructed with conventional techniques that allow via pitches of 1–10 μm. With conventional cooling, these 3D ICs are thermally limited to only one layer for high-power calculations. However, better cooling, enabling multiple layers of stacking and simultaneous active calculations, could free up the scaling of these enormous gains for even larger workloads. However, even with improved heat sinks, ultra-high-density 3D ICs are limited by their harsh thermal environment. In these systems, the hotspots for high-power calculations are embedded within high stacking of thermally resistant BEOL materials, such as ultra-low-κ interlayer dielectrics (ILDs), which can have five times higher thermal resistance than SiO2. Diamond's high thermal conductivity and low dielectric constant make it a promising substitution dielectric material, and by improving TBR with Si, its gain in Si-based 3D ICs can be further increased.

[0061] Furthermore, 3D thermal scaffolding as a technique has been reported to leverage the advantages of diamond and achieve significant temperature reductions (e.g., a 10-fold reduction in peak temperature rise in a 12-layer computing tier) by selectively patterning diamond layers and scaffolding via structures. In some of these examples, diamond is used as a thermal diffusion dielectric only in the upper power supply network layer, which is close to the hotspot and of lower performance importance than the lower signal wiring layer, and scaffolding vias are co-located with the diamond to direct heat downward to the heat sink.

[0062] Furthermore, according to this disclosure, the effect of reducing the TBR between the diamond BEOL layer and Si in such a 3D IC system was investigated by COMSOL simulation. The TBR of Si-diamond was reduced from 20 to 1.89 m 2 The effect of reducing the TBR to K / GW (which may be the lowest value among the average values ​​reported to date) on the peak temperature is examined in this disclosure for three cases: a baseline without diamond BEOL or scaffolding vias, a diamond BEOL without vias, and scaffolding with diamond vias. It was shown that reducing the TBR reduces the temperature rise due to the 3D layer (i.e., the peak temperature difference from the ambient temperature assuming a complete heatsink) by an offset that is not strongly dependent on the number of layers but increases as the hot spot becomes smaller. This is because thermal diffusion by diamond occurs after heat has entered the diamond layer through the diamond / Si interface. Smaller hot spots require more thermal diffusion and are therefore more greatly affected by improvements in TBR.

[0063] For GaN PAs, the TBR between diamond and GaN plays an essential role in determining the channel temperature under operation. Reducing the diamond / GaN TBR lowers the channel temperature, allowing high power output to be achieved before reaching the maximum operating temperature (see ATLAS User's Manual, SILVACO International, 2004). This simulation was calibrated with experimental data reported in R. Soman, M. Malakoutian, B. Shankar, D. Field, E. Asko, N. Hatui, NJ Hines, S. Graham, UK Mishra, 2022 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2022, pp. 30.8.1-30.8.4. As previously reported, the 3D all-around diamond and the TBR between diamond and GaN are 5m.2 Devices with a power output of less than K / GW reached ~23W / mm at 525K, while a TBR with the same structure achieved 20m 2 In the case of K / GW, it can only reach ~16 W / mm. However, according to experimental efforts including the examples in this disclosure, SiC and SiN x Both TBRs are 5m 2 It has been shown that the power can be reduced to less than k / gw, which may be useful, if not necessary, for higher power output and more reliable operation (e.g., before thermal runaway occurs).

[0064] Based on the above discussion of such experimental efforts relating to this disclosure, several dielectric materials have been investigated as thermal interface buffers in structures such as GaN / diamond and Si / diamond interfaces. The TBR between diamond and Si can be reduced by designing the thickness of the intermediate layer (e.g., deposition, material removal, etc.) and the proportion of crystallinity, and in some examples, it is lower than the DMM theory prediction of 1.89 m. 2 The average TBR value for K / GW has been achieved. This results in SiN x By using either a-SiC or a-SiC, the TBR between diamond and GaN can be reduced to 5m 2 It has also been shown that the temperature can be reduced to below K / GW. Interface design strategies can effectively reduce channel / junction temperatures in a variety of material systems, including but not limited to Si and GaN technologies, as well as other technologies including AlN, InP, and Ga2O3.

[0065] It is recognized and understood that, as a specific example, the figures and descriptions characterized above are provided to help illustrate certain aspects (and possibly advantages) that may be used in the manufacture of such structures and devices. These structures and devices include exemplary structures and devices described in relation to each figure, as well as other devices, and each described embodiment has one or more relevant aspects that may be modified and / or combined with other such devices, and examples like those described above may also be found in the appendix to the provisional application referenced above.

[0066] Those skilled in the art will also understand the various terms used in this disclosure in their ordinary meanings. For example, this specification may describe and / or illustrate aspects useful for carrying out the examples by various semiconductor materials / circuits, such as, or which may be illustrated using, terms such as layers, blocks, modules, devices, systems, units, controllers, and / or other circuit types. Such semiconductors and / or semiconducting materials (including parts of semiconductor structures) and circuit elements and / or associated circuits may be used together with other elements to illustrate how a particular example may be carried out in the form of structure, steps, functions, operations, activities, etc. It will also be understood that terms illustrating directions such as up / down, left / right, upper / lower, and upward / downward may be used in this specification to refer to the relative positions of elements shown in the figures. These terms are used for notational convenience only, and it should be understood that in actual use, the disclosed structures may be oriented in directions different from those shown in the figures. Accordingly, these terms should not be interpreted restrictively.

[0067] Based on the above description and illustrations, those skilled in the art will readily recognize that various modifications and changes can be made to various embodiments without strictly adhering to the exemplary embodiments and applications illustrated and described herein. For example, the methods illustrated in the figures may include steps performed in various orders, or fewer or more steps, while retaining one or more aspects of the embodiments herein. Such modifications will not deviate from the true spirit and scope of the various aspects of this disclosure, including the aspects described in the claims.

Claims

1. The substrate material is prone to accumulating or generating heat due to electrical conductivity in or near the substrate material, A diamond material that diffuses and transmits heat from the aforementioned substrate material, An intermediate layer material characterized by having a TBR (thermal boundary resistance) and a thinness of the intermediate layer material between the substrate material and the diamond material, wherein the thinness of the intermediate layer material has an upper limit designed by material deposition techniques to mitigate phonon transport losses in order to achieve a target or corresponding TBR associated with the intermediate layer material, A device equipped with the following features.

2. The apparatus according to claim 1, wherein the intermediate layer material is characterized by at least one smooth transition in the material phase in order to match one or a combination thereof of phonon group velocity, phonon frequency, or phonon mode on both opposing sides of the intermediate layer material.

3. The apparatus according to claim 1, wherein the substrate material includes a carbon diffusion portion along the side of the substrate material facing the diamond material, and the carbon diffusion portion has a cross-section characterized by a thickness parameter in the range of about 1 nm to about 10 nm.

4. The apparatus according to claim 1, wherein the intermediate layer material functions as a stress-relaxing layer that strengthens the adhesion force caused by mismatch between the grid and the coefficient of thermal expansion (CTE).

5. The apparatus according to claim 1, wherein the substrate material includes an inner surface having diffused carbon.

6. The apparatus according to claim 1, wherein the intermediate layer material is a dielectric containing SiC.

7. The apparatus according to claim 1, wherein the intermediate layer material is a dielectric containing AlC.

8. The aforementioned intermediate layer material includes an etched portion resulting from the material deposition technology, and further, Al ２ O ３ SiO ２ The apparatus according to claim 1, comprising one or more of the following: and AlN.

9. The apparatus according to claim 1, wherein the intermediate layer material is formed as a carbon-based phonon buffer and has at least two immediately adjacent material phases with a smooth material phase transition between them, thereby facilitating the matching of at least one phonon-related parameter on opposing sides of the substrate material and the diamond material.

10. The apparatus according to claim 1, wherein the substrate material is a semiconductor material.

11. The apparatus according to claim 1, wherein the substrate material is not a semiconductor material.

12. The substrate material is Si, SiC, GaAs, GaN, InP, and β-Ga ２ O ３ The apparatus according to claim 1, wherein the semiconductor material includes at least one of the following.

13. The apparatus according to claim 1, wherein the intermediate layer material formed by the material deposition technology includes an amorphous dielectric portion.

14. The apparatus according to claim 1, wherein the intermediate layer material formed by the material deposition technology includes a crystalline dielectric portion.

15. The apparatus according to claim 1, further comprising at least one semiconductor device integrated with or thermally coupled to the substrate material, wherein the at least one semiconductor device is a cause of heat accumulation or generation in the substrate material due to electrical conductivity in the vicinity of or within the substrate material.

16. A method comprising a diamond material that diffuses and transfers heat from a substrate material that tends to accumulate or generate heat due to its electrical conductivity in or near the substrate material, The present invention provides an intermediate layer material characterized by having a TBR (thermal boundary resistance) and a thinness of the intermediate layer material extending between the substrate material and the diamond material, The thinness of the intermediate layer material has an upper limit designed by the material deposition technique to mitigate phonon transport losses in order to achieve the target or corresponding TBR associated with the intermediate layer material. method.

17. The method according to claim 16, comprising accumulating or generating heat due to electrical conductivity in or near the substrate material, and using the intermediate layer material to transport phonons across a portion of the intermediate layer material associated with the thinness of the intermediate layer material.

18. The thickness of the intermediate layer material is controlled by at least one of amorphous dielectric deposition and crystalline dielectric deposition, and the TBR is 3m ２ The method according to claim 16, including the implementation such that the ratio does not exceed k / gw.

19. The method includes controlling the thickness of the intermediate layer material via at least one of amorphous dielectric deposition and crystalline dielectric deposition, and achieving an upper limit on the phonon transport loss that is mitigated as a function of the thickness of the intermediate layer material in order to achieve the target or corresponding TBR, wherein the TBR is 3m ２ The method according to claim 16, which is greater than K / GW.

20. The method according to claim 16, comprising ensuring that carbon is diffused into the substrate material during the diamond growth used to form the diamond material.

21. The method according to claim 20, comprising controlling the hydrogen plasma density in the chamber so that the carbon is diffused into the substrate material by a process in which the carbon is diffused into the substrate over a depth range of about 1 nm to about 10 nm.

22. The method according to claim 20, further comprising the carbon being diffused into the substrate material, thereby converting a portion of the interface between the substrate material and the diamond material into a carbon-based material.

23. The method according to claim 16, comprising forming the intermediate layer material after the growth of the diamond material by exposing the intermediate layer material to ions.

24. The method according to claim 16, comprising crystallizing the intermediate layer material during the growth of the diamond material.

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