Memory and its manufacturing method, electronic device

Abstract

This disclosure relates to a memory and a method for manufacturing the same, and an electronic device. The memory includes a common bit line, bit lines, and a cell array. The common bit line extends along a first direction parallel to the substrate. The bit lines are located on the first side of the common bit line and extend along a second direction parallel to the substrate. The cell array includes a plurality of cells corresponding to the bit lines, the plurality of cells located on the same side of the bit lines and arranged sequentially in the second direction. The plurality of cells includes at least one connection cell, at least one selection cell located away from the common bit line of the at least one connection cell, and a plurality of memory cells located away from the common bit line of the at least one selection cell. Both the memory cells and the selection cells include transistors coupled to the bit lines. The transistors included in the selection cells are selection transistors, which are coupled to the common bit line via the connection cells.

Description

Technical Field

[0001] (Cross - reference to related applications) This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on December 25, 2023, with an application number of 202311810441.3 and an invention title of "Memory and Its Manufacturing Method, Electronic Device", the entire content of which is incorporated herein by reference.

[0002] This disclosure relates to the field of memory technology, and particularly to memory and its manufacturing method, and electronic devices.

Background Art

[0003] With the development of semiconductor technology, in order to further pursue the miniaturization of the device structure in the memory, changing the process from planar to three - dimensional, that is, arranging each memory cell and related signal lines in the memory in a three - dimensional space has become the main development direction of the current memory structure research.

[0004] Currently, in a three - dimensional memory, the bit line and the common bit line can each extend along different directions parallel to the substrate, and the bit line can be coupled to the common bit line through a selection transistor. However, the selection transistor is usually provided between the bit line and the common bit line, and its manufacturing yield is likely to decrease due to the influence of the etching loading effect, causing memory failures.

Summary of the Invention

[0005] Based on this, the embodiments of this disclosure provide a memory and its manufacturing method, and an electronic device, which contribute to improving the manufacturing yield of the selection transistor, thereby improving the manufacturing yield and performance of the memory and the electronic device.

[0006] To achieve the above objective, in one aspect, some embodiments of the present disclosure provide a memory comprising a common bit line, bit lines, and a cell array. The common bit line extends along a first direction parallel to the substrate. The bit lines are located on the first side of the common bit line and extend along a second direction parallel to the substrate. The second and first directions intersect. The cell array comprises a plurality of cells corresponding to the bit lines, the plurality of cells located on the same side of the bit lines and arranged sequentially in the second direction. The plurality of cells comprises at least one connection cell, at least one selection cell located on the side of the at least one connection cell away from the common bit line, and a plurality of memory cells located on the side of the at least one selection cell away from the common bit line. Both the memory cells and the selection cells include transistors coupled to the bit lines. The transistors included in the selection cells are selection transistors, which are coupled to the common bit line via the connection cells.

[0007] In some embodiments of this disclosure, the transistor included in the memory cell is an access transistor. The memory cell further includes a capacitor, the capacitor comprising a first electrode coupled to the access transistor, a second electrode facing the first electrode, and a dielectric layer located between the first and second electrodes. Both the selection cell and the connection cell include a first electrode dummy structure. Each first electrode dummy structure in the selection cell and connection cell corresponding to a bit line is interconnected. The selection transistor in the selection cell is coupled to its first electrode dummy structure. The first electrode dummy structure in the connection cell near a common bit line is coupled to the common bit line.

[0008] In some embodiments of the present disclosure, the cell includes a first hole whose axis is perpendicular to the substrate, and a first housing groove extending along a direction parallel to the substrate and located on the side wall of the first hole. The first electrode and the first electrode dummy structure are both conformally covered on the inner wall of the corresponding first housing groove. A dielectric layer is conformally covered on the side wall of the first electrode and the first hole. The second electrode covers the dielectric layer and fills the first housing groove and the first hole. The selection cell and the connection cell each further include a support electrode that covers the first electrode dummy structure and fills the first housing groove, and a first filling layer that fills the first hole.

[0009] In some embodiments of the present disclosure, the cell further includes a second hole located between the bit line and the first hole, with its axis perpendicular to the substrate. Both the memory cell and the selection cell further include a second housing groove extending along a direction parallel to the substrate and located on the side wall of the second hole. The second housing groove exposes, on opposing sides in the first direction, the side wall of the bit line and the side wall of the corresponding first electrode or the corresponding first electrode dummy structure, respectively. The transistor includes a semiconductor layer conformally covering the inner wall of the corresponding second housing groove and a gate insulating layer conformally covering the semiconductor layer and the side wall of the second hole. The memory further includes a word line covering the gate insulating layer and filling the second hole in the memory cell and a selection line covering the gate insulating layer and filling the second hole in the selection cell. The connection cell further includes a second filling layer filling the second hole.

[0010] In some embodiments of the present disclosure, the cell further includes a second hole located between the bit line and the first hole, with its axis perpendicular to the substrate. The second hole exposes, on opposite sides in the first direction, the sidewalls of the bit line and the corresponding first electrode or the corresponding first electrode dummy structure. Both the access transistor and the selection transistor further include a semiconductor layer formed on the inner wall of the second hole and a gate insulating layer, wherein the semiconductor layers between adjacent access transistors in the direction perpendicular to the substrate are insulated from each other, and the semiconductor layers between adjacent selection transistors in the direction perpendicular to the substrate are insulated from each other. The memory further includes a word line covering the gate insulating layer and filling the second hole in the memory cell, and a selection line covering the gate insulating layer and filling the second hole in the selection cell. The connection cell further includes a second filling layer that fills the second hole.

[0011] In some embodiments of this disclosure, the bit line includes a first portion facing the memory cell and the selected cell, and a second portion facing the connection cell. The second portion and the common bit line are integral structures. The memory further includes a separation structure located between the first portion and the second portion.

[0012] In some embodiments of the present disclosure, the same bit line corresponds to at least two connecting cells. The isolation structure includes a first isolation section located between a first section and a second section, and a second isolation section including at least a portion of a second packed layer and connected to at least the first isolation section.

[0013] In some embodiments of the present disclosure, there are multiple bit lines, which are insulatedly arranged along a direction parallel to the substrate and insulatedly stacked along a direction perpendicular to the substrate. Along the direction parallel to the substrate, every two adjacent bit lines constitute one bit line group. Each cell corresponding to any one bit line within the bit line group is located on the same side of that bit line, away from another bit line.

[0014] In some embodiments of this disclosure, there are multiple common bit lines, and the multiple common bit lines are insulated and stacked along a direction perpendicular to the substrate. The memory further includes a stepped structure located on the side of the common bit lines away from the bit lines. The stepped structure includes a plurality of conductive steps coupled to each common bit line.

[0015] In other respects, some embodiments of the present disclosure further provide a method for manufacturing a memory, which can be used to manufacture the memory described in some embodiments.

[0016] The aforementioned manufacturing method is The steps include alternately stacking multiple first dielectric layers and multiple second dielectric layers on a substrate, A step of etching the plurality of first dielectric layers and the plurality of second dielectric layers along a direction perpendicular to the substrate to form a first etching groove extending along a first direction parallel to the substrate and at least one second etching groove located on one side of the first etching groove and extending along a second direction parallel to the substrate, wherein the second direction and the first direction intersect. The steps include etching each second dielectric layer along a direction parallel to the substrate based on the first etching groove to form a plurality of common bit line accommodating grooves, and forming a common bit line within the common bit line accommodating groove, The steps include etching each second dielectric layer along a direction parallel to the substrate based on the second etching groove to form a plurality of bit line accommodating grooves, and forming bit lines within the bit line accommodating grooves, A step of etching the plurality of first dielectric layers and the plurality of second dielectric layers along a direction perpendicular to the substrate to form an etching hole array, wherein the etching hole array includes a plurality of etching hole groups that correspond to the same side of the bit line and are sequentially arranged in the second direction, and the plurality of etching hole groups include a plurality of first etching hole groups distributed at intervals in the second direction, at least one second etching hole group located on the side closer to the common bit line of the plurality of first etching hole groups, and at least one third etching hole group located on the side closer to the common bit line of the at least one second etching hole group, A step of forming a memory cell based on a first etching hole group, wherein the memory cell includes an access transistor coupled to a corresponding bit line, A step of forming a selection cell based on a second etching hole group, wherein the selection cell includes a selection transistor coupled to a corresponding bit line, The step of forming a connection cell based on a third etching hole group, wherein a selected transistor corresponding to the same bit line is coupled to a common bit line by the corresponding connection cell.

[0017] In some embodiments of the present disclosure, the etching hole array is formed before the common bit line etching groove and bit line etching groove are formed, and the first etching hole group, the second etching hole group, and the third etching hole group each include a first hole whose axis is perpendicular to the substrate.

[0018] Correspondingly, the method for manufacturing memory is: The steps include filling each etching hole in the etching hole array with a third dielectric layer, After forming a common bit line, the third dielectric layer is removed from each first hole, The process includes the step of etching a second dielectric layer along a direction parallel to the substrate based on a first hole to form a first housing groove, Correspondingly, the step of forming a memory cell based on a first etching hole group includes the steps of forming a first electrode conformally covering the inner wall of the corresponding first housing groove, forming a dielectric layer conformally covering the side walls of the first electrode and the first hole, and forming a second electrode that covers the dielectric layer and fills the first housing groove and the first hole.

[0019] The steps of forming a selection cell based on a second etching hole group and forming a connection cell based on a third etching hole group each include forming a first electrode dummy structure conformally covering the inner wall of the corresponding first housing groove.

[0020] As described above, each first electrode dummy structure in the selection cell and connection cell corresponding to the same bit line is interconnected. A selection transistor in the same selection cell is coupled to its first electrode dummy structure. A first electrode dummy structure in a connection cell close to the common bit line is coupled to the common bit line.

[0021] In some embodiments of the present disclosure, the steps of forming a selective cell based on a second etching hole group and forming a connecting cell based on a third etching hole group each further include the steps of forming a support electrode that covers a first electrode dummy structure and fills a first housing groove, and forming a first filling layer that fills the first hole.

[0022] In some embodiments of the present disclosure, the first etching hole group, the second etching hole group, and the third etching hole group each further include a second hole located between the bit line and the first hole, with its axis perpendicular to the substrate.

[0023] Correspondingly, the step of forming a memory cell based on the first etching hole group and the step of forming a selected cell based on the second etching hole group are both, The steps include removing the third dielectric layer from the second hole, Based on the second hole, etching the second dielectric layer along a direction parallel to the substrate to form a second receiving groove, wherein the second receiving groove exposes the side walls of the bit line and the corresponding first electrode or the corresponding first electrode dummy structure on opposite sides in the first direction; Forming a semiconductor layer conformally covering the inner side wall of the corresponding second receiving groove; Forming a gate insulating layer conformally covering the semiconductor layer and the side wall of the second hole; Correspondingly, the method for manufacturing a memory further includes forming a word line covering the gate insulating layer and filling the second hole in the memory cell, and forming a selection line covering the gate insulating layer and filling the second hole in the selection cell.

[0024] In some other embodiments of the present disclosure, the method for manufacturing a memory further includes filling a first isolation layer in the first etching groove and the second etching groove before forming the memory cell, the selection cell, and the connection cell.

[0025] And the first etching hole group, the second etching hole group, and the third etching hole group are all located between the bit line and the first hole, and further include a second hole whose axis is perpendicular to the substrate. The second hole exposes the side walls of the bit line and the corresponding first electrode or the corresponding first electrode dummy structure on opposite sides in the first direction. Correspondingly, the steps of forming a memory cell based on the first etching hole group and forming a selection cell based on the second etching hole group include: Removing the third dielectric layer in the second hole; Sequentially forming an initial semiconductor layer and a gate insulating layer on the inner side wall of the second hole; Forming a word line covering the gate insulating layer and filling the second hole in the memory cell, and a selection line covering the gate insulating layer and filling the second hole in the selection cell; Removing the first isolation layer in the second etching groove; The steps include etching each first dielectric layer along a first direction until the sidewalls away from the gate insulating layer of the initial semiconductor layer are exposed, The steps include etching away an initial semiconductor layer between any adjacent second dielectric layers to form a plurality of semiconductor layers spaced apart along a direction perpendicular to the substrate, The process includes the step of forming a second separation layer that fills the gap between adjacent semiconductor layers, the removal region of the first dielectric layer, and the second etching groove, In some embodiments of the present disclosure, the same bit line corresponds to at least two connecting cells. The first etching hole group, the second etching hole group, and the third etching hole group each further include a second hole located between the bit line and the first hole, with its axis perpendicular to the substrate. The step of forming the bit line in the bit line housing groove is: The steps include forming an initial bit line in the bit line housing groove, After forming memory cells, selection cells, and connection cells, the third dielectric layer is removed from the second holes in any third etching hole group, and an initial bit line is cut along a direction parallel to the substrate based on the second hole to form a bit line, wherein the bit line includes a first portion facing the memory cells and selection cells, and a second portion facing the connection cells. The process includes the step of forming a separation structure in a second hole that communicates with the cutting region of the initial bit line.

[0026] In some embodiments of this disclosure, the end of the bit wire housing groove closest to the common bit wire housing groove communicates with the common bit wire housing groove. The common bit wire and the initial bit wire are formed simultaneously. Here, the second portion of the bit wire and the common bit wire are integrally structured.

[0027] In some embodiments of this disclosure, after forming the common bit line and the initial bit line, and before forming the memory cell, selection cell, and connection cell, the method for manufacturing the memory is as follows: The steps include etching the plurality of first dielectric layers and the plurality of second dielectric layers along a direction perpendicular to the substrate to form a third etching groove on the side away from the initial bit line of the common bit line, The steps include etching each first dielectric layer based on the third etching groove to form a plurality of insulating steps, A step of etching each second dielectric layer based on a third etching groove to form a plurality of conductive stair accommodating grooves, wherein the conductive stair accommodating grooves expose the side walls of the corresponding common bit lines, A step of forming conductive stairs coupled to a common bit wire within a conductive stairs housing groove, wherein each conductive stair and each insulating stair together constitute a stair structure, The method further includes the step of forming a covering layer that covers the staircase structure.

[0028] In other respects, some embodiments of the present disclosure further provide a memory comprising a common bit line, bit lines, dummy lines, selection lines, word lines, an access transistor, a capacitor, and a selection transistor, wherein the common bit line extends along a first direction parallel to the substrate. The bit lines are located on the first side of the common bit line and extend along a second direction parallel to the substrate. The second and first directions intersect. The dummy line, selection line, and word line are all located on the first side of the common bit line and on the same side of the bit lines and extend along a third direction perpendicular to the substrate, wherein the dummy line, selection line, and word line are sequentially arranged in the second direction and sequentially away from the common bit line, the access transistor is coupled to the word line and the bit line, the capacitor is located on the side of the access transistor away from the bit line and is coupled to the access transistor, and the selection transistor is coupled to the selection line, bit line, and common bit line.

[0029] In some embodiments of the present disclosure, the memory further includes a connecting electrode, which is located between a capacitor and a common bit line, where a select transistor is coupled to the common bit line via the connecting electrode.

[0030] Furthermore, in other respects, some embodiments of the present disclosure further provide electronic devices, which include the memory described in the above embodiments and a processor coupled to the memory.

[0031] The embodiments of this disclosure may have at least one of the following advantages.

[0032] In the embodiments of this disclosure, a plurality of cells (i.e., cell arrays) are provided on the same side along the second direction on which the bit line extends, and each of these plurality of cells consists of a plurality of memory cells arranged sequentially along a direction close to the common bit line, at least one selection cell, and at least one connection cell, and the selection transistor of the selection cell is coupled to the common bit line by the connection cell. In this way, the embodiments of this disclosure can effectively reduce or eliminate the etching loading effect during the manufacturing process of the cell array based on the distribution of each cell in the cell array, thereby effectively improving the manufacturing yield of the selection transistor and improving the manufacturing yield and performance of the memory and electronic devices.

[0033] Details of one or more embodiments of this disclosure are presented in the accompanying drawings and description below. Other features, purposes, and advantages of this disclosure will become apparent from the specification, drawings, and claims. [Brief explanation of the drawing]

[0034] [Figure 1] This is a schematic diagram of the local structure of the memory provided in several embodiments. [Figure 2] This is a schematic diagram of the positional distribution of bit lines, common bit lines, and cell arrays on the substrate, as provided in some embodiments. [Figure 3] Figure 1 is a schematic cross-sectional view of the memory along the BB line, perpendicular to the substrate. [Figure 4]This is another schematic cross-sectional view perpendicular to the substrate along the BB line of the memory shown in Figure 1. [Figure 5] This is a flowchart of a memory manufacturing method provided in several embodiments. [Figure 6] This is a schematic diagram of the structure after forming multiple first dielectric layers and multiple second dielectric layers as provided in some embodiments. [Figure 7] This is a schematic diagram of the structure after forming multiple etching hole groups, as provided in some embodiments. [Figure 8] This is a schematic diagram of the structure after filling with the third dielectric layer, as provided in some embodiments. [Figure 9] This is a schematic diagram of the structure after the common bit line and initial bit line have been formed, as provided in some embodiments. [Figure 10] This is a schematic diagram of the structure after the staircase structure has been formed, as provided in some embodiments. [Figure 11] This is a schematic diagram of the structure after forming the connecting cell, as provided in some embodiments. [Figure 12] This is a schematic diagram of the structure after forming the semiconductor layer, gate insulating layer, word line, and selection line, as provided in some embodiments. [Figure 13] This is a schematic diagram of the structure after forming the capacitors provided in some embodiments. [Figure 14] This is a schematic diagram of the structure after forming the bit lines and separation structure as provided in some embodiments. [Figure 15] This is a schematic diagram of the structure after forming another initial semiconductor layer, gate insulating layer, word line, and selection line, as provided in some embodiments. [Figure 16] This is a schematic diagram of the structure after forming another semiconductor layer and capacitor, as provided in some embodiments. [Figure 17] This is a schematic diagram of the structure after forming another bit line and separation structure as provided in some embodiments. [Modes for carrying out the invention]

[0035] To more clearly illustrate the embodiments of this disclosure or the technical solutions in the prior art, the drawings that may be used in the description of the embodiments or the prior art have been briefly introduced above. Obviously, the drawings in the following description are only a few embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these without any creative work.

[0036] To facilitate understanding of this disclosure, the disclosure will be described more comprehensively below with reference to the relevant drawings. The drawings illustrate preferred embodiments of this disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure more thorough and complete.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art in which this disclosure pertains. In this specification, terms used in the description of this disclosure are solely for the purpose of describing specific embodiments and are not intended to limit this disclosure.

[0038] While terms such as "first," "second," and "third" may be used to describe various elements, components, regions, layers, and / or parts, it should be understood that these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are simply used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, or part described below may be referred to as the second element, component, region, layer, or part.

[0039] It should be understood that when one element is considered to be "coupled" to another, it may be directly connected to the other element or connected through an intermediary element. Furthermore, in the following embodiments, "coupling" should be understood as "electrically connected," "communication connected," etc., when there is transmission of electrical signals or data between the connected objects.

[0040] Please understand that the singular forms "one," "one," and "the aforementioned / the said" may also include the plural form unless the context clearly indicates otherwise. Furthermore, please understand that terms such as "includes / including" or "having" identify the existence of the described feature, whole, step, operation, component, part, or combination thereof, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0041] Referring to Figures 1 and 2, some embodiments of the present disclosure provide a memory comprising a common bit line CBL, a bit line BL, and a cell array N. The common bit line CBL extends along a first direction (e.g., the Y direction) parallel to the substrate 1. The bit line BL is located on the first side of the common bit line CBL and extends along a second direction (e.g., the X direction) parallel to the substrate 1. The second direction (e.g., the X direction) and the first direction (e.g., the Y direction) intersect. The cell array N comprises a plurality of cells corresponding to the bit line BL, the plurality of cells located on the same side of the bit line BL and sequentially arranged along the second direction (e.g., the X direction). The plurality of cells comprises at least one connected cell U3, at least one selected cell U2 located on the side of the at least one connected cell U3 away from the common bit line CBL, and a plurality of memory cells U1 located on the side of the at least one selected cell U2 away from the common bit line CBL. Both memory cell U1 and selection cell U2 contain transistors coupled to the bit line BL. The transistor in memory cell U1 is the access transistor T1. The transistor in selection cell U2 is the selection transistor T2, which is coupled to the common bit line CBL via the connecting cell U3.

[0042] Exemplary, the common bit wire CBL and bit wire BL contain substantially the same material composition. In the embodiments of this disclosure, “substantially the same” means at least 85% or more identical.

[0043] For example, the cell array N may be arranged in a single layer, or the cell array N may be stacked in multiple layers along a third direction perpendicular to the substrate 1 (e.g., the Z direction) to form a three-dimensional memory.

[0044] In the embodiments of this disclosure, a plurality of cells (i.e., a cell array N) are provided on the same side of the bit line BL extending in a second direction (e.g., the X direction), sequentially arranged along the second direction (e.g., the X direction), and each of these plurality of cells consists of a plurality of memory cells U1, at least one selection cell U2, and at least one connection cell U3, sequentially arranged along the direction closest to the common bit line CBL, and the selection transistor T2 of the selection cell U2 is coupled to the common bit line CBL by the connection cell U3. In this way, the embodiments of this disclosure can effectively reduce or eliminate the etching loading effect during the manufacturing process of the cell array N by the distribution of each cell in the cell array N, thereby effectively improving the manufacturing yield of the selection transistor T2 and improving the manufacturing yield and performance of the memory and electronic devices.

[0045] In some embodiments of this disclosure, referring again to Figures 1 and 2, the memory cell U1 further includes a capacitor C. The capacitor C includes a first electrode 21 coupled to an access transistor T1, a second electrode 23 provided opposite the first electrode 21, and a dielectric layer 22 located between the first electrode 21 and the second electrode 23. Both the selection cell U2 and the connection cell U3 include a first electrode dummy structure 31. Here, each first electrode dummy structure 31 in the selection cell U2 and the connection cell U3 corresponding to the bit line BL can be connected to each other to form a connection electrode 9. The selection transistor T2 in the selection cell U2 is coupled to its first electrode dummy structure 31. The first electrode dummy structure 31 in the connection cell U3 that is close to the common bit line CBL is coupled to the common bit line CBL.

[0046] Figures 1 and 2 show examples where there are two selection cells U2 and two connection cells U3, respectively, but are not limited to this. For example, the number of selection cells U2 corresponding to the same bit line BL may be one, three, or more. Each selection transistor T2 in multiple selection cells U2 operates as a parallel transistor, improving the performance of the selection transistor T2 corresponding to any of the bit lines BL. Furthermore, Figure 2 schematically shows the relative positions of the bit line BL, common bit line CBL, memory cell U1, selection cell U2, and connection cell U3, and does not limit the specific installation locations, contour shapes, connection relationships, etc. of the bit line BL, common bit line CBL, memory cell U1, selection cell U2, and connection cell U3. Also, in Figure 2, the direction of current between the common bit line CBL and the bit line BL is indicated by a black arrow. That is, the current may start from the common bit line CBL, be transferred to the bit line BL via the connection cell U3 and selection cell U2 in sequence, and then be transferred to each memory cell U1 via the bit line BL.

[0047] In some embodiments of the present disclosure, as understood in conjunction with Figure 1, each cell in the cell array N includes a first hole whose axis is perpendicular to the substrate 1, and a first housing groove extending along a direction parallel to the substrate 1 and located on the side wall of the first hole. Here, the first electrode 21 and the first electrode dummy structure 31 are both conformally covered on the inner wall of the corresponding first housing groove. The dielectric layer 22 conformally covers the first electrode 21 and the side wall of the first hole. The second electrode 23 covers the dielectric layer 22 and fills the first housing groove and the first hole.

[0048] In some examples, as shown in Figure 1, both the selected cell U2 and the connected cell U3 further include a support electrode 32 that covers the first electrode dummy structure 31 and fills the first housing groove, and a first filling layer 33 that fills the first hole.

[0049] Exemplary, the connecting electrode 9 may further include each support electrode 32 that is in contact with the first electrode dummy structure 31 in the selected cell U2 and the connecting cell U3.

[0050] In several other examples, selectively, the first electrode dummy structure 31 in the selection cell U2 and the connection cell U3 may completely fill the first housing groove, and both the selection cell U2 and the connection cell U3 further include a first filling layer 33 that fills the first hole. Correspondingly, the connection electrode 9 may be configured to be connected only by the first electrode dummy structure 31 in the selection cell U2 and the connection cell U3.

[0051] Exemplary examples include, but are not limited to, a circular, elliptical, or rectangular hole. The first receiving groove surrounds the first hole and forms an annular groove.

[0052] Exemplary examples include, but are not limited to, a titanium nitride layer or a laminated structure of a titanium nitride layer and a tungsten layer.

[0053] Exemplary, the first electrode 21 and the first electrode dummy structure 31 contain substantially the same material composition.

[0054] For example, the first electrode 21 and the first electrode dummy structure 31 are formed simultaneously.

[0055] Exemplary, the support electrode 32 includes, but is not limited to, a polysilicon layer.

[0056] For example, the first packed layer 33 may be a single-layer structure or a multi-layer structure. The first packed layer 33 may be, for example, a multi-layer structure of silicon nitride and silicon oxide.

[0057] For example, the dielectric layer 22 is a high-K dielectric layer and includes, but is not limited to, a hafnium oxide layer. Here, K is the dielectric constant, and high-K means that the K value is greater than 3.9.

[0058] Exemplary, the second electrode 23 includes, but is not limited to, a polysilicon layer or a laminated structure of a titanium nitride layer and a polysilicon layer.

[0059] In some embodiments of the present disclosure, as understood in conjunction with Figures 1 and 3, each cell in the cell array N further includes a second hole located between the bit line BL and the first hole, with its axis perpendicular to the substrate 1. Here, both the memory cell U1 and the selection cell U2 further include a second housing groove extending along a direction parallel to the substrate 1 and located in the side wall of the second hole. The second housing groove exposes, on opposite sides in a first direction (e.g., the Y direction), the side wall of the bit line BL and the side wall of the corresponding first electrode 21 or the corresponding first electrode dummy structure 31, respectively. That is, the second housing groove of the memory cell U1 exposes the side wall of the corresponding first electrode 21, and the second housing groove of the selection cell U2 exposes the side wall of the corresponding first electrode dummy structure 31.

[0060] The access transistor T1 of memory cell U1 and the selection transistor T2 of selection cell U2 each include a semiconductor layer 41 conformally covering the inner wall of the corresponding second housing groove and a gate insulating layer 42 conformally covering the semiconductor layer 41 and the side wall of the second hole. Correspondingly, the memory further includes a word line WL covering the gate insulating layer 42 and filling the second hole in memory cell U1, and a selection line SL covering the gate insulating layer 42 and filling the second hole in selection cell U2. The connecting cell U3 further includes a second filling layer 34 filling the second hole.

[0061] Here, the second filling layer 34 that fills the second hole can also be considered as a dummy line DL. That is, the dummy line DL, the selection line SL, and the word line WL are arranged sequentially along the second direction (e.g., the X direction) and can be sequentially separated from the common bit line CBL.

[0062] For example, the materials for the word line WL and the selection line SL include, but are not limited to, indium tin oxide (ITO).

[0063] For example, the word line WL and the selection line SL contain approximately the same material composition.

[0064] For example, the second filling layer 34 may be an insulating material layer, such as an aluminum oxide layer, but is not limited to this.

[0065] For example, the diameters of the first hole H1 and the second hole H2 may be the same or different.

[0066] To elaborate, when understood in conjunction with Figures 1 and 4, in some other embodiments of the present disclosure, the second hole of each cell in the cell array N exposes, on opposite sides in a first direction (e.g., the Y direction), the sidewall of the bit line BL and the sidewall of the corresponding first electrode 21 or the corresponding first electrode dummy structure 31, respectively. Thus, both the access transistor T1 and the selection transistor T2 further include a semiconductor layer 41 and a gate insulating layer 42 formed on the inner wall of the second hole, so that the semiconductor layers 41 between adjacent access transistors T1 in a direction perpendicular to the substrate 1 (e.g., the Z direction) are insulated from each other, and the semiconductor layers 41 between adjacent selection transistors T2 in a direction perpendicular to the substrate 1 (e.g., the Z direction) are insulated from each other. Correspondingly, the memory further includes a word line WL covering the gate insulating layer 42 and filling the second hole in the memory cell U1, and a selection line SL covering the gate insulating layer 42 and filling the second hole in the selection cell U2. The connecting cell U3 further includes a second filling layer 34 (i.e., a dummy wire DL) which is filled into the second hole.

[0067] Exemplary, when understood in conjunction with Figures 1 and 4, there are multiple bit lines BL, and these multiple bit lines BL are insulated and arranged along a direction parallel to the substrate 1, and insulated and stacked along a direction perpendicular to the substrate 1. Here, along the direction parallel to the substrate 1, every two adjacent bit lines BL constitute one bit line group. Each cell corresponding to any one bit line BL within the bit line group is located on the same side as that bit line BL, away from another bit line BL.

[0068] Exemplary, two bit lines BL within the same bit line group may be composed of two lines on separate sides within an annular conductive layer. Correspondingly, the memory further includes a first isolation layer 61 (e.g., shown in Figure 3) or a second isolation layer 62 (e.g., shown in Figure 4) provided between two adjacent bit lines BL within the bit line group. Referring to Figure 4, in the example where a second isolation layer 62 is provided between two adjacent bit lines BL, the semiconductor layer 41 between adjacent access transistors T1 in a direction perpendicular to the substrate 1 (e.g., the Z direction), and the semiconductor layer 41 between adjacent selection transistors T2 in a direction perpendicular to the substrate 1 (e.g., the Z direction) may be insulated from each other by an extension of the second isolation layer 62 in a direction parallel to the substrate 1.

[0069] For illustrative purposes, and continuing to refer to Figure 1, the common bit line CBL may be an annular conductive layer. Correspondingly, the memory further includes a first isolation layer 61 provided in the annular region of the common bit line CBL.

[0070] Exemplary, the first separation layer 61 includes, but is not limited to, a laminated structure of a silicon nitride layer 611 and an aluminum oxide layer 612.

[0071] Exemplary, the second separation layer 62 includes, but is not limited to, a laminated structure of a silicon nitride layer and a silicon oxide layer.

[0072] Exemplary examples include, but are not limited to, a laminated structure of titanium nitride layers and tungsten metal layers for common bit lines CBL and bit lines BL.

[0073] In some embodiments of this disclosure, referring again to Figure 1, the bit line BL includes a first portion BLa facing memory cell U1 and selection cell U2, and a second portion BLb facing connection cell U3. Here, the second portion BLb and the common bit line CBL may be a single structure or may be spaced apart from each other. The memory further includes a separation structure 5 located between the first portion BLa and the second portion BLa.

[0074] In some embodiments of this disclosure, as understood in conjunction with Figure 1, the same bit line BL corresponds to at least two connecting cells U1. Here, the separation structure 5 includes a first separation section located between a first portion BLa and a second portion BLb, and a second separation section including at least a portion of the second packed layer 34 (i.e., dummy line DL) and connected to at least the first separation section, for example, the second separation section may extend to the side wall of the first electrode dummy structure 31 within the connecting cell U3. Figure 1 shows only a schematic representation of the entire separation structure 5 and does not distinguish between the first and second separation sections.

[0075] In some embodiments of this disclosure, as understood in conjunction with Figure 1, there are multiple common bit line CBLs, and the multiple common bit line CBLs are insulated and stacked along a direction perpendicular to the substrate 1 (e.g., the Z direction). The memory further includes a stepped structure S located on the side of the common bit line CBL away from the bit line BL. The stepped structure S includes multiple conductive steps coupled to each common bit line CBL.

[0076] Exemplary, the staircase structure S further includes multiple insulating stairs that are alternately stacked with multiple conductive stairs.

[0077] Here, it can be understood that the staircase structure S may be a single-sided staircase or a double-sided staircase. In the example where the staircase structure S is a double-sided staircase, the number of conductive stairs on each side of the staircase may be the same or different. Exemplarily, in the example where the staircase structure S is a double-sided staircase, the conductive stairs on one side of the staircase are coupled to the common bit line CBL of the odd-numbered layers, and the conductive stairs on the other side of the staircase are coupled to the common bit line CBL of the even-numbered layers.

[0078] Exemplary, the memory further includes an isolation barrier 81 located on the side of the common bit line CBL away from the bit line BL. The region enclosed by the isolation barrier 81 and the common bit line CBL is the installation region of the stepped structure S. The isolation barrier 81 may be, for example, a silicon oxide barrier.

[0079] Exemplary, the memory further includes a coating layer 82 that covers each step in the stepped structure S. The coating layer 82 may be, for example, a stacked structure of a first sublayer 821 and a second sublayer 822, where the first sublayer 821 includes, but is not limited to, an aluminum oxide layer, and the second sublayer 822 includes, but is not limited to, a silicon oxide layer.

[0080] Of particular note, when understood in conjunction with Figure 1, in some embodiments of this disclosure, a plurality of first dielectric layers L1 and a plurality of second dielectric layers L2 may be alternately stacked on the substrate 1. Here, the first dielectric layer L1 includes, but is not limited to, a silicon oxide layer, and the second dielectric layer L2 includes, but is not limited to, a silicon nitride layer. Correspondingly, each component device of the memory may be formed in the corresponding holes or grooves by first etching each first dielectric layer L1 and each second dielectric layer L2 to form holes or grooves.

[0081] Some embodiments of this disclosure further provide a method for manufacturing a memory and can be used to manufacture the memory described in some embodiments above.

[0082] The aforementioned memory possesses all the technical advantages, and this manufacturing method also incorporates those advantages.

[0083] Referring to Figure 5, the manufacturing method includes steps S100 to S800.

[0084] In S100, multiple first dielectric layers and multiple second dielectric layers are alternately stacked on the substrate.

[0085] In step S200, the plurality of first dielectric layers and the plurality of second dielectric layers are etched along a direction perpendicular to the substrate to form a first etching groove extending along a first direction parallel to the substrate, and at least one second etching groove located on one side of the first etching groove and extending along a second direction parallel to the substrate. The second direction and the first direction intersect.

[0086] In S300, each second dielectric layer is etched along a direction parallel to the substrate based on the first etching groove to form a plurality of common bit line accommodating grooves. Common bit lines are formed within the common bit line accommodating grooves.

[0087] In step S400, each second dielectric layer is etched along a direction parallel to the substrate based on the second etching groove to form multiple bit line accommodating grooves. Bit lines are formed within the bit line accommodating grooves.

[0088] In S500, the plurality of first dielectric layers and the plurality of second dielectric layers are etched along a direction perpendicular to the substrate to form an etching hole array, the etching hole array includes a plurality of etching hole groups that correspond to the same side of the bit line and are sequentially arranged in a second direction. The plurality of etching hole groups include a plurality of first etching hole groups distributed at intervals in the second direction, at least one second etching hole group located on the side closer to the common bit line of the plurality of first etching hole groups, and at least one third etching hole group located on the side closer to the common bit line of the at least one second etching hole group.

[0089] In S600, a memory cell is formed based on a first group of etched holes, and the memory cell includes an access transistor coupled to the corresponding bit line.

[0090] In S700, a selection cell is formed based on a second etching hole group, and the selection cell includes a selection transistor coupled to the corresponding bit line.

[0091] In S800, a connection cell is formed based on the third etching hole group. Select transistors corresponding to the same bit line are coupled to the common bit line by the corresponding connection cell.

[0092] In some embodiments of the present disclosure, the etching hole array in step S500 may be formed before the common bit line etching groove and bit line etching groove are formed. The first etching hole group, the second etching hole group, and the third etching hole group each include a first hole whose axis is perpendicular to the substrate.

[0093] Correspondingly, the memory manufacturing method further includes S510 to S530.

[0094] In S510, a third dielectric layer is filled into each etching hole of the etching hole array.

[0095] In S520, after forming a common bit line, the third dielectric layer is removed from each first hole.

[0096] In step S530, the second dielectric layer is etched along a direction parallel to the substrate based on the first hole to form the first housing groove.

[0097] Correspondingly, the step of forming a memory cell based on a first etching hole group in step S600 includes the steps of forming a first electrode conformally covering the inner wall of the corresponding first housing groove, forming a dielectric layer conformally covering the side walls of the first electrode and the first hole, and forming a second electrode that covers the dielectric layer and fills the first housing groove and the first hole.

[0098] The step of forming a selected cell based on a second etching hole group in step S700, and the step of forming a connected cell based on a third etching hole group in step S800, both include step S710.

[0099] In S710, a first electrode dummy structure is formed which conformally covers the inner wall of the corresponding first housing groove.

[0100] As described above, each first electrode dummy structure in the selection cell and connection cell corresponding to the same bit line is interconnected. A selection transistor in the same selection cell is coupled to its first electrode dummy structure. A first electrode dummy structure in a connection cell close to the common bit line is coupled to the common bit line.

[0101] In some embodiments of the present disclosure, the step of forming a selected cell based on a second etching hole group in step S700, and the step of forming a connected cell based on a third etching hole group in step S800, both further include steps S720 and S730.

[0102] In S720, a support electrode is formed that covers the first electrode dummy structure and fills the first housing groove.

[0103] In S730, a first filling layer is formed to fill the first hole.

[0104] In some embodiments of the present disclosure, the first etching hole group, the second etching hole group, and the third etching hole group each further include a second hole located between the bit line and the first hole, with its axis perpendicular to the substrate.

[0105] Correspondingly, the step of forming a memory cell based on the first etching hole group in step S600, and the step of forming a selected cell based on the second etching hole group in step S700, both include the following steps S610 to S640.

[0106] In S610, the third dielectric layer in the second hole is removed.

[0107] In S620, the second dielectric layer is etched along a direction parallel to the substrate based on the second hole to form a second housing groove, the second housing groove exposing the sidewalls of the bit line and the corresponding first electrode or the corresponding first electrode dummy structure on opposite sides in the first direction.

[0108] In S630, a semiconductor layer is formed that conformally covers the inner wall of the corresponding second housing groove.

[0109] In S640, a gate insulating layer is formed which conformally covers the semiconductor layer and the sidewall of the second hole.

[0110] Correspondingly, the method for manufacturing the memory further includes step S650.

[0111] In S650, a word line is formed that covers the gate insulating layer and fills the second hole in the memory cell, and a selection line is formed that covers the gate insulating layer and fills the second hole in the selection cell.

[0112] In some other embodiments of the present disclosure, the method for manufacturing a memory further includes filling a first separation layer into a first etching groove and a second etching groove before forming a memory cell, a selection cell, and a connection cell.

[0113] Furthermore, the first etching hole group, the second etching hole group, and the third etching hole group each further include a second hole located between the bit line and the first hole, with its axis perpendicular to the substrate. The second hole exposes, on opposite sides in the first direction, the sidewall of the bit line and the sidewall of the corresponding first electrode or the corresponding first electrode dummy structure. Correspondingly, the step of forming a memory cell based on the first etching hole group in step S600, and the step of forming a selected cell based on the second etching hole group in step S700, each include the following steps S610' to S670'.

[0114] In S610', the third dielectric layer in the second hole is removed.

[0115] In S620', an initial semiconductor layer and a gate insulating layer are sequentially formed on the inner wall of the second hole.

[0116] In S630', a word line is formed that covers the gate insulating layer and fills the second hole in the memory cell, and a selection line is formed that covers the gate insulating layer and fills the second hole in the selection cell.

[0117] In step S640', the first separation layer in the second etching groove is removed.

[0118] In S650', each first dielectric layer is etched along the first direction until the sidewalls away from the gate insulating layer of the initial semiconductor layer are exposed.

[0119] In S660', the initial semiconductor layer between any adjacent second dielectric layers is etched away to form a plurality of semiconductor layers spaced apart along a direction perpendicular to the substrate.

[0120] In S670', a second separation layer is formed to fill the gap between adjacent semiconductor layers, the removal region of the first dielectric layer, and the second etching groove.

[0121] In some embodiments of this disclosure, the same bit line corresponds to at least two connection cells. The step of forming the bit line in the bit line housing groove in step S400 includes the following steps S410 to S430.

[0122] In S410, an initial bit line is formed within the bit line housing groove.

[0123] In S420, after forming the memory cell, selection cell, and connection cell, the third dielectric layer in the second hole in any of the third etching hole groups is removed, and an initial bit line is cut along a direction parallel to the substrate based on the second hole to form a bit line, where the bit line includes a first portion facing the memory cell and selection cell, and a second portion facing the connection cell.

[0124] In S430, a separation structure is formed in the cutting region of the initial bit line and in the second hole that communicates with it.

[0125] In some embodiments of this disclosure, the end of the bit wire housing groove closest to the common bit wire housing groove communicates with the common bit wire housing groove. The common bit wire and the initial bit wire are formed simultaneously. Here, the second portion of the bit wire and the common bit wire may be an integral structure.

[0126] In some embodiments of this disclosure, after forming the common bit line and the initial bit line, and before forming the memory cell, selection cell, and connection cell, the method for manufacturing the memory further includes the following steps S401 to S405.

[0127] In S401, the plurality of first dielectric layers and the plurality of second dielectric layers are etched along a direction perpendicular to the substrate, and a third etching groove is formed on the side away from the initial bit line of the common bit line.

[0128] In S402, each first dielectric layer is etched based on the third etching groove to form multiple insulating steps.

[0129] In S403, each second dielectric layer is etched based on the third etching groove to form a plurality of conductive stair accommodating grooves, and the conductive stair accommodating grooves expose the side walls of the corresponding common bit lines.

[0130] In S404, conductive stairs are formed within the conductive stair housing groove, which are coupled to a common bit wire, and each conductive stair and each insulating stair together constitute a staircase structure.

[0131] In S405, a covering layer is formed to cover the staircase structure.

[0132] In the embodiments of this disclosure, unless otherwise expressly described herein, there are no strict order restrictions on the execution of the steps in the above method, and these steps do not necessarily have to be performed in the order described, but may be performed in other ways. Furthermore, at least some of the steps may include multiple substeps or stages, and these substeps or stages do not necessarily have to be completed at the same time, but may be performed at different times, and the order in which these substeps or stages are performed does not necessarily have to be sequential, but may be performed alternately or in rotation with at least some of the other steps or substeps or stages of other steps.

[0133] To more clearly explain the memory manufacturing methods described in some of the above embodiments, the following embodiments will detail some memory manufacturing methods in combination with Figures 6 to 17.

[0134] In step S100, referring to Figure 6, a plurality of first dielectric layers L1 and a plurality of second dielectric layers L2 are alternately stacked on the substrate 1.

[0135] For example, the first dielectric layer L1 includes, but is not limited to, a silicon oxide layer. The second dielectric layer L2 includes, but is not limited to, a silicon nitride layer.

[0136] Exemplary, the substrate 1 can be constructed using semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate 1 may have a single-layer structure or a multilayer structure. For example, the substrate 1 may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or another III / V or II / VI semiconductor substrate. Alternatively, for example, the substrate 1 may be a layered substrate such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator.

[0137] For example, the number of layers of the first dielectric layer L1 and the second dielectric layer L2 can be selected and set as required. Furthermore, the alternating stacking of the first dielectric layer L1 and the second dielectric layer L2 may begin and end with the first dielectric layer L1. This is described in detail as an example in the following embodiments of this disclosure, but is not limited thereto; for example, it may also begin with the second dielectric layer L2 and end with the first dielectric layer L1.

[0138] Exemplary examples include, but are not limited to, chemical vapor deposition (CVD) processes for forming the first dielectric layer L1 and the second dielectric layer L2.

[0139] In step S500, referring to Figure 7, each first dielectric layer L1 and each second dielectric layer L2 are etched along a direction perpendicular to the substrate (e.g., the Z direction) to form an etching hole array. The etching hole array includes a plurality of etching hole groups that correspond to the same side of the bit line BL and are sequentially arranged along a second direction (e.g., the X direction). The plurality of etching hole groups includes a plurality of first etching hole groups M1 distributed at intervals in the second direction (e.g., the X direction), at least one second etching hole group M2 located on the side of the plurality of first etching hole groups M1 closer to the common bit line CBL, and at least one third etching hole group M3 located on the side of the at least one second etching hole group M2 closer to the common bit line CBL.

[0140] Here, the first etching hole group M1 may be used for manufacturing memory cells, the second etching hole group M2 may be used for manufacturing selected cells, and the third etching hole group M3 may be used for manufacturing connected cells.

[0141] When forming the etching hole array, it can be understood that the bit line BL and common bit line CBL have not yet been formed. In Figure 7, the areas where the bit line BL and common bit line CBL are planned to be formed are shown to clearly illustrate the distribution location of each etching hole.

[0142] For example, the first etching hole group M1, the second etching hole group M2, and the third etching hole group M3 correspond to the same side on which the bit line BL extends along the second direction (e.g., the X direction), and are sequentially distributed in the direction closer to the common bit line CBL along the second direction (e.g., the X direction).

[0143] For example, the first etching hole group M1, the second etching hole group M2, and the third etching hole group M3 each include a first hole H1 whose axis is perpendicular to the substrate, and a second hole H2 located between the bit line BL and the first hole H1, whose axis is perpendicular to the substrate 1.

[0144] For example, the diameters of the first hole H1 and the second hole H2 may be the same or different.

[0145] For example, the spaces between adjacent third etching hole groups M3 and adjacent second etching hole groups M2 along a second direction (e.g., the X direction) may be spaced without any spacing, or only with relatively small spacing. For instance, the spacing between adjacent third etching hole groups M3 and adjacent second etching hole groups M2 along a second direction (e.g., the X direction) may be smaller than the spacing between adjacent first etching hole groups M1 along a second direction (e.g., the X direction).

[0146] In step S510, referring to Figure 8, the third dielectric layer L3 is filled into each etching hole of the etching hole array.

[0147] For example, the third dielectric layer L3 is made of a different material than the first dielectric layer L1 and the second dielectric layer L2. For instance, the third dielectric layer L3 includes, but is not limited to, an aluminum oxide layer.

[0148] In step S200, as understood in conjunction with Figure 9, each first dielectric layer L1 and each second dielectric layer L2 are etched along a direction perpendicular to the substrate 1 (e.g., the Z direction) to form a first etching groove extending along a first direction parallel to the substrate 1 (e.g., the Y direction), and at least one second etching groove located on one side of the first etching groove and extending along a second direction parallel to the substrate 1 (e.g., the X direction). Here, the second direction (e.g., the X direction) and the first direction (e.g., the Y direction) intersect, for example, orthogonal.

[0149] Although the first and second etching grooves are not shown in Figure 9, the first etching groove can be understood as the ring-shaped region of the subsequently formed common bit line CBL, and the second etching groove can be understood as the spacing region between two subsequently formed adjacent bit lines BL. Furthermore, the first and second etching grooves may penetrate each first dielectric layer L1 and each second dielectric layer L2, exposing the surface of the substrate 1.

[0150] In steps S300 and S400, as understood in conjunction with Figure 9, each second dielectric layer L2 may be etched along a direction parallel to the substrate 1 based on the first etching groove to form a plurality of common bit line accommodating grooves, and a common bit line CBL may be formed within the common bit line accommodating grooves. Alternatively, each second dielectric layer L2 may be etched along a direction parallel to the substrate 1 based on the second etching groove to form a plurality of bit line accommodating grooves, and a bit line BL may be formed within the bit line accommodating grooves.

[0151] Here, the coupling relationship between the initial bit line BLA and the common bit line CBL is matched, and it can be understood that the end of the bit line housing groove closest to the common bit line housing groove may communicate with the common bit line housing groove, or it may be provided at a distance.

[0152] In some embodiments, the end of the bit wire housing groove closest to the common bit wire housing groove communicates with the common bit wire housing groove. The bit wire BL can be obtained by first forming an initial bit wire BLA in the bit wire housing groove (for example, as shown in Figure 9), and then cutting the initial bit wire BLA (for example, as shown in Figure 14).

[0153] For example, the first etching groove and the second etching groove can be formed using a dry etching process. The bit line accommodating groove and the common bit line accommodating groove can be formed using a wet etching process.

[0154] For example, the common bit line housing groove is annular. The bit line housing grooves corresponding to two adjacent initial bit lines BLA may be interconnected and also annular.

[0155] For example, the initial bit line BLA and the common bit line CBL may be formed simultaneously, and a single-layer conductive layer or a multilayer conductive layer may be used. For instance, both the initial bit line BLA and the common bit line CBL have a multilayer structure of a titanium nitride layer 71 and a tungsten metal layer 72.

[0156] For illustrative purposes, continuing with Figure 9, the first separation layer 61 is filled into the first etching groove and the second etching groove before the memory cell U1, the selection cell U2, and the connection cell U3 are formed.

[0157] For example, the first isolation layer 61 may be a single-layer insulating layer or a multi-layer insulating layer. For instance, the first isolation layer 61 may include, but is not limited to, a lamination of a silicon nitride layer 611 and an aluminum oxide layer 612.

[0158] In some embodiments of the present disclosure, referring again to Figure 9, the method for manufacturing the memory further includes forming an isolation barrier 81 on the side of the common bit line CBL away from the bit line BL, and forming a stepped structure S in the region enclosed by the isolation barrier 81 and the common bit line CBL. The isolation barrier 81 may be, for example, a silicon oxide barrier.

[0159] For illustrative purposes, referring to Figure 10, after forming the common bit line CBL and the initial bit line BLA, and before forming the memory cell U1, the selected cell U2, and the connecting cell U3, the method for manufacturing the memory further includes the following steps S401 to S405.

[0160] In step S401, each first dielectric layer L1 and each second dielectric layer L2 are etched along a direction perpendicular to the substrate 1 (for example, the Z direction) to form a third etching groove on the side away from the initial bit line BLA of the common bit line CBL.

[0161] For example, the third etching groove can be formed using a dry etching process.

[0162] In step S402, each first dielectric layer L1 is etched based on the third etching groove to form a plurality of insulating steps S1.

[0163] In step S403, each second dielectric layer L2 is etched based on the third etching groove to form a plurality of conductive stair accommodating grooves, the conductive stair accommodating grooves exposing the side walls of the corresponding common bit lines CBL.

[0164] For example, conductive stairwell grooves can be formed using a wet etching process.

[0165] In step S404, conductive stairs S2 are formed within the conductive stairs housing groove, which are coupled to a common bit wire CBL. Each conductive stair S2 and each insulating stair S1 together constitute a staircase structure S.

[0166] For example, the conductive staircase S2 includes, but is not limited to, a tungsten metal layer.

[0167] In step S405, a covering layer 82 is formed to cover the staircase structure S.

[0168] For example, the coating layer 82 may be a laminated structure of a first sublayer 821 and a second sublayer 822, where the first sublayer 821 includes, but is not limited to, an aluminum oxide layer, and the second sublayer 822 includes, but is not limited to, a silicon oxide layer.

[0169] While the above embodiment provides an illustrative method for forming one type of staircase structure S, the method for forming the staircase structure S is not limited thereto, and any other method that can be used to manufacture and obtain a staircase structure is also applicable to this disclosure.

[0170] In step S520, as understood in conjunction with Figure 11, after forming the common bit line CBL, the third dielectric layer L3 is removed from each first hole H1.

[0171] For example, the third dielectric layer L3 within the first pore H1 can be removed using a dry etching process.

[0172] In step S530, as understood in conjunction with Figure 11, the second dielectric layer L2 is etched along a direction parallel to the substrate 1 based on the first hole H1 to form the first housing groove.

[0173] For example, the first accommodating groove can be formed using a wet etching process.

[0174] In steps S600, S700, and S800, when understood in conjunction with Figures 11 to 14, memory cell U1 is formed based on the first etching hole group M1, selected cell U2 is formed based on the second etching hole group M2, and connected cell U3 is formed based on the third etching hole group M3.

[0175] Here, the structures of the memory cell U1, selection cell U2, and connection cell U3 can be found in the relevant descriptions in some of the embodiments described above and will not be detailed here. The manufacturing processes of the memory cell U1, selection cell U2, and connection cell U3 are interactive; for example, the access transistor T1 of the memory cell U1 and the selection transistor T2 of the selection cell U2 may be manufactured simultaneously.

[0176] Exemplary, as shown in Figure 11, in step S710, after forming the first housing groove, the first electrode 21 may conformally cover the inner wall of the first housing groove corresponding to the first etching hole group M1, and at the same time, the first electrode dummy structure 31 may conformally cover the inner wall of the first housing groove corresponding to the second etching hole group M2 and the third etching hole group M3. Here, each first electrode dummy structure 31 in the selected cell U2 and the connecting cell U3 corresponding to the same bit line BL is connected to each other to form a connecting electrode 9. The first electrode dummy structure 31 in the connecting cell U3 that is close to the common bit line CBL is coupled to the common bit line CBL.

[0177] For example, the first electrode 21 and the first electrode dummy structure 31 can be formed using the same material and an atomic layer deposition (ALD) process.

[0178] In step S720, a support electrode 32 is formed that covers the first electrode dummy structure 31 and fills the first housing grooves corresponding to the second etching hole group M2 and the third etching hole group M3. Alternatively, a support electrode 32 that covers the first electrode 21 and fills the first housing grooves corresponding to the first etching hole group M1 can be formed simultaneously.

[0179] Exemplary, the support electrode 32 includes, but is not limited to, a polysilicon layer.

[0180] In step S730, a first filling layer 33 is formed to fill each of the first holes H1.

[0181] For example, the first packed layer 33 has a laminated structure of a silicon nitride layer and a silicon oxide layer.

[0182] In some other embodiments, the first electrode dummy structure 31 formed in the selection cell U2 and the connection cell U3 may completely fill the first housing groove. Correspondingly, forming the selection cell U2 and the connection cell U3 each further includes forming a first filling layer 33 that fills the first hole. The connection electrode 9 may be formed solely by the connection of the first electrode dummy structure 31 in the selection cell U2 and the connection cell U3.

[0183] To elaborate, the hole diameter size of the second hole H2 within the etching hole group is matched, and the access transistor T1 of the memory cell U1 and the selection transistor T2 of the selection cell U2 may have multiple possible embodiments.

[0184] In some possible embodiments, when understood in combination with Figures 3, 12, and 13, the step of forming memory cell U1 based on a first etching hole group M1 in step S600, and the step of forming selected cell U2 based on a second etching hole group M2 in step S700, both include the following steps S610 to S640.

[0185] In step S610, the third dielectric layer L3 in the second holes H2 within each first etching hole group M1 and each second etching hole group M2 can be removed, for example, using a dry or wet etching process.

[0186] In this case, the third dielectric layer L3 in the second hole H2 within the third etching hole group M3 constitutes the second packing layer 34 in the second hole H2 within the connecting cell U3, and can also be considered as a dummy wire DL.

[0187] In step S620, the second dielectric layer L2 is etched along a direction parallel to the substrate 1 based on the second holes H2 in each first etching hole group M1 and each second etching hole group M2 to form second housing grooves. The second housing groove corresponding to the first etching hole group M1 exposes the sidewalls of the bit line BL and the corresponding sidewalls of the first electrode 21 on opposing sides in the first direction (e.g., the Y direction). The second housing groove corresponding to the second etching hole group M2 exposes the sidewalls of the bit line BL and the corresponding sidewalls of the first electrode dummy structure 31 on opposing sides in the first direction (e.g., the Y direction).

[0188] For example, the second accommodating groove can be formed using a wet etching process.

[0189] In step S630, a semiconductor layer 41 is formed which conformally covers the inner wall of the corresponding second housing groove. Here, the semiconductor layer 41 of the access transistor T1 in the same memory cell U1 is in contact with its first electrode 21. The semiconductor layer 41 of the selection transistor T2 in the same selection cell U2 is in contact with its first electrode dummy structure 31.

[0190] For example, the semiconductor layer 41 may include a metal oxide layer, such as an indium gallium zinc oxide (IGZO) layer, but is not limited thereto.

[0191] For example, the semiconductor layer 41 can be formed using an atomic layer deposition process.

[0192] In step S640, a gate insulating layer 42 is formed which conformally covers the semiconductor layer 41 and the sidewall of the second hole H2.

[0193] In step S650, a word line WL is formed that covers the gate insulating layer 42 and fills the second hole H2 in the memory cell U1, and a selection line SL is formed that covers the gate insulating layer 42 and fills the second hole H2 in the selection cell U2.

[0194] For example, the word line WL and the selection line SL are formed simultaneously using the same material, for instance, ITO.

[0195] For example, referring to Figure 13, after forming the word line WL and the selection line SL, the first packing layer 33 in the first hole H1 within the first etching hole group M1 and the support electrode 32 in the corresponding first housing groove may be removed to expose the first electrode 21. Subsequently, a dielectric layer 22 conformally covering the first electrode 21 and the side walls of the first hole H1, and a second electrode 23 covering the dielectric layer 22 and filling the first housing groove and the first hole H1 are formed, thereby manufacturing and obtaining a capacitor C.

[0196] For illustrative purposes, referring to Figure 14, the same bit line BL corresponds to at least two connection cells U3. Forming the bit line BL in the bit line housing groove in step S400 includes the following steps S410 to S430.

[0197] In step S410, an initial bit line BLA is formed in the bit line housing groove, as shown in Figures 9 to 13.

[0198] In step S420, as shown in Figure 14, after forming the memory cell U1, the selection cell U2, and the connection cell U3, the third dielectric layer L3 (i.e., the second packed layer 34) in the second hole H2 within any of the third etching hole groups M3 is removed, and the initial bit line BLA is etched and cut along the direction parallel to the substrate 1 based on the second hole H2 to form the bit line BL. Here, the bit line BL includes a first portion BLa facing the memory cell U1 and the selection cell U2, and a second portion BLb facing the connection cell U3.

[0199] For example, the second part BLb of the bit line BL and the common bit line CBL are a single integrated structure.

[0200] In step S430, as shown in Figure 14, a separation structure 5 is formed in the cutting region of the initial bit line BLA and in the second hole H2 that communicates with it.

[0201] Exemplary, the separation structure 5 is formed using an insulating material and includes, but is not limited to, a silicon oxide layer.

[0202] In several other possible embodiments, as understood in combination with Figures 4, 15, and 16, the second hole H2 exposes, on opposite sides in the first direction (e.g., the Y direction), the sidewalls of the bit wire BL and the corresponding first electrode 21 or the corresponding first electrode dummy structure 31, respectively.

[0203] Correspondingly, forming memory cell U1 based on the first etching hole group M1 in step S600 and forming selected cell U2 based on the second etching hole group M2 in step S700 may both include the following steps S610' to S670'.

[0204] In step S610', the third dielectric layer L3 in the second hole H2 within each first etching hole group M1 and each second etching hole group M2 can be removed, for example, using a dry or wet etching process.

[0205] In step S620', an initial semiconductor layer 41A and a gate insulating layer 42 are sequentially formed on the inner walls of the second holes H2 in each first etching hole group M1 and each second etching hole group M2.

[0206] In step S630', a word line WL is formed that covers the gate insulating layer 42 and fills the second hole H2 in the memory cell U1, and a selection line SL is formed that covers the gate insulating layer 42 and fills the second hole H2 in the selection cell U2.

[0207] In step S640', the first separation layer 61 in the second etching groove is removed.

[0208] In step S650', each first dielectric layer L1 is etched along a first direction (e.g., the Y direction) until the sidewalls away from the gate insulating layer 42 of the initial semiconductor layer 41A are exposed.

[0209] In step S660', the initial semiconductor layer 41A between any adjacent second dielectric layer L2 is etched away to form a plurality of semiconductor layers 41 spaced apart along a direction perpendicular to the substrate 1 (e.g., the Z direction).

[0210] In step S670', a second separation layer 62 is formed to fill the gaps between adjacent semiconductor layers 41, the removal region of the first dielectric layer L1, and the second etching groove.

[0211] Exemplary, the second separation layer 62 includes, but is not limited to, a laminated structure of a silicon nitride layer and a silicon oxide layer.

[0212] As described above, the semiconductor layer 41 of an access transistor T1 within the same memory cell U1 is in contact with its first electrode 21, and the semiconductor layers 41 of adjacent access transistors T1 in a direction perpendicular to the substrate 1 (e.g., the Z direction) are insulated from each other by the extended portion of the second isolation layer 62 in a direction parallel to the substrate 1.

[0213] The semiconductor layer 41 of a selected transistor T2 within the same selected cell U2 is in contact with its first electrode dummy structure 31, and the semiconductor layers 41 of adjacent selected transistors T2 in a direction perpendicular to the substrate 1 (e.g., the Z direction) are insulated from each other by the extended portion of the second isolation layer 62 in a direction parallel to the substrate 1.

[0214] For example, referring to Figure 16, after forming the word line WL and the selection line SL, the first packing layer 33 in the first hole H1 within the first etching hole group M1 and the support electrode 32 in the corresponding first housing groove may be removed to expose the first electrode 21. Subsequently, a dielectric layer 22 conformally covering the first electrode 21 and the side walls of the first hole H1, and a second electrode 23 covering the dielectric layer 22 and filling the first housing groove and the first hole H1 are formed, thereby manufacturing and obtaining a capacitor C.

[0215] For illustrative purposes, referring to Figure 17, the same bit line BL corresponds to at least two connection cells U3. Forming the bit line BL in the bit line housing groove in step S400 includes the following steps S410 to S430.

[0216] In step S410, an initial bit line BLA is formed in the bit line housing groove, as shown in Figures 9 to 13.

[0217] In step S420, as shown in Figure 17, after forming the memory cell U1, the selection cell U2, and the connection cell U3, the third dielectric layer L3 (i.e., the second packed layer 34) in the second hole H2 within any of the third etching hole groups M3 is removed, and the initial bit line BLA is etched and cut along the direction parallel to the substrate 1 based on the second hole H2 to form the bit line BL. Here, the bit line BL includes a first portion BLa facing the memory cell U1 and the selection cell U2, and a second portion BLb facing the connection cell U3.

[0218] For example, the second part BLb of the bit line BL and the common bit line CBL are a single integrated structure.

[0219] In step S430, as shown in Figure 17, a separation structure 5 is formed in the cutting region of the initial bit line BLA and in the second hole H2 that communicates with it.

[0220] Referring to Figures 14 and 17, some embodiments of the present disclosure further provide a memory comprising a common bit line CBL, a bit line BL, a dummy line DL, a selection line SL, a word line WL, an access transistor T1, a capacitor C, and a selection transistor T2. The common bit line CBL extends along a first direction (e.g., the Y direction) parallel to the substrate 1. The bit line BL is located on the first side of the common bit line CBL and extends along a second direction (e.g., the X direction) parallel to the substrate 1. The second direction (e.g., the X direction) and the first direction (e.g., the Y direction) intersect, for example, orthogonal.

[0221] Continuing to refer to Figures 14 and 17, the dummy line DL, the selection line SL, and the word line WL are all located on the first side of the common bit line CBL, on the same side of the bit line BL, and extend along a third direction (e.g., the Z direction) perpendicular to the substrate 1. Here, the dummy line DL, the selection line SL, and the word line WL are sequentially arranged along a second direction (e.g., the X direction) and sequentially move away from the common bit line CBL. The access transistor T1 is coupled to the word line WL and the bit line BL. The capacitor C is located on the side of the access transistor T1 away from the bit line BL and is coupled to the access transistor T1. The selection transistor T2 is coupled to the selection line SL, the bit line BL, and the common bit line CBL.

[0222] For example, the access transistor T1 is provided surrounding the word line WL. The selection transistor T2 is provided surrounding the selection line SL.

[0223] For example, the word wire WL and the selection wire SL are conductive wires and can be formed using, for example, ITO. The dummy wire DL is an insulating wire and can be formed using, for example, a high-K dielectric material and can be formed using, for example, aluminum oxide.

[0224] Exemplary, the orthographic projection shapes of the word lines WL, selection lines SL, and dummy lines DL onto substrate 1 are the same or similar. At least one dummy line DL, at least one selection line SL, and multiple word lines WL are arranged in a column along a second direction (e.g., the X direction) away from the common bit line CBL.

[0225] Furthermore, the structures of the access transistor T1, selection transistor T2, capacitor C, bit line BL, common bit line CBL, and other constituent film layers in the memory can all be found in the relevant descriptions in some of the embodiments described above and will not be detailed here.

[0226] This memory possesses all of the technical advantages of the aforementioned memory. In some embodiments of this disclosure, referring again to Figures 14 and 17, the memory further includes a connection electrode 9. The connection electrode 9 is located between the capacitor C and the common bit line CBL. Here, the selection transistor T2 is coupled to the common bit line CBL via the connection electrode 9.

[0227] Exemplary, the connecting electrode 9 includes at least two first electrode dummy structures 31 coupled to each other, where at least one first electrode dummy structure 31 is located on the side away from the bit line BL of the selection transistor T2 and is in contact with the semiconductor layer 41 of the selection transistor T2. At least one first electrode dummy structure 31 is located on the side away from the bit line BL of the dummy line DL.

[0228] For example, the first electrode dummy structure 31 is formed simultaneously using the same material as the first electrode 21 of the capacitor C.

[0229] For example, the connecting electrode 9 may further include a support electrode 32 that is in contact with the first electrode dummy structure 31.

[0230] Some embodiments of this disclosure further provide electronic devices, such as data storage devices, photocopiers, network devices, consumer electronics, measuring instruments, mobile phones, computers, and other devices having data storage capabilities.

[0231] The electronic device may include a memory as described in some of the above embodiments and a processor coupled to the memory.

[0232] The memory structure can be found in the relevant descriptions in some of the embodiments described above. The processor can control the read / write operations of the memory.

[0233] The electronic device may further include other necessary elements or components, and the embodiments of this disclosure are not limited thereto.

[0234] For example, the electronic device may include a housing and a circuit board provided within the housing. The memory and processor may be integrated on the circuit board.

[0235] The technical features of the embodiments described above can be combined in any way, and for the sake of brevity, not all possible combinations of the technical features of the embodiments described above have been explained. However, as long as there is no inconsistency in these combinations of technical features, they should all be considered to be within the scope of this specification.

[0236] The embodiments described above are merely examples of some embodiments of the present disclosure, and although the descriptions are relatively specific and detailed, this should not be understood as limiting the scope of the claims. It should be noted that, provided that those skilled in the art do not deviate from the concept of the present disclosure, several further modifications and improvements can be made, all of which fall within the scope of the present disclosure. Therefore, the scope of the patent protection of the present disclosure should be based on the appended claims. [Explanation of Symbols]

[0237] CBL Common Bit Line BL bit line BLA Initial Bit Line BLa Part 1 BLb Part 2 N-cell array U1 Memory Cell U2 Selected cell U3 Connected Cell T1 Access Transistor T2 Select Transistor M1 First Etching Hole Group M2 Second etching hole group M3 Third Etching Hole Group C Capacitor H1 1st hole H2 2nd hole WL Word Line SL Selection Line DL dummy wire S staircase structure S1 Insulated Staircase S2 conductive stairs L1 First Dielectric Layer L2 Second Dielectric Layer L3 Third Dielectric Layer 1 circuit board 21 1st electrode 22 Dielectric layer 23 2nd electrode 31. First electrode dummy structure 32 Support electrode 33 1st packed bed 34 Second packed bed 41 Semiconductor layer 41A Initial semiconductor layer 42 Gate Insulation Layer 5 Separation structure 61 1st separation layer 611 Silicon Nitride Layer 612 Aluminum Oxide Layer 62 Second separation layer 71 Titanium Nitride Layer 72 Tungsten metal layer 81 Separation barrier 82 Covering layer 821 First Sublayer 822 Second Sublayer 9. Connecting electrodes

Claims

1. It is memory, A common bit line (CBL) extends along a first direction (Y) parallel to the substrate (1), A bit line (BL) located on the first side of the common bit line and extending along a second direction (X) parallel to the substrate, wherein the second direction and the first direction intersect with the bit line, A cell array (N) including a plurality of cells (U1, U2, U3) corresponding to the bit line, wherein the plurality of cells are located on the same side of the bit line and are arranged sequentially in the second direction, The plurality of cells include at least one connection cell (U3), at least one selection cell (U2) located away from the common bit line of the at least one connection cell, and a plurality of memory cells (U1) located away from the common bit line of the at least one selection cell, wherein both the memory cells and the selection cell include transistors coupled to the bit line, the transistor included in the selection cell is a selection transistor (T2), and the selection transistor is further coupled to the common bit line via the connection cell. Memory.

2. The transistor included in the memory cell is an access transistor (T1), and the memory cell further includes a capacitor (C), the capacitor includes a first electrode (21) coupled to the access transistor, a second electrode (23) provided opposite to the first electrode, and a dielectric layer (22) located between the first electrode and the second electrode. The selected cell and the connected cell both include a first electrode dummy structure (31), Each of the first electrode dummy structures in the selection cell and the connection cell corresponding to the bit line is connected to each other, the selection transistor in the selection cell is coupled to its first electrode dummy structure, and the first electrode dummy structure in the connection cell that is close to the common bit line is coupled to the common bit line. The memory according to claim 1.

3. The aforementioned cell is A first hole (H1) whose axis is perpendicular to the substrate, It includes a first receiving groove that extends in a direction parallel to the substrate and is located on the side wall of the first hole, The first electrode and the first electrode dummy structure are both conformally coated on the inner wall of the corresponding first housing groove, the dielectric layer is conformally coated on the side walls of the first electrode and the first hole, and the second electrode covers the dielectric layer and fills the first housing groove and the first hole. The selected cell and the connected cell each further include a support electrode (32) that covers the first electrode dummy structure and fills the first housing groove, and a first filling layer (33) that fills the first hole. The memory according to claim 2.

4. The aforementioned cell is The present invention further includes a second hole (H2) located between the bit line and the first hole, with its axis perpendicular to the substrate, Each memory cell and the selection cell further includes a second housing groove extending in a direction parallel to the substrate and located on the side wall of the second hole, the second housing groove exposing, on opposing sides in the first direction, the side wall of the bit line and the side wall of the corresponding first electrode or the corresponding first electrode dummy structure, respectively, the transistor includes a semiconductor layer (41) conformally covering the inner wall of the corresponding second housing groove and a gate insulating layer (42) conformally covering the semiconductor layer and the side wall of the second hole, the memory further includes a word line (WL) covering the gate insulating layer and filling the second hole in the memory cell, and a selection line (SL) covering the gate insulating layer and filling the second hole in the selection cell, The connecting cell further includes a second packed layer (34) that fills the second hole. The memory according to claim 3.

5. The aforementioned cell is The present invention further includes a second hole (H2) located between the bit line and the first hole, with its axis perpendicular to the substrate, The second hole exposes, on opposite sides in the first direction, the sidewalls of the bit line and the corresponding first electrode or the corresponding first electrode dummy structure, respectively, and both the access transistor and the selection transistor further include a semiconductor layer (41) and a gate insulating layer (42) formed on the inner wall of the second hole, the semiconductor layers between adjacent access transistors in a direction perpendicular to the substrate are insulated from each other, and the semiconductor layers between adjacent selection transistors in a direction perpendicular to the substrate are insulated from each other, and the memory further includes a word line (WL) covering the gate insulating layer and filling the second hole in the memory cell, and a selection line (SL) covering the gate insulating layer and filling the second hole in the selection cell, The connecting cell further includes a second packed layer (34) that fills the second hole. The memory according to claim 3.

6. The bit line includes a first portion (BLa) facing the memory cell and the selected cell, and a second portion (BLb) facing the connected cell. The second part and the common bit line are an integrated structure. The memory further includes a separation structure (5) located between the first part and the second part. The memory according to any one of claims 1 to 5.

7. The same bit line corresponds to at least two of the connected cells, The separation structure includes a first separation portion located between the first portion and the second portion, and a second separation portion which includes at least a portion of the second packed layer and is connected to at least the first separation portion. The memory according to claim 6.

8. The number of bit lines is multiple, and the multiple bit lines are insulated and arranged along a direction parallel to the substrate, and insulated and stacked along a direction perpendicular to the substrate. Along the direction parallel to the substrate, one bit line group is formed for every two adjacent bit lines, and each cell corresponding to any one bit line within the bit line group is located on the same side of the bit line, away from another bit line. The memory according to claim 6.

9. The number of the common bit lines is multiple, and the multiple common bit lines are insulated and stacked along a direction perpendicular to the substrate. The memory further includes a stepped structure (S) located on the side of the common bit line away from the bit line, and the stepped structure includes a plurality of conductive steps (S2) coupled to each of the common bit lines. The memory according to claim 6.

10. A method for manufacturing memory, The steps include alternately stacking a plurality of first dielectric layers (L1) and a plurality of second dielectric layers (L2) on a substrate (1), A step of etching the plurality of first dielectric layers and the plurality of second dielectric layers along a direction perpendicular to the substrate to form a first etching groove extending along a first direction (Y) parallel to the substrate and at least one second etching groove located on one side of the first etching groove and extending along a second direction (X) parallel to the substrate, wherein the second direction and the first direction intersect, The steps include etching each of the second dielectric layers along a direction parallel to the substrate based on the first etching groove to form a plurality of common bit line accommodating grooves, and forming a common bit line (CBL) within the common bit line accommodating groove, The steps include etching each of the second dielectric layers along a direction parallel to the substrate based on the second etching groove to form a plurality of bit line accommodating grooves, and forming bit lines (BL) within the bit line accommodating grooves, A step of etching the plurality of first dielectric layers and the plurality of second dielectric layers along a direction perpendicular to the substrate to form an etching hole array, wherein the etching hole array includes a plurality of etching hole groups that correspond to the same side of the bit line and are sequentially arranged in the second direction, and the plurality of etching hole groups include a plurality of first etching hole groups (M1) distributed at intervals in the second direction, at least one second etching hole group (M2) located on the side of the plurality of first etching hole groups closer to the common bit line, and at least one third etching hole group (M3) located on the side of the at least one second etching hole group closer to the common bit line, A step of forming a memory cell (U1) based on the first etching hole group, wherein the memory cell includes an access transistor (T1) coupled to the corresponding bit line, A step of forming a selection cell (U2) based on the second etching hole group, wherein the selection cell includes a selection transistor (T2) coupled to the corresponding bit line, The step of forming a connecting cell (U3) based on the third etching hole group is included, The selection transistor corresponding to the same bit line is further coupled to the common bit line by the corresponding connecting cell. A method for manufacturing memory, including

11. The etching hole array is formed before the common bit line etching groove and the bit line etching groove are formed, and the first etching hole group, the second etching hole group, and the third etching hole group each include a first hole (H1) whose axis is perpendicular to the substrate. The method for manufacturing the memory is as follows: The steps include filling each etching hole in the etching hole array with a third dielectric layer (L3), After forming the common bit line, the step of removing the third dielectric layer in each of the first holes, The process further includes the step of etching the second dielectric layer along a direction parallel to the substrate based on the first hole to form a first housing groove, The step of forming the memory cell based on the first etching hole group includes: forming a first electrode (21) conformally covering the inner wall of the corresponding first housing groove; forming a dielectric layer (22) conformally covering the side walls of the first electrode and the first hole; and forming a second electrode (23) that covers the dielectric layer and fills the first housing groove and the first hole. The steps of forming the selected cell based on the second etching hole group and forming the connecting cell based on the third etching hole group each include forming a first electrode dummy structure (31) conformally covering the inner wall of the corresponding first housing groove, Each of the first electrode dummy structures in the selection cell and the connection cell corresponding to the same bit line is connected to each other, the selection transistor in the same selection cell is coupled to its first electrode dummy structure, and the first electrode dummy structure in the connection cell close to the common bit line is coupled to the common bit line. A method for manufacturing a memory according to claim 10.

12. The steps of forming the selected cell based on the second etching hole group and forming the connecting cell based on the third etching hole group are both, The steps include forming a support electrode (32) that covers the first electrode dummy structure and fills the first housing groove, The process further includes the step of forming a first filling layer (33) that fills the first hole, The method for manufacturing a memory according to claim 11.

13. The first etching hole group, the second etching hole group, and the third etching hole group each further include a second hole (H2) located between the bit line and the first hole, with its axis perpendicular to the substrate. The steps of forming the memory cell based on the first etching hole group and forming the selected cell based on the second etching hole group are both, The steps include removing the third dielectric layer within the second hole, A step of etching the second dielectric layer along a direction parallel to the substrate based on the second hole to form a second housing groove, wherein the second housing groove exposes the side walls of the bit line and the corresponding first electrode or the corresponding first electrode dummy structure on opposite sides in the first direction, respectively. The steps include forming a semiconductor layer (41) conformally covering the inner wall of the corresponding second housing groove, The step includes forming a gate insulating layer (42) that conformally covers the semiconductor layer and the side walls of the second hole, The method for manufacturing the memory is as follows: The steps include forming a word line (WL) that covers the gate insulating layer and fills the second hole in the memory cell, and forming a selection line (SL) that covers the gate insulating layer and fills the second hole in the selection cell, A method for manufacturing a memory according to claim 11.

14. The method for manufacturing the memory is as follows: The process further includes filling the first etching groove and the second etching groove with a first separation layer (61) before forming the memory cell, the selected cell, and the connecting cell, The first etching hole group, the second etching hole group, and the third etching hole group each further include a second hole (H2) located between the bit line and the first hole, with its axis perpendicular to the substrate, wherein the second hole exposes, on opposing sides in the first direction, the sidewall of the bit line and the sidewall of the corresponding first electrode or the corresponding first electrode dummy structure, and the steps of forming the memory cell based on the first etching hole group and forming the selected cell based on the second etching hole group are both, The steps include removing the third dielectric layer within the second hole, The steps include sequentially forming an initial semiconductor layer (41A) and a gate insulating layer (42) on the inner wall of the second hole, The steps include forming a word line (WL) that covers the gate insulating layer and fills the second hole in the memory cell, and a selection line (SL) that covers the gate insulating layer and fills the second hole in the selection cell, The steps include removing the first separation layer in the second etching groove, The steps include etching each of the first dielectric layers along the first direction until the sidewalls away from the gate insulating layer of the initial semiconductor layer are exposed, The steps include etching away the initial semiconductor layer between any adjacent second dielectric layers to form a plurality of semiconductor layers (41) spaced apart along a direction perpendicular to the substrate, The process includes the step of forming a second separation layer (62) that fills the gap between adjacent semiconductor layers, the removal region of the first dielectric layer, and the second etching groove, A method for manufacturing a memory according to claim 11.

15. The same bit line corresponds to at least two of the connected cells, The first etching hole group, the second etching hole group, and the third etching hole group each further include a second hole (H2) located between the bit line and the first hole, with its axis perpendicular to the substrate, and the step of forming the bit line in the bit line housing groove is: The steps include forming an initial bit line (BLA) in the bit line housing groove, A step of forming the memory cell, the selection cell, and the connection cell, then removing the third dielectric layer in the second hole in any of the third etching hole groups, and etching the initial bit line along a direction parallel to the substrate based on the second hole to form the bit line (BL), wherein the bit line includes a first portion (BLa) facing the memory cell and the selection cell, and a second portion (BLb) facing the connection cell. The step includes forming a separation structure (5) in the second hole that communicates with the cutting region of the initial bit line, A method for manufacturing a memory according to claim 11.

16. The end of the bit wire housing groove closest to the common bit wire housing groove communicates with the common bit wire housing groove, and the common bit wire and the initial bit wire are formed simultaneously. The second portion of the bit line and the common bit line have an integrated structure. A method for manufacturing a memory according to claim 15.

17. After forming the common bit line and the initial bit line, and before forming the memory cell, the selected cell, and the connected cell, the method for manufacturing the memory is as follows: The steps include etching the plurality of first dielectric layers and the plurality of second dielectric layers along a direction perpendicular to the substrate, and forming a third etching groove on the side of the common bit line away from the initial bit line, The steps include etching each of the first dielectric layers based on the third etching groove to form a plurality of insulating steps (S1), A step of etching each of the second dielectric layers based on the third etching groove to form a plurality of conductive stair accommodating grooves, wherein the conductive stair accommodating grooves expose the side walls of the corresponding common bit lines, The step of forming a conductive staircase (S2) coupled to the common bit wire within the conductive staircase housing groove, wherein each conductive staircase and each insulating staircase together constitute a staircase structure (S), The step of forming a covering layer (82) that covers the aforementioned staircase structure further includes, A method for manufacturing a memory according to claim 15.

18. It is memory, A common bit line (CBL) extends along a first direction (Y) parallel to the substrate (1), A bit line (BL) is located on the first side of the common bit line, extends along a second direction (X) parallel to the substrate, and intersects the second direction with the first direction. A dummy line (DL), a selection line (SL), and a word line (WL) are all located on the first side of the common bit line, all located on the same side of the bit line, and all extending along a third direction (Z) perpendicular to the substrate. An access transistor (T1) coupled to the word line and the bit line, A capacitor (C) is located on the side of the access transistor away from the bit line and is coupled to the access transistor. The system includes a selection transistor (T2) coupled to the selection line, the bit line, and the common bit line, The dummy line, the selection line, and the word line are arranged sequentially in the second direction and move sequentially away from the common bit line. Memory.

19. The system further includes a connecting electrode (9) located between the capacitor and the common bit line, The selection transistor is coupled to the common bit line via the connecting electrode. The memory according to claim 18.

20. A memory according to any one of claims 1 to 9 or any one of claims 18 to 19, A processor coupled to the aforementioned memory, Electronic devices, including those mentioned above.

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