Gap-filling process for high-density, seamless silicon-containing materials

Abstract

An exemplary processing method may include supplying a silicon-containing precursor to a processing area of ​​a semiconductor processing chamber. A substrate may be housed in the processing area. Features may be defined on the substrate. The method may include forming a plasma emission of the silicon-containing precursor and depositing a silicon-containing material on the substrate. The method may include supplying a hydrogen-containing precursor to a processing area, forming a plasma emission of the hydrogen-containing precursor, and etching the silicon-containing material from the sidewalls of the features.

Description

[Technical Field]

[0001]

[0001] Cross-reference with related applications This application claims the interests and priority of U.S. Patent Application No. 18 / 209,732, filed on 14 June 2023, entitled “DENSIFIED SEAM-FREE SILICON-CONTAINING MATERIAL GAP FILL PROCESSES,” which is incorporated herein by reference in its entirety.

[0002]

[0002] This technology relates to semiconductor processing. More specifically, this technology relates to depositing, etching, and transforming materials to form a high-density, seamless silicon-containing material. [Background technology]

[0003]

[0003] Integrated circuits are made possible by a process that generates intricately patterned material layers on the substrate surface. Generating patterned material on a substrate requires a controlled method for forming and removing exposed material. As devices become smaller, material formation can affect subsequent operations. For example, in gap-filling operations, material may be formed or deposited to fill trenches or other features formed on a semiconductor substrate. These filling operations can be difficult because features may be characterized by higher aspect ratios and reduced limit dimensions. For example, because deposition may occur on top of a feature and along its sidewalls, continued deposition can pinch off parts of the feature, including between sidewalls, and create voids within the feature. This can affect the performance of the device and subsequent processing operations.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used to manufacture high-quality devices and structures. This technology addresses these and other needs. [Overview of the project]

[0005]

[0005] An exemplary deposition method may include supplying a silicon-containing precursor to a processing area of ​​a semiconductor processing chamber. A substrate may be housed in the processing area. Features may be defined on the substrate. The processing area may be at least partially defined between a faceplate and a substrate support on which the substrate is placed. The method may include forming a plasma emission of the silicon-containing precursor. The method may include depositing a silicon-containing material on a substrate. The method may include supplying a hydrogen-containing precursor to a processing area of ​​a semiconductor processing chamber. The method may include forming a plasma emission of the hydrogen-containing precursor. The method may include etching the silicon-containing material from the sidewalls of features using the plasma emission of the hydrogen-containing precursor.

[0006]

[0006] In some embodiments, features may be characterized by an aspect ratio of about 1:1 or greater. Features may be characterized by a width of about 100 nm or less. The method may include supplying a conversion precursor to a processing area of ​​a semiconductor processing chamber, forming a plasma emission of the conversion precursor, and converting the residual silicon-containing material to a silicon-nitrogen-containing material or a silicon-oxygen-containing material. The wet etching rate of the converted silicon-containing material may be about 5 Å / min or less. The plasma power supply may operate at about 20 MHz or greater while converting the residual silicon-containing material to a silicon-nitrogen-containing material or a silicon-oxygen-containing material. The plasma emission of the silicon-containing precursor may be formed at a first power level from the plasma power supply. The plasma emission of the hydrogen-containing precursor may be formed at a second power level from the plasma power supply that is greater than the first power level. The plasma emission of the conversion precursor may be formed at a third power level from the plasma power supply that is greater than the second power level. This method may include densifying the residual silicon-containing material within the features. Densification may include reducing the hydrogen content of the silicon-containing material to approximately 30 atomic percent or less. Etching may be performed halogen-free. This method may be repeated over a second cycle. The substrate temperature may be maintained at approximately 450°C or less. The pressure in the semiconductor process chamber is maintained at approximately 1 Torr or more.

[0007]

[0007] Some embodiments of the present technology may include a semiconductor processing method. The method may include i) forming a plasma ejecta of a silicon-containing precursor. The method may include ii) depositing the silicon-containing material on a substrate. The substrate may define features. The substrate may be placed on a substrate support. The method may include iii) forming a plasma ejecta of a hydrogen-containing precursor. The method may include iv) etching the silicon-containing material from the sidewalls of the features using the plasma ejecta of the hydrogen-containing precursor. The method may include v) forming a plasma ejecta of a conversion precursor. The method may include vi) converting the remaining silicon-containing material into a silicon-nitrogen-containing material or a silicon-oxygen-containing material. The method may include repeating steps i) through vi) to iteratively fill the features.

[0008]

[0008] In some embodiments, the thickness of the silicon-containing material at the bottom of the feature may be about 5 nm or less per cycle. The method may include applying bias power to the substrate support while the residual silicon-containing material is being converted to a silicon-nitrogen-containing material or a silicon-oxygen-containing material. Etching can completely remove the silicon-containing material from the sidewalls of the feature above the base filling of the feature. The conversion precursor may include a nitrogen-containing precursor or an oxygen-containing precursor. The method may include increasing the density of the residual silicon-containing material within the feature. The substrate temperature may be maintained at a temperature of about 350°C or less.

[0009]

[0009] Some embodiments of the present technology may include a semiconductor processing method. The method may include supplying a silicon-containing precursor to a processing area of ​​a semiconductor processing chamber. A substrate may be housed in the processing area. Features may be defined on the substrate. The processing area may be at least partially defined between a faceplate and a substrate support on which the substrate is placed. The method may include forming a plasma emission of the silicon-containing precursor. The plasma emission of the silicon-containing precursor may be formed at a first power level from a plasma power source. The method may include depositing a silicon-containing material on a substrate. The method may include supplying a hydrogen-containing precursor to a processing area of ​​a semiconductor processing chamber. The method may include forming a plasma emission of the hydrogen-containing precursor. The plasma emission of the hydrogen-containing precursor may be formed at a second power level from a plasma power source that is greater than the first power level. The method may include etching the silicon-containing material from the sidewalls of features using the plasma emission of the hydrogen-containing precursor. Etching can completely remove the silicon-containing material from the sidewalls of features above the base filling of the features. This method may include increasing the density of residual silicon-containing material within a feature. This method may include supplying a conversion precursor to the processing area of ​​a semiconductor processing chamber. This method may include forming plasma emissions of the conversion precursor. This method may include converting the residual silicon-containing material into a silicon-nitrogen-containing material or a silicon-oxygen-containing material.

[0010]

[0010] In some embodiments, the silicon-containing substrate may be amorphous silicon or contain amorphous silicon.

[0011]

[0011] Such technologies can offer many advantages over conventional systems and techniques. For example, by sequentially performing deposition, etching, and conversion steps according to embodiments of the technology, the sidewall coverage can be limited or controlled, thereby limiting the formation of seams or voids in small features. In addition, by performing a conversion operation following an etching operation according to embodiments of the technology, the sidewall coverage can be reduced before the material is converted, thereby increasing the resistance of the material to subsequent etching. Along with these numerous advantages and features, these embodiments and other embodiments will be described in more detail below with reference to the accompanying drawings.

[0012]

[0012] Further understanding of the nature and advantages of the technology of this disclosure can be obtained by referring to the remainder of this specification and the drawings. [Brief explanation of the drawing]

[0013] [Figure 1]

[0013] A schematic cross-sectional view of an exemplary processing chamber according to several embodiments of the present technology is shown. [Figure 2]

[0014] The following are exemplary steps in a processing method according to several embodiments of this technology. [Figure 3]

[0015] Figures A through C show schematic cross-sectional views of a substrate during processing according to several embodiments of this technology. [Modes for carrying out the invention]

[0014]

[0016] Several drawings are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes only and should not be considered to scale unless explicitly stated otherwise. Furthermore, as schematic diagrams, they are provided to aid understanding and may not include all aspects or information compared to a realistic depiction, and may include exaggerated material for illustrative purposes.

[0015]

[0017] In the attached drawings, similar components and / or features may have the same reference numeral. Furthermore, various components of the same type may be distinguished according to their reference numerals by letters that distinguish between similar components. Where only a first reference numeral is used in this specification, its description is applicable to any of the similar components having the same first reference numeral, regardless of the letters used.

[0016]

[0018] Silicon-containing materials can be used in various structures and processes in the manufacture of semiconductor devices, such as sacrificial materials, dummy gate materials, or trench-filling materials including insulating materials for the trench bottom. In gap-filling processes, some processes utilize plasma-enhanced deposition under process conditions to increase deposition directionality, which can allow the deposited material to better fill features on the substrate. In some deposition processes, the deposited material may be characterized by a relatively large amount of hydrogen. Increasing the amount of hydrogen may result in the formation of a material with a lower density than other formed films.

[0017]

[0019] As feature sizes continue to shrink, plasma-enhanced deposition can become challenging for narrow features. These features may be further characterized by higher aspect ratios. For example, deposition on the sidewalls of features can lead to more pinching of the feature, and at smaller feature sizes, flow and deposition within the feature are further restricted, potentially resulting in seams or voids in the deposited material. Conventional techniques have attempted to address the formation of seams or voids by performing intermittent etching processes to remove material from the sidewalls of the filled feature. However, conventional etching processes require many cycles and / or the use of halogen etchants to remove material from the sidewalls of the filled feature and suppress the formation of seams or voids. The incorporation of halogen etchants can leave halogen residues that may interfere with further processing steps. In addition, conventional techniques may result in the formation of low-quality silicon-containing materials with poor mechanical and / or electrical properties.

[0018]

[0020] This technology can overcome these limitations by performing halogen-free intermittent etching on the formed film. This limits or prevents sidewall coverage during trench filling, potentially enabling an improved filling process. Furthermore, etching may not leave halogen residues that could interfere with further processing steps. Specifically, a halogen-free etching process can prevent structural non-uniformity. In addition, this technology can deposit silicon-containing materials that can be converted, for example, into silicon-nitrogen-containing or silicon-oxygen-containing materials with desirable mechanical and / or electrical properties. By depositing and converting materials according to this technology, high-quality materials can be formed.

[0019]

[0021] After describing a general aspect of a chamber in accordance with some embodiments of the present technology in which the plasma processing steps described below can be performed, a specific methodology can be described. The technology described is used to improve a number of film forming processes and can be applicable to various processing chambers and steps, and thus it should be understood that the present technology is not intended to be limited to the specific films, chambers, or processes described.

[0020]

[0022] FIG. 1 shows a schematic cross-sectional view of an exemplary processing chamber 100 according to some embodiments of the present technology. This figure can show an overview of a system incorporating one or more aspects of the present technology and / or a system that can perform one or more deposition or other processing steps in accordance with an embodiment of the present technology. Additional details of the chamber 100 or the method being performed can be described further below. Chamber 100 can be utilized to form a film layer in accordance with some embodiments of the present technology, but it should be understood that the method can be similarly performed in any chamber in which film formation can occur. Processing chamber 100 can include a chamber body 102, a substrate support 104 disposed inside the chamber body 102, and a lid assembly 106 coupled to the chamber body 102 and sealing the substrate support 104 within the processing space 120. Substrate 103 is supplied to the processing space 120 through an opening 126, which can be conventionally sealed for processing using a slit valve or a door. Substrate 103 can be placed on the surface 105 of the substrate support during processing. Substrate support 104 can be rotatable along an axis 147 where the shaft 144 of the substrate support 104 can be located, as indicated by arrow 145. Alternatively, the substrate support 104 can be lifted and rotated as needed during the deposition process.

[0021]

[0023] The plasma profile modulator 111 can be disposed within the processing chamber 100 to control the plasma distribution across the substrate 103 disposed on the substrate support 104. The plasma profile modulator 111 can include a first electrode 108. This first electrode 108 is disposed adjacent to the chamber body 102 and can separate the chamber body 102 from other components of the lid assembly 106. The first electrode 108 can be part of the lid assembly 106 or a separate sidewall electrode. The first electrode 108 is an annular or ring-shaped member and can be a ring electrode. The first electrode 108 can be a continuous loop around the outer periphery of the processing chamber 100 surrounding the processing space 120 or, if desired, discontinuous at selected locations. The first electrode 108 can also be a perforated electrode such as a perforated ring or mesh electrode, or, for example, a flat electrode such as a secondary gas distributor.

[0022]

[0024] One or more isolators 110a, 110b, which can be a dielectric material such as ceramic or metal oxide (e.g., aluminum oxide and / or aluminum nitride), contact the first electrode 108 and can electrically and thermally separate the first electrode 108 from the gas distributor 112 (also referred to as a faceplate) and the chamber body 102. The gas distributor 112 can define apertures 118 for distributing process precursors into the processing space 120. The gas distributor 112 can be connected to a first power source 142, such as an RF generator, an RF power source, a DC power source, a pulsed DC power source, a pulsed RF power source, or any other power source that can be connected to the processing chamber. In some embodiments, the first power source 142 can be an RF power source.

[0023]

[0025] The gas distributor 112 may be a conductive or non-conductive gas distributor. Furthermore, the gas distributor 112 may also be formed from conductive and non-conductive components. For example, the body of the gas distributor 112 may be conductive, while the faceplate of the gas distributor 112 is non-conductive. The gas distributor 112 may be powered by a first power supply 142, such as shown in Figure 1, or in some embodiments, the gas distributor 112 may be connected to earth.

[0024]

[0026] The first electrode 108 may be coupled to a first tuning circuit 128 that can control the grounding path of the processing chamber 100. The first tuning circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be a variable capacitor or other circuit element, or may include these. The first tuning circuit 128 may be one or more inductors 132, or may include these. The first tuning circuit 128 may be any circuit that enables a variable or controllable impedance under the plasma conditions present in the processing space 120 during processing. In some embodiments as illustrated, the first tuning circuit 128 may include a first circuit leg and a second circuit leg connected in parallel between ground and the first electronic sensor 130. The first circuit leg may include a first inductor 132A. The second circuit leg may include a second inductor 132B connected in series with the first electronic controller 134. A second inductor 132B may be positioned between the first electronic controller 134 and a node connecting both the first and second circuit legs to the first electronic sensor 130. The first electronic sensor 130 is a voltage or current sensor and is connected to the first electronic controller 134, thereby providing some degree of closed-loop control over the plasma conditions inside the processing space 120.

[0025]

[0027] The second electrode 122 may be connected to the substrate support 104. The second electrode 122 may be embedded within the substrate support 104 or connected to the surface of the substrate support 104. The second electrode 122 may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed configuration of conductive elements. The second electrode 122 is a tuning electrode and may be connected to a second tuning circuit 136 by a conduit 146 and a cable having a selected resistance, such as 50 ohms, which is located, for example, within the shaft 144 of the substrate support 104. The second tuning circuit 136 may have a second electronic sensor 138 and a second electronic controller 140 (which may be a second variable capacitor). The second electronic sensor 138 is a voltage or current sensor and may be connected to the second electronic controller 140 to provide further control over plasma conditions in the processing space 120.

[0026]

[0028] A third electrode 124 (which may be a bias electrode and / or an electrostatic chuck electrode) may be connected to a substrate support 104. The third electrode may be connected to a second power supply 150 through a filter 148 (which may be an impedance matching circuit). The second power supply 150 may be a DC power supply, a pulsed DC power supply, an RF bias power supply, a pulsed RF source or bias power supply, or a combination of these or other power supplies. In some embodiments, the second power supply 150 may be an RF bias power supply.

[0027]

[0029] The lid assembly 106 and substrate support 104 in Figure 1 can be used with any processing chamber for plasma or heat treatment. During operation, the processing chamber 100 can control the plasma conditions in the processing space 120 in real time. The substrate 103 is placed on the substrate support 104, and a process gas can flow through the lid assembly 106 using the inlet 114 according to any desired flow plan. The gas can be discharged from the processing chamber 100 through the outlet 152. Power can be coupled to the gas distributor 112 to form a plasma in the processing space 120. In some embodiments, the substrate can be electrically biased using a third electrode 124.

[0028]

[0030] When the plasma in the processing space 120 is excited, a potential difference can be established between the plasma and the first electrode 108. A potential difference can also be established between the plasma and the second electrode 122. Electronic controllers 134, 140 can then be used to adjust the flow characteristics of the ground path, which are represented by two tuning circuits 128, 136. Setpoints can be provided for the first tuning circuit 128 and the second tuning circuit 136 to provide separate control over the deposition rate and the uniformity of plasma density from the center to the edge. In embodiments where both electronic controllers are variable capacitors, electronic sensors can separately adjust the variable capacitors to maximize the deposition rate and minimize thickness non-uniformity.

[0029]

[0031] Each of the tuning circuits 128 and 136 may have a variable impedance that can be adjusted using their respective electronic controllers 134 and 140. If the electronic controllers 134 and 140 are variable capacitors, the capacitance range of each variable capacitor and the inductances of the first inductor 132A and the second inductor 132B may be selected to provide an impedance range. This range depends on the frequency and voltage characteristics of the plasma and may have a minimum value within the capacitance range of each variable capacitor. Thus, when the capacitance of the first electronic controller 134 is at its minimum or maximum, the impedance of the first tuning circuit 128 becomes high, which may result in a plasma shape with minimal air or lateral coverage on the substrate support. As the capacitance of the first electronic controller 134 approaches the value that minimizes the impedance of the first tuning circuit 128, the air coverage of the plasma grows to its maximum, effectively covering the entire working area of ​​the substrate support 104. When the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may contract away from the chamber wall, and the air coverage of the substrate support may decrease. The second electronic controller 140 has a similar effect, and since the capacitance of the second electronic controller 140 can be changed, the air coverage of the plasma on the substrate support can be increased or decreased.

[0030]

[0032] Electronic sensors 130 and 138 may be used to tune their respective circuits 128 and 136 in a closed loop. Depending on the type of sensor used, a current or voltage setpoint may be set for each sensor, and control software may be provided to the sensors to determine the adjustments to their respective electronic controllers 134 and 140 to minimize deviations from the setpoint. Thus, the plasma shape can be selected and dynamically controlled during processing. Although the foregoing description is based on electronic controllers 134 and 140 (which may be variable capacitors), it will be understood that any electronic component with adjustable characteristics may be used to provide tuning circuits 128 and 136 with adjustable impedance.

[0031]

[0033] The processing chamber 100 may be used for a processing method that may include forming or etching a material for a semiconductor structure in some embodiments of the Art. The described chamber should not be considered limiting, and it should be understood that any chamber that can be configured to perform the operations described may be used similarly. Figure 2 shows exemplary steps in processing method 200 according to some embodiments of the Art. The method may be performed in various processing chambers, including the processing chamber 100 described above, and on one or more mainframes or tools. Method 200 may include a number of arbitrary steps. These steps may or may not be particularly relevant to some embodiments of the method according to the Art. For example, many of the steps, while described to provide a broader range of structure formation, may be performed by alternative methods that are not critical to the Art or would be easily understood. Method 200 may describe the steps schematically shown in Figures 3A-3C. These illustrations will be explained in conjunction with the steps of Method 200. It should be understood that only partial schematic diagrams are shown, and the substrate may include any number of additional materials and features having various properties and characteristics as shown in the figures.

[0032]

[0034] Method 200 may include additional steps before commencing the enumerated steps. For example, the additional processing steps may include forming a structure on the substrate, which may include both the formation and removal of material. For example, a transistor structure, a memory structure, or any other structure may be formed. The prior processing steps may be performed in the chamber in which Method 200 may be performed, or the processing may be performed in one or more other processing chambers before the substrate is supplied to one or more semiconductor processing chambers in which Method 200 may be performed. In any case, Method 200 may optionally include supplying a semiconductor substrate to a processing area of ​​a semiconductor processing chamber, such as the processing chamber 100 described above, or to another chamber, which may include the components described above. The substrate may be a pedestal, such as a substrate support 104, which may be present in the processing area of ​​a chamber, such as the processing space 120 described above, and may be deposited on a substrate support.

[0033]

[0035] A substrate on which several processes have been performed is the substrate 305 of structure 300, which may show a partial view of the substrate on which semiconductor processing can be performed. Structure 300 should be understood to show only some of the top layers during processing in order to illustrate aspects of the art. The substrate 305 may contain a material on which one or more features 310 may be formed. The substrate 305 may be any number of materials used in the semiconductor processing. The substrate material may be a dielectric material containing silicon, germanium, silicon oxide or silicon nitride, a metallic material, or any number of combinations of these materials, or may contain these and be a material formed in the substrate 305 or structure 300. Feature 310 may be characterized by any shape or configuration according to the art. In some embodiments, a feature may be a trench structure or opening formed in the substrate 305, or may include a trench structure or opening.

[0034]

[0036] Feature 310 can be characterized by any shape or size, but in some embodiments, feature 310 can be characterized by a higher aspect ratio or a ratio of the depth of the feature to the width across the feature. For example, in some embodiments, feature 310 can be characterized by an aspect ratio of about 1:1 or greater, and can be characterized by an aspect ratio of about 2:1 or greater, about 3:1 or greater, about 5:1 or greater, about 10:1 or greater, or greater. Furthermore, features may be characterized by narrow width or diameter across the entire feature, including the space between two sidewalls, such as dimensions of approximately 100 nm or less, and may be characterized by overall feature widths of approximately 90 nm or less, approximately 80 nm or less, approximately 70 nm or less, approximately 60 nm or less, approximately 50 nm or less, approximately 40 nm or less, approximately 30 nm or less, approximately 20 nm or less, approximately 17 nm or less, approximately 15 nm or less, approximately 12 nm or less, approximately 10 nm or less, approximately 9 nm or less, approximately 8 nm or less, approximately 7 nm or less, approximately 6 nm or less, approximately 5 nm or less, or less.

[0035]

[0037] In some embodiments, Method 200 may include optional processing steps, such as pretreatment, which can be performed to prepare the surface of the substrate 305 for deposition. Once prepared, Method 200 may include, in step 205, supplying one or more precursors to a processing area of ​​a semiconductor processing chamber housing the structure 300. The precursors may include not only one or more silicon-containing precursors, but also one or more diluent gases or carrier gases, such as an inert gas or other gas, supplied with the silicon-containing precursors. Silicon-containing precursors that may be used during the formation of the silicon-containing material 315 include silane (SiH4), disilane (Si2H6), trisilane (Si3H8), and tetrasilane (Si4H 10 ), Pentasilane (Si5H 12This may include, but is not limited to, other organosilanes including cyclohexasilane, silicon tetrafluoride (SiF4), silicon tetrachloride (SiCl4), dichlorosilane (SiH2Cl2), tetraethyl orthosilicate (TEOS), and any other silicon-containing precursors that can be used to form silicon-containing films. In some embodiments, the silicon-containing material may be nitrogen-free, oxygen-free, and / or carbon-free.

[0036]

[0038] The deposited plasma ejecta may be formed in step 210 from a deposition precursor containing a silicon-containing precursor. The deposited plasma ejecta is formed within the processing region, thereby enabling the deposition material to be deposited on the substrate. For example, in some embodiments, a capacitively coupled plasma may be formed within the processing region by applying a plasma output to a faceplate or substrate support as described above.

[0037]

[0039] The power applied during deposition is a low-power plasma that can limit dissociation and maintain the amount of hydrogen uptake into the deposited material. Therefore, in some embodiments, the plasma power supply may supply a plasma output of about 300 W or less to the faceplate or substrate support, and may supply power of about 250 W or less, about 200 W or less, about 150 W or less, about 100 W or less, about 50 W or less, or less. If the plasma output to the faceplate or substrate support exceeds, for example, 350 W, the substrate 305, such as the sidewall defining the feature 310, may be damaged.

[0038]

[0040] During the deposition process, an additional power source, a bias power source, may be engaged and coupled to the substrate support as described above to provide a bias to the plasma generated above the substrate 305. The bias can attract plasma emissions to the substrate 305 and increase deposition at the bottom of the feature 310. The applied bias power may be relatively low to limit damage to the structure. Thus, in some embodiments, the bias power source may supply a plasma output of about 1000 W or less to the faceplate or substrate support, and may supply power of about 750 W or less, about 600 W or less, about 500 W or less, about 400 W or less, or less. Furthermore, by adjusting the source power and the applied bias power, the density of the deposited silicon-containing material 315 may be increased during the deposition process. In embodiments, both source power and bias power may be applied to the faceplate support, such as via a second power source 150 as described above.

[0039]

[0041] In step 215, a silicon-containing material may be deposited onto the substrate from plasma emissions of a silicon-containing precursor. The silicon-containing material may be amorphous silicon or may contain amorphous silicon. The deposited material may at least partially fill features on the substrate to provide bottom-up gap filling. As shown in Figure 3A, the silicon-containing material 315 may be deposited on the substrate 305, on the bottom of the feature 310, as well as on top of the feature 310 on the substrate 305, and on the sidewalls of the feature 310. The amount of silicon-containing material 315 deposited on the sidewalls may be relatively small or thin, but as formation continues, the feature 310 may be pinched off. If pinched off occurs, seams or voids may form in the material as gap filling progresses. Therefore, a series of deposition and etching steps, as further described below, may be performed to deposit seam-free silicon-containing material 315 on the feature 310.

[0040]

[0042] Following a certain amount of deposition, in some embodiments of this technology, a processing or modification process may be formed which is configured to etch back the formed material. This process may be performed in the same chamber as the deposition and may be carried out in a circulating process to fill the features. In some embodiments, the flow of silicon-containing precursor may be stopped and the processing area may be purged. Following the purging, in step 220, a hydrogen-containing precursor may be supplied to the processing area of ​​the semiconductor processing chamber. In step 225, a processing plasma ejecta is formed, which may be a capacitively coupled plasma formed within the processing area, although in some embodiments, an inductively coupled plasma may also be applied. The processing plasma ejecta is formed by applying a plasma output to a faceplate or substrate support, and in some embodiments, no other power source may be engaged.

[0041]

[0043] Similar to the deposition process, during the processing process, a bias power supply may be engaged to provide a bias to the plasma generated above the substrate. This can cause plasma emitters to be attracted to the substrate, which can impact the film and lead to densification of the deposited silicon-containing material 315. Any hydrogen-containing material may be used, but in some embodiments, diatomic hydrogen or deuterium may be used as a hydrogen-containing precursor, along with one or more additional precursors, to generate the processing plasma. Hydrogen radicals and ions can readily penetrate the material formed within the feature 310, releasing hydrogen absorbed from the silicon-containing material 315 and potentially causing densification. The applied bias power may be relatively low to limit sputtering of the generated film, and in addition to limiting potential damage to the structure. Similarly, the amount of heavier material supplied to form the plasma may be reduced to limit sputtering of the deposited film. In addition, by adjusting the applied source power and bias power, an etching process may be performed to reduce the sidewall coverage of the deposited material.

[0042]

[0044] The etching process can be performed halogen-free. If halogen-containing materials are present, halogen residue may remain on the features 310 after filling them with silicon-containing material 315. This halogen residue may contaminate the structure 300 and lead to non-uniformity during further processing. Therefore, the etching process can be performed even without halogens or halogen-containing materials.

[0043]

[0045] As previously mentioned, hydrogen, or any other hydrogen-containing material, can be used to generate plasma within the processing area by supplying power from a plasma power source to the faceplate. In some embodiments, the source plasma output may be greater than the plasma output used during deposition. For example, the supplied plasma output may be about 100W or more, about 200W or more, about 300W or more, about 400W or more, or more. By increasing the source plasma output during processing plasma formation, a larger amount of plasma emission can be generated. However, the source plasma output may be kept below about 1000W, about 900W or less, about 800W or less, about 700W or less, about 600W or less, or less, so as not to damage the underlying structure. Furthermore, the bias power can also be adjusted to minimize damage to the underlying structure. For example, the bias power may be kept below about 1000W, about 750W or less, about 600W or less, about 500W or less, about 400W or less, or less. During certain processes, the bias power may be higher than the plasma source power, but in other processes, the bias power can be alternatively kept lower than the plasma output.

[0044]

[0046] Applying a greater bias can increase the directionality of the supply perpendicular to the plane across the entire substrate. Therefore, reducing the supplied bias power can decrease the amount of directionality, which can increase the interaction of plasma emitters within the feature. The plasma emitters can then etch the silicon-containing material 315 in step 230, removing the silicon-containing material 315 from the sidewalls of the feature 310. The plasma emitters can completely remove the silicon-containing material 315 from the sidewalls of the feature 310 above the base filling of the silicon-containing material 315. The base filling of the silicon-containing material may refer to the silicon-containing material 315 deposited at the bottom of the feature 310, or it may refer to the silicon-containing material 315 deposited first toward the bottom of the feature 310. In embodiments, the bottom-to-sidewall ratio of the silicon-containing material 315 of the feature after etching is about 1:1 or greater, and may be, for example, about 2:1 or greater, about 3:1 or greater, about 4:1 or greater, about 5:1 or greater, about 6:1 or greater, or greater. Depending on the depth of the feature, the silicon-containing material 315 at the bottom of the feature may be etched less because the plasma emissions do not reach the material.

[0045]

[0047] Simultaneously, or additionally, more directionally supplied plasma emitters may penetrate the residual silicon-containing material 315 formed on the bottom of feature 310 and / or on the substrate 305. This penetration may reduce the hydrogen uptake for densifying the film in an optional step 235. Densification in step 235 may be obtained from plasma emitters of one or more precursors, or, in embodiments, may be another step using, for example, an inert precursor to densify the residual silicon-containing material 315. As shown in Figure 3B, the silicon-containing material 315 may be removed from the sidewalls of feature 310, from the overhang region of substrate 305, and / or from the top surface of substrate 305. This removal may allow the deposited silicon-containing material 315 to be retained in the bottom region of feature 310. This process also reduces the incorporation of hydrogen into the remaining material (e.g., to less than 40 atomic percent), and can reduce hydrogen incorporation to less than 35 atomic percent, less than 30 atomic percent, less than 25 atomic percent, less than 20 atomic percent, less than 15 atomic percent, less than 10 atomic percent, less than 5 atomic percent, or less.

[0046]

[0048] Additional adjustments may be made to further increase the etching of material deposited along the sidewalls of features by adjusting one or more characteristics of the supplied plasma output or bias power. For example, in some embodiments, both the plasma power supply and the bias power supply may operate in continuous wave mode. In addition, one or both of the power supplies may operate in pulsed mode. In some embodiments, the source power may operate in continuous wave mode or pulsed mode, while the bias power operates in pulsed mode. The pulse frequency of the source power is about 1 MHz or higher and may be about 3 MHz or higher, about 5 MHz or higher, about 13.5 MHz or higher, about 15 MHz or higher, about 17.5 MHz or higher, about 20 MHz or higher, about 22.5 MHz or higher, about 25 MHz or higher, about 27.5 MHz or higher, or higher. The pulse frequency of the bias power is about 5 MHz or lower and may be about 4 MHz or lower, about 4 MHz, about 3 MHz or lower, about 2 MHz or lower, or lower. The duty cycle of the bias power is approximately 75% or less, and the bias power can operate with duty cycles of approximately 70% or less, approximately 60% or less, approximately 50% or less, approximately 40% or less, approximately 30% or less, approximately 20% or less, approximately 10% or less, approximately 5% or less, or less. By operating the bias power with a reduced duty cycle, such as an on-time duty cycle of approximately 50% or less, a longer time per cycle can be allocated to more isotropic etching within the feature, which can lead to better removal of material from the sidewalls.

[0047]

[0049] After etching the silicon-containing material 315 from the sidewall of a feature using a plasma emission of a hydrogen-containing precursor, the thickness of the silicon-containing material 315 at the bottom of the feature may be approximately 5 nm or less. If the thickness increases, subsequent conversion of the silicon-containing material 315 may not process the entire thickness of the material. Therefore, the thickness of the silicon-containing material 315 at the bottom of the feature after etching may be approximately 4.5 nm or less, approximately 4 nm or less, approximately 3.5 nm or less, approximately 3 nm or less, approximately 2.5 nm or less, approximately 2 nm or less, approximately 1.5 nm or less, approximately 1 nm or less, approximately 0.5 nm or less, or less.

[0048]

[0050] In one embodiment, the silicon-containing material 315 may be converted to another silicon-containing material. The flow of the hydrogen-containing precursor used during etching may be stopped and the processing area may be purged. Following the purging, the conversion precursor may be supplied to the processing area of ​​the semiconductor processing chamber in step 240. Depending on what the silicon-containing material 315 is converted to, the conversion precursor may be or include a nitrogen-containing precursor, an oxygen-containing precursor, or other precursors useful for semiconductor processing. An exemplary nitrogen-containing precursor may be or include nitrogen molecules (N2), nitrous oxide (N2O), ammonia (NH3), or any other nitrogen-containing substance useful for semiconductor processing. In one exemplary embodiment, the nitrogen-containing precursor may include nitrogen molecules (N2) together with hydrogen molecules (H2). An exemplary oxygen-containing precursor may be or include oxygen molecules (O2), ozone (O3), or other oxygen-containing substances useful for semiconductor processing.

[0049]

[0051] The conversion plasma ejecta may be formed in step 245 from a conversion precursor containing a nitrogen-containing precursor or an oxygen-containing precursor. The conversion plasma ejecta may also be formed within the processing region, thereby enabling the conversion of the remaining silicon-containing material 315 after etching in step 230. For example, in some embodiments, a capacitively coupled plasma may be formed within the processing region by applying the plasma output to a faceplate or substrate support as described above. In some embodiments, an inductively coupled plasma may also be applied.

[0050]

[0052] The plasma emissions of the conversion precursor may be formed at a third power level from a plasma power source greater than the second power level. For example, the plasma power source may supply a plasma output of about 500W or more to the faceplate or substrate support, and may supply power of about 600W or more, about 700W or more, about 800W or more, about 900W or more, about 100W or more, or more. Complete conversion of the material can be achieved at a plasma output of about 500W or more. However, to prevent damage to the structure, the plasma power source may supply a plasma output of about 2000W or less to the faceplate or substrate support, and may supply power of about 1750W or less, about 1500W or less, about 1250W or less, about 1000W or less, or less.

[0051]

[0053] Similar to the deposition and / or etching processes, during the conversion process, a bias power supply can be activated to provide a bias to the plasma generated above the substrate. This can cause plasma emitters to be attracted to the substrate and collide with the film, resulting in sufficient interaction with the silicon-containing material 315. The applied bias power may be relatively low to limit damage to the structure. Thus, in some embodiments, the bias power supply may supply a plasma output of about 1000 W or less to the faceplate or substrate support, and may supply power of about 750 W or less, about 600 W or less, about 500 W or less, about 400 W or less, or less.

[0052]

[0054] In some embodiments, the plasma power supply may operate at approximately 20 MHz or higher while converting the residual silicon-containing material 315 to a silicon-nitrogen-containing material or a silicon-oxygen-containing material. By operating at higher plasma output frequencies, bias power may not be required. A higher frequency plasma power supply may generate a high-density plasma with an increased radical portion compared to a reduced ionic portion. With an increased radical portion, the silicon-containing material 315 may be sufficiently converted without the need for bias power. Therefore, in some embodiments, the conversion process may be performed without bias power.

[0053]

[0055] Method 200 may include converting the residual silicon-containing material 315, for example, into a silicon-nitrogen-containing material or a silicon-oxygen-containing material. By contacting the residual silicon-containing material 315 with a conversion precursor, the conversion precursor may modify the structure of the silicon-containing material 315. For example, if the conversion precursor includes a nitrogen-containing precursor, nitrogen may be incorporated into the residual silicon-containing material 315 to form a silicon-nitrogen-containing material. By operating each process of deposition, etching, and conversion to intermittently fill the feature, the entire thickness of the residual silicon-containing material 315 may be converted.

[0054]

[0056] Due to the high quality of the material, the wet etching rate of the converted silicon-containing material may be about 5 Å / min or less. For example, the wet etching rate of the converted silicon-containing material may be about 4.8 Å / min or less, about 4.6 Å / min or less, about 4.4 Å / min or less, about 4.2 Å / min or less, about 4 Å / min or less, about 3.8 Å / min or less, about 3.6 Å / min or less, about 3.4 Å / min or less, about 3.2 Å / min or less, about 3 Å / min or less, or less. By the steps of method 200, a high-quality silicon-containing material similar to an atomic layer deposition (ALD) quality material may be deposited and converted. Therefore, the silicon-containing material 315 of the present technology may be characterized by improved wet etching resistance compared to the prior art.

[0055]

[0057] The present technology may also provide a material having desirable electrical properties. For example, the leakage current of the converted silicon-containing material at 2 MV / cm is maintained at about 1.0E-7 A / cm 2 or less, about 9.0E-8 A / cm 2 or less, about 8.0E-8 A / cm 2 or less, about 7.0E-8 A / cm 2 or less, about 6.0E-8 A / cm 2 or less, about 5.0E-8 A / cm 2 or less, about 4.0E-8 A / cm 2 or less, about 3.0E-8 A / cm 2 or less, about 2.0E-8 A / cm 2 or less, about 1.0E-8 A / cm 2 or less, or may be maintained at or less. Further, 0.001 A / cm2 The breakdown voltage of the converted silicon-containing material is maintained at approximately 5.0 MV / cm or higher, and may be maintained at approximately 5.5 MV / cm or higher, approximately 6.0 MV / cm or higher, approximately 6.5 MV / cm or higher, approximately 7.0 MV / cm or higher, or higher. Finally, the dielectric constant of the converted silicon-containing material is approximately 8 or less, and may be maintained at approximately 7.8 or less, approximately 7.6 or less, approximately 7.4 or less, approximately 7.2 or less, approximately 7 or less, or lower.

[0056]

[0058] As shown in Figure 2, the deposition process, etching process, and conversion process can be repeated any number of times within a cycle to fill the features in embodiments of this technology. As shown in Figure 3C, the deposition process, etching process, and conversion process can fill the features with a silicon-containing material 315, such as a silicon-nitrogen-containing material, a silicon-oxygen-containing material, or any other silicon-containing material. For example, the process can be repeated for a second cycle, a third cycle, a fourth cycle, a fifth cycle, a sixth cycle, a seventh cycle, or any number of cycles necessary to fill the features 310 with the silicon-containing material 315 to a desired level.

[0057]

[0059] Temperature and pressure can also affect the process of this technology. For example, the process is performed at temperatures below approximately 450°C, and may be performed at temperatures below approximately 400°C, below approximately 350°C, below approximately 300°C, below approximately 250°C, below approximately 225°C, below approximately 200°C, below approximately 180°C, below approximately 160°C, below approximately 140°C, below approximately 120°C, below approximately 100°C, below approximately 80°C, below approximately 60°C, below approximately 40°C, or below. The temperature may be maintained within any of these ranges throughout the entire method, including during deposition, etching, and conversion. At higher temperatures, crystalline silicon-containing materials may be formed instead of amorphous silicon-containing materials. However, this technology is not limited to amorphous silicon-containing materials, and crystalline silicon-containing materials can also be etched and converted in subsequent steps. However, higher temperatures may also result in higher quality materials, characterized by improved wet etching resistance, as mentioned above. Therefore, the process is carried out at temperatures above approximately 200°C, and may be carried out at temperatures above approximately 225°C, above approximately 250°C, above approximately 275°C, above approximately 300°C, above approximately 325°C, above approximately 350°C, above approximately 375°C, above approximately 400°C, or higher.

[0058]

[0060] The pressure within the semiconductor processing chamber is maintained at a relatively low level for all processes (e.g., chamber pressure of approximately 20 Torr or less), and the pressure may be maintained at approximately 18 Torr or less, approximately 16 Torr or less, approximately 14 Torr or less, approximately 12 Torr or less, approximately 10 Torr or less, approximately 8 Torr or less, approximately 6 Torr or less, approximately 4 Torr or less, approximately 2 Torr or less, or below. However, if the pressure is too low, the feature filling rate may be slow. Furthermore, if the pressure is too high, pattern loading may be reduced or lines may bend. Therefore, the pressure within the semiconductor processing chamber is maintained at approximately 1 Torr or more, approximately 2 Torr or more, and the pressure may be maintained at approximately 3 Torr or more, approximately 4 Torr or more, approximately 5 Torr or more, approximately 6 Torr or more, approximately 7 Torr or more, or above. By performing processes according to some embodiments of this technology, improved filling of narrow features utilizing silicon-containing materials can be produced.

[0059]

[0061] The above description includes numerous details for illustrative purposes to facilitate understanding of the various embodiments of this technology. However, it will be apparent to those skilled in the art that certain embodiments can be implemented without some of these details, or with additional details.

[0060]

[0062] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, many well-known processes and elements have not been described in order to avoid unnecessarily obscuring the art of the present invention. Therefore, the above description should not be construed as limiting the scope of the art. Moreover, while methods or processes may be described sequentially or stepwise, it should be understood that steps may be performed simultaneously or in an order different from that listed.

[0061]

[0063] Where a range of values ​​is given, unless explicitly stated otherwise in the context, each intervening value between the upper and lower limits of that range is understood to be specifically disclosed down to the smallest unit of the lower limit. Any narrow range between any stated or unstated intervening values ​​within the stated range, and any other stated or intervening values ​​within that stated range, are also included. The upper and lower limits of such narrower ranges may be individually included in or excluded from that range. Each range in which one, neither, or both of the limit values ​​are included is also included in the Art, provided that there are any limit values ​​specifically excluded within the stated range. Where a stated range includes one or both limit values, it also includes ranges that exclude one or both of the included limit values.

[0062]

[0064] As used herein and in the appended claims, the singular forms "a," "an," and "the" include multiple references unless otherwise explicitly stated in the context. For example, where “silicon-containing precursors” is mentioned, it includes multiple such precursors; where “silicon-containing materials” is mentioned, it includes references to one or more materials and equivalents well known to those skilled in the art, and so on.

[0063]

[0065] Furthermore, the terms “comprise(s),” “comprising,” “contain(s),” “containing,” “include(s),” and “including,” as used herein and in the claims, are intended to identify the presence of the described feature, integer, component, or action, but not to exclude the presence or addition of one or more other features, integers, components, actions, or groups.

Claims

1. A semiconductor processing method, The method involves supplying a silicon-containing precursor to a processing area of ​​a semiconductor processing chamber, wherein a substrate is housed within the processing area, the substrate defines features, and the processing area is at least partially defined between a faceplate and a substrate support on which the substrate is placed. Forming plasma emissions of the silicon-containing precursor, Depositing a silicon-containing material onto the substrate, The hydrogen-containing precursor is supplied to the processing area of ​​the semiconductor processing chamber, Forming plasma ejecta of the hydrogen-containing precursor, In order to provide residual silicon-containing material, the silicon-containing material is etched from the sidewall of the feature with the plasma emitted from the hydrogen-containing precursor. A semiconductor processing method, including the following.

2. The aforementioned feature is characterized by an aspect ratio of approximately 1:1 or greater. The semiconductor processing method according to claim 1, wherein the feature is characterized by a width extending over the feature of approximately 100 nm or less.

3. The conversion precursor is supplied to the processing area of ​​the semiconductor processing chamber, Forming plasma emitters of the aforementioned conversion precursor, The remaining silicon-containing material is converted into a silicon-nitrogen-containing material or a silicon-oxygen-containing material. The semiconductor processing method according to claim 1, further comprising:

4. The semiconductor processing method according to claim 3, wherein the wet etching rate of the converted silicon-containing material is about 5 Å / min or less.

5. The semiconductor processing method according to claim 3, wherein the plasma power supply operates at approximately 20 MHz or higher while the plasma power supply is converting the remaining silicon-containing material into a silicon-nitrogen-containing material or a silicon-oxygen-containing material.

6. The plasma emission of the silicon-containing precursor is formed at a first power level from the plasma power source. The semiconductor processing method according to claim 1, wherein the plasma emission of the hydrogen-containing precursor is formed at a second power level from the plasma power source that is greater than the first power level.

7. The plasma emission of the silicon-containing precursor is formed at a first power level from the plasma power source. The plasma emission of the hydrogen-containing precursor is formed at a second power level from the plasma power source that is greater than the first power level. The semiconductor processing method according to claim 3, wherein the plasma emission of the conversion precursor is formed at a third power level from the plasma power source that is greater than the second power level.

8. The method of increasing the density of the residual silicon-containing material within the feature includes reducing the hydrogen content of the silicon-containing material to about 30 atomic percent or less. The semiconductor processing method according to claim 1, further comprising:

9. The semiconductor processing method according to claim 1, wherein the etching is performed in a halogen-free manner.

10. The semiconductor processing method according to claim 1, wherein the method is repeated over a second cycle.

11. The temperature of the substrate is maintained at a temperature of approximately 450°C or lower. The semiconductor processing method according to claim 1, wherein the pressure in the semiconductor processing chamber is maintained at a pressure of about 1 Torr or more.

12. A semiconductor processing method, i) Forming a plasma emission of silicon-containing precursors, ii) Depositing a silicon-containing material onto a substrate, wherein the substrate defines features and the substrate is placed on a substrate support, iii) Forming a plasma emission product of a hydrogen-containing precursor, iv) Etching the silicon-containing material from the sidewall of the feature using the plasma emitted from the hydrogen-containing precursor, v) Forming plasma emissions of the conversion precursor, vi) Converting the remaining silicon-containing material into a silicon-nitrogen-containing material or a silicon-oxygen-containing material, To iteratively fill the aforementioned features, steps i) to vi) are repeated. A semiconductor processing method, including the following.

13. The semiconductor processing method according to claim 12, wherein the thickness of the silicon-containing material at the bottom of the feature is about 5 nm or less per cycle.

14. While the residual silicon-containing material is being converted to a silicon-nitrogen-containing material or a silicon-oxygen-containing material, bias power is applied to the substrate support. The semiconductor processing method according to claim 12, further comprising:

15. The semiconductor processing method according to claim 12, wherein the etching completely removes the silicon-containing material from the sidewall of the feature above the base filling of the feature.

16. The semiconductor processing method according to claim 12, wherein the conversion precursor includes a nitrogen-containing precursor or an oxygen-containing precursor.

17. To increase the density of the remaining silicon-containing material within the aforementioned feature. The semiconductor processing method according to claim 12, further comprising:

18. The semiconductor processing method according to claim 12, wherein the temperature of the substrate is maintained at a temperature of approximately 350°C or lower.

19. A semiconductor processing method, The method involves supplying a silicon-containing precursor to a processing area of ​​a semiconductor processing chamber, wherein a substrate is housed within the processing area, the substrate defines features, and the processing area is at least partially defined between a faceplate and a substrate support on which the substrate is placed. The process involves forming a plasma emission of the silicon-containing precursor, wherein the plasma emission of the silicon-containing precursor is formed at a first power level from the plasma power source. Depositing a silicon-containing material onto the substrate, The hydrogen-containing precursor is supplied to the processing area of ​​the semiconductor processing chamber, The process involves forming a plasma emission of the hydrogen-containing precursor, wherein the plasma emission of the hydrogen-containing precursor is formed at a second power level from the plasma power source that is greater than the first power level. Etching the silicon-containing material from the sidewall of the feature using the plasma emission of the hydrogen-containing precursor, wherein the etching completely removes the silicon-containing material from the sidewall of the feature above the base filling of the feature, To increase the density of the remaining silicon-containing material within the aforementioned feature, The conversion precursor is supplied to the processing area of ​​the semiconductor processing chamber, Forming plasma emitters of the aforementioned conversion precursor, The remaining silicon-containing material is converted into a silicon-nitrogen-containing material or a silicon-oxygen-containing material. A semiconductor processing method, including the following.

20. The semiconductor processing method according to claim 19, wherein the silicon-containing material includes amorphous silicon.

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