Circuit boards and chip packages including them

Abstract

The circuit board according to the embodiment includes a first metal layer and a second metal layer disposed on the first metal layer, wherein the first metal layer includes an oxide layer formed by oxidizing a region to a certain depth from the lower surface of the first metal layer, the first metal layer and the second metal layer include a plurality of electrode patterns spaced apart from each other on the oxide layer, and the oxide layer insulates the plurality of electrode patterns from each other.

Description

Technical Field

[0001] The embodiments relate to a circuit board, particularly to a circuit board applied to a smart IC and a chip package including the same.

Background Art

[0002] A smart IC card is a card incorporating at least one integrated circuit chip or chip module. More specifically, a smart IC card generally makes a plastic-based resin into a thin card shape, and then incorporates a central processing unit such as a microprocessor capable of inputting / outputting information and even processing information without another power source, and a storage device capable of storing information in a predetermined capacity. Thus, it means a device capable of performing simple operations by itself. To realize such a smart IC card, a semiconductor chip with a thin thickness is mounted on a circuit pattern of a printed circuit board, and on the opposite surface of the printed circuit board, a contact terminal is formed such that a circuit pattern electrically connected to the semiconductor chip is connected to an external card reader or the like in a contact or non-contact manner, and a card body on which the chip package is mounted is required.

[0003] The above-mentioned smart IC cards are widely used in various fields such as credit cards, USIM cards, security cards, identity certificates, etc. The circuit board applied to such a smart IC card includes an insulating layer and a circuit pattern layer disposed on the insulating layer.

[0004] At this time, the circuit pattern layer includes a bonding part and a contact part. The bonding part means the upper surface of the circuit pattern layer. For example, the bonding part means the surface of the circuit pattern layer that is connected to the IC chip among the surfaces of the circuit pattern layer. Also, the contact part means the lower surface or the second surface of the circuit pattern layer. For example, the contact part means the surface of the circuit pattern layer that contacts an external device (e.g., a card reader) among the surfaces of the circuit pattern layer.

[0005] Furthermore, a surface treatment layer is placed on the bonding portion and contact portion of the circuit pattern layer, respectively. The surface treatment layer is formed to impart a certain level or higher to the bonding portion and contact portion of the circuit pattern layer, providing them with wire bonding properties, corrosion resistance, oxidation resistance, wear resistance, and hardness.

[0006] However, conventional circuit boards, as described above, require the formation of a surface treatment layer on the circuit pattern layer, which complicates the manufacturing process and increases manufacturing costs. Furthermore, conventional circuit boards have the problem that the overall thickness increases by the thickness of the surface treatment layer.

[0007] (Patent Document 1) KR10-2002-0011361A [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] The embodiment aims to provide a circuit board with a new structure and a chip package containing the same.

[0009] Furthermore, the embodiment aims to provide a circuit board and a chip package including the same, in which the surface treatment layer on at least one of the bonding portions and contact portions of the circuit pattern layer is removed.

[0010] Furthermore, the embodiment aims to provide a circuit board and a chip package including the same that can be made slimmer by significantly reducing the overall thickness.

[0011] Furthermore, the embodiment aims to provide a circuit board and a chip package including the same that can remove the insulating layer contained in an existing circuit board.

[0012] Furthermore, the embodiment aims to provide a circuit board and a chip package including the same that can improve the adhesion between the insulating layer and the circuit pattern layer.

[0013] Furthermore, the embodiment aims to provide a circuit board and a chip package including a circuit pattern layer having different surface roughness on the top, side, and bottom surfaces. [Means for solving the problem]

[0014] The circuit board according to the embodiment includes a first metal layer and a second metal layer disposed on the first metal layer, wherein the first metal layer includes an oxide layer formed by oxidizing a region to a certain depth from the lower surface of the first metal layer, the first metal layer and the second metal layer include a plurality of electrode patterns spaced apart from each other on the oxide layer, and the oxide layer insulates the plurality of electrode patterns from each other.

[0015] The material further includes an organic layer located beneath the oxide layer, and the organic layer functions as an insulating layer that insulates the plurality of electrode patterns together with the oxide layer.

[0016] Furthermore, the second metal layer is an alloy layer containing nickel (Ni) and iron (Fe), and the first metal layer is a metal layer plated or deposited on the lower surface of the second metal layer.

[0017] Furthermore, the second metal layer comprises a first metal having a content in the range of 60% to 80% by weight, a second metal having a content in the range of 10% to 22% by weight, a third metal having a content in the range of 3% to 20% by weight, and a fourth metal having a content in the range of 3% to 10% by weight, wherein the first metal contains either nickel (Ni) or iron (Fe), the second metal contains chromium (Cr), the third metal contains the first metal and one other from nickel (Ni) and iron (Fe), and the fourth metal contains either silver (Ag), silicon (Si), or a silver (Ag)-silicon (Si) alloy.

[0018] Furthermore, the first metal layer contains copper (Cu).

[0019] Furthermore, the overall thickness of the first metal layer including the oxide layer is in the range of 7 μm to 15 μm, the thickness of the oxide layer in the first metal layer is in the range of 3 μm to 5 μm, and the thickness of the second metal layer is in the range of 100 μm to 200 μm.

[0020] Furthermore, the overall thickness of the first metal layer including the oxide layer is in the range of 2 μm to 10 μm, the thickness of the oxide layer in the first metal layer is in the range of 0.2 μm to 5 μm, and the thickness of the second metal layer is in the range of 20 μm to 50 μm.

[0021] Furthermore, the oxide layer includes at least one opening, and the first metal layer includes a first region that overlaps perpendicularly with the opening and a second region excluding the first region, the first region of the first metal layer having a recess connected to the opening, and the thickness of the first region of the first metal layer is smaller than the thickness of the second region of the first metal layer.

[0022] Furthermore, the second metal layer includes a third region that overlaps perpendicularly with the opening and the recess, and a fourth region excluding the third region, the recess penetrating the upper and lower surfaces of the first metal layer, and the lower surface of the third region of the second metal layer being exposed without contact with the first metal layer and the oxide layer.

[0023] Furthermore, the circuit board includes a first adhesive layer disposed between the oxide layer and the organic layer, the organic layer includes at least one through-hole, and the first adhesive layer includes an open region that overlaps perpendicularly with the through-hole.

[0024] Furthermore, the lower surface of the oxide layer of the first metal layer has an arithmetic mean roughness (Ra) in the range of 0.5 μm to 0.9 μm or a 10-point mean roughness (Rz) in the range of 1.5 μm to 2.5 μm.

[0025] On one hand, the chip package according to the embodiment includes an insulating layer including at least one through hole, a circuit pattern layer disposed on the insulating layer, an adhesive layer disposed on the lower surface of the insulating layer, an IC chip attached to the adhesive layer, and a connecting member connecting between the lower surface of the circuit pattern layer vertically overlapping with the through hole and the IC chip. The circuit pattern layer includes a first metal layer and a second metal layer disposed on the first metal layer. The first metal layer is formed by oxidizing a region with a certain depth from the lower surface of the first metal layer and includes an oxide layer corresponding to the insulating layer. The second metal layer is an alloy layer including nickel (Ni) and iron (Fe).

[0026] Also, the adhesive layer is disposed on the lower surface of the oxide layer.

[0027] Also, the chip package includes an organic layer disposed under the oxide layer, and the adhesive layer is disposed on the lower surface of the organic layer.

[0028] Also, the chip package includes a first surface layer disposed on the lower surface of the first metal layer vertically overlapping with the through hole and including nickel (Ni), and a second surface layer disposed on the lower surface of the first surface layer and including gold (Au). One end of the connecting member is connected to the terminal of the IC chip, and the other end of the connecting member is connected to the second surface layer.

Advantages of the Invention

[0029] The circuit board of the embodiment includes an insulating layer and a circuit pattern layer disposed on the insulating layer. The circuit pattern layer includes a first metal layer and a second metal layer. And the second metal layer is a rolled alloy layer, and the first metal layer is a metal layer formed on one surface of the rolled alloy layer. At this time, an oxide layer formed by oxidizing the surface of the first metal layer is formed at the interface between the first metal layer and the insulating layer. At this time, the oxide layer has a bed structure and can improve the adhesion between the first metal layer and the insulating layer.

[0030] As a result, the embodiment can solve the reliability problem of the circuit pattern layer including the first metal layer peeling off from the insulating layer by improving the adhesion between the insulating layer and the first metal layer.

[0031] Furthermore, the embodiment can further improve the insulating properties of the circuit board by using an oxide layer disposed between the first metal layer and the insulating layer.

[0032] On the other hand, in the embodiment, a second metal layer of the circuit pattern layer is formed using an alloy containing nickel (Ni)-chromium (Cr)-iron (Fe), and at least one of the following metals: silver (Ag), silicon (Si), and their alloys. As a result, the second metal layer in the embodiment can have a certain level of wear resistance, corrosion resistance, oxidation resistance, and hardness. Through this, in the embodiment, the surface treatment layer that would otherwise be formed on the contact portion of the circuit pattern layer can be omitted or removed, thereby simplifying the manufacturing process of the circuit board and reducing manufacturing costs.

[0033] On the other hand, the first metal layer of the embodiment includes a recess formed in a region that overlaps perpendicularly with the through-hole of the insulating layer. This recess can solve the problem of electrical reliability that arises when an oxide layer remains in the bonding portion of the circuit pattern layer. As a result, the embodiment can improve the electrical reliability of the circuit board and chip package, and further improve the reliability of the product.

[0034] Furthermore, the recess of the first metal layer may have a structure that penetrates the first metal layer. As a result, the lower surface of the second metal layer, which overlaps perpendicularly with the recess of the first metal layer, can function as a bonding portion of the circuit pattern layer. In this case, the second metal layer of the circuit pattern layer in the embodiment can have a certain level of wire bonding ability or higher. Through this, in the embodiment, not only the surface treatment layer that should be formed on the contact portion of the circuit pattern layer but also the surface treatment layer that should be formed on the bonding portion of the circuit pattern layer can be omitted or removed. Through this, the embodiment can further simplify the manufacturing process of the circuit board and further reduce manufacturing costs.

[0035] Furthermore, in this embodiment, the insulating layer can be constructed using only the oxide layer formed on the underside of the first metal layer. That is, in this embodiment, the insulating layer of organic material is removed while the metal oxide layer performs the function of an insulating layer.

[0036] In other words, the insulating layer of the circuit board in the embodiment may consist only of an oxide layer formed on the lower surface of the first metal layer. This allows the embodiment to further reduce the thickness of the circuit board by using the oxide layer to perform the function of an insulating layer.

[0037] Furthermore, in the embodiment, the thickness of the second metal layer of the circuit pattern layer can be increased by the thickness of the insulating layer of the organic material by removing the insulating layer of the organic material. In this case, the second metal layer is a rolled alloy. In this case, if the rolled alloy is manufactured to a thickness of 100 μm or less, an additional rolling process is required, which increases the manufacturing cost. Thus, the embodiment can eliminate the additional rolling process required to reduce the thickness of the rolled alloy without increasing the thickness of the product. Through this, the embodiment can simplify the manufacturing process of the circuit board and reduce manufacturing costs. Furthermore, the embodiment can improve the overall warpage characteristics of the circuit board by increasing the thickness of the second metal layer. [Brief explanation of the drawing]

[0038] [Figure 1] This figure shows a chip package related to a comparative example. [Figure 2] This is a diagram showing a circuit board according to the first embodiment. [Figure 3] Figure 2 is a plan view of the circuit board as seen from above. [Figure 4] Figure 2 is a plan view of the circuit board as seen from below. [Figure 5] This figure shows a first modified example of the circuit board shown in Figure 2. [Figure 6] This figure shows a third modified example of the circuit board shown in Figure 2. [Figure 7] This figure shows a fourth modified example of the circuit board shown in Figure 2. [Figure 8] This figure shows a chip package according to the first embodiment. [Figure 9] This figure shows a circuit board according to the second embodiment. [Figure 10] This figure shows a modified example of the circuit board of the second embodiment shown in Figure 9. [Figure 11] This figure shows a chip package of the second embodiment. [Modes for carrying out the invention]

[0039] The embodiments disclosed herein will be described in detail below with reference to the accompanying drawings, but identical or similar components will be given the same reference numeral regardless of the drawing reference numerals, and redundant descriptions will be omitted. The suffixes “module” and “part” used for components in the following description are added or used interchangeably to facilitate the preparation of the specification and do not have any mutually distinguishing meaning or role in themselves. Furthermore, in the description of the embodiments disclosed herein, if a specific description of such prior art is deemed to interfere with the gist of the embodiments disclosed herein, such detailed description will be omitted. In addition, the accompanying drawings are provided to facilitate understanding of the embodiments disclosed herein, and it should be understood that the accompanying drawings do not limit the technical idea disclosed herein and include all modifications, equivalents or substitutes that fall within the idea and technical scope of the present invention.

[0040] Terms including ordinal numbers such as "first," "second," etc., can be used to describe a variety of components, but the components are not limited by such terms. The terms are used solely for the purpose of distinguishing one component from another.

[0041] When it is stated that one component is “linked” or “connected” to another component, it should be understood that it may be directly “linked” or “connected” to the other component, and that other components may exist in between. On the other hand, when it is stated that one component is “directly linked” or “directly connected” to another component, it should be understood that there are no other components in between.

[0042] A singular expression can include multiple expressions unless the context clearly indicates otherwise.

[0043] In this application, terms such as “includes” or “having” are intended to specify the presence of features, figures, steps, actions, components, parts, or combinations thereof as described in the specification, and should be understood not to preemptively exclude the presence or addition of one or more other features, figures, steps, actions, components, parts, or combinations thereof.

[0044] The embodiments of the present invention will be described in detail below with reference to the attached drawings.

[0045] -Comparative Example-

[0046] Prior to describing the examples, comparative examples that are comparable to the circuit boards of the examples described herein will be explained.

[0047] Figure 1 shows a chip package related to a comparative example.

[0048] Referring to Figure 1, the chip package according to the comparative example includes an insulating layer 10, a circuit pattern layer 20, a first surface treatment layer 30, a second surface treatment layer 40, an adhesive layer 50, an IC chip 60, and a connecting member 70.

[0049] The comparative example chip package includes an insulating layer 10, and a circuit pattern layer 20 is arranged on at least one surface of the insulating layer 10.

[0050] In this comparative example, the circuit pattern layer 20 is a copper layer containing pure copper.

[0051] The insulating layer 10 includes at least one through-hole 15. The circuit pattern layer 20 includes a bonding portion that overlaps perpendicularly with the through-hole 15. For example, at least a portion of the circuit pattern layer 20 overlaps perpendicularly with the through-hole 15, and the lower surface of the circuit pattern layer 20 that overlaps perpendicularly with the through-hole 15 functions as a bonding portion that is electrically connected to the IC chip 60.

[0052] Furthermore, the upper surface of the circuit pattern layer 20 functions as a contact part, such as a connector, that comes into contact with an external device (for example, a card reader).

[0053] In this case, the bonding portion and the contact portion of the circuit pattern layer 20 are required to have different characteristics from each other.

[0054] For example, the bonding portion of the circuit pattern layer 20 requires a certain level of wire bonding performance in order to bond the connecting member 70, which is electrically connected to the IC chip 60.

[0055] Furthermore, the contacts of the circuit pattern layer 20 are exposed to the outside of the chip package, and therefore require a certain level of corrosion resistance, oxidation resistance, wear resistance, and hardness for a continuous connection with external devices.

[0056] As a result, in the comparative example circuit board, a first surface treatment layer 30 is formed on the bonding portion of the circuit pattern layer 20, and a second surface treatment layer 40 is formed on the contact portion of the circuit pattern layer 20. The first surface treatment layer 30 and the second surface treatment layer 40 each contain a nickel metal layer (Ni) and a gold metal layer (Au), respectively.

[0057] The nickel metal layer prevents oxidation of the copper (Cu) forming the circuit pattern layer 20, while also acting as a barrier to prevent the copper (Cu) from diffusing into the gold metal layer. Furthermore, the gold metal layer of the first surface treatment layer 30 is formed on the outermost surface of the bonding portion of the circuit pattern layer 20, providing the bonding portion with a certain level of wire bonding capability. Furthermore, the gold metal layer of the second surface treatment layer 40 is formed on the outermost surface of the contact portion of the circuit pattern layer 20, providing the contact with a certain level of corrosion resistance, oxidation resistance, wear resistance, and hardness.

[0058] However, the circuit boards in the comparative examples described above require the formation of a first surface treatment layer 30 and a second surface treatment layer 40 on the bonding portion and contact portion of the circuit pattern layer 20, respectively. This complicates the manufacturing process and increases manufacturing costs.

[0059] Furthermore, in the comparative example, the thickness of the gold metal layer of the second surface treatment layer 40 is reduced in order to reduce manufacturing costs. However, when the thickness of the gold metal layer is reduced, there is a problem that wear of the gold metal layer occurs during prolonged use of the circuit board, which impairs the product design.

[0060] On the other hand, in the comparative example, the circuit pattern layer 20 is formed of an aluminum alloy in order to remove at least one of the first and second surface treatment layers described above. However, the aluminum alloy has low strength. As a result, in order for the contact portion of the circuit pattern layer to have a certain level of corrosion resistance, oxidation resistance, wear resistance, and hardness, the thickness of the aluminum alloy must be 80 μm or more.

[0061] Furthermore, if the thickness of the aluminum alloy exceeds 80 μm, the overall thickness of the circuit board increases, the line width and pitch of the circuit pattern layer 20 increase, and the circuit integration density decreases.

[0062] -Examples-

[0063] Figure 2 shows a circuit board according to the first embodiment, Figure 3 is a plan view of the circuit board of Figure 2 viewed from above, and Figure 4 is a plan view of the circuit board of Figure 2 viewed from below.

[0064] The circuit board of the first embodiment will be described below with reference to Figures 2 to 4.

[0065] Referring to Figures 2 to 4, the circuit board of the first embodiment includes an insulating layer 110 and a circuit pattern layer.

[0066] Specifically, the circuit pattern layer includes a first metal layer 120 disposed on the insulating layer 110 and a second metal layer 130 disposed on the first metal layer 120. Furthermore, one surface of the first metal layer 120 includes an oxide layer 125 formed using an oxide. For example, the oxide layer 125 of the first metal layer 120 is formed between the first metal layer 120 and the insulating layer 110.

[0067] The oxide layer 125 can perform the function of improving the adhesion between the circuit pattern layer and the insulating layer 110. Furthermore, the oxide layer 125 can function as the insulating layer 110. For example, the oxide layer 125 formed on the surface of the first metal layer 120 is non-conductive. Therefore, the oxide layer 125 can also be said to be an insulator that performs an insulating function together with the insulating layer 110 in the circuit board of the first embodiment.

[0068] Here, although the drawing shows the oxide layer 125 as a separate layer from the first metal layer 120, the oxide layer 125 is essentially a part of the first metal layer 120.

[0069] As a result, the insulating layer of the circuit board in the first embodiment may include a "first insulating layer" corresponding to the insulating layer 110 and a "second insulating layer" corresponding to the oxide layer 125 of the first metal layer 120.

[0070] The insulating layer 110 contains an insulating material.

[0071] The insulating layer 110 has a thickness in the range of 60 μm to 120 μm, or in the range of 70 μm to 110 μm, or in the range of 80 μm to 100 μm.

[0072] If the thickness of the insulating layer 110 is less than 60 μm, the rigidity of the circuit board will be weakened, which may reduce the warping characteristics of the circuit board. If the thickness of the insulating layer is less than 60 μm, it may not be possible to stably form the circuit pattern layer on the circuit board. For example, if the thickness of the insulating layer 110 is less than 60 μm, the processability in the patterning process for forming the circuit pattern layer will be reduced.

[0073] If the thickness of the insulating layer 110 exceeds 120 μm, the overall thickness of the circuit board increases, which in turn increases the thickness of the chip package.

[0074] The insulating layer 110 includes at least one through hole 110T.

[0075] The through-hole 110T penetrates the upper and lower surfaces of the insulating layer 110.

[0076] A circuit pattern layer is formed on the insulating layer 110. The circuit pattern layer is formed on the upper surface of the insulating layer 110. However, the embodiment is not limited thereto, and the circuit pattern layer may be formed on the lower surface of the insulating layer 110.

[0077] The circuit pattern layer includes a plurality of metal layers.

[0078] For example, the circuit pattern layer includes a first metal layer 120 disposed on the upper surface of the insulating layer 110. The circuit pattern layer also includes a second metal layer 130 disposed on the upper surface of the first metal layer 120.

[0079] The second metal layer 130 is an alloy layer. The first metal layer 120 can be described as a plated or deposited metal layer formed on one surface of the second metal layer 130, which is the alloy layer. The first metal layer 120 is arranged on the lower surface of the second metal layer 130 with a certain thickness in order to form the oxide layer 125.

[0080] That is, the second metal layer 130 is an alloy layer manufactured by a rolling method. As a result, due to the characteristics of an alloy layer manufactured by a rolling method, the surface roughness of the second metal layer 130 can be very low. The first metal layer 120 may be a plated layer formed on one surface of the second metal layer 130 by an electroless plating method or a deposited layer deposited by a sputtering method.

[0081] The first metal layer 120 contains copper. However, the examples are not limited thereto, and the first metal layer 120 may also be formed by plating or vapor-depositing another metal layer, excluding copper, onto one surface of the second metal layer 130.

[0082] In the first metal layer 120, the oxide layer 125 has an arithmetic mean roughness (Ra) in the range of 0.5 μm to 0.9 μm. Furthermore, the oxide layer 125 of the first metal layer 120 can have a 10-point mean roughness (Rz) in the range of 1.5 μm to 2.5 μm. In this case, the oxide layer 125 is a part of the first metal layer 120, and therefore the arithmetic mean roughness (Ra) and 10-point mean roughness (Rz) of the oxide layer 125 can also be considered the surface roughness of the lower surface of the first metal layer 120.

[0083] As a result, the embodiment can improve the adhesion between the circuit pattern layer and the insulating layer 110 by having the oxide layer 125 of the first metal layer 120 have a surface roughness within the range described above.

[0084] In this embodiment, the first metal layer 120 includes an oxide layer 125 formed on its lower surface that contacts the insulating layer 110. Specifically, in the first embodiment, the first metal layer 120 includes an oxide layer 125 formed at the interface between the first metal layer 120 and the insulating layer 110. The oxide layer 125 is formed by oxidizing a region of a certain depth on the lower surface of the first metal layer 120 using an oxidizing agent. The oxide layer 125 has a bed structure. In this embodiment, the adhesion force with the insulating layer 110 can be improved because the oxide layer 125 has a bed structure. As a result, the embodiment can solve the problem of the circuit pattern layer peeling off from the insulating layer 110.

[0085] Furthermore, the oxide layer 125 of the first metal layer 120 has insulating properties. Therefore, the embodiment can further improve the insulating properties between the circuit pattern layer including the first metal layer 120 and the insulating layer 110. As a result, the embodiment can improve the electrical reliability of the circuit pattern layer.

[0086] The oxide layer 125 includes an opening 125T. For example, the oxide layer 125 is partially formed on the lower surface of the first metal layer 120. For example, the oxide layer 125 includes an opening 125T on the lower surface of the first metal layer 120 that overlaps perpendicularly with the through hole 110T of the insulating layer 110. As a result, at least a portion of the first metal layer 120 overlaps perpendicularly with the through hole 110T of the insulating layer 110 and the opening 125T of the oxide layer 125.

[0087] Furthermore, in the first embodiment, at least a portion of the oxide layer 125 does not overlap perpendicularly with the first metal layer 120 and the second metal layer 130. For example, the first metal layer 120 and the second metal layer 130 include a plurality of electrode patterns (not shown) that are spaced apart from each other horizontally on the insulating layer 110. The oxide layer 125 of the first embodiment is then positioned on the upper surface of the insulating layer 110 between the plurality of electrode patterns. Through this, the first embodiment can further improve the insulation properties between the plurality of electrode patterns using the oxide layer 125.

[0088] In the first embodiment, the thickness of the first metal layer 120 is in the range of 2 μm to 10 μm. Preferably, the thickness of the first metal layer 120 is in the range of 2.5 μm to 9.5 μm. More preferably, the thickness of the first metal layer 120 is in the range of 3 μm to 9 μm. In this case, the thickness of the first metal layer 120 refers to the total thickness including the thickness of the oxide layer 125.

[0089] If the thickness of the first metal layer 120 is less than 2 μm, the oxide layer 125 of the first metal layer 120 will not have the target level of surface roughness, which may reduce the adhesion between the insulating layer 110. Also, if the thickness of the first metal layer 120 is less than 2 μm, the oxide layer 125 may not have the target thickness. If the oxide layer 125 does not have the target thickness, the adhesion between the first metal layer 120 and the insulating layer 110 may decrease, or the insulating properties of the circuit board may decrease.

[0090] Furthermore, if the thickness of the first metal layer 120 exceeds 10 μm, the thickness of the circuit pattern layer and the thickness of the circuit board can be increased in proportion to the thickness of the first metal layer 120. This can make it difficult to slim down the circuit board and chip package.

[0091] The thickness of the oxide layer 125 in the first metal layer 120 is in the range of 0.2 μm to 5 μm. Preferably, the thickness of the oxide layer 125 is in the range of 0.22 μm to 4.8 μm. More preferably, the thickness of the oxide layer 125 is in the range of 0.25 μm to 4.5 μm.

[0092] If the thickness of the oxide layer 125 in the first metal layer 120 is less than 0.2 μm, the insulating properties between the circuit pattern layer and the insulating layer 110 due to the oxide layer 125 may decrease. Furthermore, if the thickness of the oxide layer 125 exceeds 5 μm, the decrease in the strength of the oxide layer 125 may cause damage to the oxide layer 125. Moreover, if the strength of the oxide layer 125 decreases, the adhesion between the insulating layer 110 and the first metal layer 120 decreases, which may cause the first metal layer 120 to peel off from the insulating layer 110.

[0093] The second metal layer 130 is placed on the first metal layer 120. The second metal layer 130 is an alloy layer. For example, the second metal layer 130 is formed from an alloy mainly composed of nickel (Ni) or iron (Fe). For example, the second metal layer 130 may be an alloy layer formed by a rolling method.

[0094] The second metal layer 130 has a thickness in the range of 20 μm to 50 μm. For example, the second metal layer 130 has a thickness in the range of 25 μm to 45 μm. For example, the second metal layer 130 has a thickness of 30 μm to 40 μm. If the thickness of the second metal layer 130 is less than 20 μm, the resistance of the second metal layer 130 increases, which can increase signal loss. For example, if the thickness of the second metal layer 130 is less than 20 μm, the signal transmission characteristics of the circuit board may deteriorate. If the thickness of the second metal layer 130 exceeds 50 μm, the overall thickness of the circuit board can be increased.

[0095] In this embodiment, the thickness of the second metal layer 130 is 50 μm or less, and the surface treatment layer formed on the contact portion of the second metal layer 130 can be omitted or removed. This can be achieved by the properties of the alloy forming the second metal layer 130, which will be described below.

[0096] The circuit pattern layer, which includes the first metal layer 120 and the second metal layer 130, includes an upper surface and a lower surface. The upper surface of the circuit pattern layer refers to the upper surface of the second metal layer 130, and the lower surface of the circuit pattern layer refers to the lower surface of the first metal layer 120.

[0097] Specifically, the contact portion of the circuit pattern layer refers to the upper surface of the second metal layer 130. Furthermore, the contact portion of the circuit pattern layer refers to the outermost region located on the circuit board and the chip package containing it. For example, the contact portion of the circuit pattern layer refers to the region exposed to the outside from the circuit board and the chip package.

[0098] Furthermore, the bonding portion of the circuit pattern layer refers to the region connected to the IC chip 170 in the chip package. For example, the bonding portion of the circuit pattern layer refers to the region that overlaps perpendicularly with the through-hole 110T of the insulating layer 110. In this case, the oxide layer 125 of the first metal layer 120 is partially formed on the lower surface of the first metal layer 120. For example, the oxide layer 125 is formed in the remaining region of the lower surface of the first metal layer 120, excluding the region that overlaps perpendicularly with the through-hole 110T. As a result, the oxide layer 125 includes an opening 125T that overlaps perpendicularly with the through-hole 110T of the insulating layer 110. The region of the lower surface of the first metal layer 120 that overlaps perpendicularly with the through-hole 110T of the insulating layer 110 and the opening 125T of the oxide layer 125 functions as the bonding portion.

[0099] In this case, the second metal layer 130 is required to have a certain level of corrosion resistance, oxidation resistance, wear resistance, and hardness. For example, the contact portion of the circuit pattern layer corresponding to the upper surface of the second metal layer 130 is required to have a certain level of corrosion resistance, oxidation resistance, wear resistance, and hardness.

[0100] As a result, in the comparative example, a second surface treatment layer 40 was formed on the contact portion of the circuit pattern layer.

[0101] In contrast, in this embodiment, the second metal layer 130 is formed using one of the first and second alloys having a certain level or higher corrosion resistance, oxidation resistance, wear resistance, hardness, and wire bonding properties. Through this, in this embodiment, the surface treatment layer formed on the contact portion of the second metal layer 130 can be omitted or removed.

[0102] In other words, in the embodiment, the second metal layer 130 is made to have a certain level of corrosion resistance, oxidation resistance, wear resistance, hardness, and wire bonding properties, even without the surface treatment layer, by changing the metal content in the alloy forming the second metal layer 130. This is achieved by the types of metals that make up the second metal layer 130 and their content, as described below.

[0103] The following describes the metal composition ratio in the alloy forming the second metal layer 130.

[0104] In this case, the second metal layer 130 is formed from either the first alloy or the second alloy. The first alloy is mainly composed of nickel (Ni), and the second alloy is mainly composed of iron (Fe).

[0105] -First Alloy-

[0106] The second metal layer 130 may be formed from a first alloy mainly composed of nickel (Ni).

[0107] The first alloy possesses a certain level of corrosion resistance, oxidation resistance, wear resistance, hardness, and wire bonding properties.

[0108] That is, the first alloy forming the second metal layer 130 is mainly composed of nickel (Ni). For example, the nickel (Ni) content in the first alloy forming the second metal layer 130 is in the range of 60% by weight (wt.%) to 80% by weight. For example, the nickel (Ni) content of the first alloy is 65% by weight to 78% by weight or 70% by weight to 75% by weight.

[0109] If the nickel (Ni) content in the first alloy is less than 60% by weight, the corrosion resistance, oxidation resistance, wear resistance, hardness, and wire bonding properties of the second metal layer 130 will decrease. As a result, a surface treatment layer must be formed on the contact portion of the second metal layer 130, which complicates the manufacturing process, increases the thickness of the circuit board, and increases manufacturing costs.

[0110] Specifically, if the nickel (Ni) content in the first alloy is less than 60% by weight, the surface roughness change rate (%) of the second metal layer 130 exceeds 10%. The surface roughness change rate (%) is related to the corrosion resistance, oxidation resistance, and wear resistance of the second metal layer 130.

[0111] As a result, the nickel (Ni) content in the first alloy forming the second metal layer 130 is in the range of 60% to 80% by weight, and as a result, the surface roughness change rate (%) is 10% or less, preferably 8% or less, and more preferably 5% or less.

[0112] Furthermore, if the nickel (Ni) content in the first alloy exceeds 80% by weight, the etching rate (μm / min) in the process of forming the second metal layer 130 using the first alloy decreases. That is, if the nickel (Ni) content in the first alloy exceeds 80% by weight, the hardness of the first alloy becomes too high, and a certain range of etching rate (μm / min) cannot be achieved in the process of forming the second metal layer 130. In addition, if the nickel (Ni) content in the first alloy exceeds 80% by weight, a problem occurs in which nickel ions are eluted onto the surface of the second metal layer 130 formed from the first alloy.

[0113] On the other hand, the first alloy forming the second metal layer 130 contains chromium (Cr). The chromium (Cr) content in the first alloy is in the range of 10% by weight (wt.%) to 22% by weight. For example, the chromium (Cr) content in the first alloy is in the range of 11% by weight to 21% by weight, or 12% by weight to 18% by weight.

[0114] If the chromium (Cr) content in the first alloy is less than 10% by weight, the amount of nickel leaching onto the surface of the second metal layer 130 formed from the first alloy increases.

[0115] In this case, if the chromium (Cr) content in the first alloy is less than 10% by weight, the effect of chromium (Cr) in preventing the leaching of nickel (Ni) decreases, which leads to problems with the reliability of the product due to the leaching of nickel ions to the outside. For this reason, the first alloy forming the second metal layer 130 in the example contains chromium (Cr) in an amount of 10% by weight or more.

[0116] On the other hand, if the chromium (Cr) content in the first alloy exceeds 22% by weight, the hardness of the second metal layer 130 increases, and as a result, the etching rate (μm / min) of the second metal layer 130 decreases. Also, if the chromium (Cr) content of the second metal layer 130 exceeds 22% by weight, the wire bonding properties of the second metal layer 130 decrease.

[0117] Furthermore, if the chromium (Cr) content in the first alloy is less than 10% by weight or more than 22% by weight, the content of other metals (e.g., nickel or iron) decreases or increases by the corresponding amount, which results in problems because the content of the other metals does not satisfy the optimal range described herein.

[0118] On the other hand, the first alloy forming the second metal layer 130 contains iron (Fe). The iron (Fe) content in the first alloy is in the range of 3 wt.% to 20 wt%. The iron (Fe) content in the first alloy can be in the range of 5 wt.% to 15 wt% or 7 wt.% to 11 wt%. In the first embodiment, the iron (Fe) serves to improve the rollability (or ductility) of the first alloy.

[0119] In this case, if the iron (Fe) content in the first alloy is less than 3% by weight, the rollability of the first alloy decreases, making it difficult to manufacture the first alloy and the second metal layer 130 to a thickness of 50 μm or less.

[0120] Furthermore, if the iron (Fe) content in the first alloy exceeds 20% by weight, the nickel (Ni) content and iron (Fe) content decrease, resulting in an increase in the amount of nickel leached or an increase in the percentage change in surface roughness.

[0121] On the other hand, the first alloy forming the second metal layer 130 contains one of the following metals: silver (Ag), silicon (Si), and silver (Ag)-silicon (Si) alloy. The silver (Ag), silicon (Si), and silver (Ag)-silicon (Si) alloys can enable the first alloy to have a certain level of wire bonding properties or higher.

[0122] As a result, the first alloy may be any one of the following: nickel (Ni)-chromium (Cr)-iron (Fe)-silver (Ag) alloy, nickel (Ni)-chromium (Cr)-iron (Fe)-silicon (Si) alloy, and nickel (Ni)-chromium (Cr)-iron (Fe)-silver (Ag)-silicon (Si) alloy.

[0123] In the first alloy, one of the metals silver (Ag), silicon (Si), and silver (Ag)-silicon (Si) alloy is present in an amount ranging from 3% to 10% by weight.

[0124] If the content of any one of the metals among silver (Ag), silicon (Si), and silver (Ag)-silicon (Si) alloy in the first alloy is less than 3% by weight, the wire bonding property of the second metal layer 130 is less than 4 gf.

[0125] In the first alloy constituting the second metal layer 130, if the content of any one of silver (Ag), silicon (Si), or silver (Ag)-silicon (Si) alloy exceeds 10% by weight, the content of nickel (Ni), chromium (Cr), or iron (Fe) decreases accordingly, which causes problems with at least one of the following properties of the circuit pattern layer: resistance (Ω), etching rate (μm / min), surface roughness change rate, and nickel elution amount.

[0126] On the other hand, the first alloy constituting the second metal layer 130 contains at least one additive.

[0127] For example, the first alloy forming the second metal layer 130 includes one additive selected from manganese (Mn), tin (Sn), zinc (Zn), and alloys containing at least two of these. For example, the additive selected from manganese (Mn), tin (Sn), zinc (Zn), and alloys containing at least two of these is added to refine the structure of the alloy constituting the second metal layer 130 and achieve solid solution strengthening.

[0128] Specifically, the content of any one additive selected from manganese (Mn), tin (Sn), zinc (Zn), and alloys containing at least two of these shall be in the range of 1% to 5% by weight.

[0129] In other words, if the content of any one additive selected from manganese (Mn), tin (Sn), zinc (Zn), and alloys containing at least two of these is less than 1% by weight, the strengthening effect of the solid solution is insufficient, which reduces the wear resistance, oxidation resistance, and corrosion resistance of the second metal layer 130.

[0130] Furthermore, if the content of any one additive selected from manganese (Mn), tin (Sn), zinc (Zn), and alloys containing at least two of these exceeds 5% by weight, the resistive properties of the second metal layer 130 increase, and the resulting signal loss increases.

[0131] Furthermore, if the content of any one additive selected from manganese (Mn), tin (Sn), zinc (Zn), and alloys containing at least two of these exceeds 5% by weight, the hardness of the second metal layer 130 increases, and the etching rate (μm / min) decreases as a result.

[0132] -Second Alloy-

[0133] On the other hand, the second metal layer 130 can be formed from a second alloy mainly composed of iron (Fe).

[0134] In this case, the second alloy contains the metals that make up the first alloy. However, the content of each metal in the second alloy is different from the content of each metal in the first alloy. For example, the first alloy is mainly composed of nickel, and the second alloy is mainly composed of iron. As a result, the content of nickel (Ni), iron (Fe), and chromium (Cr) in the second alloy is different from the content of nickel (Ni), iron (Fe), and chromium (Cr) in the first alloy.

[0135] That is, the second alloy forming the second metal layer 130 is mainly composed of iron (Fe). For example, the iron (Fe) content in the second alloy is within the range of 60% by weight (wt.%) to 80% by weight, or 61% by weight to 78% by weight, or 63% by weight to 75% by weight. The optimal range for the iron (Fe) content in the second alloy is 63% by weight to 75% by weight.

[0136] If the iron (Fe) content in the second alloy is less than 60% by weight, the rollability of the second alloy decreases, which increases the thickness of the second alloy and further increases the thickness of the second metal layer 130. If the iron (Fe) content in the second alloy exceeds 80% by weight, the wear resistance, corrosion resistance, and oxidation resistance of the second metal layer 130 formed from the second alloy decreases. Also, if the iron (Fe) content in the second alloy exceeds 80% by weight, the resistance (Ω) of the second metal layer 130 formed from the second alloy increases, which increases signal transmission loss. Furthermore, if the iron (Fe) content in the second alloy is less than 60% by weight or more than 80% by weight, the content of other metals (e.g., nickel and chromium) decreases or increases by a corresponding amount, which leads to problems because the content of the other metals cannot be within the optimal range described herein.

[0137] On the other hand, the chromium (Cr) content in the second alloy satisfies the range of 10 wt.% to 22 wt%, 13 wt% to 21 wt%, or 15 wt% to 20 wt%. In other words, the optimal range for the chromium (Cr) content in the second alloy is 15 wt% to 20 wt%.

[0138] If the chromium (Cr) content in the second alloy is less than 10% by weight, the amount of nickel leaching onto the surface of the second alloy increases. Also, if the chromium (Cr) content in the second alloy is less than 10% by weight, the hardness of the second metal layer 130 formed from the second alloy decreases. Furthermore, if the chromium (Cr) content in the second alloy exceeds 22% by weight, the wire bonding properties decrease.

[0139] On the other hand, the nickel (Ni) content in the second alloy satisfies the range of 3 wt.% to 20 wt.%, 5 wt.% to 18 wt.%, or 7 wt.% to 15 wt. That is, the optimal range for the nickel (Ni) content in the second alloy is 7 wt.% to 15 wt.

[0140] If the nickel (Ni) content in the second alloy is less than 3% by weight, the surface roughness change rate (%) of the second metal layer 130 exceeds 10%. Furthermore, if the nickel (Ni) content in the second alloy exceeds 20% by weight, the etching rate (μm / min) in the etching process used to form the second metal layer 130 decreases.

[0141] Figure 5 shows a first modified example of the circuit board shown in Figure 2.

[0142] Referring to Figure 5, the circuit board of the first modified example includes an insulating layer 110 and a circuit pattern layer. The circuit pattern layer is disposed on the insulating layer 110 and includes a first metal layer 120 which includes an oxide layer 125. The circuit pattern layer also includes a second metal layer 130 which is disposed on the first metal layer 120.

[0143] In this case, the lower surface of the first metal layer 120 of the circuit board in Figure 2 had the same height throughout its entire surface. For example, the lower surface of the first metal layer 120 of the circuit board in Figure 2 did not have any steps.

[0144] In contrast, the circuit board of the first modified example has a step on the lower surface of the first metal layer 120. For example, the lower surface of the first metal layer 120 includes a first region that overlaps perpendicularly with the through-hole 110T of the insulating layer 110 and a second region excluding the first region. The height of the first region on the lower surface of the first metal layer 120 is different from the height of the second region on the lower surface of the first metal layer 120. Preferably, the height of the first region on the lower surface of the first metal layer 120 is higher than the height of the second region on the lower surface of the first metal layer 120.

[0145] For example, the thickness of the first region of the first metal layer 120 is smaller than the thickness of the second region. Specifically, the lower surface of the first metal layer 120 includes a through hole 110T of the insulating layer 110 and a recess 120S that overlaps perpendicularly with the opening 125T of the oxide layer 125. The recess 120S is formed by removing a portion of the lower surface of the first metal layer 120 during the process of forming the through hole 110T of the insulating layer 110 and the opening 125T of the oxide layer 125. In this case, if the recess 120S does not exist, the oxide layer 125 may remain in at least a portion of the region of the lower surface of the first metal layer 120 that overlaps perpendicularly with the through hole 110T. If the oxide layer 125 remains in the region overlapping with the through hole 110T, the electrical reliability between the IC chip 170 and the circuit pattern layer may decrease. As a result, in the first modified example, a recess 120S is formed on the lower surface of the first metal layer 120 during the process of forming the through hole 110T and the opening 125T. Through this, the embodiment improves the electrical reliability between the bonding portion of the circuit pattern layer and the IC chip 170.

[0146] In the first modified example, the recess 120S was described as being formed by removing a portion of the first metal layer 120, but the invention is not limited to this.

[0147] For example, in the second modified example, the recess 120S has a through-hole type that penetrates the upper and lower surfaces of the first metal layer 120. As a result, the through-hole 110T of the insulating layer 110, the opening 125T of the oxide layer 125, and the lower surface of the second metal layer 130 in the region perpendicularly overlapping with the recess 120S of the first metal layer 120 are exposed. The exposed lower surface of the second metal layer 130 then functions as a bonding area.

[0148] In this case, in the first embodiment and the first modification, the lower surface of the first metal layer 120 functioned as a bonding portion for the circuit pattern layer. As a result, in the first embodiment and the first modification, a surface treatment layer should be formed on the lower surface of the bonding portion for wire bonding with the IC chip 170.

[0149] In contrast, as in the second modified example, when the recess 120S penetrates the first metal layer 120, the lower surface of the second metal layer 130 functions as the bonding portion of the circuit pattern layer. The second metal layer 130 is formed of a first or second alloy having a certain level of wire bonding properties. As a result, in the circuit board of the second modified example, the surface treatment layer placed on the bonding portion of the circuit pattern layer can be removed.

[0150] Figure 6 shows a third modified example of the circuit board shown in Figure 2.

[0151] Referring to Figure 6, the circuit board of the third modified example includes an insulating layer 110, a first metal layer 120, and a second metal layer 130. In this case, the insulating layer 110, the first metal layer 120, and the second metal layer 130 can have substantially the same structure as those of the first embodiment. Therefore, a detailed explanation of this is omitted.

[0152] In this case, the oxide layer 125 in the first embodiment included only the opening 125T formed in a region perpendicular to the through-hole 110T of the insulating layer 110.

[0153] In contrast, the oxide layer 125a of the circuit board in the third modified example includes a first opening 125T1 and a second opening 125T2.

[0154] The first opening 125T1 of the oxide layer 125a is formed in a region that overlaps perpendicularly with the through hole 110T. The first opening 125T1 corresponds to the opening 125T of the previous embodiment.

[0155] Furthermore, the second opening 125T2 of the oxide layer 125a is formed in the region between the multiple electrode patterns of the circuit pattern layer. For example, in the third modified example, the oxide layer 125a is removed along with the first metal layer 120 and the second metal layer 130 during the process of forming the multiple electrode patterns of the circuit pattern layer. As a result, the oxide layer 125a further includes the second opening 125T2 between the multiple electrode patterns.

[0156] Figure 7 shows a fourth modified example of the circuit board shown in Figure 2.

[0157] Referring to Figure 7, the circuit board includes an insulating layer 110, a first metal layer 120, and a second metal layer 130, corresponding to the circuit board in Figure 2. An oxide layer 125 is formed on the lower surface of the first metal layer 120.

[0158] In this case, the circuit board of the fourth modified example includes a first adhesive layer 140 disposed between the oxide layer 125 of the first metal layer 120 and the insulating layer 110.

[0159] The first adhesive layer 140 may be a bonding sheet. The first adhesive layer 140 may be, but is not limited to, an epoxy-based bonding sheet.

[0160] The first adhesive layer 140 is placed between the oxide layer 125 of the first metal layer 120 and the insulating layer 110. This further improves the adhesion between the circuit pattern layer and the insulating layer 110 in the fourth modified example.

[0161] The first adhesive layer 140 may have the same planar area as the insulating layer 110. For example, the first adhesive layer 140 may include open regions 140T corresponding to through holes 110T of the insulating layer 110.

[0162] In the fourth modified example, by placing the first adhesive layer 140 between the oxide layer 125 of the first metal layer 120 and the insulating layer 110, the adhesion between the insulating layer 110 and the circuit pattern layer can be further improved. As a result, the embodiment can prevent the circuit pattern layer from peeling off from the insulating layer 110, thereby further improving the electrical reliability of the circuit pattern layer.

[0163] Figure 8 shows a chip package according to the first embodiment. In this case, the chip package of the first embodiment may include the circuit board shown in Figure 7. However, the embodiment is not limited to this. For example, the chip package of the first embodiment may also include circuit boards of other embodiments other than the circuit board shown in Figure 7.

[0164] The chip package of the first embodiment includes a surface treatment layer 150. The surface treatment layer 150 is formed on the lower surface of the circuit pattern layer in a region that overlaps perpendicularly with the through holes 110T of the insulating layer 110 and the openings 125T of the oxide layer 125. The surface treatment layer 150 is formed on the bonding portion of the circuit pattern layer. Preferably, the surface treatment layer 150 is formed on the lower surface of the first metal layer 120 that overlaps perpendicularly with the through holes 110T and the openings 125T.

[0165] In this case, if the recess 120S in the second modified example has a through-hole structure that penetrates the first metal layer 120, the surface treatment layer 150 can be omitted. Specifically, the second metal layer 130 has a certain level of wire bonding ability. In this case, if the recess 120S penetrates the first metal layer 120, the lower surface of the second metal layer 130, rather than the lower surface of the first metal layer 120, can function as the bonding portion of the circuit pattern layer. As a result, the surface treatment layer 150 can also be omitted or removed.

[0166] On the other hand, when the surface treatment layer 150 is formed on the bonding portion, the surface treatment layer 150 contains a metal having a certain level of wire bonding properties. For this purpose, the surface treatment layer 150 includes a plurality of surface layers. For example, the surface treatment layer 150 includes a first surface layer containing nickel. The surface treatment layer 150 also includes a second surface treatment layer containing gold, which is placed below the first surface layer. The first surface layer may have a thickness in the range of 2 μm to 3 μm. If the thickness of the first surface layer is less than 2 μm, the bonding reliability between the first metal layer 120 and the second surface layer may decrease. If the thickness of the first surface layer exceeds 3 μm, the manufacturing cost may increase. On the other hand, the second surface layer may have a thickness in the range of 0.2 μm to 0.5 μm. If the thickness of the second surface layer is less than 0.2 μm, the wire bonding properties may decrease. If the thickness of the second surface layer exceeds 0.5 μm, the manufacturing cost may increase.

[0167] The chip package includes a second adhesive layer 160 disposed on the underside of the insulating layer 110 of the circuit board. The second adhesive layer 160 is for bonding the IC chip 170 to the underside of the insulating layer 110. The second adhesive layer 160 may, but is not limited to, epoxy, thermosetting adhesive, and UV adhesive.

[0168] An IC chip 170 is attached to the second adhesive layer 160. The IC chip 170 includes terminals 180. The terminals 180 of the IC chip 170 are electrically connected to the bonding portion of the circuit pattern layer (specifically the surface treatment layer 150) via a connecting member 190 such as a wire. Specifically, one end of the connecting member 190 is connected to the terminals 180 of the IC chip 170, and the other end is connected to the lower surface of the surface treatment layer 150.

[0169] On the other hand, the chip package includes a molding layer. The molding layer may, but is not limited to, an EMC (Epoxy Molding Compound). The molding layer is located on the underside of the insulating layer 110. The molding layer molds the IC chip 170 and the connecting member 190.

[0170] Figure 9 shows a circuit board according to the second embodiment.

[0171] The following describes a circuit board according to the second embodiment.

[0172] In this case, the circuit board of the first embodiment included an insulating layer 110. The insulating layer 110 was an insulating layer made of an organic material.

[0173] In contrast, the circuit board of the second embodiment has the insulating layer 110 included in the circuit board of the first embodiment removed.

[0174] Referring to Figure 9, the circuit board includes a first metal layer 220 and a second metal layer 230 disposed on the first metal layer 220.

[0175] In this case, the first metal layer 220 of the second embodiment corresponds to the first metal layer 120 of the first embodiment, and the second metal layer 230 of the second embodiment corresponds to the second metal layer 130 of the first embodiment.

[0176] However, the circuit board of the second embodiment has a structure in which the insulating layer 110 is removed from the circuit board of the first embodiment. As a result, the first metal layer 220 and the second metal layer 230 in the circuit board of the second embodiment have different thicknesses than the first metal layer and the second metal layer of the first embodiment.

[0177] Specifically, the insulating layer of the circuit board in the second embodiment includes only an oxide layer 225 formed by oxidizing a portion of the first metal layer 220. That is, in the second embodiment, the oxide layer 225 performs the function of the insulating layer 110 of the circuit board in the first embodiment.

[0178] In other words, the insulating layer of the circuit board in the second embodiment is an oxide layer 225 formed by oxidizing a portion of the first metal layer 220. Furthermore, the second embodiment uses the oxide layer 225 to perform the function of an insulating layer, thereby further reducing the thickness of the product compared to the circuit board of the first embodiment.

[0179] Furthermore, if the circuit board of the second embodiment has the same thickness as the circuit board of the first embodiment, the thickness of the second metal layer 230 can be increased compared to the first embodiment. In this case, the second metal layer 230 is a rolled alloy. When a rolled alloy is manufactured to a thickness of 100 μm or less, an additional rolling process is required, which increases the manufacturing cost. In contrast, the circuit board of the second embodiment can eliminate the additional rolling process, thereby simplifying the manufacturing process and reducing manufacturing costs. Moreover, the circuit board of the second embodiment can increase the thickness of the second metal layer while maintaining the same thickness as the first embodiment, thereby improving the overall warpage characteristics of the circuit board.

[0180] The first metal layer 220 has a thickness in the range of 7 μm to 15 μm. If the thickness of the first metal layer 220 is less than 7 μm, it becomes difficult to form an oxide layer 225 of a certain thickness or more on the underside of the first metal layer 220, which reduces the insulating properties of the circuit board. Also, if the thickness of the first metal layer 220 exceeds 5 μm, the overall thickness of the circuit board increases.

[0181] The oxide layer 225 in the first metal layer 220 has a thickness in the range of 3 μm to 5 μm. If the thickness of the oxide layer 225 in the first metal layer 220 is 3 μm or less, the insulation properties will decrease, and the electrical reliability of the circuit board will decrease. Also, if the thickness of the oxide layer 225 exceeds 5 μm, the strength of the oxide layer 225 will decrease, which may cause damage problems.

[0182] The oxide layer 225 includes an opening 225T. The opening 225T is formed in a region of the lower surface of the first metal layer 220 that functions as a bonding portion. The opening 225T is formed by removing a portion of the oxide layer 225 formed on the lower surface of the first metal layer 220.

[0183] The second metal layer 230 has a thickness in the range of 100 μm to 200 μm. If the thickness of the second metal layer 230 is less than 100 μm, the warpage characteristics of the circuit board will decrease. Also, if the thickness of the second metal layer 230 is less than 100 μm, an additional process is required in the rolling process for manufacturing the second metal layer 230. If the thickness of the second metal layer 230 exceeds 200 μm, the overall thickness of the circuit board will increase.

[0184] Figure 10 shows a modified example of the circuit board of the second embodiment shown in Figure 9.

[0185] Referring to Figure 10, the circuit board of the modified version of the second embodiment includes a recess 220S formed in the region of the lower surface of the first metal layer 220 that overlaps perpendicularly with the opening 225T of the oxide layer 225.

[0186] The recess 220S has a shape that is recessed from the lower surface to the upper surface of the first metal layer 220.

[0187] The recess 220S is formed corresponding to the opening 225T of the oxide layer 225.

[0188] Furthermore, the recess 220S serves to completely remove the oxide layer 225 remaining on the lower surface of the first metal layer 220, which functions as the bonding portion.

[0189] In this case, the recess 220S in other modifications may have a structure that penetrates the first metal layer 220.

[0190] Figure 11 shows a chip package of the second embodiment.

[0191] Referring to Figure 11, the chip package of the second embodiment may include the circuit board shown in Figure 9 or Figure 10.

[0192] The chip package of the second embodiment includes a surface treatment layer 250. The surface treatment layer 250 is formed on the lower surface of the first metal layer 220 which overlaps perpendicularly with the opening 225T.

[0193] As an example, the surface treatment layer 250 is placed within a recess 220S of the first metal layer 220. The surface treatment layer 250 includes a first surface layer containing nickel and a second surface layer containing gold.

[0194] The chip package includes an adhesive layer 260 disposed on the lower surface of the oxide layer 225 of the circuit board.

[0195] An IC chip 270 is attached to the adhesive layer 260. The IC chip 270 includes terminals 280. The terminals 280 of the IC chip 270 are electrically connected to the bonding portion of the circuit pattern layer (specifically the surface treatment layer 250) via a connecting member 290 such as a wire.

[0196] On the other hand, the chip package includes a molding layer.

[0197] In the second embodiment, the insulating layer of the circuit board is made possible by using only the oxide layer formed on the lower surface of the first metal layer.

[0198] The circuit board of the embodiment includes an insulating layer and a circuit pattern layer disposed on the insulating layer. The circuit pattern layer includes a first metal layer and a second metal layer. The second metal layer is a rolled alloy layer, and the first metal layer is a metal layer formed on one surface of the rolled alloy layer. At the interface between the first metal layer and the insulating layer, an oxide layer is formed by oxidizing the surface of the first metal layer. At this time, the oxide layer has a bed structure, which can improve the adhesion between the first metal layer and the insulating layer.

[0199] As a result, the embodiment can solve the reliability problem of the circuit pattern layer including the first metal layer peeling off from the insulating layer by improving the adhesion between the insulating layer and the first metal layer.

[0200] Furthermore, the embodiment can further improve the insulating properties of the circuit board by using an oxide layer disposed between the first metal layer and the insulating layer.

[0201] On the other hand, in the embodiment, a second metal layer of the circuit pattern layer is formed using an alloy containing nickel (Ni)-chromium (Cr)-iron (Fe), and at least one of silver (Ag), silicon (Si), and alloys thereof. As a result, the second metal layer in the embodiment can have a certain level of wear resistance, corrosion resistance, oxidation resistance, and hardness. Through this, in the embodiment, the surface treatment layer that would otherwise be formed on the contact portion of the circuit pattern layer can be omitted or removed, thereby simplifying the manufacturing process of the circuit board and reducing manufacturing costs.

[0202] On the other hand, the first metal layer of the embodiment includes a recess formed in a region that overlaps perpendicularly with the through-hole of the insulating layer. This recess can solve the problem of electrical reliability that arises when an oxide layer remains in the bonding portion of the circuit pattern layer. As a result, the embodiment can improve the electrical reliability of the circuit board and chip package, and further improve the reliability of the product.

[0203] Furthermore, the recess of the first metal layer may have a structure that penetrates the first metal layer. As a result, the lower surface of the second metal layer, which overlaps perpendicularly with the recess of the first metal layer, can function as a bonding portion of the circuit pattern layer. In this case, the second metal layer of the circuit pattern layer in the embodiment can have a certain level of wire bonding ability or higher. Through this, in the embodiment, not only the surface treatment layer that should be formed on the contact portion of the circuit pattern layer but also the surface treatment layer that should be formed on the bonding portion of the circuit pattern layer can be omitted or removed. Through this, the embodiment can further simplify the manufacturing process of the circuit board and further reduce manufacturing costs.

[0204] Furthermore, in this embodiment, the insulating layer can be constructed using only the oxide layer formed on the underside of the first metal layer. That is, in this embodiment, the insulating layer of organic material is removed while the metal oxide layer performs the function of an insulating layer.

[0205] In other words, the insulating layer of the circuit board in the embodiment may consist only of an oxide layer formed on the lower surface of the first metal layer. This allows the embodiment to further reduce the thickness of the circuit board by using the oxide layer to perform the function of an insulating layer.

[0206] Furthermore, in the embodiment, the thickness of the second metal layer of the circuit pattern layer can be increased by the thickness of the insulating layer of the organic material by removing the insulating layer of the organic material. In this case, the second metal layer is a rolled alloy. In this case, if the rolled alloy is manufactured to a thickness of 100 μm or less, an additional rolling process is required, which increases the manufacturing cost. Thus, the embodiment can eliminate the additional rolling process required to reduce the thickness of the rolled alloy without increasing the thickness of the product. Through this, the embodiment can simplify the manufacturing process of the circuit board and reduce manufacturing costs. Furthermore, the embodiment can improve the overall warpage characteristics of the circuit board by increasing the thickness of the second metal layer.

[0207] The features, structures, and effects described in the examples above are included in at least one example and are not necessarily limited to just one example. Furthermore, the features, structures, and effects exemplified in each example can be combined or modified and implemented in other examples by a person with ordinary skill in the field to which the example belongs. Therefore, content related to such combinations and modifications should be interpreted as being included within the scope of the examples.

[0208] The above description has focused on examples, but these are merely illustrative and not limiting. Anyone with ordinary knowledge in the field to which these examples belong will understand that a variety of modifications and applications not illustrated above are possible, as long as they do not deviate from the essential characteristics of these examples. For example, each component specifically shown in the examples can be modified and implemented. Such differences related to modifications and applications should be interpreted as being included within the scope of the examples set forth in the attached claims.

Claims

1. The first metal layer and The invention includes a second metal layer disposed on the first metal layer, The first metal layer is It includes an oxide layer formed by oxidizing a region to a certain depth from the lower surface of the first metal layer, The first metal layer and the second metal layer include a plurality of electrode patterns spaced apart from each other on the oxide layer. The oxide layer insulates the multiple electrode patterns from each other, and the circuit board.

2. The organic layer disposed on the lower surface of the oxide layer further comprises The circuit board according to claim 1, wherein the organic layer functions as an insulating layer that insulates between the plurality of electrode patterns together with the oxide layer.

3. The second metal layer is an alloy layer containing nickel (Ni) and iron (Fe), The circuit board according to claim 1 or claim 2, wherein the first metal layer is a metal layer plated or deposited on the lower surface of the second metal layer.

4. The aforementioned second metal layer is A first metal having a content in the range of 60% to 80% by weight, A second metal having a content in the range of 10% to 22% by weight, A third metal having a content in the range of 3% to 20% by weight, It contains a fourth metal having a content ranging from 3% to 10% by weight, The first metal comprises either nickel (Ni) or iron (Fe), The second metal contains chromium (Cr), The third metal comprises nickel (Ni) and iron (Fe), one of the first metal and one other. The circuit board according to claim 3, wherein the fourth metal comprises one of silver (Ag), silicon (Si), and a silver (Ag)-silicon (Si) alloy.

5. The circuit board according to claim 4, wherein the first metal layer contains copper (Cu).

6. The overall thickness of the first metal layer including the oxide layer is in the range of 7 μm to 15 μm. The thickness of the oxide layer in the first metal layer is in the range of 3 μm to 5 μm. The circuit board according to claim 1, wherein the thickness of the second metal layer is in the range of 100 μm to 200 μm.

7. The overall thickness of the first metal layer including the oxide layer is in the range of 2 μm to 10 μm. The thickness of the oxide layer in the first metal layer is in the range of 0.2 μm to 5 μm. The circuit board according to claim 2, wherein the thickness of the second metal layer is in the range of 20 μm to 50 μm.

8. The oxide layer includes at least one opening, The first metal layer is A first region that overlaps perpendicularly with the opening, Including the second region excluding the first region, A recess is formed in the first region of the first metal layer, which is connected to the opening. The circuit board according to claim 1 or claim 2, wherein the thickness of the first region of the first metal layer is less than the thickness of the second region of the first metal layer.

9. The second metal layer includes a third region that overlaps perpendicularly with the opening and the recess, and a fourth region excluding the third region. The recess penetrates the upper and lower surfaces of the first metal layer, The circuit board according to claim 8, wherein the lower surface of the third region of the second metal layer is exposed without contact with the first metal layer and the oxide layer.

10. It includes a first adhesive layer disposed between the oxide layer and the organic layer, The organic layer includes at least one through hole, The circuit board according to claim 2, wherein the first adhesive layer includes an open region that overlaps perpendicularly with the through hole.

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