A substrate having a thick embedded dielectric layer and a method for preparing such a substrate.

Abstract

The present invention relates to a final substrate (S) comprising a top layer (5) made of a semiconductor material, a dielectric layer (4) having a thickness greater than 200 nm, a charge trapping layer (2), and a base substrate (3), arranged in a continuous manner and in contact with each other. The final substrate (S) has a curvature of less than 60 microns, preferably less than 40 microns. The exposed surface of the top layer (5) has a roughness of less than 0.3 nm as a root mean square measurement over a range of 30 microns × 30 microns. The present invention also relates to a method for preparing such a substrate.

Description

Technical Field

[0001] The present invention relates to a semiconductor-on-insulator type substrate having a charge trapping layer larger than 200 nm and an insulating (or dielectric) layer having a relatively high thickness. These substrates are particularly applicable in the field of radio frequency integrated devices, that is, electronic devices that process signals within a frequency range of about 3 kHz to 300 GHz, for example, in the field of telecommunication (telephone communication, Wi-Fi, Bluetooth, etc.). These substrates are also particularly applicable in the field of photonics. The present invention also relates to a method for manufacturing such a substrate.

Background Art

[0002] Document WO 2022 / 023630 discloses that the formation of a semiconductor-on-insulator type final substrate provided with a charge trapping layer and a thick dielectric layer (with a thickness greater than 200 nm according to this document) is particularly complex. According to the introduction of this document, in the industry, it is preferable to dispose this dielectric layer on the support substrate of the final substrate, and the dielectric layer made of silicon oxide can be obtained by oxidizing the surface portion of the charge trapping layer. The oxidation step tends to deform the support substrate and result in significant curvature (in the jargon used in the semiconductor field, it is denoted by the term "warpage", which is defined as the displacement of the central point of the median plane of the substrate from the reference plane). This warpage is generally measured by an interferometry method, for example, using a WaferSight (trademark) device from KLA. The presence of such warpage complicates the step of transferring the upper layer of the substrate and, more generally, the handling of the support substrate on the production line by conventional equipment. Generally, for a disk-shaped substrate having a diameter of 300 mm, it is required to limit this warpage to less than 60 microns, preferably less than 40 microns.

[0003] Furthermore, in numerous applications, it is essential that the exposed surface of the upper layer is extremely smooth, exhibiting a roughness much smaller than 0.5 nm in root mean square measurements over a 30 micron × 30 micron interatomic force measurement range. To obtain an upper layer exhibiting such roughness, it is known that the substrate is subjected to one or more thermal annealing processes in a neutral or reducing atmosphere after the upper layer has been transferred to the support substrate.

[0004] This annealing can be called "rapid thermal annealing," which consists of exposing the upper exposed surface to a thermal annealing atmosphere for a very short time, less than two minutes. The neutral or reducing atmosphere in the annealing chamber is rapidly heated to a processing temperature, which can reach 1200°C, and then cooled over a heating / cooling gradient that can exceed 50° / s. During this process, the substrate is held in the furnace chamber on multiple tips of a support, via its rear surface. However, the applicant has observed that this type of annealing generates dislocation lines or dislocation surfaces at the points where the substrate contacts the support. These dislocation lines or dislocation surfaces originate from thermal stress and gravity experienced by the substrate during the very rapid temperature changes it is subjected to. They sometimes render the substrate unsuitable for use in subsequent microelectronic component manufacturing steps, and at the very least, can result in the formation of non-functional components when these defects are aligned in a row.

[0005] As an alternative to rapid annealing, prolonged annealing can be applied during the final steps of substrate preparation, and is often referred to in this field as "batch annealing" because the substrates are generally placed in batches in the furnace chamber in a horizontal or vertical configuration. The atmosphere in the chamber is gradually increased at a gentle gradient of a few degrees per minute until the processing temperature reaches approximately 1100°C. The process continues at this temperature for an extended period of time, ranging from several minutes to several hours. The gentle gradient allows for limiting the thermal stress to which the substrate is exposed, thus limiting the appearance of dislocation lines or dislocation planes, which are observed at the end of rapid heat treatment.

[0006] The applicant observed that, as reported in the graph of Figure 1, the warpage of the substrate (on the vertical axis of this graph), caused by the warpage of the support substrate after oxidation of the trapping layer, could be compensated for by exposing the substrate to high temperatures (on the horizontal axis of this graph) during the finishing step, strictly above 1050°C to reduce this warpage to less than 40 microns, and approaching 1100°C to obtain a warpage of less than 30 microns. In the graph of Figure 1, the data collected at 1050°C, 1075°C, and 1100°C were obtained after long-term annealing, and the data collected at 1200°C was obtained after rapid annealing.

[0007] The applicant also observed that the roughness of the exposed surface of the upper layer of the substrate tends to worsen with increasing temperature when the dielectric layer (formed by oxidation of the trapping layer of the support) has a thickness greater than 200 nm. This is shown by the measurements reported in the graph of Figure 2, which reports the roughness of the exposed surface of the upper layer (measured by interatomic forces over a measurement range of 30 microns × 30 microns) in the central part (reference letter "C") and at the edge (reference letter "B") where the annealing temperature is increased. These anneals were performed on final substrates, each having a dielectric layer embedded to a depth of 400 nm, obtained by oxidation of the trapping layer of the support substrate, as described above. In this case, it is observed that the roughness tends to increase almost exponentially with increasing annealing temperature. The stacking forming the substrate is found to be thermally unstable when the dielectric layer has a thickness greater than 200 nm, and this instability degrades the free surface condition of the substrate. In some cases, the finishing heat treatment can cause this thermal instability due to the relaxation of stress in this layering process, and this relaxation itself directly manifests as increased roughness on the surface of the upper layer.

[0008] Therefore, it does not seem easy to obtain an insulator-on-a-semiconductor type final substrate having a thick dielectric layer that is greater than 200 nm thick, exhibits both low roughness (below the limits shown in the above section) and small warpage of, for example, less than 60 microns, and advantageously free from an excessive amount of dislocation planes or dislocation lines. [Overview of the project] [Problems that the invention aims to solve]

[0009] One objective of the present invention is to propose a solution to this problem. More specifically, the present invention proposes a substrate having an embedded dielectric layer greater than 2000 nm thick that exhibits both low roughness and small warpage. The present invention also proposes a method for preparing such a substrate. [Means for solving the problem]

[0010] To achieve this goal, the subject of the present invention proposes a method for preparing a final substrate having a thick embedded dielectric layer, and the method is The steps include preparing a support substrate having a charge trapping layer placed on a base substrate, The steps include forming a dielectric layer having a thickness greater than 200 nm on a charge trapping layer, A step of transferring the upper layer containing the semiconductor material to the dielectric layer, The step of finishing the exposed surface of the upper layer Includes.

[0011] According to the present invention, the step of forming a dielectric layer is carried out by high-density plasma chemical vapor deposition, and the finishing step includes a first annealing carried out in a neutral or reducing atmosphere at a temperature higher than 1050°C for a duration longer than 30 minutes.

[0012] Remarkably, this method makes it possible to obtain a final substrate that exhibits both reduced warpage and a satisfactory surface condition.

[0013] According to other advantageous and non-limiting features of the present invention, which can be implemented individually or in any technically feasible combination, The step of forming the dielectric layer includes high-density plasma chemical vapor deposition of the dielectric layer, followed by high-density annealing of the supporting substrate. High-density annealing is performed in a neutral atmosphere at temperatures below 1000°C and for a duration of less than one hour. The finishing step includes thinning the upper layer before and / or after the first annealing; Thinning is performed by sacrificial oxidation. The finishing step includes a second annealing, which is carried out in a neutral or reducing atmosphere at a temperature higher than 1050°C for a duration of less than 2 minutes. The neutral or reducing atmosphere for the first annealing is provided with or consists of argon. The step of forming the dielectric layer does not include polishing the exposed surface of the dielectric layer. The semiconductor material is silicon. The dielectric layer is made of silicon dioxide. The dielectric layer has a thickness of 400 nm or more. The step of transferring the upper layer includes injecting element species called "light" element species into the donor substrate to form a weakened plane therein, bonding the donor substrate to the support substrate, and fragmenting the donor substrate within the weakened plane.

[0014] In another embodiment, the present invention proposes a final substrate comprising, in a continuous manner and in contact with one another: a top layer made of a semiconductor material, a dielectric layer having a thickness greater than 200 nm, a charge trapping layer, and a base substrate.

[0015] According to the present invention, the final substrate has an exposed surface made of a semiconductor material having a roughness of less than 0.3 nm measured using the root mean square term, and a warpage of less than 60 microns, preferably less than 40 microns, over a range of 30 microns × 30 microns.

[0016] According to this, other advantageous and non-limiting features of other aspects of the invention, which can be implemented alone or in any technically feasible combination, The upper layer is made of silicon. The dielectric layer is made of silicon oxide. The final substrate takes the shape of a disk having a diameter of 300 mm or more. The final substrate has a total length of dislocation planes or dislocation lines of less than 20 mm in measurements by deflectometry.

[0017] Other features and advantages of the present invention will become apparent from the following detailed description of the present invention, which is given with reference to the accompanying drawings.

Brief Description of the Drawings

[0018] [Figure 1] It is a graph associating the warp of a silicon-on-insulator type substrate with the temperature of annealing applied during the step of finishing the preparation of this substrate. [Figure 2] It is a graph associating the roughness of the exposed surface of the upper layer of the final substrate with the temperature of annealing applied during the step of finishing the preparation of this substrate, for a dielectric layer embedded at a depth of 400 nm. [Figure 3] It is a diagram showing a substrate according to the present invention. [Figure 4a] It is a diagram showing a method for preparing a final substrate according to the present invention. [Figure 4b] It is a diagram showing a method for preparing a final substrate according to the present invention. [Figure 4c] It is a diagram showing a method for preparing a final substrate according to the present invention. [Figure 4d] It is a diagram showing a method for preparing a final substrate according to the present invention. [Figure 5a] It is a diagram showing warp measurement values taken during an experiment that enables the present invention to be achieved. [Figure 5b] It is a diagram showing roughness measurement values taken during an experiment that enables the present invention to be achieved. [Figure 6]This figure shows the advantages of using "long-duration" annealing rather than "rapid" annealing in the manufacturing method according to the present invention, from the perspective of dislocation-type defects. [Modes for carrying out the invention]

[0019] Referring to Figure 3, the substrate S of one embodiment comprises a base substrate 3, a charge trapping layer 2 (referred to as the "trapping layer" for the remainder of this description) disposed on the base substrate 3, a dielectric layer 4 disposed on and in direct contact with the trapping layer 2, and an upper layer 5 disposed on the dielectric layer 4. The base substrate 3, on which the charge trapping layer and the dielectric layer 4 are provided, forms the support substrate 1 of the final substrate S.

[0020] The substrate S (and therefore the support substrate 1) may take the form of a wafer, for example, a disc with a diameter of 300 mm. The substrate has a curvature of less than 60 microns, preferably less than 40 microns, so that it can be compatible with subsequent component manufacturing steps.

[0021] The base substrate 3 has a thickness of several hundred microns. Preferably, the base substrate 3 exhibits a high resistivity greater than 100 or 1000 Ωcm, and even more preferably greater than 3000 Ωcm. This limits the density of charges, i.e., holes or electrons, that can move within the base substrate 3 and thus degrade the radio frequency performance of the final substrate S. However, the present invention is not limited to a base substrate 3 exhibiting such resistivity, and advantages in terms of RF performance are also available when the base substrate 3 exhibits a more typical resistivity of less than 1000 Ωcm, approximately several hundred Ωcm, or 100 Ωcm or less.

[0022] For reasons of availability and cost, the base substrate 3 is preferably made of silicon, and especially single-crystal silicon. For example, it can be a CZ substrate containing a small amount of interstitial oxygen, and as is well known, this type of substrate has a resistivity that can be greater than 1000 Ωcm. The base substrate 3 can be formed from another material as an alternative: this material can be, for example, sapphire, silicon carbide, silicon germanium, III-V material, glass, etc. It can also be a more standard single-crystal CZ substrate as an alternative, which has a resistivity of less than 1000 Ωcm, or can be n-doped or p-doped, and can be a CZ substrate containing a large or moderate amount of interstitial oxygen having a resistivity of about 500 Ωcm or less.

[0023] The support substrate 1 also has a trapping layer 2 disposed in direct contact with the base substrate 3. The trapping layer 2 has a resistivity greater than 500 Ωcm, preferably greater than 1000 Ωcm, and more preferably greater than 10 kΩcm. As is well known, the function of the trapping layer is to trap any charge carriers that may be present within the support 1 and to limit their mobility. This is especially true when the substrate S has a semiconductor structure that emits an electromagnetic field penetrating into the support substrate 1, and thus can interact with these charges and make them mobile. The trapping layer 2 typically has a thickness between 1 micron, 15 microns, and even 20 microns.

[0024] The trapping layer 2 can generally consist of a non-single-crystal semiconductor layer exhibiting structural defects such as dislocations, grain boundaries, amorphous regions, gaps, inclusions, pores, and others. These structural defects form traps for any charges flowing through the material, for example, at the locations of incomplete or dangling chemical bonds. Conduction is thus hindered in the trapping layer, resulting in high resistivity.

[0025] For the same reasons of availability and cost already mentioned, the trapping layer 2 is preferably made of polycrystalline silicon. However, it may consist of or comprise other polycrystalline semiconductor materials. Of course, this charge trapping layer 2 may be formed by a different technique than that involving the layer formed from polycrystalline silicon. This layer may also consist of or comprise carbon, or silicon carbide, or an alloy of silicon and carbon, for example, in the form of an intermediate layer inserted into the thickness of the polycrystalline silicon. When the trapping layer 2 consists of silicon carbide or an alloy of silicon and carbon, its thickness is preferably a few nanometers (e.g., 2 nm) to several tens of nanometers (e.g., 50 nm). Alternatively, electric traps may be formed in layer 2 by ion bombardment with a relatively heavy element (e.g., argon) to create crystal defects in the surface portion of the base substrate 3 where charges can be trapped. Also, for example, if the base substrate is made of silicon, it is possible to conceive of a charge trapping layer 2 formed from a porous material by making the surface portion of the base substrate 3 porous. The trapping layer may also comprise a silicon-rich oxide having an atomic silicon concentration of 50% to 99.9%. This silicon-rich oxide may also comprise nitrogen. It may also comprise crystalline silicon content having a size of less than 10 nm, and preferably less than 5 nm. Alternatively, it may have a polycrystalline form and comprise amorphous content.

[0026] In either case, trapping layer 2 exhibits a high resistivity greater than 500 Ωcm. For this purpose, trapping layer 2 is intentionally not doped, i.e., 10 per cubic centimeter. 14 It has a charge carrier dopant concentration of less than a certain number of atoms. It can be enriched with nitrogen or carbon to improve its resistivity properties.

[0027] Returning to the overall description of Figure 3, the support substrate 1 also comprises a dielectric layer 4, which is directly placed on the trapping layer 2. For example, the dielectric layer 4 may consist of or comprise silicon dioxide or silicon nitride. This can also be a stack of these materials. The thickness of the dielectric layer 4 can typically be 10 nm to 10 microns, but in relation to this description, this layer has a greater thickness than 200 nm, preferably 200 nm to 1000 nm.

[0028] The substrate S comprises an upper layer 5 on or in contact with the dielectric layer 4 of the support substrate 1. The thin layer is usually made of single-crystal silicon, but can be made of any other material depending on the nature of the device to be formed thereon. In the fields of electro-optics and photonics, when the substrate S is intended to receive integrated semiconductor components, the thin layer 5 can therefore be made of single-crystal silicon, or any other single-crystal semiconductor material such as germanium, silicon-germanium, or silicon carbide.

[0029] In all cases, and regardless of the properties of the upper layer, it has very little roughness, and its exposed surface exhibits a roughness of less than 0.3 nm in measurements using the root mean square term over a range of 30 microns × 30 microns.

[0030] The ability to produce thick, embedded dielectric substrates (greater than 200 nm) exhibiting both low surface roughness and minimal warpage constitutes a highly noteworthy aspect of the present invention. Furthermore, the substrate has low-density dislocation planes or dislocation lines. These dislocation planes or lines can be measured by inspection equipment implementing deflectometry techniques, such as those described in U.S. Patent No. 7812942. Generally, it is desirable to minimize the total length of these dislocation planes or lines to less than a threshold of, for example, 20 mm, which is indeed the case with the substrate according to the present invention.

[0031] Preparation of the circuit board Next, a method for preparing the substrate shown in Figures 4a to 4d is presented.

[0032] In the first preparation step shown in Figure 4a, the support substrate 1 is prepared. The trapping layer 2 can be fabricated on the base substrate 3 using industry-standard deposition equipment if it is made of polycrystalline silicon or formed from silicon-rich oxides. This may involve RPCVD (Remote Plasma Excited Chemical Vapor Deposition) or PECVD (Plasma Excited Chemical Vapor Deposition). This may also involve LPCVD (Low Pressure Chemical Vapor Deposition). However, as seen above, the formation of the trapping layer on or within the base substrate 3 can be achieved in many other ways, for example, by implanting heavy element species or by making the surface layer of the base substrate 3 porous.

[0033] Optionally, during this preparation step, a thin dielectric layer could be formed on the base substrate 3, for example, by oxidation or deposition of an oxide thickness, before the trapping layer 2 is formed thereon.

[0034] In the second step of the preparation method, shown in Figure 4b, a dielectric layer 4 having a thickness greater than 200 nm is formed. Very commonly, there are numerous options for forming this dielectric layer 4 so that it is embedded in the substrate S at its edges. The dielectric layer may be formed on the support substrate 1 by deposition of the trapping layer 2 or by treatment (e.g., oxidation). It may also be formed on a substrate called a “donor” substrate, which gives rise to the upper layer 5. According to the present invention, and for reasons that will become apparent in the remainder of this description, the dielectric layer 4 is produced on the trapping layer 3 by high-density plasma chemical vapor deposition. This technique carries out the deposition of this dielectric layer 4 and ion sputtering simultaneously. This has the particular advantage of giving rise to a thick layer with low roughness, and thus its formation step can not include smoothing treatments such as polishing. After this step of forming the dielectric layer, the support substrate 1 is provided. This support substrate may have considerable warping, sometimes greater than 60 microns, when the support substrate 1 is circular and has a diameter of 300 mm.

[0035] It should be noted that the method for preparing the support substrate 1 may also include the step of annealing the dielectric layer 4. This annealing, called high-density annealing, is advantageously carried out in a neutral atmosphere. It is performed at a temperature higher than the deposition temperature of the dielectric layer 4, preferably below 1000°C, for a relatively short period of time, less than 1 hour, for example, 30 minutes.

[0036] Continuing the description of the method for manufacturing the final substrate S, the third step following the second step involves the transfer of the upper layer 5, comprising a semiconductor material, to the dielectric layer 4. As is well known, this transfer can be achieved by bonding the free surface of the donor substrate 1' to the support substrate 1, preferably by molecular bonding. Since the dielectric layer 4 is formed in advance on the support substrate 1, the donor substrate 1' itself does not need to be provided by such a dielectric layer. Nevertheless, it is conceivable that the donor substrate may be provided with a fine dielectric thickness (e.g., less than 150 nm). However, preferentially, the donor substrate does not have a dielectric surface layer that is intentionally formed. The properties of the donor substrate 1' are selected according to the desired properties of the upper layer 5, as already described in the previous section of this description. Thus, this can be a substrate formed from a single-crystal semiconductor, such as silicon.

[0037] Following this bonding step, the donor substrate has a reduced thickness to form the upper layer 5, as shown in Figure 4d. This reduction step can be achieved by mechanical and / or chemical thinning. However, preferentially, the thickness of the donor substrate 1' is reduced by fracturing in a pre-formed weakened plane, for example, by the principle of Smart Cut™ technology. According to the principle of this technology, the transfer of the upper layer 5 includes the step of implanting elemental species called “light” elemental species, such as hydrogen and / or helium ions, into the donor substrate 1' to form a weakened plane therein. This weakened plane has a free surface on the donor substrate and defines the upper layer 5 to be transferred. After the donor substrate 1' is bonded to the support substrate 1, the donor substrate is fractured in the weakened plane by applying a force of mechanical or thermal origin.

[0038] After this thinning, or preferably crushing, step, after a step to finish the thin layer 5, such as heat treatment under a reducing or neutral atmosphere, and after the thickness reduction step, sacrificial oxidation may be performed.

[0039] To our great surprise, the applicant has found that when the dielectric layer 4 is formed by high-density plasma chemical vapor deposition, and the finishing step includes annealing carried out in a neutral or reducing atmosphere at a temperature higher than 1050°C for a period longer than 30 minutes, it is possible to obtain both reduced warpage and a satisfactory surface condition.

[0040] Accordingly, Figures 5a and 5b show the measured characteristics of the substrate prepared by the method described above, specifically the warpage of the final substrate S (Figure 5a) and the roughness of the exposed surface of the upper layer 5 (Figure 5b, where this roughness measurement, expressed in nm, is taken by interatomic forces over a measurement range of 30 microns × 30 microns). In Figure 5a, it can be seen that the warpage of the final substrate S can be reduced by increasing the annealing temperature in the finishing step. When this annealing brings the substrate to 1050°C, the warpage is approximately 55 microns, which is already very satisfactory. The results at 1200°C obtained using rapid annealing also allow for a reduction in substrate warpage, but it should be noted that this may increase dislocation-type defects, as mentioned in the introduction to this application.

[0041] Figure 5b also shows, unexpectedly, that after the annealing finishing step was applied, the measured roughness of the upper layer 5 remained stable as the temperature increased and was at a level of less than 0.3 nm in measurements using the root mean square term, and this was also very satisfactory both at the edges of the substrate (symbol "B") and at its center (symbol "C"). It will be recalled that the applicant's preparation observations reported in Figure 2 showed that the roughness of the exposed surface of this upper layer 5 increased with increasing temperature.

[0042] Accordingly, the preparation method according to the present invention utilizes these results to propose various finishing sequences for the finishing step. In all of these possible sequences, there is at least one annealing, designated as “first annealing”, which is performed in a neutral or reducing atmosphere at a temperature higher than 1050°C for a period longer than 30 minutes. In all of these cases, a dielectric layer 4 embedded in the final substrate is also obtained by high-density plasma chemical vapor deposition on the charge trapping layer 2.

[0043] Therefore, the finishing step may include at least one step of thinning the upper layer 5. This at least one thinning step may be performed before and / or after the first annealing. Thus, the finishing sequence performed during the finishing step corresponds to a thinning-annealing, annealing-thinning, or thinning-annealing-thinning sequence. This thinning of the layer may be performed in particular by sacrificial oxidation of the upper layer (i.e., oxidation of the sacrificial thickness of this layer, followed by the removal of this oxidized thickness).

[0044] Furthermore, the finishing steps may include annealing other than the first annealing already described. In a variation of one embodiment, the finishing sequence that may thus be included may include a rapid second annealing, which is performed in a neutral or reducing atmosphere at a temperature higher than 1050°C for a duration of less than 2 minutes. The second annealing may be performed before or after the first annealing.

[0045] The neutral or reducing atmosphere used during the first annealing, and optionally during the second annealing, is preferably composed mainly of or exclusively of argon.

[0046] The temperature for the first annealing can preferably be selected within the range of 1050°C to 1100°C so as not to adversely affect the quality of the trapping layer 2. Excessive thermal history during the finishing steps can effectively result in modifications to its crystallinity and electrical effectiveness. To further improve the smoothing effect of this first annealing, the apparatus in which this annealing is performed can follow the teachings in the document of European Patent No. 3011590, even to the lower end of the preferred temperature range.

[0047] To avoid dislocation-type defects in the final substrate, it would be preferable to avoid introducing rapid annealing into the finishing sequence, although this cannot be completely eliminated.

[0048] Figure 6 illustrates the advantages of using "long-duration" annealing only in the finishing sequence, rather than "rapid" annealing, from the perspective of dislocation-type defects. The left portion of this figure shows a map of dislocations in the final substrate, in contrast to a finishing sequence that includes annealing performed in a neutral or reducing atmosphere at a temperature above 1050°C for a period longer than 30 minutes, without any rapid annealing. This left portion shows the absence or substantial absence of such defects.

[0049] The right-hand portion of this figure represents a map of dislocations present in the final substrate after rapid heat treatment. Compared to the left-hand portion, the differences in terms of defects will be easily noticeable.

[0050] These maps of dislocations can be prepared by inspection equipment that implements deflectometry techniques, such as those described in U.S. Patent No. 7812942.

[0051] Regardless of the finishing sequence used, the preparation method described herein makes it possible to propose a final substrate comprising, in sequence and in contact with one another, the following: a silicon-based, for example, semiconductor-based upper layer having a thickness greater than 200 nm, a dielectric layer, a charge trapping layer, and a base substrate. The dielectric layer may, in particular, have a thickness of 400 nm or more. The exposed surface of the semiconductor-based upper layer of this final substrate has a roughness of less than 0.3 nm, measured using the root mean square term, over a range of 5 microns × 5 microns, and a warpage of less than 60 microns, preferably less than 40 microns. It is advantageous that this final substrate has a total length of dislocation planes or dislocation lines of less than 20 mm.

[0052] Of course, the present invention is not limited to the embodiments described, and modifications thereto may be applied without departing from the scope of the invention as defined in the patent claims.

Claims

1. A method for preparing a final substrate (S) having a thick embedded dielectric layer (4), The steps include preparing a support substrate (1) which has a charge trapping layer (2) placed on a base substrate (3), The steps include forming the dielectric layer (4) having a thickness greater than 200 nm on the charge trapping layer (2), The steps include transferring the upper layer (5) containing the semiconductor material to the dielectric layer (4), The steps include finishing the exposed surface of the upper layer (5), In a method including, The preparation method is characterized in that the step of forming the dielectric layer (4) is carried out by high-density plasma chemical vapor deposition, and the finishing step comprises a first annealing carried out in a neutral or reducing atmosphere at a temperature higher than 1050°C for a duration longer than 30 minutes.

2. The preparation method according to claim 1, wherein the step of forming the dielectric layer (4) includes high-density annealing of the support substrate after high-density plasma chemical vapor deposition of the dielectric layer.

3. The preparation method according to claim 2, wherein the high-density annealing is performed in a neutral atmosphere at a temperature of less than 1000°C and for a duration of less than 1 hour.

4. The preparation method according to any one of claims 1 to 3, wherein the finishing step includes thinning the upper layer (5) before and / or after the first annealing.

5. The preparation method according to any one of claims 1 to 4, wherein the finishing step comprises a second annealing, the second annealing being carried out in a neutral or reducing atmosphere at a temperature higher than 1050°C for a duration of less than two minutes.

6. The preparation method according to any one of claims 1 to 5, wherein the neutral or reducing atmosphere for the first annealing comprises or consists of argon.

7. The preparation method according to any one of claims 1 to 6, wherein the step of forming the dielectric layer (4) does not include polishing the exposed surface of the dielectric layer (4).

8. The preparation method according to any one of claims 1 to 7, wherein the semiconductor material of the upper layer (5) is silicon.

9. The preparation method according to any one of claims 1 to 8, wherein the dielectric layer (4) is made of silicon dioxide.

10. The preparation method according to any one of claims 1 to 9, wherein the dielectric layer (4) has a thickness of 400 nm or more.

11. The method according to any one of claims 1 to 10, wherein the step of transferring the upper layer includes injecting an element species called a "light" element species into the donor substrate (1') to form a weakened plane therein, joining the donor substrate to the support substrate (1), and crushing the donor substrate within the weakened plane.

12. A final substrate (S) comprising an upper layer (5) made of a semiconductor material, a dielectric layer (4) having a thickness greater than 200 nm, a charge trapping layer (2), and a base substrate (3) in a continuous manner and in contact with each other, characterized in that the final substrate (S) has a warp of less than 60 microns, preferably less than 40 microns, and the exposed surface of the upper layer (5) exhibits a roughness of less than 0.3 nm in a 30 micron × 30 micron area, measured using the root mean square term.

13. The final substrate (S) according to claim 12, wherein the upper layer (5) is made of silicon.

14. The final substrate (S) according to claim 12 or 13, wherein the dielectric layer (4) is made of silicon oxide.

15. The final substrate (S) according to any one of claims 12 to 14, having a total length of dislocation plane or dislocation line of less than 20 mm as measured by deflectometry.

Images