Display boards and display devices

Abstract

A display board comprising a base, a plurality of first light-emitting units and a plurality of second light-emitting units located in a first display area, a plurality of first pixel circuits located in the first display area, and a plurality of second pixel circuits located in a second display area. Each first light-emitting unit includes at least one first light-emitting element, and each second light-emitting unit includes at least one second light-emitting element. At least one first light-emitting unit is adjacent to at least one second light-emitting unit. At least one first pixel circuit is electrically connected to at least one first light-emitting element and configured to drive the light emission of at least one first light-emitting element. At least one second pixel circuit is electrically connected to at least one second light-emitting element and configured to drive the light emission of at least one second light-emitting element.

Description

Technical Field

[0001] (Cross - reference to related applications) This application claims the priority of a Chinese patent application with the application number 202310722592.7 and the invention title "Display Substrate and Display Device", which was filed with the Chinese Patent Office on June 16, 2023, and the content thereof should be understood to be incorporated herein by reference.

[0002] This text relates to the field of display technology, but is not limited thereto, and particularly relates to display substrates and display devices.

Background Art

[0003] Organic light - emitting diodes (OLEDs, Organic Light Emitting Diodes) and quantum dot light - emitting diodes (QLEDs, Quantum - dot Light Emitting Diodes) are active light - emitting display devices, and have advantages such as self - luminous, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, lightweight, bendable, and low cost.

Summary of the Invention

Means for Solving the Problems

[0004] The following is an overview of the main topics described in detail in this text. This overview is not intended to limit the scope of protection of the claims.

[0005] In embodiments of the present disclosure, display substrates and display devices are provided.

[0006] In one embodiment, this embodiment provides a display board comprising a base, a plurality of first light-emitting units, a plurality of second light-emitting units, a plurality of first pixel circuits, and a plurality of second pixel circuits. The base includes a first display area and a second display area located on at least one side of the first display area. The plurality of first light-emitting units and the plurality of second light-emitting units are located in the first display area, the first light-emitting units include at least one first light-emitting element, the second light-emitting units include at least one second light-emitting element, and the first light-emitting units are adjacent to at least one second light-emitting unit. The plurality of first pixel circuits are located in the first display area, and at least one of the plurality of first pixel circuits is electrically connected to the at least one first light-emitting element and configured to drive the emission of light from the at least one first light-emitting element. The plurality of second pixel circuits are located in the second display area, and at least one of the plurality of second pixel circuits is electrically connected to the at least one second light-emitting element and configured to drive the emission of light from the at least one second light-emitting element.

[0007] In some exemplary embodiments, the plurality of first light-emitting units and the plurality of second light-emitting units are spaced apart along at least one of the first and second directions, the first direction intersects the second direction.

[0008] In some exemplary embodiments, in the first direction, one first light-emitting unit and one second light-emitting unit are spaced apart, and in the second direction, one first light-emitting unit and one second light-emitting unit are spaced apart.

[0009] In some exemplary embodiments, the plurality of first light-emitting units include a plurality of rows of first light-emitting units, and each row of first light-emitting units includes a plurality of first light-emitting units arranged sequentially along the second direction. The plurality of second light-emitting units include a plurality of rows of second light-emitting units, and each row of second light-emitting units includes a plurality of second light-emitting units arranged sequentially along the second direction. In the first direction, one row of first light-emitting units and one row of second light-emitting units are spaced apart.

[0010] In some exemplary embodiments, the plurality of first light-emitting units include multiple rows of first light-emitting units, and each row of first light-emitting units includes multiple first light-emitting units arranged sequentially along the first direction. The plurality of second light-emitting units include multiple rows of second light-emitting units, and each row of second light-emitting units includes multiple second light-emitting units arranged sequentially along the first direction. In the second direction, one row of first light-emitting units and one row of second light-emitting units are spaced apart.

[0011] In some exemplary embodiments, adjacent first and second light-emitting units are aligned in the first direction, and adjacent first and second light-emitting units are aligned in the second direction, or adjacent first and second light-emitting units are misaligned in the second direction.

[0012] In some exemplary embodiments, the ratio of the light-emitting areas of the second light-emitting element and the first light-emitting element emitting light of the same color is less than 1.

[0013] In some exemplary embodiments, the number of first light-emitting elements included in at least one first light-emitting unit is the same as the number of second light-emitting elements included in at least one second light-emitting unit.

[0014] In some exemplary embodiments, the at least one first light-emitting unit includes four first light-emitting elements, which are a first light-emitting element that emits light of one first color, a first light-emitting element that emits light of one second color, and a first light-emitting element that emits light of two third colors. The at least one second light-emitting unit includes four second light-emitting elements, which are a second light-emitting element that emits light of one first color, a second light-emitting element that emits light of one second color, and a second light-emitting element that emits light of two third colors.

[0015] In some exemplary embodiments, the plurality of first light-emitting elements and plurality of second light-emitting elements in the first display area are arranged in multiple rows and multiple columns. In at least one first light-emitting unit, the two first light-emitting elements that emit third-color light are arranged in the same column, the first light-emitting element that emits first-color light and the first light-emitting element that emits second-color light are arranged in the same column, and the four first light-emitting elements of the first light-emitting unit are arranged in different rows. In at least one second light-emitting unit, the two second light-emitting elements that emit third-color light are arranged in the same column, the second light-emitting element that emits first-color light and the second light-emitting element that emits second-color light are arranged in the same column, and the four first light-emitting elements of the second light-emitting unit are arranged in different rows.

[0016] In some exemplary embodiments, the plurality of first light-emitting elements and plurality of second light-emitting elements in the first display area are arranged in multiple rows and multiple columns. In at least one first light-emitting unit, the first light-emitting elements that emit two third-color light are arranged in the same row, the first light-emitting element that emits first-color light and the first light-emitting element that emits second-color light are arranged in the same row, and the four first light-emitting elements of the first light-emitting unit are arranged in different columns. In at least one second light-emitting unit, the second light-emitting elements that emit two third-color light are arranged in the same row, the first light-emitting element that emits first-color light and the second light-emitting element that emits second-color light are arranged in the same row, and the four second light-emitting elements of the second light-emitting unit are arranged in different columns.

[0017] In some exemplary embodiments, four first light-emitting elements in the first light-emitting unit are electrically connected in a one-to-one correspondence to four first pixel circuits, the four first pixel circuits are arranged sequentially along a first direction, and the orthographic projection of each first pixel circuit on the base at least partially overlaps with the orthographic projection of the connected first light-emitting elements on the base.

[0018] In some exemplary embodiments, the four first pixel circuits are arranged symmetrically with respect to a first midline along the first direction of the four first pixel circuits, the first and second first pixel circuits in the four first pixel circuits are arranged symmetrically with respect to a second midline along the first direction of the two first pixel circuits, and the third and fourth first pixel circuits are arranged symmetrically with respect to a third midline along the first direction of the two first pixel circuits.

[0019] In some exemplary embodiments, the four first pixel circuits are electrically connected to a first power line, and the first power line forms a mesh in the first display area.

[0020] In some exemplary embodiments, in a direction perpendicular to the display substrate, the display substrate includes a circuit structure layer located on the base, the circuit structure layer includes a plurality of first pixel circuits and a plurality of second pixel circuits, and each pixel circuit in the plurality of first pixel circuits and the plurality of second pixel circuits includes at least one first type transistor, at least one second type transistor and a memory capacitor. The circuit structure layer includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer and a sixth conductive layer, which are set on the base. The first semiconductor layer includes at least the active layer of the first type transistor of the pixel circuit, the first conductive layer includes at least the gate electrode of the first type transistor of the pixel circuit and the first electrode of the memory capacitor, the second conductive layer includes at least the second electrode of the memory capacitor of the pixel circuit, the second semiconductor layer includes at least the active layer of the second type transistor of the pixel circuit, the third conductive layer includes at least the gate electrode of the second type transistor of the pixel circuit, the fourth conductive layer includes at least a plurality of connection electrodes, the fifth conductive layer includes at least a plurality of data lines, and the sixth conductive layer includes at least the first power line.

[0021] In some exemplary embodiments, the first display area includes a plurality of first sub-areas and a plurality of second sub-areas, wherein at least one first sub-area in the plurality of first sub-areas is provided with at least one first light-emitting unit, and at least one second sub-area in the plurality of second sub-areas is provided with at least one second light-emitting unit. The second conductive layer further includes a first scan line, a light-emitting control line, a first reset control line, and a second reset control line electrically connected to the first pixel circuit, the first scan line, the light-emitting control line, the first reset control line, and the second reset control line extending along a first direction. In a second direction, the first scan line and the first reset control line bypass from one side of the second sub-area, the light-emitting control line and the second reset control line bypass from the other side of the second sub-area, and the second direction intersects the first direction.

[0022] In some exemplary embodiments, the first display area includes a plurality of first sub-areas and a plurality of second sub-areas, wherein at least one first sub-area in the plurality of first sub-areas is provided with at least one first light-emitting unit, and at least one second sub-area in the plurality of second sub-areas is provided with at least one second light-emitting unit. The third conductive layer further includes a first initial signal line, a second initial signal line, a third initial signal line, and a second scan line electrically connected to the first pixel circuit, the first initial signal line, the second initial signal line, the third initial signal line, and the second scan line extending along a first direction. In a second direction, the first initial signal line and the second scan line bypass from one side of the second sub-area, the second initial signal line and the third initial signal line bypass from the other side of the second sub-area, and the second direction intersects the first direction.

[0023] In some exemplary embodiments, the ratio of the first light-emitting units to the second light-emitting units in the first display area is 0.8 to 1.2.

[0024] In some exemplary embodiments, the light transmittance of the first display area is greater than that of the second display area. The display substrate further includes a plurality of third light-emitting elements and a plurality of third pixel circuits located in the second display area, wherein at least one third pixel circuit in the plurality of third pixel circuits is electrically connected to at least one third light-emitting element in the plurality of third light-emitting elements and is configured to drive the emission of light from the at least one third light-emitting element. The plurality of second pixel circuits are spaced apart from the plurality of third pixel circuits.

[0025] In some exemplary embodiments, the orthographic projection of the at least one first pixel circuit on its base coincides with the orthographic projection of the at least one first light-emitting element on its base. The at least one second pixel circuit is electrically connected to the at least one second light-emitting element via at least one conductive connection line, and the orthographic projection of the at least one second pixel circuit on its base does not coincide with the orthographic projection of the at least one second light-emitting element on its base.

[0026] In some exemplary embodiments, the orthographic projection of the at least one conductive connection line on the base overlaps with the orthographic projection of the at least one first pixel circuit on the base.

[0027] In other aspects, the present embodiment provides a display device, including the display substrate as described above and a sensor located on the non-display surface side of the display substrate, and the orthographic projection of the sensor on the display substrate at least partially overlaps with the first display area of the display substrate.

[0028] Other aspects can be understood after reading and understanding the drawings and the detailed description.

[0029] The drawings are provided for understanding the technical solutions of the present application, are part of the specification, are used to interpret the technical solutions of the present application together with the embodiments of the present application, and are not intended to limit the technical solutions of the present application.

Brief Description of the Drawings

[0030] [Figure 1] It is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. [Figure 2] It is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 3] It is an operation timing diagram of the pixel circuit according to FIG. 2. [Figure 4A] It is a partial schematic diagram of a first display area according to at least one embodiment of the present disclosure. [Figure 4B] It is a partial schematic diagram of a first display area according to at least one embodiment of the present disclosure. [Figure 5] It is a schematic diagram of the connection relationship between a light-emitting element and a pixel circuit according to at least one embodiment of the present disclosure. [Figure 6] It is a partial plan schematic diagram of a first display area according to at least one embodiment of the present disclosure. [Figure 7A] It is a schematic diagram of a first display area after forming a first semiconductor layer in FIG. 6. [Figure 7B]This is a schematic diagram of one of the first sub-areas in Figure 7A. [Figure 8A] Figure 6 is a schematic diagram of the first display area after the formation of the first conductive layer. [Figure 8B] This is a schematic diagram of the first conductive layer in Figure 8A. [Figure 8C] This is a schematic diagram of one of the first sub-areas in Figure 8A. [Figure 9A] Figure 6 is a schematic diagram of the first display area after the formation of the second conductive layer. [Figure 9B] This is a schematic diagram of the second conductive layer in Figure 9A. [Figure 9C] This is a schematic diagram of one of the first sub-areas in Figure 9A. [Figure 10A] This is a schematic diagram of the first display area after the formation of the second semiconductor layer in Figure 6. [Figure 10B] This is a schematic diagram of the second semiconductor layer in Figure 10A. [Figure 10C] This is a schematic diagram of one of the first sub-areas in Figure 10A. [Figure 11A] Figure 6 is a schematic diagram of the first display area after the formation of the third conductive layer. [Figure 11B] This is a schematic diagram of the third conductive layer in Figure 11A. [Figure 11C] This is a schematic diagram of one of the first sub-areas in Figure 11A. [Figure 12] Figure 6 is a schematic diagram of one of the first sub-areas after the formation of the fifth insulating layer. [Figure 13A] Figure 6 is a schematic diagram of the first display area after the formation of the fourth conductive layer. [Figure 13B] This is a schematic diagram of the fourth conductive layer in Figure 13A. [Figure 13C] This is a schematic diagram of one of the first sub-areas in Figure 13A. [Figure 14] Figure 6 is a schematic diagram of one of the first sub-areas after the formation of the seventh insulating layer. [Figure 15A] Figure 6 is a schematic diagram of the first display area after the formation of the fifth conductive layer. [Figure 15B] This is a schematic diagram of the fifth conductive layer in Figure 15A. [Figure 15C] This is a schematic diagram of one of the first sub-areas in Figure 15A. [Figure 16] Figure 6 is a schematic diagram of one of the first sub-areas after the formation of the eighth insulating layer. [Figure 17A] Figure 6 is a schematic diagram of the first display area after the formation of the sixth conductive layer. [Figure 17B] This is a schematic diagram of the sixth conductive layer in Figure 17A. [Figure 17C] This is a schematic diagram of one of the first sub-areas in Figure 17A. [Figure 18] This is a schematic diagram of the first display area after the ninth insulating layer has been formed in Figure 6. [Figure 19A] Figure 6 is a schematic diagram of the first display area after the conductive connecting layer has been formed. [Figure 19B] This is a schematic diagram of the conductive connecting layer in Figure 19A. [Figure 20] Figure 6 is a schematic diagram of the first display area after the anode layer has been formed. [Figure 21] This is another illustrative diagram of the first display area relating to at least one embodiment of the present disclosure. [Figure 22] This is another illustrative diagram of the first display area relating to at least one embodiment of the present disclosure. [Figure 23] This is another illustrative diagram of the first display area relating to at least one embodiment of the present disclosure. [Figure 24] This is another illustrative diagram of the first display area relating to at least one embodiment of the present disclosure. [Figure 25] This is another illustrative diagram of the first display area relating to at least one embodiment of the present disclosure. [Figure 26] This is another illustrative diagram of the first display area relating to at least one embodiment of the present disclosure. [Figure 27] This is another illustrative diagram of the first display area relating to at least one embodiment of the present disclosure. [Figure 28]This is another illustrative diagram of the first display area relating to at least one embodiment of the present disclosure. [Figure 29] This is another illustrative diagram of the first display area relating to at least one embodiment of the present disclosure. [Figure 30] This is another illustrative diagram of the first display area relating to at least one embodiment of the present disclosure. [Figure 31] This is another illustrative diagram of the first display area relating to at least one embodiment of the present disclosure. [Figure 32] This is another illustrative diagram of the first display area relating to at least one embodiment of the present disclosure. [Figure 33] This is another illustrative diagram of the first display area relating to at least one embodiment of the present disclosure. [Figure 34] This is another illustrative diagram of the first display area relating to at least one embodiment of the present disclosure. [Figure 35] This is another illustrative diagram of the first display area relating to at least one embodiment of the present disclosure. [Figure 36] This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. [Modes for carrying out the invention]

[0031] The embodiments of this disclosure will be described in detail below with reference to the drawings. The embodiments can be carried out in many different forms. The methods and content can be converted to other forms without departing from the gist and scope of this disclosure, so as can be easily understood by those skilled in the art. Accordingly, this disclosure should not be construed as being limited only to the descriptions of the embodiments below. Where there is no conflict, the embodiments and features of the embodiments of this disclosure can be combined with each other.

[0032] In the drawings, for clarity, the size, layer thickness, or area of ​​one or more components may be shown in an enlarged manner. Therefore, one embodiment of the present disclosure is not limited to such size, and the shape and size of one or more components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically represent ideal examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0033] In this specification, ordinal numbers such as “first,” “second,” and “third” are used to avoid confusion of constituent elements and do not limit them in terms of quantity. The term “plural” in this disclosure refers to two or more quantities.

[0034] In this specification, for convenience, the positions of components are described with reference to the drawings using terms indicating orientation or positional relationships such as "center," "top," "bottom," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside." This is for the purpose of describing and simplifying this specification, and is not intended to indicate or suggest that the described apparatus or element has a specific orientation or must be configured and operated in a specific orientation. Therefore, it is not intended to limit this disclosure. The positional relationships of components may be appropriately changed depending on the orientation of the component being described. Therefore, the terms used may be appropriately changed in some cases, not limited to those described in the specification.

[0035] In this specification, unless explicitly stated or limited, the terms “attach,” “connect,” and “connect” should be understood broadly. For example, this could be a fixed connection, a removable connection, or an integrated connection; a mechanical connection, or a connection; a direct connection, an indirect connection via a linker, or internal communication between two elements. Those skilled in the art will understand the meaning of these terms in this disclosure depending on the specific circumstances.

[0036] In this specification, “electrically connected” includes cases where components are connected via an element having an electrical function. The “element having an electrical function” is not particularly limited and only needs to be capable of transmitting electrical signals between the connected components. Examples of “elements having an electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and many other types of elements with functions.

[0037] In this specification, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to the region through which current primarily flows.

[0038] In this specification, the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode. When using transistors with opposite polarity, or when the direction of current changes during operation in the circuit, the functions of the "source electrode" and the "drain electrode" may be converted to each other. Therefore, in this specification, the "source electrode" and the "drain electrode" may be converted to each other. The gate electrode may also be further referred to as the control electrode.

[0039] In this specification, "parallel" refers to a state in which the angle formed by two straight lines is -10° or greater and 10° or less, and therefore also includes a state in which the angle is -5° or greater and 5° or less. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is 80° or greater and 100° or less, and therefore also includes a state in which the angle is 85° or greater and 95° or less.

[0040] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined and may be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons, and small deformations due to tolerances may exist, such as chamfers, arcs, and other deformations.

[0041] In this disclosure, "light transmittance" refers to the ability of light rays to pass through a medium, and is the percentage of the light beam passing through a transparent or translucent object compared to the incident light beam.

[0042] In this disclosure, "approximately" and "about" do not strictly define boundaries and allow for a range of error between the process and measurement. In this disclosure, "about the same" means that the difference in numerical values ​​is within 10%.

[0043] In this disclosure, "A extends along direction B" means that A includes a main body and secondary parts connected to the main body, the main body is a line, line segment or elongated object, the main body extends along direction B, and the length of the main body extending along direction B is greater than the length of the secondary parts extending in other directions. In all instances in this disclosure, "A extends along direction B" means "the main body of A extends along direction B."

[0044] With the continuous development of display technology, display equipment is typically equipped with cameras to meet the demands of image capture or facial recognition. To maximize screen-to-body ratio, technologies such as notch displays, drop-shaped displays, and punch-hole displays have emerged. These technologies create a perforation in a localized area of ​​the display area and place the camera below the perforation, thereby reducing the area occupied by the camera and improving screen-to-body ratio. However, these technologies require the removal of a portion of the display area, resulting in a portion of the screen being unusable and preventing further improvement of screen-to-body ratio. To achieve true full-screen display while avoiding perforation of the display area and ensuring the practicality of the display substrate, the bottom camera area typically employs either an external pixel circuit placement method or an internal pixel circuit placement method.

[0045] The external pixel circuit placement method refers to a method of improving the light transmittance of the camera area below the screen by placing the pixel circuit, which is connected to the light-emitting element in the camera area below the screen, in the display area, thereby separating the light-emitting element and the pixel circuit. Since the pixel circuit is not installed in the camera area below the screen, there are no other shielding layers in this area other than the anode of the light-emitting element, and high light transmittance can be achieved. However, in this method, the pixel circuit and the light-emitting element must be electrically connected via conductive connection lines, and the size (e.g., hole diameter) of the camera area below the screen of a display substrate using the external pixel circuit placement method is limited by the space available for the conductive connection lines. Increasing the hole diameter of the camera area below the screen requires the addition of a masking process for the conductive connection lines, which increases costs. Furthermore, the material used for the conductive connection lines is usually a transparent conductive material, such as indium tin oxide (ITO). Because ITO has a high sheet resistance, the conductive connection lines are heavily loaded, which easily affects the brightness of the light-emitting element in the camera area below the screen, reducing the brightness of the camera area below the screen and causing display defects in the camera area below the screen, such as vertical display defects (Mura).

[0046] The pixel circuit integration method refers to the placement of light-emitting elements and the pixel circuits connected to them in the camera area below the screen. Compared to the external pixel circuit placement method, the integrated method eliminates the need for long conductive connection wires between the pixel circuits and light-emitting elements in the camera area below the screen, thus avoiding display defects in the camera area caused by conductive connection wires. Furthermore, the integrated method does not limit the size of the camera area below the screen, and can support camera areas with large apertures. However, in display boards employing the pixel circuit integration method, the anode of the light-emitting element in the camera area below the screen cannot completely block the pixel circuit, thus affecting the light transmittance of the camera area below the screen.

[0047] This embodiment provides a display board and a display device that can support increasing the size of the camera area below the screen while ensuring the light transmittance of the camera area below the screen.

[0048] This embodiment provides a display board comprising a base, a plurality of first light-emitting units, a plurality of second light-emitting units, a plurality of first pixel circuits, and a plurality of second pixel circuits. The base includes a first display area and a second display area located on at least one side of the first display area. The plurality of first light-emitting units and the plurality of second light-emitting units are located in the first display area, with each first light-emitting unit including at least one first light-emitting element, and each second light-emitting unit including at least one second light-emitting element, and each first light-emitting unit being adjacent to at least one second light-emitting unit. The plurality of first pixel circuits are located in the first display area, and at least one first pixel circuit in the plurality of first pixel circuits is electrically connected to at least one first light-emitting element and configured to drive the emission of light from the at least one first light-emitting element. The plurality of second pixel circuits are located in the second display area, and at least one second pixel circuit in the plurality of second pixel circuits is electrically connected to at least one second light-emitting element and configured to drive the emission of light from the at least one second light-emitting element.

[0049] The display board according to this embodiment employs a method that combines external placement and internal placement of pixel circuits, thereby ensuring the light transmittance of the first display area and supporting an increase in the size of the first display area.

[0050] In some exemplary embodiments, the plurality of first light-emitting units and the plurality of second light-emitting units may be spaced apart along at least one of the first and second directions. The first direction intersects the second direction. For example, the first direction may be perpendicular to the second direction. In some examples, the plurality of first light-emitting units and the plurality of second light-emitting units may be spaced apart in either the first or second direction. For example, in the first direction, one first light-emitting unit and one second light-emitting unit may be spaced apart, and in the second direction, one first light-emitting unit and one second light-emitting unit may be spaced apart. In other examples, the plurality of first light-emitting units and the plurality of second light-emitting units may be spaced apart along only the first or second direction. By spaced apart the first and second light-emitting units in this example, light-emitting elements with externally located pixel circuits and light-emitting elements with built-in pixel circuits can be rationally laid out, achieving an optimal combination of light transmittance and size for the first display area, thereby improving the performance and user experience of the display board. Furthermore, by installing the first light-emitting unit and the second light-emitting unit with a gap between them, brightness compensation between the first and second light-emitting elements can be facilitated, thereby improving the brightness uniformity of the first display area.

[0051] In some exemplary embodiments, the ratio of the light-emitting areas of the second and first light-emitting elements emitting light of the same color may be less than 1. In some examples, the ratio of the light-emitting areas of the second and first light-emitting elements emitting light of the same color may be 0.4 to 0.8, for example, about 0.5. This example improves the situation where the brightness is dim due to the external placement of the pixel circuit of the second light-emitting element by reducing the light-emitting area of ​​the second light-emitting element.

[0052] In some exemplary embodiments, the number of first light-emitting elements in at least one first light-emitting unit may be the same as the number of second light-emitting elements in at least one second light-emitting unit. In some examples, at least one first light-emitting unit may include four first light-emitting elements, each emitting light of one first color, one first light-emitting element emitting light of one second color, and two first light-emitting elements emitting light of two third colors. At least one second light-emitting unit may include four second light-emitting elements, each emitting light of one first color, one second light-emitting element emitting light of one second color, and two second light-emitting elements emitting light of two third colors. However, this embodiment is not limited thereto. For example, the first light-emitting unit and the second light-emitting unit may each contain three light-emitting elements. In this example, by making the number of light-emitting elements in the first and second light-emitting units the same, brightness compensation between adjacent light-emitting elements emitting light of the same color can be facilitated, contributing to brightness uniformity of the first display area.

[0053] In some exemplary embodiments, the ratio of the first light-emitting units to the second light-emitting units in the first display area may be 0.8 to 1.2, or for example, about 1. The ratio of the number of first light-emitting units to the second light-emitting units in this example can effectively reduce the number of conductive connection lines and wiring space connected to the externally located pixel circuit, and can support an increase in the size of the first display area.

[0054] In some exemplary embodiments, the light transmittance of the first display area may be greater than that of the second display area. The display substrate may further include a plurality of third light-emitting elements and a plurality of third pixel circuits located in the second display area. At least one third pixel circuit is electrically connected to at least one third light-emitting element and configured to drive the emission of light from the at least one third light-emitting element. The plurality of second pixel circuits may be spaced apart from the plurality of third pixel circuits. In this example, the display effect of the display substrate can be ensured by providing a second display area with a light transmittance less than that of the first display area.

[0055] In some examples, the sum of the number of first and second light-emitting elements in a unit area may be less than or equal to the number of third light-emitting elements in a unit area. Alternatively, the density of first and second light-emitting elements in a first display area may be less than or equal to the density of third light-emitting elements in a second display area. Alternatively, the pixel density (PPI, Pixels Per Inch) of a first display area may be less than or equal to the pixel density of a second display area.

[0056] The implementation of this embodiment will be explained below with several examples.

[0057] Figure 1 is a schematic diagram of a display board according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 1, the display board may include a display area AA and a peripheral area BB located outside the display area AA. The display area AA of the display board may include at least a first display area A1 and a second display area A2. The second display area A2 may at least partially surround the first display area A1. For example, the second display area A2 may surround the periphery of the first display area A1. The peripheral area BB may surround the periphery of the second display area A2. However, this embodiment is not limited thereto.

[0058] In some examples, as shown in Figure 1, the first display area A1 may be a light-transmitting display area and may further be referred to as the Full Display With Camera (FDC) area. The second display area A2 may further be referred to as the normal display area. For example, the orthographic projection of a sensor (e.g., hardware such as a camera) on the display board may be located within the first display area A1 of the display board. In some examples, as shown in Figure 1, the first display area A1 may be circular, and the size of the orthographic projection of the sensor on the display board may be less than or equal to the size of the first display area A1. However, this embodiment is not limited thereto. In other examples, the first display area A1 may be rectangular, and the size of the orthographic projection of the sensor on the display board may be less than or equal to the size of the inscribed circle of the first display area A1.

[0059] In some examples, as shown in Figure 1, the first display area A1 may be located in the middle of the top of the display area AA. The second display area A2 may surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area A1 may be located in other positions such as the upper left corner, lower left corner, lower right corner, or upper right corner of the display area AA. For example, the second display area A2 may surround at least one side of the first display area A1.

[0060] In some examples, as shown in Figure 1, the display area AA may be a rectangle, for example, a rounded rectangle. The first display area A1 may be circular or elliptical. However, this embodiment is not limited to these shapes. For example, the first display area A1 may be a rectangle, a semicircle, a pentagon, or other shape.

[0061] In some examples, display area AA may have multiple subpixels. At least one subpixel may include a pixel circuit and a light-emitting element. The pixel circuit may be configured to drive the connected light-emitting element. For example, the pixel circuit may be configured to provide a drive current to drive the light emission of the light-emitting element. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0062] In some examples, the light-emitting element may be any one of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element may be an OLED, which can emit red, green, blue, or white light under the drive of the corresponding pixel circuit. The emission color of the light-emitting element can be determined according to the requirements. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited thereto.

[0063] Figure 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit in this example is described as having an 8T1C structure. In some examples, as shown in Figure 2, the pixel circuit in this example may include eight transistors (i.e., first transistors T1 to eighth transistors T8) and one memory capacitor Cst. The first transistor T1 may be further referred to as the first reset transistor, the second transistor T2 may be further referred to as the threshold compensation transistor, the third transistor T3 may be further referred to as the drive transistor, the fourth transistor T4 may be further referred to as the data writing transistor, the fifth transistor T5 may be further referred to as the first light emission control transistor, the sixth transistor T6 may be further referred to as the second light emission control transistor, the seventh transistor T7 may be further referred to as the second reset transistor, and the eighth transistor T8 may be further referred to as the third reset transistor. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer placed between the anode and the cathode.

[0064] In some examples, the first transistor T1 and the third to eighth transistors T3 to T8 may be first-type transistors, such as P-type transistors, and the second transistor T2 may be a second-type transistor, such as an N-type transistor. However, this embodiment is not limited to this. For example, all of the transistors in the pixel circuit may be either P-type transistors or N-type transistors.

[0065] In some examples, the first type of transistors in the pixel circuit (e.g., including the first transistor T1 and the third to eighth transistors T8) may be low-temperature polysilicon film transistors, while the second type of transistors in the pixel circuit (e.g., including the second transistor T2) may be oxide film transistors. The active layer of the low-temperature polysilicon film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide film transistor is made of oxide semiconductor. Low-temperature polysilicon film transistors have advantages such as high mobility and fast charging, while oxide film transistors have advantages such as low leakage current. By integrating low-temperature polysilicon film transistors and oxide film transistors onto a single display substrate, a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate can be formed, and by utilizing the advantages of both, low-frequency driving can be achieved, power consumption can be reduced, and display attributes can be improved.

[0066] In some examples, as shown in Figure 2, the pixel circuit may be electrically connected to a first scan line GL1, a second scan line GL2, a data line DL, a first power line PL1, a second power line PL2, a light emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a first reset control line RST1, and a second reset control line RST2. The first power line PL1 may be configured to provide a constant first voltage signal VDD to the pixel circuit, and the second power line PL2 may be configured to provide a constant second voltage signal VSS to the pixel circuit, wherein the first voltage signal VDD is greater than the second voltage signal VSS. The first scan line GL1 may be configured to provide a first scan signal SCAN1 to the pixel circuit. The second scan line GL2 may be configured to provide a second scan signal SCAN2 to the pixel circuit. The data line DL may be configured to provide a data signal to the pixel circuit. The light emission control line EML may be configured to provide a light emission control signal EM to the pixel circuit. The first reset control line RST1 may be configured to provide a first reset control signal RESET1 to the pixel circuit. The second reset control line may be configured to provide a second reset control signal RESET2 to the pixel circuit.

[0067] In some examples, as shown in Figure 2, the gate electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The gate electrode of the fourth transistor T4 is electrically connected to the first scan line GL1, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2. The gate electrode of the second transistor T2 is electrically connected to the second scan line GL2, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3. The gate electrode of the fifth transistor T5 is electrically connected to the light emission control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power line PL1, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The gate electrode of the sixth transistor T6 is electrically connected to the light emission control line EML, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The gate electrode of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the third node N3. The gate electrode of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The gate electrode of the eighth transistor T8 is electrically connected to the second reset control line RST2, the first electrode of the eighth transistor T8 is electrically connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2. The first electrode of the memory capacitor Cst is electrically connected to the first node N1, and the second electrode of the memory capacitor Cst is electrically connected to the first power line PL1.

[0068] In this example, the first node N1 is the connection point of the memory capacitor Cst, the second transistor T2, and the third transistor T3; the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, the eighth transistor T8, and the third transistor T3; the third node N3 is the connection point of the first transistor T1, the third transistor T3, the second transistor T2, and the sixth transistor T6; and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7, and the light-emitting element EL.

[0069] Figure 3 is an operation timing diagram of the pixel circuit shown in Figure 2. The operation process of the pixel circuit shown in Figure 2 will be explained below with reference to Figure 3. The first transistor T1 and the third transistors T3 to the eighth transistors T8 of the pixel circuit are P-type transistors, and the second transistor T2 is an N-type transistor.

[0070] In some examples, as shown in Figures 2 and 3, the operation process of the pixel circuit may include at least a first stage S1, a second stage S2, a third stage S3, and a fourth stage S4 during the display time of one frame.

[0071] The first stage S1 is called the first reset stage. The second reset control signal RESET2 from the second reset control line RST2 is a low-level signal that turns on the seventh transistor T7 and the eighth transistor T8, and the second scan signal SCAN2 from the second scan line GL2 is a high-level signal that turns on the second transistor T2. The eighth transistor T8 is turned on, and the third initial signal from the third initial signal line INIT3 is provided to the second node N2. The seventh transistor T7 is turned on, and the second initial signal from the second initial signal line INIT2 is provided to the fourth node N4, initializing the fourth node N4. The first scan signal SCAN1 from the first scan line GL1 is a high-level signal, the first reset control signal RESET1 from the first reset control line RST1 is a high-level signal, and the light emission control signal EM from the light emission control line EML is a high-level signal that turns off the fourth transistor T4, the first transistor T1, the fifth transistor T5, and the sixth transistor T6. The light-emitting element (EL) does not emit light at this stage.

[0072] The second stage S2 is called the second reset stage. The first reset control signal RESET1, transmitted by the first reset control line RST1, is a low-level signal, turning on the first transistor T1. The second scan signal SCAN2, transmitted by the second scan line GL2, is a high-level signal, turning on the second transistor T2. With the first transistor T1 and the second transistor T2 turned on, the first initial signal line INIT1 is supplied to the first node N1, initializing the first node N1. The second reset control signal RESET2, transmitted by the second reset control line RST2, is a high-level signal, the first scan signal SCAN1, transmitted by the first scan line GL1, is a high-level signal, and the light emission control signal EM, transmitted by the light emission control line EML, is a high-level signal, turning off the seventh transistor T7, the eighth transistor T8, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. The light-emitting element EL does not emit light during this stage.

[0073] The third stage S3 is called the data writing stage or threshold compensation stage. The first scan signal SCAN1 from the first scan line GL1 is a low-level signal, and the fourth transistor T4 turns on. The second scan signal SCAN2 from the second scan line GL2 is a high-level signal, and the second transistor T2 turns on. In this stage, the first electrode of the memory capacitor Cst is at a low level, and the third transistor T3 turns on. The second transistor T2, the fourth transistor T4, and the third transistor T3 are turned on, and the data voltage Vdata output from the data line DL is provided to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage Vdata output from the data line DL and the threshold voltage of the third transistor T3 is stored in the memory capacitor Cst, and the voltage at the first electrode of the memory capacitor Cst (i.e., the first node N1) is Vdata - |Vth|, where Vdata is the data voltage output from the data line DL and Vth is the threshold voltage of the third transistor T3. The first reset control signal RESET1 from the first reset control line RST1 is a high-level signal, the second reset control signal RESET2 from the second reset control line RST2 is a high-level signal, and the light emission control signal EM from the light emission control line EML is a high-level signal, causing the first transistor T1, the seventh transistor T7, the eighth transistor T8, the fifth transistor T5, and the sixth transistor T6 to be turned off.

[0074] In the fourth stage S4, the light emission control signal EM from the light emission control line EML is switched from a high-level signal to a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The second scan signal SCAN2 from the second scan line GL2 is a low-level signal, turning off the second transistor T2. The first scan signal SCAN1 from the first scan line GL1, the first reset control signal RESET1 from the first reset control line RST1, and the second reset control signal RESET2 from the second reset control line RST2 are high-level signals, turning off the fourth transistor T4, the first transistor T1, the seventh transistor T7, and the eighth transistor T8. The first voltage signal VDD output from the first power line PL1 may provide a drive voltage to the anode of the light-emitting element EL via the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, thereby driving the light emission of the light-emitting element EL.

[0075] During the pixel circuit drive process, the drive current flowing through the third transistor T3 is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage at the first node N1 is Vdata - |Vth|, the drive current of the third transistor T3 is given by the following equation.

[0076] I = K × (Vgs - Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata] 2

[0077] I is the drive current flowing through the third transistor T3, i.e., the drive current that drives the light-emitting element; K is a constant; Vgs is the voltage difference between the gate electrode of the third transistor T3 and the first electrode; Vth is the threshold voltage of the third transistor T3; Vdata is the data voltage output from the data line DL; and VDD is the first voltage signal output from the first power line PL1.

[0078] As can be seen from the above equation, the current flowing through the light-emitting element is not related to the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the third transistor T3. Furthermore, the pixel circuit of this embodiment can improve the display performance of the light-emitting element by improving the display failure situation caused by low frequencies.

[0079] In some examples, as shown in Figure 1, a plurality of first light-emitting elements 21, a plurality of second light-emitting elements 22, and a plurality of first pixel circuits 11 may be installed in the first display area A1 of the display board. At least one first pixel circuit 11 is electrically connected to at least one first light-emitting element 21 and configured to drive the emission of light from at least one first light-emitting element 21. A plurality of second pixel circuits 12, a plurality of third pixel circuits 13, and a plurality of third light-emitting elements 23 may be installed in the second display area A2. The circuit structures of the first pixel circuit 11, second pixel circuit 12, and third pixel circuit 13 in this example may be the same, for example, the 8T1C structure described above. At least one second pixel circuit 12 may be electrically connected to at least one second light-emitting element 22 via at least one conductive connection line 15 and configured to drive the emission of light from at least one second light-emitting element 22. The conductive connection line 15 may extend from the first display area A1 to the second display area A2. At least one third pixel circuit 13 is electrically connected to at least one third light-emitting element 23 and is configured to drive the emission of light from at least one third light-emitting element 23.

[0080] For example, multiple first pixel circuits 11 may be electrically connected in a one-to-one correspondence to multiple first light-emitting elements 21, and one first pixel circuit 11 may be configured to drive one first light-emitting element 21. The orthographic projection of the base of the first light-emitting element 21 will at least partially overlap with the orthographic projection of the base of the connected first pixel circuit 11. Multiple second pixel circuits 12 may be electrically connected in a one-to-one correspondence to multiple second light-emitting elements 22, and one second pixel circuit 12 may be configured to drive one second light-emitting element 22. The orthographic projection of the base of the second light-emitting element 22 may not overlap with the orthographic projection of the base of the connected second pixel circuit 12. Multiple third pixel circuits 13 may be electrically connected in a one-to-one correspondence to multiple third light-emitting elements 23, and one third pixel circuit 13 may be configured to drive one third light-emitting element 23. The orthographic projection of the base of the third light-emitting element 23 will at least partially overlap with the orthographic projection of the base of the connected third pixel circuit 13. However, this embodiment is not limited thereto. In other examples, multiple first pixel circuits may be configured to drive one first light-emitting element, or one first pixel circuit may be configured to drive multiple first light-emitting elements. Furthermore, for example, multiple second pixel circuits may be configured to drive one second light-emitting element, or one second pixel circuit may be configured to drive multiple second light-emitting elements. Furthermore, for example, multiple third pixel circuits may be configured to drive one third light-emitting element, or one third pixel circuit may be configured to drive multiple third light-emitting elements.

[0081] Figures 4A and 4B are schematic local views of a first display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 4A, the first display area may include a plurality of first sub-areas A11 and a plurality of second sub-areas A12. At least one first sub-area A11 is adjacent to at least one second sub-area A12, for example, the first sub-area A11 is adjacent to two second sub-areas A12 in a first direction X and is located between these two second sub-areas A12, and the first sub-area A11 is adjacent to two second sub-areas A12 in a second direction Y and is located between these two second sub-areas A12. The first direction X intersects the second direction Y, for example, the first direction X may be perpendicular to the second direction Y.

[0082] In some examples, as shown in Figure 4A, one first light-emitting unit 2a may be installed in the first sub-area A11, and one second light-emitting unit 2b may be installed in the second sub-area A12. The multiple first light-emitting units 2a and multiple second light-emitting units 2b in the first display area may be arranged in arrays of multiple rows and multiple columns. A row of light-emitting units may include multiple first light-emitting units 2a and multiple second light-emitting units 2b installed at intervals along the first direction X, and a column of light-emitting units may include multiple first light-emitting units 2a and multiple second light-emitting units 2b installed at intervals along the second direction Y. In the first direction X, the first light-emitting units 2a and second light-emitting units 2b are installed with one unit spacing between them, and in the second direction Y, the first light-emitting units 2a and second light-emitting units 2b are installed with one unit spacing between them. For example, one first light-emitting unit 2a may be adjacent to four second light-emitting units 2b. In this example, "A is adjacent to B" means that A and B are close together and there are no other objects of the same type between them. In this example, by installing the first and second light-emitting units with a gap between them in both the first and second directions, it is not only possible to ensure the light transmittance of the first display area, but it is also advantageous for realizing a larger first display area, and further advantageous for improving the brightness uniformity of the first display area by performing brightness compensation.

[0083] In some examples, as shown in Figures 4A and 4B, adjacent first light-emitting units 2a and second light-emitting units 2b are installed aligned in the first direction X, and adjacent first light-emitting units 2a and second light-emitting units 2b are installed aligned in the second direction Y. In this example, "installing A and B aligned in direction C" means that the connecting line between the center positions of A and B in direction C is approximately parallel to direction C.

[0084] In some examples, as shown in Figure 4A, the first light-emitting unit 2a may include at least one first light-emitting element, for example, four first light-emitting elements, and the second light-emitting unit 2b may include at least one second light-emitting element, for example, four second light-emitting elements. The number of first light-emitting elements included in the first light-emitting unit 2a may be the same as the number of second light-emitting elements included in the second light-emitting unit 2b. However, this embodiment is not limited to this. In other examples, the number of first light-emitting elements included in the first light-emitting unit may be greater than the number of second light-emitting elements included in the second light-emitting unit, or the number of first light-emitting elements included in the first light-emitting unit may be less than the number of second light-emitting elements included in the second light-emitting unit. In this example, by making the number of first light-emitting elements included in the first light-emitting unit the same as the number of second light-emitting elements included in the second light-emitting unit, it is easier to control the ratio of first light-emitting elements to second light-emitting elements, which is advantageous for designing brightness compensation between the first and second light-emitting elements.

[0085] In some examples, as shown in Figures 4A and 4B, the multiple light-emitting elements (including multiple first and multiple second light-emitting elements) in the first display area may be arranged in multiple rows and multiple columns. A row of light-emitting elements may include multiple first and multiple second light-emitting elements arranged along a first direction X, and a column of light-emitting elements may include multiple first and multiple second light-emitting elements arranged along a second direction Y. A column of light-emitting units may include four columns of light-emitting elements, and a row of light-emitting units may include two rows of light-emitting elements. For example, a column of light-emitting units may include light-emitting elements in columns d, d+1, d+2, and d+3, and a row of light-emitting units may include light-emitting elements in rows c and c+1, where a, b, c, and d are all integers greater than 0.

[0086] In some examples, as shown in Figures 4A and 4B, a first light-emitting unit 2a may include four first light-emitting elements: a first light-emitting element 21a that emits light of one first color, a first light-emitting element 21b that emits light of one second color, and first light-emitting elements 21c and 21d that emit light of two third colors. The four first light-emitting elements included in the first light-emitting unit 2a may be installed in two rows of light-emitting elements, the first light-emitting element 21a that emits light of the first color and the first light-emitting element 21b that emits light of the second color may be installed in the same row of light-emitting elements, the first light-emitting elements 21c and 21d that emit light of two third colors may be installed in the same row of light-emitting elements, and the four first light-emitting elements may be installed in light-emitting elements in different columns.

[0087] In some examples, as shown in Figures 4A and 4B, one second light-emitting unit 2b may include four second light-emitting elements: a second light-emitting element 22a that emits one first color of light, a second light-emitting element 22b that emits one second color of light, and second light-emitting elements 22c and 22d that emit two third colors of light. The four second light-emitting elements included in one second light-emitting unit 2b may be arranged in two rows of light-emitting elements, the second light-emitting element 22a that emits the first color of light and the second light-emitting element 22b that emits the second color of light may be arranged in the same row of light-emitting elements, the second light-emitting elements 22c and 22d that emit two third colors of light may be arranged in the same row of light-emitting elements, and the four second light-emitting elements may be arranged in different columns of light-emitting elements. The arrangement of the four second light-emitting elements in the second light-emitting unit in this example and the arrangement of the four first light-emitting elements in the first light-emitting unit are substantially the same. The arrangement of the light-emitting elements in this example may be advantageous for designing brightness compensation between the first and second light-emitting elements.

[0088] In some examples, as shown in Figure 4B, in the c-th row of light-emitting elements, the second light-emitting elements 22c and 22d emitting two third-color light and the first light-emitting elements 21c and 21d emitting two third-color light may be arranged periodically along the first direction X, and in the c+1th row of light-emitting elements, the second light-emitting element 22a emitting first-color light, the second light-emitting element 22b emitting second-color light, the first light-emitting element 21a emitting first-color light and the first light-emitting element 21b emitting second-color light may be arranged periodically along the first direction X. In the d-th column of light-emitting elements, the second light-emitting element 22a that emits the first color of light and the first light-emitting element 21b that emits the second color of light may be spaced apart along the second direction X; in the d+1-th column of light-emitting elements, the second light-emitting element 22c (or 22d) that emits the second color of light and the first light-emitting element 21c (or 21d) that emits the third color of light may be spaced apart along the second direction Y; in the d+2-th column of light-emitting elements, the second light-emitting element 22b that emits the second color of light and the first light-emitting element 21a that emits the first color of light may be spaced apart along the second direction Y; and in the d+3-th column of light-emitting elements, the second light-emitting element 22d that emits the second color of light and the first light-emitting element 21d that emits the third color of light may be spaced apart along the second direction Y.

[0089] In some examples, as shown in Figure 4A, the installation order of the first light-emitting element 21a that emits the first color of light and the first light-emitting element 21b that emits the second color of light is reversed in different first light-emitting units located in adjacent rows of light-emitting units. For example, in the first light-emitting unit located in row b, the first light-emitting element 21a that emits the first color of light and the first light-emitting element 21b that emits the second color of light may be installed sequentially along the first direction X. In the first light-emitting element located in row b+1, the first light-emitting element 21b that emits the second color of light and the first light-emitting element 21a that emits the first color of light may be installed sequentially along the first direction X.

[0090] In some examples, as shown in Figure 4A, the installation order of the first light-emitting element 21a that emits the first color of light and the first light-emitting element 21b that emits the second color of light is reversed in different first light-emitting units located in adjacent rows of light-emitting units. For example, in the first light-emitting unit located in row a, the first light-emitting element 21b that emits the second color of light and the first light-emitting element 21a that emits the first color of light may be installed sequentially along the first direction X. In the first light-emitting unit located in row a+1, the first light-emitting element 21a that emits the first color of light and the first light-emitting element 21b that emits the second color of light may be installed sequentially along the first direction X.

[0091] In some examples, as shown in Figure 4A, the installation order of the second light-emitting element 22a that emits the first color of light and the second light-emitting element 22b that emits the second color of light is reversed in different second light-emitting units located in adjacent rows of light-emitting units, and the installation order of the second light-emitting element 22a that emits the first color of light and the second light-emitting element 22b that emits the second color of light is reversed in different second light-emitting units located in adjacent rows of light-emitting units. The installation method of the second light-emitting elements within the second light-emitting unit is similar to the installation method of the first light-emitting elements within the first light-emitting unit, so it will not be explained again here.

[0092] In some examples, the first color of light may be red light (R), the second color of light may be blue light (B), and the third color of light may be green light (G). However, this embodiment is not limited to these.

[0093] In some examples, the first light-emitting element of the first light-emitting unit 2a in the first display area may be configured to provide brightness compensation for a second light-emitting element that emits light of the same color in an adjacent second light-emitting unit 2b. For example, a first light-emitting element 21b that emits blue light in the first light-emitting unit 2a in the a-th row (b+1) and a-th row (b+3) may provide brightness compensation for a second light-emitting element 22b that emits blue light in the second light-emitting unit 2b in the a-th row (b+2). Similarly, a first light-emitting element 21a that emits red light in the first light-emitting unit 2a in the a-th row (b+1) and a-th row (b+3) may provide brightness compensation for a second light-emitting element 22a that emits red light in the second light-emitting unit 2b in the a-th row (b+2). The first light-emitting element 21c emitting green light in the first light-emitting unit 2a of column a+1, row b, the first light-emitting element 21d emitting green light in the first light-emitting unit 2a of column a, row b+1, and the first light-emitting element 21c emitting green light in the first light-emitting unit 2a of column a+1, row b+2 may compensate for the brightness of the second light-emitting element 22c emitting green light in the second light-emitting unit 2b of column a+1, row b+1. In this example, by using the first light-emitting element in the first light-emitting unit to compensate for the brightness of the second light-emitting element emitting light of the same color in the adjacent second light-emitting unit, the situation in which the brightness of the second light-emitting element is dim can be effectively improved.

[0094] Figure 5 is a schematic diagram of the connection relationship between a light-emitting element and a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 5, the first display area A1 may include a plurality of first pixel circuits (e.g., including first pixel circuits 11a, 11b, 11c, and 11d), a plurality of first light-emitting elements, and a plurality of second light-emitting elements, and the second display area A2 may include a plurality of second pixel circuits 12, a plurality of third pixel circuits 13, and a plurality of third light-emitting elements (not shown). The first pixel circuits and first light-emitting elements may be located in the first sub-area A11, and the second light-emitting elements may be located in the second sub-area A12. The light transmittance of the second sub-area A12 may be greater than the light transmittance of the first sub-area A11. For example, the first sub-area A11 may be a non-light-transmitting region, and the second sub-area A12 may include a non-light-transmitting region and a light-transmitting region. The positions of the anode and wiring of the second light-emitting element within the second sub-area A12 may be in a non-light-transmitting region, and the region between the anodes of adjacent second light-emitting elements where no metal wiring is installed may be a light-transmitting region.

[0095] In some examples, as shown in Figure 5, the four first pixel circuits of each first sub-area A11 may be arranged sequentially along the first direction X. For example, the first pixel circuits 11a, 11b, 11c, and 11d may be installed sequentially along the first direction X. The four first light-emitting elements of the first light-emitting unit may be electrically connected to the four first pixel circuits in a one-to-one correspondence. For example, a first light-emitting element that emits light of a first color (e.g., a red first light-emitting element) may be electrically connected to the first pixel circuit 11a, a first light-emitting element that emits light of one third color (e.g., a green first light-emitting element) may be electrically connected to the first pixel circuit 11b, a first light-emitting element that emits light of a second color (e.g., a blue first light-emitting element) may be electrically connected to the first pixel circuit 11c, and a first light-emitting element that emits light of another third color (e.g., a green first light-emitting element) may be electrically connected to the first pixel circuit 11d.

[0096] In some examples, as shown in Figure 5, no pixel circuit may be installed in the second sub-area A12, and the four second light-emitting elements in the second sub-area A12 may be electrically connected to the second pixel circuit 12 in the second display area A2 via conductive connection lines 15. Within the second sub-area A12, the light-transmitting regions between adjacent second light-emitting elements can be connected to each other to form a continuous light-transmitting region, thereby improving the light transmittance of the first display area.

[0097] In some examples, as shown in Figure 5, multiple second pixel circuits 12 may be arranged within the second display area A2 with spacing between multiple third pixel circuits 13. Within the second display area A2, an area for installing the second pixel circuits 12 can be obtained by reducing the size of the third pixel circuit 13 in the first direction X. For example, the size of the third pixel circuit 13 in the first direction X may be smaller than the size of the third light-emitting element in the first direction X.

[0098] In some examples, the space for one or two columns of second pixel circuits can be increased by compressing the original third pixel circuits for each f column along the first direction X, and the space occupied by the f columns of pixel circuits before compression may be the same as the space occupied by the f+1 or f+2 columns of pixel circuits after compression. f may be an integer greater than 1. In this example, f may be 4, and the space for two columns of second pixel circuits can be increased by compressing the four columns of third pixel circuits. However, this embodiment is not limited to this.

[0099] In some examples, as shown in Figure 5, the second pixel circuit 12 may be placed in the second display area A2 on both sides (e.g., left and right) along the first direction X of the first display area A1, or it may not be necessary to place the second pixel circuit in the second display area on both sides (e.g., top and bottom) along the second direction Y of the first display area A1, or an invalid pixel circuit may be placed therein, thereby maintaining the uniformity of the multiple film layer components within the second display area during the etching process. An invalid pixel circuit is not electrically connected to any light-emitting element, but may have substantially the same structure as the second pixel circuit in the row or column in which it is located. This embodiment is not limited thereto.

[0100] In some examples, as shown in Figure 5, a second light-emitting element located near the center of the first display area A1 may be electrically connected to a second pixel circuit 12 located near the first display area A1 within the second display area A2, while a second light-emitting element located near the edge of the first display area A1 may be electrically connected to a second pixel circuit located away from the first display area A1. This embodiment does not limit the connection relationship between the second pixel circuit and the second light-emitting element.

[0101] Figure 6 is a schematic local plan view of a first display area according to at least one embodiment of the present disclosure. Figure 6 shows first and second light-emitting units in columns a to a+2 and rows b to b+3. In some examples, as shown in Figure 6, the first display area of ​​the display substrate may include a plurality of first sub-areas and a plurality of second sub-areas spaced apart along a first direction X and a second direction Y in a plane parallel to the display substrate. A first sub-area may include one first light-emitting unit (including four first light-emitting elements 21a, 21b, 21c, and 21d) and four first pixel circuits, and a second sub-area may include one second light-emitting unit (including four second light-emitting elements 22a, 22b, 22c, and 22d). The second sub-area where the second light-emitting unit in column a+1, row b+1 is located may be surrounded by the first sub-area where the first light-emitting unit in column a+1, row b is located, the first sub-area where the first light-emitting unit in column a, row b+1 is located, the first sub-area where the first light-emitting unit in column a+2, row b+1 is located, and the first sub-area where the first light-emitting unit in column a+1, row b+2 is located. The first sub-area where the first light-emitting unit in column a+1, row b is located, the first sub-area where the first light-emitting unit in column a+2, row b+1 is located, and the first sub-area where the first light-emitting unit in column a+1, row b+2 is located may be in communication with each other.

[0102] In some examples, in a direction perpendicular to the display substrate, the display substrate may include a base, a circuit structure layer, a conductive connection layer, and a light-emitting structure layer mounted on the base. The light-emitting structure layer may be located on the side of the circuit structure layer away from the base, and the conductive connection layer may be located between the circuit structure layer and the light-emitting structure layer. The circuit structure layer of the first display area may include a plurality of first pixel circuits, and the light-emitting structure layer of the first display area may include a plurality of first light-emitting elements and a plurality of second light-emitting elements.

[0103] In some examples, the circuit structure layer may include a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer, which are placed on the base. A first insulating layer may be placed between the first semiconductor layer and the first conductive layer, a second insulating layer may be placed between the first conductive layer and the second conductive layer, a third insulating layer may be placed between the second conductive layer and the second semiconductor layer, a fourth insulating layer may be placed between the second semiconductor layer and the third conductive layer, a fifth insulating layer may be placed between the third conductive layer and the fourth conductive layer, a sixth insulating layer and a seventh insulating layer may be placed between the fourth conductive layer and the fifth conductive layer, an eighth insulating layer may be placed between the fifth conductive layer and the sixth conductive layer, and a ninth insulating layer may be placed on the side of the sixth conductive layer away from the base. In some examples, the first to sixth insulating layers may be inorganic insulating layers, and the seventh to ninth insulating layers may be organic insulating layers. This embodiment is not limited thereto.

[0104] In some examples, the conductive connection layer may include multiple conductive connection lines, which may extend from the first display area to the second display area, thereby realizing an electrical connection between the second light-emitting element and the second pixel circuit.

[0105] In some examples, the light-emitting structure layer may include an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode layer, which are sequentially installed on the circuit structure layer. The anode layer may be electrically connected to the pixel circuit of the circuit structure layer, the organic light-emitting layer may be connected to the anode layer, and the cathode layer may be connected to the organic light-emitting layer. The organic light-emitting layer may emit light rays of the corresponding color under the driving of the anode and cathode layers.

[0106] In some examples, the sealing structure layer may include a first sealing layer, a second sealing layer, and a third sealing layer that are stacked together. The first and third sealing layers may be made of inorganic materials, the second sealing layer may be made of organic materials, and the second sealing layer may be placed between the first and third sealing layers, forming a stacked structure of inorganic material / organic material / inorganic material that can prevent external water vapor from entering the light-emitting structure layer. In some possible realizations, the display substrate may include other film layers, such as a touch structure layer, a color filter layer, etc., and this embodiment is not limited thereto.

[0107] The structure of a display substrate will be described below with examples of the manufacturing process of the display substrate. The “patterning process” described in this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metallic materials, inorganic materials, or transparent conductive materials, and processes such as organic material coating, mask exposure, and development for organic materials. Deposition may be one or more of sputtering, vapor deposition coating, or chemical vapor deposition. Coating may be one or more of spray coating, spin coating, and inkjet printing. Etching may be one or more of dry etching and wet etching. This disclosure is not limited. A “thin film” refers to a single thin film produced on a base by deposition, coating, or other processes using a certain material. If the “thin film” does not require a patterning process throughout the entire manufacturing process, the “thin film” is also referred to as a “layer.” If the “thin film” requires a patterning process throughout the entire manufacturing process, it is referred to as a “thin film” before the patterning process and as a “layer” after the patterning process. Each "layer" after the patterning process contains at least one "pattern".

[0108] In this disclosure, "A and B are placed on the same layer" means that A and B are formed simultaneously by the same patterning process, or that the distance between the base-side surfaces of A and B and the base is essentially the same, or that the base-side surfaces of A and B are in direct contact with the same film layer. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B is within the boundary range of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. In this disclosure, "shape of A" means the shape of the orthographic projection of A on the base.

[0109] In some examples, the manufacturing process of the display board may include the following operations. Below, the circuit structure layers will be described using two first pixel circuits in the first sub-area of ​​the first display area as an example. In this example, the first pixel circuit will be described as having the aforementioned 8T1C structure. The first first pixel circuit (i.e., the first pixel circuit 11a) may include a first transistor 31a, a second transistor 32a, a third transistor 33a, a fourth transistor 34a, a fifth transistor 35a, a sixth transistor 36a, a seventh transistor 37a, an eighth transistor 38a, and a memory capacitor, and the second first pixel circuit (i.e., the first pixel circuit 11b) may include a first transistor 31b, a second transistor 32b, a third transistor 33b, a fourth transistor 34b, a fifth transistor 35b, a sixth transistor 36b, a seventh transistor 37b, an eighth transistor 38b, and a memory capacitor. Refer to the equivalent circuit diagram shown in Figure 2 for the connection relationships of the eight transistors and memory capacitor in each first pixel circuit.

[0110] (1) A base is provided. In some examples, the base may be a rigid base or a flexible base. For example, the rigid base may be one or more of glass and quartz, but is not limited to these. The flexible base may be one or more of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyaryl ester, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber, but is not limited to these. In some examples, the flexible base includes a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer that are laminated together. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the water and oxygen resistance of the base.

[0111] (2) A first semiconductor layer is formed. In some examples, a first semiconductor thin film is deposited on a base, and the first semiconductor thin film is patterned by a patterning process to form a first semiconductor layer to be placed on the base. In some examples, the material of the first semiconductor layer may be amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene.

[0112] Figure 7A is a schematic diagram of the first display area after the formation of the first semiconductor layer in Figure 6. Figure 7B is a schematic diagram of one of the first sub-areas in Figure 7A.

[0113] In some examples, as shown in Figures 7A and 7B, the first semiconductor layer of the first display area may include active layers of at least several first type transistors of several first pixel circuits (for example, the first active layer 310a of the first transistor of the first pixel circuit 11a in the first sub-area, the third active layer 330a of the third transistor, the fourth active layer 340a of the fourth transistor, the fifth active layer 350a of the fifth transistor, the sixth active layer 360a of the sixth transistor, the seventh active layer 370a of the seventh transistor, and the eighth active layer 380a of the eighth transistor, and the first active layer 310b of the first transistor of the first pixel circuit 11b, the third active layer 330b of the third transistor, the fourth active layer 340b of the fourth transistor, the fifth active layer 350b of the fifth transistor, the sixth active layer 360b of the sixth transistor, the seventh active layer 370b of the seventh transistor, and the eighth active layer 380b of the eighth transistor).

[0114] In some examples, within a first sub-area, the first semiconductor layer patterns of four first pixel circuits may be substantially symmetric with respect to the first median O1, the first semiconductor layer patterns of first pixel circuits 11a and 11b may be substantially symmetric with respect to the second median O2, and the first semiconductor layer patterns of first pixel circuits 11c and 11d may be substantially symmetric with respect to the third median O3. The first semiconductor layer patterns in different first sub-areas may be independent of each other.

[0115] In some examples, within a first sub-area, the first, third, fourth, fifth, sixth, and seventh active layers of four first pixel circuits may be an integrated structure connected to one another. The seventh active layer 370a of the first pixel circuit 11a and the seventh active layer 370b of the first pixel circuit 11b may be connected to each other. The fifth active layer 350b of the first pixel circuit 11b and the fifth active layer of the first pixel circuit 11c may be connected to each other. The seventh active layer of the first pixel circuit 11c and the seventh active layer of the first pixel circuit 11d may be connected to each other. The first active layer of each first pixel circuit may be located on the second direction Y side of the third active layer, and the eighth active layer may be located on the opposite side of the second direction Y of the third active layer.

[0116] In some examples, the shapes of the third active layer 330a and 330b may be roughly U-shaped, the shapes of the fourth active layer 340a and 340b and the fifth active layer 350a and 350b may be roughly I-shaped, and the shapes of the first active layer 310a and 310b, the sixth active layer 360a and 360b, the seventh active layer 370a and 370b, and the eighth active layer 380a and 380b may be roughly L-shaped. However, this embodiment is not limited to these shapes.

[0117] In some examples, the active layer of each transistor includes a first area, a second area, and a channel area located between the first and second areas. The material of the first semiconductor layer may include, for example, polysilicon. The channel area may not be doped with impurities and may have semiconductor properties. The first and second areas may be doped regions located on either side of the channel area and are conductive because they are doped with impurities. The impurities may be changed depending on the type of transistor. In some examples, the doped regions of the active layer may be interpreted as the source or drain electrodes of the transistor. The portion of the active layer between transistors may be interpreted as impurity-doped wiring and may be used for the electrical connection of the transistors. This embodiment is not limited thereto.

[0118] (2) A first conductive layer is formed. In some examples, a first insulating thin film and a first conductive thin film are sequentially deposited on the base on which the above structure is formed, and the first conductive thin film is patterned by a patterning process to form a first insulating layer and a first conductive layer placed on the first insulating layer. In some examples, the first conductive layer may further be referred to as a first gate metal layer.

[0119] Figure 8A is a schematic diagram of the first display area after the formation of the first conductive layer in Figure 6. Figure 8B is a schematic diagram of the first conductive layer in Figure 8A. Figure 8C is a schematic diagram of one of the first sub-areas in Figure 8A.

[0120] In some examples, as shown in Figures 8A to 8C, the first conductive layer of the first display area may include at least a plurality of first scan lines (e.g., first scan lines GL1(i), GL1(i+1), GL1(i+2), GL1(i+3)), a plurality of light emission control lines (e.g., light emission control lines EML(i), EML(i+1), EML(i+2), EML(i+3)), a plurality of first reset control lines (e.g., first reset control lines RST1(i), RST1(i+1), RST1(i+2), RST1(i+3)), a plurality of second reset control lines (e.g., second reset control lines RST2(i), RST2(i+1), RST2(i+2), RST2(i+3)), and first electrodes of memory capacitors of a plurality of first pixel circuits (e.g., first electrodes 391a, 391b).

[0121] In some examples, within the first sub-area, the first scan line GL1(i) may be located on the second direction Y side of the first electrodes (e.g., 391a and 391b) of the memory capacitor of the first pixel circuit, and the first reset control line RST1(i) may be located on the second direction Y side of the first scan line GL1(i). The light emission control line EML(i) may be located on the opposite side of the second direction Y of the first electrodes (e.g., 391a and 391b) of the memory capacitor of the first pixel circuit, and the second reset control line RST2(i) may be located on the opposite side of the second direction Y of the light emission control line EML(i).

[0122] In some examples, the first reset control line RST1(i), the first scan line GL1(i), the second reset control line RST2(i), and the light emission control line EML(i) can be bent to bypass an adjacent second sub-area along the first direction X of the first sub-area in which they are located. For example, the first reset control line RST1(i) and the first scan line GL1(i) may bypass the second sub-area along the second direction Y, and the second reset control line RST2(i) and the light emission control line EML(i) may bypass the second sub-area along the opposite side of the second direction Y. In this example, installing the wiring of the first conductive layer so that it is bent to bypass the second sub-area is advantageous in improving the light transmittance of the second sub-area.

[0123] In some examples, the shape of the first reset control line RST1(i) may be a bent shape extending substantially along the first direction X. Within the first sub-area, the overlapping region between the first reset control line RST1(i) and the first active layer of the four first pixel circuits may be the gate electrodes of the first transistors of the four first pixel circuits (e.g., including the gate electrode of the first transistor 31a and the gate electrode of the first transistor 31b).

[0124] In some examples, the shape of the first scan line GL1(i) may be a bent shape extending approximately along the first direction X. Within the first sub-area, the overlapping region between the first scan line GL1(i) and the fourth active layer of the four first pixel circuits may be the gate electrodes of the fourth transistors of the four first pixel circuits (e.g., including the gate electrode of the fourth transistor 34a and the gate electrode of the fourth transistor 34b).

[0125] In some examples, the shape of the light emission control line EML(i) may be a bent shape extending approximately along a first direction X. Within the first sub-area, the overlapping region between the light emission control line EML(i) and the fifth active layer of the four first pixel circuits may be the gate electrodes of the fifth transistors of the four first pixel circuits (e.g., including the gate electrodes of the fifth transistors 35a and 35b), and the overlapping region between the light emission control line EML(i) and the sixth active layer of the four first pixel circuits may be the gate electrodes of the sixth transistors of the four first pixel circuits (e.g., including the gate electrodes of the sixth transistors 36a and 36b).

[0126] In some examples, the shape of the second reset control line RST2(i) may be a bent shape extending approximately along the first direction X. Within the first sub-area, the overlapping region between the second reset control line RST2(i) and the seventh active layer of the four first pixel circuits may be the gate electrodes of the seventh transistors of the four first pixel circuits (e.g., including the gate electrodes of the seventh transistors 37a and 37b), and the overlapping region between the second reset control line RST2(i) and the eighth active layer of the four first pixel circuits may be the gate electrodes of the eighth transistors of the four first pixel circuits (e.g., including the gate electrodes of the eighth transistors 38a and 38b).

[0127] In some examples, the first electrode 391a of the memory capacitor in the first pixel circuit 11a may also serve as the gate electrode of the third transistor 33a, and the first electrode 391b of the memory capacitor in the first pixel circuit 11b may also serve as the gate electrode of the third transistor 33b. The orthographic projection of the first electrodes 391a and 391b on the base may be approximately rectangular. This embodiment is not limited to this.

[0128] (3) A second conductive layer is formed. In some examples, a second insulating thin film and a second conductive thin film are sequentially deposited on the base on which the above structure is formed, and the second conductive thin film is patterned by a patterning process to form a second insulating layer and a second conductive layer placed on the second insulating layer. In some examples, the second conductive layer may further be referred to as a second gate metal layer.

[0129] Figure 9A is a schematic diagram of the first display area after the formation of the second conductive layer in Figure 6. Figure 9B is a schematic diagram of the second conductive layer in Figure 9A. Figure 9C is a schematic diagram of one of the first sub-areas in Figure 9A.

[0130] In some examples, as shown in Figures 9A to 9C, the second conductive layer of the first display area may include at least a plurality of second scanning auxiliary lines (e.g., second scanning auxiliary lines GL2b(i), GL2b(i+1), GL2b(i+2), GL2b(i+3)) and the second electrodes of the memory capacitors of a plurality of first pixel circuits (e.g., second electrodes 392a, 392b).

[0131] In some examples, the shape of the second scanning guide line GL2b(i) may be a bent line extending approximately along the first direction X. Within the first sub-area, the second scanning guide line GL2b(i) may be located on the second direction Y side of the second electrodes (e.g., 392a and 392b) of the memory capacitor of the first pixel circuit. The second scanning guide line GL2b(i) may bypass the second sub-area from the second direction Y side and be located on the opposite side of the second direction Y of the first scanning line GL1(i).

[0132] In some examples, within a first sub-area, the orthographic projection of the base of the second electrode of the memory capacitor of each first pixel circuit may be a rectangular structure having approximately one hollow area, and the orthographic projection of the base of the hollow area may be approximately rectangular, and the rectangle may have rounded corners or chamfers. The second electrode 392a of the memory capacitor of the first pixel circuit 11a may be electrically connected to the second electrode 392b of the memory capacitor of the first pixel circuit 11b via a first plate connection block 392-1, the second electrode 392b of the memory capacitor of the first pixel circuit 11b may be electrically connected to the second electrode of the memory capacitor of the first pixel circuit 11c via a second plate connection block 392-2, and the second electrode of the memory capacitor of the first pixel circuit 11c may be electrically connected to the second electrode of the memory capacitor of the first pixel circuit 11d via another first plate connection block 392-1. The side of the second electrode of the memory capacitor of the first pixel circuits 11a and 11d that is away from the rest of the first pixel circuits may be electrically connected to one second electrode plate connection block 392-2. The length L1 of the first electrode plate connection block 392-1 along the second direction Y may be less than the length L2 of the second electrode plate connection block 392-2 along the second direction Y. The second electrode of the memory capacitor may then be electrically connected to the first power line via the second electrode plate connection block. In this example, the second electrodes of the memory capacitors of the four first pixel circuits in the first subarea may be an integrated structure connected to each other, which is advantageous for ensuring uniform transmission of the first voltage signal along the first direction X.

[0133] (4) A second semiconductor layer is formed. In some examples, a third insulating thin film and a second semiconductor thin film are sequentially deposited on the base on which the above pattern is formed, and the second semiconductor thin film is patterned by a patterning process to form a third insulating layer and a second semiconductor layer to be placed on the third insulating layer. In some examples, the material of the second semiconductor layer may include indium gallium zinc oxide (IGZO).

[0134] Figure 10A is a schematic diagram of the first display area after the formation of the second semiconductor layer in Figure 6. Figure 10B is a schematic diagram of the second semiconductor layer in Figure 10A. Figure 10C is a schematic diagram of one of the first sub-areas in Figure 10A.

[0135] In some examples, as shown in Figures 10A to 10C, the second semiconductor layer of the first display area may include the active layers of at least several second type transistors of first pixel circuits (for example, the second active layer 320a of the second transistor 32a of the first pixel circuit 11a in the first sub-area, and the second active layer 320b of the second transistor 32b of the first pixel circuit 11b).

[0136] In some examples, within a first sub-area, the second semiconductor layer patterns of the four first pixel circuits may be substantially symmetric with respect to the first median O1, the second semiconductor layer patterns of the first pixel circuits 11a and 11b may be substantially symmetric with respect to the second median O2, and the second semiconductor layer patterns of the first pixel circuits 11c and 11d may be substantially symmetric with respect to the third median O3.

[0137] In some examples, the shapes of the second active layers 320a and 320b may be approximately L-shaped. The overlapping region between the second scanning auxiliary line GL2b(i) and the second active layer 320a may be the bottom gate of the second transistor 32a, and the overlapping region between the second scanning auxiliary line GL2b(i) and the second active layer 320b may be the bottom gate of the second transistor 32b.

[0138] (5) A third conductive layer is formed. In some examples, a fourth insulating thin film and a third conductive thin film are sequentially deposited on the base on which the above pattern is formed, and the third conductive thin film is patterned by a patterning process to form a fourth insulating layer and a third conductive layer placed on the fourth insulating layer. In some examples, the third conductive layer may further be referred to as a third gate metal layer.

[0139] Figure 11A is a schematic diagram of the first display area after the formation of the third conductive layer in Figure 6. Figure 11B is a schematic diagram of the third conductive layer in Figure 11A. Figure 11C is a schematic diagram of one of the first sub-areas in Figure 11A.

[0140] In some examples, as shown in Figures 11A to 11C, the third conductive layer of the first display area may include at least several second scan lines (e.g., second scan lines GL2(i), GL2(i+1), GL2(i+2), GL2(i+3)), several first initial signal lines (e.g., first initial signal lines INIT1(i), INIT1(i+1), INIT1(i+2), INIT1(i+3)), several second initial signal lines (e.g., second initial signal lines INIT2(i), INIT2(i+1), INIT2(i+2), INIT2(i+3)) and several third initial signal lines (e.g., third initial signal lines INIT3(i), INIT3(i+1), INIT3(i+2), INIT3(i+3)). The shape of each of the first initial signal line, second scan line, second initial signal line, and third initial signal line may be a bent shape extending approximately along the first direction X.

[0141] In some examples, within the first sub-area, the first initial signal line INIT1(i) and the second scan line GL2(i) may be located on the second direction Y side of the memory capacitor, while the second initial signal line INIT2(i) and the third initial signal line INIT3(i) may be located on the opposite side of the second direction Y side of the memory capacitor. The first initial signal line INIT1(i) may be located on the second direction Y side of the second scan line GL2(i). The second initial signal line INIT2(i) may be located on the opposite side of the second direction Y side of the third initial signal line INIT3(i).

[0142] In some examples, the first initial signal line INIT1(i), the second scan line GL2(i), the second initial signal line INIT2(i), and the third initial signal line INIT3(i) can be bent to bypass an adjacent second sub-area along the first direction X of the first sub-area in which they are located. For example, the first initial signal line INIT1(i) and the second scan line GL2(i) may bypass the second sub-area along the second direction Y, and the second initial signal line INIT2(i) and the third initial signal line INIT3(i) may bypass the second sub-area along the opposite side of the second direction Y. In this example, installing the wiring of the third conductive layer so that it is bent to bypass the second sub-area is advantageous in improving the light transmittance of the second sub-area.

[0143] In some examples, the orthographic projection of the first initial signal line INIT1(i) on the base may at least partially overlap with the orthographic projection of the first reset control line RST1(i) on the base, the orthographic projection of the second scan line GL2(i) on the base may at least partially overlap with the orthographic projection of the second scan auxiliary line GL2b(i) on the base, the orthographic projection of the third initial signal line INIT3(i) on the base may at least partially overlap with the orthographic projection of the light emission control line EML(i) on the base, and the orthographic projection of the second initial signal line INIT2(i) on the base may at least partially overlap with the orthographic projection of the second reset control line RST2(i) on the base. In this example, by laminating the wiring of different conductive layers, excessive occupancy of wiring space can be avoided, which is advantageous in saving wiring space and thereby improves the light transmittance of the first display area.

[0144] (6) A fifth insulating layer is formed. In some cases, a fifth insulating thin film is deposited on the base on which the above pattern is formed, and the fifth insulating thin film is patterned by a patterning process to form the fifth insulating layer.

[0145] Figure 12 is a schematic diagram of one first sub-area after the fifth insulating layer has been formed in Figure 6. In some examples, as shown in Figure 12, multiple vias may be opened in the fifth insulating layer of the first indicated area, for example, including vias V1 to V19, V21 to V22, V23 to V24, V25 to V29, and V31 to V34.

[0146] In some examples, the fifth insulating layer, fourth insulating layer, third insulating layer, second insulating layer, and first insulating layer in vias V1 to V19 may be removed to expose a portion of the surface of the first semiconductor layer. The fifth insulating layer, fourth insulating layer, third insulating layer, and second insulating layer in vias V21 and V22 may be removed to expose a portion of the surface of the first conductive layer. The fifth insulating layer, fourth insulating layer, and third insulating layer in vias V23 and V24 may be removed to expose a portion of the surface of the second conductive layer. The fifth insulating layer in vias V25 to V29 may be removed to expose a portion of the surface of the third conductive layer. The fifth insulating layer and fourth insulating layer in vias V31 to V34 may be removed to expose the surface of the second semiconductor layer.

[0147] (7) A fourth conductive layer is formed. In some examples, a fourth conductive thin film is deposited on the base on which the aforementioned pattern is formed, and the fourth conductive thin film is patterned by a patterning process to form a fourth conductive layer on the fifth insulating layer. In some examples, the fourth conductive layer may further be referred to as the first source-drain metal layer.

[0148] Figure 13A is a schematic diagram of the first display area after the formation of the fourth conductive layer in Figure 6. Figure 13B is a schematic diagram of the fourth conductive layer in Figure 13A. Figure 13C is a schematic diagram of one of the first sub-areas in Figure 13A.

[0149] In some examples, as shown in Figures 13A to 13C, the fourth conductive layer of the first display area may include at least a number of connecting electrodes (for example, the first to ninth connecting electrodes 409 and the eleventh to seventeenth connecting electrodes 417).

[0150] In some examples, the shape of the first connecting electrode 401 may be substantially rectangular. The first connecting electrode 401 may be electrically connected to the fourth active layer of the fourth transistor 34a of the first pixel circuit 11a via the third via V3.

[0151] In some examples, the shape of the second connecting electrode 402 may be a stripe extending approximately along the second direction Y. One end of the second connecting electrode 402 may be electrically connected to the second active layer of the second transistor 32a of the first pixel circuit 11a via the 31st via V31, and the other end may be electrically connected to the first electrode 391a of the memory capacitor via the 21st via V21. The second connecting electrode 402 may be electrically connected to the gate electrode of the third transistor 33a, the first electrode 391a of the memory capacitor, and the first electrode of the second transistor 32a, and the second connecting electrode 402 may serve as the first node of the first pixel circuit 11a.

[0152] In some examples, the shape of the third connecting electrode 403 may be a stripe extending approximately along the second direction Y. One end of the third connecting electrode 403 may be electrically connected to the first active layer of the first transistor 31a of the first pixel circuit 11a via the second via V2, the other end may be electrically connected to the second active layer of the second transistor 32a via the 32nd via V32, and further may be electrically connected to the third active layer of the third transistor 33a via the 6th via V6.

[0153] In some examples, the shape of the fourth connecting electrode 404 may be a bent shape extending approximately along the second direction Y. The fourth connecting electrode 404 may be electrically connected to the fourth active layer of the fourth transistor 34a of the first pixel circuit 11a via the fourth via V4, and further electrically connected to the eighth active layer of the eighth transistor 38a via the eighth via V8.

[0154] In some examples, the shape of the fifth connecting electrode 405 may be a stripe extending approximately along the second direction Y. The fifth connecting electrode 405 may be electrically connected to the fifth active layer of the fifth transistor 35a of the first pixel circuit 11a via the fifth via V5, and may also be electrically connected to the second electrode plate connecting block 392-2 via the 23rd via V23, thereby achieving an electrical connection with the second electrode 392a of the memory capacitor.

[0155] In some examples, the shape of the sixth connecting electrode 406 may be substantially rectangular. The sixth connecting electrode 406 may be electrically connected to the sixth active layer of the sixth transistor 36a of the first pixel circuit 11a via the seventh via V7.

[0156] In some examples, the shape of the seventh connecting electrode 407 may be approximately L-shaped. The seventh connecting electrode 407 may be electrically connected to the eighth active layer of the eighth transistor 38a of the first pixel circuit 11a via the ninth via V9, and may also be electrically connected to the third initial signal line INIT3(i) via the 26th via V26.

[0157] In some examples, the shape of the eighth connecting electrode 408 may be a stripe extending approximately along the second direction Y. The eighth connecting electrode 408 may be electrically connected to the seventh active layer of the seventh transistor 37a of the first pixel circuit 11a via the tenth via V10, and may also be electrically connected to the second initial signal line INIT2(i) via the 27th via V27.

[0158] In some examples, the shape of the ninth connecting electrode 409 may be an arch shape extending approximately along the second direction Y. One end of the ninth connecting electrode 409 may be electrically connected to the first active layer of the first transistor 31a of the first pixel circuit 11a via the first via V1, and further electrically connected to the first initial signal line INIT1(i) via the 25th via V25, and the other end may be electrically connected to the first active layer of the first transistor 31b of the first pixel circuit 11b via the 11th via V11, and further electrically connected to the first initial signal line INIT1(i) via the 28th via V28.

[0159] In some examples, the shape of the 11th connecting electrode 411 may be substantially rectangular. The 11th connecting electrode 411 may be electrically connected to the fourth active layer of the fourth transistor 34b of the first pixel circuit 11b via the 13th via V13.

[0160] In some examples, the shape of the 12th connecting electrode 412 may be a stripe extending approximately along the second direction Y. One end of the 12th connecting electrode 412 may be electrically connected to the second active layer of the second transistor 32b of the first pixel circuit 11b via the 33rd via V31, and the other end may be electrically connected to the first electrode 391b of the memory capacitor via the 22nd via V22. The 12th connecting electrode 412 may be electrically connected to the gate electrode of the third transistor 33b, the first electrode 391b of the memory capacitor, and the first electrode of the second transistor 32b, and the 12th connecting electrode 412 may serve as the first node of the first pixel circuit 11b.

[0161] In some examples, the shape of the 13th connecting electrode 413 may be a stripe extending substantially along the second direction Y. One end of the 13th connecting electrode 413 may be electrically connected to the first active layer of the first transistor 31b of the first pixel circuit 11b via the 12th via V12, the other end may be electrically connected to the second active layer of the second transistor 32b via the 34th via V34, and further electrically connected to the third active layer of the third transistor 33b via the 16th via V16.

[0162] In some examples, the shape of the 14th connecting electrode 414 may be a bent shape extending substantially along the second direction Y. The 14th connecting electrode 414 may be electrically connected to the fourth active layer of the fourth transistor 34b of the first pixel circuit 11b via the 14th via V14, and may also be electrically connected to the eighth active layer of the eighth transistor 38b via the 18th via V18.

[0163] In some examples, the shape of the 15th connecting electrode 415 may be a stripe extending approximately along the second direction Y. The 15th connecting electrode 415 may be electrically connected to the fifth active layer of the fifth transistor 35b of the first pixel circuit 11b via the 15th via V15, and may also be electrically connected to another second electrode plate connecting block 392-2 via the 24th via V24, thereby achieving an electrical connection with the second electrode 392b of the memory capacitor.

[0164] In some examples, the shape of the 16th connecting electrode 416 may be substantially rectangular. The 16th connecting electrode 416 may be electrically connected to the 6th active layer of the 6th transistor 36b of the 1st pixel circuit 11b via the 17th via V17.

[0165] In some examples, the shape of the 17th connecting electrode 417 may be approximately L-shaped. The 17th connecting electrode 417 may be electrically connected to the 8th active layer of the 8th transistor 38b of the first pixel circuit 11b via the 19th via V19, and may also be electrically connected to the 3rd initial signal line INIT3(i) via the 29th via V29.

[0166] In some examples, within the first sub-area, the first pixel circuits 11a and 11b may be approximately symmetric with respect to the second median O2, the first pixel circuits 11c and 11d may be approximately symmetric with respect to the third median O3, and the first pixel circuits 11a and 11b, and the first pixel circuits 11c and 11d may be approximately symmetric with respect to the first median O1.

[0167] In some examples, the first pixel circuits in multiple first sub-areas arranged along a first direction X may be aligned in the first direction X, and the first pixel circuits in multiple first sub-areas arranged along a second direction Y may be aligned in the second direction Y. For example, four rows of first pixel circuits may be arranged in one row of first sub-areas.

[0168] (8) Forming the sixth insulating layer and the seventh insulating layer. In some examples, the sixth insulating thin film is deposited on the base on which the above pattern is formed, then the seventh insulating thin film is applied, and the seventh insulating thin film and the sixth insulating thin film are patterned by a patterning process to form the sixth insulating layer and the seventh insulating layer. In some examples, the sixth insulating layer may be further referred to as a passivation layer, and the seventh insulating layer may be further referred to as a first flat layer.

[0169] Figure 14 is a schematic diagram of one first sub-area after the formation of the seventh insulating layer in Figure 6. In some examples, as shown in Figure 14, multiple vias may be opened in the seventh insulating layer of the first shown area, for example, including vias 41 V41 to 46 V46. The seventh insulating layer and the sixth insulating layer within vias 41 V41 to 46 V46 may be removed, exposing a portion of the surface of the fourth conductive layer.

[0170] (9) A fifth conductive layer is formed. In some examples, a fifth conductive thin film is deposited on the base on which the above pattern is formed, and the fifth conductive thin film is patterned by a patterning process to form a fifth conductive layer on the seventh insulating layer. In some examples, the fifth conductive layer may be further referred to as the second source-drain metal layer.

[0171] Figure 15A is a schematic diagram of the first display area after the formation of the fifth conductive layer in Figure 6. Figure 15B is a schematic diagram of the fifth conductive layer in Figure 15A. Figure 15C is a schematic diagram of one of the first sub-areas in Figure 15A.

[0172] In some examples, as shown in Figures 15A to 15C, the fifth conductive layer of the first display area may include at least several data lines (e.g., data lines DL(j-4), DL(j-3), DL(j-2), DL(j-1), DL(j), DL(j+1), DL(j+2), DL(j+3), DL(j+4), DL(j+5), DL(j+6), DL(j+7)), several first anode connection electrodes (e.g., first anode connection electrodes 422a, 422b, 422c, and 422d), several first power supply connection electrodes (e.g., first power supply connection electrodes 423a, 423b, and 423c), and several first shield electrodes (e.g., first shield electrodes 421a and 421b).

[0173] In some examples, multiple data lines may be bent in shape, extending approximately along the second direction Y. Four first subpixels within each first subarea are electrically connected to four data lines in a one-to-one correspondence. Data line DL(j) may also be electrically connected to the first connection electrode 401 via the 41st via V41, thereby electrically connecting to the fourth transistor of the first pixel circuit 11a. Data line DL(j+1) may also be electrically connected to the 11th connection electrode 411 via the 45th via V45, thereby electrically connecting to the fourth transistor of the first pixel circuit 11b. Data line DL(j+2) may also be electrically connected to the fourth transistor of the first pixel circuit 11c. Data line DL(j+3) may also be electrically connected to the fourth transistor of the first pixel circuit 11d.

[0174] In some examples, the four data lines electrically connected to the four first pixel circuits within the first sub-area can be divided into two groups and route around the first sub-area and the adjacent second sub-area in the second direction Y. For example, the data line DL(j) connected to the first pixel circuit 11a and the data line DL(j+1) connected to the first pixel circuit 11b may route around the adjacent second sub-area in the second direction Y from the opposite side of the first direction X, while the data line DL(j+2) connected to the first pixel circuit 11c and the data line DL(j+2) connected to the first pixel circuit 11d may route around the adjacent second sub-area in the second direction Y from the first direction X side. In this example, arranging the data lines to bend and route around the second sub-area is advantageous in reducing the space occupied by the wiring, thereby improving the light transmittance of the first display area.

[0175] In some examples, the shapes of the first anode connection electrodes 422a, 422b, 422c, and 422d may be approximately rectangular. The first anode connection electrodes 422a and 422b may be located between data lines DL(j) and DL(j+1), and the first anode connection electrodes 422c and 422d may be located between data lines DL(j+2) and DL(j+3).

[0176] In some examples, the first anode connection electrode 422a may be electrically connected to the sixth connection electrode 406 via the 43rd via V43, thereby achieving an electrical connection with the sixth transistor of the first pixel circuit 11a. The first anode connection electrode 422b may be electrically connected to the 16th connection electrode 416 via the 46th via V46, thereby achieving an electrical connection with the sixth transistor of the first pixel circuit 11b. The first anode connection electrode 422c may be electrically connected to the sixth transistor of the first pixel circuit 11c. The first anode connection electrode 422d may be electrically connected to the sixth transistor of the first pixel circuit 11d.

[0177] In some examples, the shapes of the first power supply connection electrodes 423a, 423b, and 423c may be approximately rectangular. The first power supply connection electrode 423a may be located on the side opposite to the first direction X of the data line DL(j), the first power supply connection electrode 423b may be located between the data lines DL(j+1) and DL(j+2), and the first power supply connection electrode 423c may be located on the side of the first direction X of the data line DL(j+3).

[0178] In some examples, the first power supply connection electrode 423a may be electrically connected to the fifth connection electrode 405 via the 42nd via V42, thereby achieving an electrical connection with the fifth transistor and memory capacitor of the first pixel circuit 11a. The second power supply connection electrode 423b may be electrically connected to the 15th connection electrode 415 via the 44th via V44, thereby achieving an electrical connection with the fifth transistor and memory capacitor of the first pixel circuits 11b and 11c. The third power supply connection electrode 423c may be electrically connected to the fifth transistor and memory capacitor of the first pixel circuit 11d.

[0179] In some examples, the shapes of the first shield electrodes 421a and 421b may be roughly n-shaped. The first shield electrode 421a may be located between data lines DL(j) and DL(j+1), and the first shield electrode 421b may be located between data lines DL(j+2) and DL(j+3). The orthogonal projection at the base of the first shield electrode 421a may cover the orthogonal projection at the base of the second connection electrode 402 and the twelfth connection electrode 412, thereby providing shielding for the first node of the first pixel circuit 11a and the first node of the first pixel circuit 11b, thereby blocking the influence of remaining signals on the first nodes of the first pixel circuits 11a and 11b. The second shield electrode 421b can provide shielding for the first node of the first pixel circuit 11c and the first node of the first pixel circuit 11d, thereby blocking the influence of remaining signals on the first nodes of the first pixel circuits 11c and 11d.

[0180] (10) A 8th insulating layer is formed. In some examples, the 8th insulating thin film is applied to the base on which the above pattern is formed, and the 8th insulating thin film is patterned by a patterning process to form the 8th insulating layer. In some examples, the 8th insulating layer may further be referred to as the 2nd planar layer.

[0181] Figure 16 is a schematic diagram of one first sub-area after the formation of the eighth insulating layer in Figure 6. In some examples, as shown in Figure 16, multiple vias may be opened in the eighth insulating layer of the first shown area, for example, including via 51 to via 59. The eighth insulating layer within vias 51 to 59 may be removed, exposing a portion of the surface of the fifth conductive layer.

[0182] (11) A sixth conductive layer is formed. In some examples, a sixth conductive thin film is deposited on the base on which the above pattern is formed, and the sixth conductive thin film is patterned by a patterning process to form a sixth conductive layer on the eighth insulating layer. In some examples, the sixth conductive layer may further be referred to as a third source-drain metal layer.

[0183] Figure 17A is a schematic diagram of the first display area after the formation of the sixth conductive layer in Figure 6. Figure 17B is a schematic diagram of the sixth conductive layer in Figure 17A. Figure 17C is a schematic diagram of one of the first sub-areas in Figure 17A.

[0184] In some examples, as shown in Figures 17A to 17C, the sixth conductive layer of the first display area may include at least a plurality of second anode connection electrodes (e.g., second anode connection electrodes 431a, 431b, 431c, and 431d), a plurality of third anode connection electrodes (e.g., third anode connection electrodes 432a, 432b, 432c, and 432d), and a first power line 44.

[0185] In some examples, the first power lines 44 of the first display area may have a mesh structure. The first power lines 44 of the first sub-area may be substantially symmetrical with respect to the first central line O1. The first power lines 44 of the first sub-area may include first extension segments 441a and 441b, second extension segments 442a and 442b, third extension segments 443a, 443b and 443c, and fourth extension segments 444a and 444b. The first extension segments 441a and 441b, the second extension segments 442a and 442b, the third extension segments 443a, 443b and 443c, and the fourth extension segments 444a and 444b may be an integrated structure connected to each other. The second sub-area may be surrounded by first extension segments 441a and 441b in the first sub-area adjacent to the second direction Y, and fourth extension segments 444a and 44b in the first sub-area adjacent to the first direction X. The first extension segments, third extension segment, and fourth extension segment of the first power line 44 in different first sub-areas may be electrically connected in correspondence to form a mesh-like design within the entire first display.

[0186] In some examples, the shapes of the first extension segments 441a and 441b may be stripes extending substantially along the first direction X. The first extension segment 441a may be located on the opposite side of the second direction Y from the first shield electrodes 421a and 421b, and the first extension segment 441b may be located on the second direction Y side from the first shield electrodes 421a and 421b.

[0187] In some examples, the shapes of the second extension segments 442a and 442b may be stripes extending substantially along the second direction Y. The second extension segment 442a may be electrically connected to the first shield electrode 421a via the 51st via V51, and the second extension segment 442b may be electrically connected to the first shield electrode 421b via the 52nd via V52. Both ends of the second extension segment 442a may be electrically connected to the first extension segments 441a and 441b, respectively, and both ends of the second extension segment 442b may be electrically connected to the first extension segments 441a and 441b, respectively.

[0188] In some examples, the shape of the third extension segments 443a, 443b, and 443c may be a stripe extending substantially along the second direction Y. The third extension segment 443a may be electrically connected to the first power supply connection electrode 423a via the 53rd via V53, the third extension segment 443b may be electrically connected to the first power supply connection electrode 423b via the 54th via V54, and the third extension segment 443c may be electrically connected to the first power supply connection electrode 423c via the 55th via V55. Both ends of the third extension segment 443a may be electrically connected to the first extension segments 441a and 441b, respectively, both ends of the third extension segment 443b may be electrically connected to the first extension segments 441a and 441b, respectively, and both ends of the third extension segment 443c may be electrically connected to the first extension segments 441a and 441b, respectively. The three third extension segments and the two second extension segments may be installed at intervals along the first direction X.

[0189] In some examples, the shapes of the fourth extension segments 444a and 444b may be stripes extending approximately along the second direction Y. Both ends of the fourth extension segment 444a may be electrically connected to the first extension segments 441a and 441b, respectively, and both ends of the fourth extension segment 444b may be electrically connected to the first extension segments 441a and 441b, respectively. The fourth extension segment 444a is located on the opposite side of the first direction X from the third extension segment 443a, and the fourth extension segment 444b is located on the first direction X side from the third extension segment 443c.

[0190] In some examples, in the first sub-area, the two first extension segments 441a and 441b, the two second extension segments 442a and 442b, and the three third extension segments 443a, 443b, and 443c of the first power line 44 may be connected and enclosed to form four accommodation regions. The four accommodation regions correspond one-to-one with four first pixel circuits, and one second anode connection electrode may be installed within each accommodation region.

[0191] The mesh-like design within the first sub-area of ​​the first power line in this example ensures a symmetrical design of the circuit structure layer, thereby avoiding display differences at different viewing angles (e.g., differences in left and right viewing angles) caused by the circuit structure layer.

[0192] In some examples, the second anode connection electrode 431a may be located in a siding region between the third extension segment 443a and the second extension segment 442a. The shape of the second anode connection electrode 431a may be dumbbell-shaped, extending approximately along the second direction Y. The second anode connection electrode 431a may also be electrically connected to the first anode connection electrode 422a via the 56th via V56, thereby achieving an electrical connection with the sixth transistor of the first pixel circuit 11a.

[0193] In some examples, the second anode connection electrode 431b may be located in a accommodating region between the third extension segment 443b and the second extension segment 442a. The shape of the second anode connection electrode 432b may be dumbbell-shaped, extending approximately along the second direction Y. The second anode connection electrode 431b may also be electrically connected to the first anode connection electrode 422b via the 57th via V57, thereby achieving an electrical connection with the sixth transistor of the first pixel circuit 11b.

[0194] In some examples, the second anode connection electrode 431c may be located in a accommodating region between the third extension segment 443b and the second extension segment 442b. The shape of the second anode connection electrode 432c may be dumbbell-shaped, extending substantially along the second direction Y. The second anode connection electrode 431c may also be electrically connected to the first anode connection electrode 422c via the 58th via V58, thereby achieving an electrical connection with the sixth transistor of the first pixel circuit 11c.

[0195] In some examples, the second anode connection electrode 431d may be located in a accommodating region between the third extension segment 443c and the second extension segment 442b. The shape of the second anode connection electrode 432d may be dumbbell-shaped, extending along one direction that intersects both the first and second directions. The second anode connection electrode 432d may also be electrically connected to the first anode connection electrode 422d via the 59th via V59, thereby achieving an electrical connection with the sixth transistor of the first pixel circuit 11d.

[0196] In some examples, the shapes of the third anode connection electrodes 432a, 432b, 432c, and 432d are substantially rectangular, and the rectangle has chamfers and rounded corners. The third anode connection electrodes 432a, 432b, 432c, and 432d may be located within a region formed by being surrounded by first extension segments 441a and 441b adjacent in the second direction Y, and fourth extension segments 444a and 44b adjacent in the first direction X. The third anode connection electrodes 432a and 432b are aligned along the first direction X and adjacent to the first extension segment 441a in one first sub-area in the second direction Y. The third anode connection electrodes 423c and 423d may be aligned along the first direction X and adjacent to the first extension segment 441b in another first sub-area in the second direction Y.

[0197] (12) A ninth insulating layer is formed. In some examples, a ninth insulating thin film is applied to the base on which the above pattern is formed, and the ninth insulating thin film is patterned by a patterning process to form a ninth insulating layer. In some examples, the ninth insulating layer may further be referred to as a third flat layer.

[0198] Figure 18 is a schematic diagram of the first display area after the ninth insulating layer has been formed in Figure 6. In some examples, as shown in Figure 18, multiple vias may be opened in the ninth insulating layer of the first display area, for example, including vias 61 to 68. The ninth insulating layer within vias 61 to 68 may be removed, exposing a portion of the surface of the sixth conductive layer.

[0199] Up to this point, the manufacturing of the circuit structure layer can be completed. The film layer structure of the circuit structure layer in the second display area is similar to that of the film layer in the first display area, so it will not be explained again here.

[0200] (13) A conductive connection layer is formed. In some examples, a transparent conductive thin film is deposited on the base on which the above pattern is formed, and the transparent conductive thin film is patterned by a patterning process to form a conductive connection layer. In this example, one conductive connection layer is described as an example. However, this embodiment is not limited to this. In other examples, multiple conductive connection layers may be provided, or a flat layer may be provided between adjacent conductive connection layers.

[0201] Figure 19A is a schematic diagram of the first display area after the conductive connection layer has been formed in Figure 6. Figure 19B is a schematic diagram of the conductive connection layer in Figure 19A.

[0202] In some examples, as shown in Figures 19A and 19B, the conductive connection layer of the first display area may include a plurality of conductive connection wires (e.g., conductive connection wires 15a, 15b, 15c, and 15d) and a plurality of fourth anode connection electrodes (e.g., fourth anode connection electrodes 461a, 461b, 461c, and 461d).

[0203] In some examples, the shape of the fourth anode connection electrodes 461a, 461b, 461c, and 461d may be substantially rectangular, and the rectangle may have rounded corners or bevels. The fourth anode connection electrode 461a may be electrically connected to the second anode connection electrode 431a via the 61st via V61. The fourth anode connection electrode 461b may be electrically connected to the second anode connection electrode 431b via the 62nd via V62. The fourth anode connection electrode 461c may be electrically connected to the second anode connection electrode 431c via the 63rd via V63. The fourth anode connection electrode 461d may be electrically connected to the second anode connection electrode 431d via the 64th via V64.

[0204] In some examples, multiple conductive connection lines may extend at least along a first direction X, from a first display area to a second display area, and be electrically connected to a second pixel circuit in the second display area. Conductive connection line 15a may be electrically connected to a third anode connection electrode 432a via via 65 V65, conductive connection line 15b may be electrically connected to a third anode connection electrode 432c via via 66 V66, conductive connection line 15c may be electrically connected to a third anode connection electrode 432b via via 67 V67, and conductive connection line 15d may be electrically connected to a third anode connection electrode 432d via via 68 V68. The orthographic projection of the base of the conductive connection line may overlap with the orthographic projection of the base of at least one first pixel circuit. For example, the orthographic projections of the bases of the conductive connection lines 15a, 15b, 15c, and 15d may all overlap with the orthographic projections of the bases of the four first pixel circuits connected to the four first light-emitting elements of the first light-emitting unit in the a-th column and b+1-th row.

[0205] In some examples, the conductive connection layer may be made of a transparent conductive material, such as ITO. The conductive connection wire passes through the second sub-area, but it is possible to avoid affecting the light transmittance of the second sub-area.

[0206] (14) A light-emitting structure layer is formed. In some examples, a tenth insulating thin film is applied to the base on which the above pattern is formed, and the tenth insulating thin film is patterned by a patterning process to form a tenth insulating layer. Multiple vias may be opened in the tenth insulating layer, and the multiple vias may expose the surface of a portion of the conductive connection layer. Subsequently, an anode thin film is deposited on the base on which the above pattern is formed, and the anode thin film is patterned by a patterning process to form an anode layer.

[0207] Figure 20 is a schematic diagram of the first display area after the anode layer has been formed in Figure 6. In some examples, as shown in Figure 20, the first display area may include the anodes of a plurality of first light-emitting elements (e.g., the anode 211a of the first light-emitting element 21a, the anode 211b of the first light-emitting element 21b, the anode 211c of the first light-emitting element 21c, and the anode 211d of the first light-emitting element 21d), and the anodes of a plurality of second light-emitting elements (e.g., the anode 221a of the second light-emitting element 22a, the anode 221b of the second light-emitting element 22b, the anode 221c of the second light-emitting element 22c, and the anode 221d of the second light-emitting element 22d).

[0208] In some examples, the anode 211a of the first light-emitting element 21a that emits a first color of light may be electrically connected to the fourth anode connection electrode 461a via a via opened in the tenth insulating layer. The anode 211b of the first light-emitting element 21b that emits a second color of light may be electrically connected to the fourth anode connection electrode 461c via a via opened in the tenth insulating layer. The anode 211c of the first light-emitting element 21c that emits a third color of light may be electrically connected to the fourth anode connection electrode 461b via a via opened in the tenth insulating layer. The anode 211d of the first light-emitting element 21d that emits a third color of light may be electrically connected to the fourth anode connection electrode 461d via a via opened in the tenth insulating layer.

[0209] In some examples, the anode 221a of the second light-emitting element 22a that emits a first color of light may be electrically connected to a conductive connection line 15c via a via opened in the tenth insulating layer. The anode 221b of the second light-emitting element 22b that emits a second color of light may be electrically connected to a conductive connection line 15a via a via opened in the tenth insulating layer. The anode 221c of the second light-emitting element 22c that emits a third color of light may be electrically connected to a conductive connection line 15b via a via opened in the tenth insulating layer. The anode 221d of the second light-emitting element 22d that emits a third color of light may be electrically connected to a conductive connection line 15d via a via opened in the tenth insulating layer.

[0210] In some examples, a pixel-defining thin film is applied to a base on which the aforementioned pattern is formed, and a pixel-defining layer is formed by the processes of masking, exposure, and development. Multiple pixel apertures exposing the anode layer may be formed in the pixel-defining layer. An organic light-emitting layer is formed within the formed pixel apertures, and the organic light-emitting layer is connected to the anode layer. Subsequently, a cathode thin film is deposited, and the cathode thin film is patterned by a patterning process to form a cathode pattern, and the cathode is connected to the organic light-emitting layer.

[0211] In some examples, as shown in Figure 6, the pixel definition layer of the first display area may include a plurality of first pixel apertures (e.g., first pixel apertures 210a, 210b, 210c, and 210d) and a plurality of second pixel apertures (e.g., second pixel circuits 220a, 220b, 220c, and 220d). The shapes of the plurality of first pixel apertures and the plurality of second pixel apertures may be approximately circular.

[0212] In some examples, the first pixel aperture 210a may expose a portion of the surface of the anode 211a, the first pixel aperture 210b may expose a portion of the surface of the anode 211b, the first pixel aperture 210c may expose a portion of the surface of the anode 211c, and the first pixel aperture 210d may expose a portion of the surface of the anode 211d. The second pixel aperture 220a may expose a portion of the surface of the anode 221a, the second pixel aperture 220b may expose a portion of the surface of the anode 221b, the second pixel aperture 220c may expose a portion of the surface of the anode 221c, and the second pixel aperture 220d may expose a portion of the surface of the anode 221d.

[0213] In some examples, the light-emitting area of ​​the first light-emitting element 21b that emits a second color of light may be larger than the light-emitting area of ​​the first light-emitting element 21a that emits a first color of light. The light-emitting area of ​​the first light-emitting element 21a that emits a first color of light may be larger than the light-emitting area of ​​the first light-emitting element 21c or 21d that emit a third color of light. The light-emitting areas of the first light-emitting elements 21c and 21d that emit a third color of light may be the same. In this example, the light-emitting area of ​​the light-emitting element may refer to the area of ​​the stacked region of the anode, organic light-emitting layer and cathode that is exposed from the pixel aperture of the pixel definition layer.

[0214] In some examples, the light-emitting area of ​​the second light-emitting element 22b that emits the second color of light may be larger than the light-emitting area of ​​the second light-emitting element 22a that emits the first color of light. The light-emitting area of ​​the second light-emitting element 22a that emits the first color of light may be larger than the light-emitting area of ​​the second light-emitting element 22c or 22d that emits the third color of light. The light-emitting areas of the second light-emitting elements 22c and 22d that emit the third color of light may be the same.

[0215] In some examples, the light-emitting area of ​​the first light-emitting element may be larger than the light-emitting area of ​​the second light-emitting element that emits light of the same color. For example, the ratio of the light-emitting areas of the second light-emitting element and the first light-emitting element that emit light of the same color may be 0.4 to 0.8, or for example, about 0.5. For example, the light-emitting area of ​​the second light-emitting element 22a that emits light of the first color may be about half the light-emitting area of ​​the first light-emitting element 21a that emits light of the first color. The light-emitting area of ​​the second light-emitting element 22b that emits light of the second color may be about half the light-emitting area of ​​the first light-emitting element 21b that emits light of the second color. The light-emitting area of ​​the second light-emitting element 22c (or 22d) that emits light of the third color may be about half the light-emitting area of ​​the first light-emitting element 21c (or 21d) that emits light of the third color.

[0216] This example reduces the light-emitting area of ​​the second light-emitting element, thereby mitigating the situation where the brightness of the second light-emitting element is dim due to a decrease in current density caused by a large load on the conductive connection lines, and is advantageous for improving the brightness of the second light-emitting element.

[0217] In some examples, the pixel definition layer of the first sub-area may use a black material to shield the first pixel circuit and wiring of the first sub-area, and the pixel definition layer of the second sub-area may use a transparent material to improve the light transmittance of the second sub-area. This embodiment is not limited to these examples.

[0218] In some examples, after manufacturing the light-emitting structural layer, a sealing layer may be formed on the cathode, and the sealing layer may include a laminated structure of inorganic material / organic material / inorganic material.

[0219] In some examples, the first, second, third, fourth, fifth, and sixth conductive layers may be made of metallic materials, such as one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first, second, third, fourth, fifth, and sixth conductive layers may be made of one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON), and may be a single layer, multi-layer structure, or composite layer. The seventh, eighth, and ninth insulating layers may be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer may be made of an organic material such as polyimide, acrylic, or polyethylene terephthalate. The anode layer may be made of a reflective material such as metal, and the cathode may be made of a transparent conductive material. However, this embodiment is not limited to these materials.

[0220] The structure of the display board and its manufacturing process in this embodiment are merely illustrative descriptions. In some exemplary embodiments, the structure can be modified or the patterning process can be increased or decreased according to actual demand. The manufacturing process according to this exemplary embodiment can be implemented using currently mature manufacturing equipment, is highly compatible with conventional manufacturing processes, is easy to implement, has high production efficiency, low production costs, and a high yield rate.

[0221] In some examples, the structure of the second and third pixel circuits in the second display area may be approximately the same as the structure of the first pixel circuit, the third light-emitting element emitting light of the same color may have approximately the same light-emitting area as the first light-emitting element, and the structure of the third light-emitting element in the second display area may be approximately the same as the structure of the first light-emitting element; therefore, these will not be explained again here.

[0222] The display board in this example incorporates a first pixel circuit connected to the first light-emitting element of the first display area, and has an externally located second pixel circuit connected to the second light-emitting element. This allows for a rational layout of light-emitting elements with externally located pixel circuits and light-emitting elements with internally located pixel circuits, achieving an optimal combination of light transmittance and size for the first display area, thereby improving the performance and user experience of the display board.

[0223] Figure 21 is another illustrative diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 21, the first sub-area A11 and the second sub-area A12 of the first display area may be spaced apart along the second direction Y. The first sub-area A11 may include a row of first light-emitting units 2a (including a plurality of first light-emitting units 2a installed sequentially along the first direction X), and the second sub-area A12 may include a row of second light-emitting units 2b (including a plurality of second light-emitting units 2b installed sequentially along the first direction X). In the second direction Y, the first light-emitting units 2a and the second light-emitting units 2b may be aligned and spaced apart.

[0224] In some examples, as shown in Figure 21, the first light-emitting unit 2a may include a first light-emitting element 21a that emits light of a first color, a first light-emitting element 21b that emits light of a second color, and first light-emitting elements 21c and 21d that emit light of two third colors. The second light-emitting unit 2b may include a second light-emitting element 22a that emits light of a first color, a second light-emitting element 22b that emits light of a second color, and second light-emitting elements 22c and 22d that emit light of two third colors. The arrangement of the light-emitting elements in this example can be found in the description of the above embodiment and will not be repeated here.

[0225] In this example, the display board is arranged such that a row of first light-emitting units and a row of second light-emitting units are spaced apart in a second direction. This allows for a rational layout of light-emitting elements with externally placed pixel circuits and light-emitting elements with built-in pixel circuits, achieving an optimal combination of light transmittance and size for the first display area, thereby improving the performance and user experience of the display board. The remaining details regarding the display board in this example can be found in the description of the previously mentioned embodiment and will not be repeated here.

[0226] Figure 22 is another illustrative diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 22, the first sub-area A11 and the second sub-area A12 of the first display area may be spaced apart along the first direction X. The first sub-area A11 may include a row of first light-emitting units 2a (including a plurality of first light-emitting units 2a installed sequentially along the second direction Y), and the second sub-area A12 may include a row of second light-emitting units 2b (including a plurality of second light-emitting units 2b installed sequentially along the second direction Y). In the first direction X, the first light-emitting units 2a and the second light-emitting units 2b may be aligned and spaced apart.

[0227] In this example, the display board is arranged such that a row of first light-emitting units and a row of second light-emitting units are spaced apart in the first direction. This allows for a rational layout of light-emitting elements with externally placed pixel circuits and light-emitting elements with built-in pixel circuits, achieving an optimal combination of light transmittance and size for the first display area, thereby improving the performance and user experience of the display board. Further details regarding the display board in this example can be found in the description of the previously mentioned embodiment and will not be repeated here.

[0228] Figure 23 is another illustrative diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 23, the first sub-area A11 and the second sub-area A12 of the first display area may be spaced apart in either the first direction X or the second direction Y. The first sub-area A11 may include two first light-emitting units 2a installed sequentially along the first direction X, and the second sub-area A12 may include two second light-emitting units 2b installed sequentially along the first direction X. In the first direction X, the two first light-emitting units 2a and the two second light-emitting units 2b may be aligned and spaced apart. In the second direction Y, one first light-emitting unit 2a and one second light-emitting unit 2b may be aligned and spaced apart. However, this embodiment is not limited thereto. In other examples, the two first light-emitting units and the one second light-emitting unit may be spaced apart in a first direction, or the two first light-emitting units and the one second light-emitting unit may be spaced apart in a second direction.

[0229] In this example, the display board is arranged such that two first light-emitting units and two second light-emitting units are spaced apart in the first and second directions. This allows for a rational layout of light-emitting elements with externally placed pixel circuits and light-emitting elements with built-in pixel circuits, achieving an optimal combination of light transmittance and size for the first display area, thereby improving the performance and user experience of the display board. The remaining details regarding the display board in this example can be found in the description of the previously mentioned embodiment and will not be repeated here.

[0230] Figure 24 is another illustrative diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 24, the first sub-area A11 and the second sub-area A12 of the first display area may be spaced apart along either the first direction X or the second direction Y. The first sub-area A11 may include one first light-emitting unit 2a, and the second sub-area A12 may include one second light-emitting unit 2b. In the second direction Y, the first light-emitting unit 2a and the second light-emitting unit 2b may be aligned and spaced apart. In the first direction X, the first light-emitting unit 2a and the second light-emitting unit 2b may be aligned and spaced apart.

[0231] In some examples, as shown in Figure 24, the first light-emitting unit 2a may include a first light-emitting element 21a that emits a first color of light, a first light-emitting element 21b that emits a second color of light, and two first light-emitting elements 21c and 21d that emit two third colors of light. The first light-emitting elements 21a and 21b may be spaced apart in the same column of light-emitting elements, the first light-emitting elements 21c and 21d may be spaced apart in the same column of light-emitting elements, and the first light-emitting elements 21a, 21b, 21c and 21d may be spaced apart in the light-emitting elements of different rows.

[0232] In some examples, as shown in Figure 24, the second light-emitting unit 2b may include a second light-emitting element 22a that emits a first color of light, a second light-emitting element 22b that emits a second color of light, and two second light-emitting elements 22c and 22d that emit two third colors of light. The second light-emitting elements 22a and 22b may be spaced apart in the same column of light-emitting elements, the second light-emitting elements 22c and 22d may be spaced apart in the same column of light-emitting elements, and the second light-emitting elements 22a, 22b, 22c and 22d may be spaced apart in the light-emitting elements of different rows.

[0233] In this example, the display board is designed so that the first light-emitting unit (including four first light-emitting elements arranged in two vertical rows) and the second light-emitting unit (including four second light-emitting elements arranged in two vertical rows) are spaced apart in both the first and second directions. This allows for a rational layout of light-emitting elements with externally located pixel circuits and light-emitting elements with built-in pixel circuits, achieving an optimal combination of light transmittance and size for the first display area, thereby improving the performance and user experience of the display board. Further details regarding the display board in this example can be found in the description of the previously mentioned embodiment and will not be repeated here.

[0234] Figure 25 is another illustrative diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 25, the first sub-area A11 and the second sub-area A12 of the first display area may be spaced apart along the first direction X. The first sub-area A11 may include a row of first light-emitting units 2a (including a plurality of first light-emitting units 2a installed sequentially along the second direction Y), and the second sub-area A12 may include a row of second light-emitting units 2b (including a plurality of second light-emitting units 2b installed sequentially along the second direction Y). In the first direction X, the first light-emitting units 2a and the second light-emitting units 2b may be aligned and spaced apart.

[0235] In this example, the display board is arranged such that the first light-emitting unit (including four first light-emitting elements arranged in two vertical rows) and the second light-emitting unit (including four second light-emitting elements arranged in two vertical rows) are spaced apart in the first direction. This allows for a rational layout of light-emitting elements with externally located pixel circuits and light-emitting elements with built-in pixel circuits, achieving an optimal combination of light transmittance and size for the first display area, thereby improving the performance and user experience of the display board. Further details regarding the display board in this example can be found in the description of the previously mentioned embodiment and will not be repeated here.

[0236] Figure 26 is another illustrative diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 26, the first sub-area A11 and the second sub-area A12 of the first display area may be spaced apart along the second direction Y. The first sub-area A11 may include a row of first light-emitting units 2a (including a plurality of first light-emitting units 2a installed sequentially along the first direction X), and the second sub-area A12 may include a row of second light-emitting units 2b (including a plurality of second light-emitting units 2b installed sequentially along the first direction X). In the second direction Y, the first light-emitting units 2a and the second light-emitting units 2b may be aligned and spaced apart.

[0237] In this example, the display board is arranged such that the first light-emitting unit (including four first light-emitting elements arranged in two vertical rows) and the second light-emitting unit (including four second light-emitting elements arranged in two vertical rows) are spaced apart in a second direction. This allows for a rational layout of light-emitting elements with externally located pixel circuits and light-emitting elements with built-in pixel circuits, achieving an optimal combination of light transmittance and size for the first display area, thereby improving the performance and user experience of the display board. The remaining details regarding the display board in this example can be found in the description of the previously mentioned embodiment and will not be repeated here.

[0238] Figure 27 is another illustrative diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 27, the first sub-area A11 and the second sub-area A12 of the first display area may be spaced apart along either the first direction X or the second direction Y. The first sub-area A11 may include one first light-emitting unit 2a, and the second sub-area A12 may include one second light-emitting unit 2b. In the second direction Y, the first light-emitting unit 2a and the second light-emitting unit 2b may be aligned and spaced apart. In the first direction X, the first light-emitting unit 2a and the second light-emitting unit 2b may be aligned and spaced apart.

[0239] In some examples, as shown in Figure 27, the first light-emitting unit 2a may include a first light-emitting element 21a that emits light of a first color, a first light-emitting element 21b that emits light of a second color, and a first light-emitting element 21c that emits light of a third color. The first light-emitting elements 21a and 21b may be spaced apart in the same row of light-emitting elements, the first light-emitting element 21c may be spaced apart in the same row of light-emitting elements, and the first light-emitting elements 21a, 21b, and 21c may be spaced apart in different rows of light-emitting elements. The arrangement of the three first light-emitting elements in the first light-emitting unit 2a forms a roughly triangular shape.

[0240] In some examples, as shown in Figure 27, the second light-emitting unit 2b may include a second light-emitting element 22a that emits one first color of light, a second light-emitting element 22b that emits one second color of light, and second light-emitting elements 22c and 22d that emit one third color of light. The second light-emitting elements 22a and 22b may be spaced apart in the same row of light-emitting elements, the second light-emitting element 22c may be spaced apart in the same row of light-emitting elements, and the second light-emitting elements 22a, 22b and 22c may be spaced apart in different rows of light-emitting elements. The arrangement of the three first light-emitting elements in the second light-emitting unit 2b forms a roughly triangular shape.

[0241] In this example, the display board is designed so that the first light-emitting unit (including three first light-emitting elements arranged in a triangle) and the second light-emitting unit (including three second light-emitting elements arranged in a triangle) are spaced apart in both the first and second directions. This allows for a rational layout of light-emitting elements with externally located pixel circuits and light-emitting elements with built-in pixel circuits, achieving an optimal combination of light transmittance and size for the first display area, thereby improving the performance and user experience of the display board. The remaining details regarding the display board in this example can be found in the description of the previously mentioned embodiment and will not be repeated here.

[0242] Figure 28 is another illustrative diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 28, the first sub-area A11 and the second sub-area A12 of the first display area may be spaced apart along the second direction Y. The first sub-area A11 may include one row of first light-emitting units 2a, and the second sub-area A12 may include one row of second light-emitting units 2b. In the second direction Y, the first light-emitting units 2a and the second light-emitting units 2b may be aligned and spaced apart.

[0243] In this example, the display board is arranged such that the first light-emitting unit (including three first light-emitting elements arranged in a triangle) and the second light-emitting unit (including three second light-emitting elements arranged in a triangle) are spaced apart in a second direction. This allows for a rational layout of light-emitting elements with externally located pixel circuits and light-emitting elements with internally located pixel circuits, achieving an optimal combination of light transmittance and size, thereby improving the performance and user experience of the display board. The remaining details regarding the display board in this example can be found in the description of the previously mentioned embodiment and will not be repeated here.

[0244] Figure 29 is another illustrative diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 29, the first sub-area A11 and the second sub-area A12 of the first display area may be spaced apart along the first direction X. The first sub-area A11 may include a row of first light-emitting units 2a, and the second sub-area A12 may include a row of second light-emitting units 2b. In the first direction X, the first light-emitting units 2a and the second light-emitting units 2b may be aligned and spaced apart.

[0245] In this example, the display board is configured such that the first light-emitting unit (including three first light-emitting elements arranged in a triangle) and the second light-emitting unit (including three second light-emitting elements arranged in a triangle) are spaced apart in the first direction. This allows for a rational layout of light-emitting elements with externally located pixel circuits and light-emitting elements with built-in pixel circuits, achieving an optimal combination of light transmittance and size for the first display area, thereby improving the performance and user experience of the display board. Further details regarding the display board in this example can be found in the description of the previously mentioned embodiment and will not be repeated here.

[0246] Figure 30 is another illustrative diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 30, the first sub-area A11 and the second sub-area A12 of the first display area may be spaced apart along either the first direction X or the second direction Y. The first sub-area A11 may include one first light-emitting unit 2a, and the second sub-area A12 may include one second light-emitting unit 2b. In the first direction X and the second direction Y, the first light-emitting unit 2a and the second light-emitting unit 2b may be aligned and spaced apart.

[0247] In some examples, as shown in Figure 30, the first light-emitting unit 2a may include a first light-emitting element 21a that emits light of a first color, a first light-emitting element 21b that emits light of a second color, and a first light-emitting element 21c that emits light of a third color. The first light-emitting elements 21a, 21c, and 21b may be arranged sequentially along the first direction X. The second light-emitting unit 2b may include a second light-emitting element 22a that emits light of a first color, a second light-emitting element 22b that emits light of a second color, and second light-emitting elements 22c and 22d that emit light of a third color. The second light-emitting elements 22a, 22c, and 22b may be arranged sequentially along the first direction X. In this example, the light-emitting element may be arranged periodically along the first direction X, with a repeating unit consisting of a light-emitting element that emits a first color of light, a light-emitting element that emits a third color of light, and a light-emitting element that emits a second color of light. In the second direction Y, light-emitting elements that emit light of the same color may be aligned and installed.

[0248] In this example, the display board is configured such that the first light-emitting unit (including three first light-emitting elements arranged along the first direction) and the second light-emitting unit (including three second light-emitting elements arranged along the first direction) are spaced apart in both the first and second directions. This allows for a rational layout of light-emitting elements with externally located pixel circuits and light-emitting elements with built-in pixel circuits, thereby achieving an optimal combination of light transmittance and size for the first display area, and improving the performance and user experience of the display board. Further details regarding the display board in this example can be found in the description of the previously mentioned embodiment and will not be repeated here.

[0249] Figure 31 is another illustrative diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 31, the first sub-area A11 and the second sub-area A12 of the first display area may be spaced apart along the second direction Y. The first sub-area A11 may include a row of first light-emitting units 2a, and the second sub-area A12 may include a row of second light-emitting units 2b. In the second direction Y, the first light-emitting units 2a and the second light-emitting units 2b may be aligned and spaced apart. However, this embodiment is not limited thereto. In other examples, the first sub-area and the second sub-area may be spaced apart along the first direction X. The first sub-area may include a row of first light-emitting units, and the second sub-area may include a row of second light-emitting units.

[0250] In this example, the display board is configured such that the first light-emitting unit (including three first light-emitting elements arranged along the first direction) and the second light-emitting unit (including three second light-emitting elements arranged along the first direction) are spaced apart in the second direction. This allows for a rational layout of light-emitting elements with externally located pixel circuits and light-emitting elements with built-in pixel circuits, thereby achieving an optimal combination of light transmittance and size for the first display area, and improving the performance and user experience of the display board. The remaining details regarding the display board in this example can be found in the description of the previously mentioned embodiment and will not be repeated here.

[0251] Figure 32 is another illustrative diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 32, the light-emitting elements of the first display area may be periodically arranged along a first direction X with a repeating unit consisting of a light-emitting element that emits a second color of light (e.g., blue light B), a light-emitting element that emits a first color of light (e.g., red light R), and a light-emitting element that emits a third color of light (e.g., green light G), and in a second direction Y, the light-emitting elements that emit the same color of light may be offset. The light-emitting elements that emit the second color of light in one row of repeating units may be aligned in the second direction Y with the light-emitting elements that emit the first color of light in the row above. The light-emitting elements in adjacent rows may be arranged so as to be offset by one element in the second direction Y.

[0252] In some examples, as shown in Figure 32, the first sub-area A11 and the second sub-area A12 of the first display area may be spaced apart in a fourth direction D4 that intersects both the first direction X and the second direction Y. The first sub-area A11 may include a plurality of first light-emitting units 2a installed sequentially along the third direction D3, and the second sub-area A12 may include a plurality of second light-emitting units 2b installed sequentially along the third direction D3, and the third direction D3 may intersect with the fourth direction D4, for example, they may be perpendicular to each other. The first light-emitting unit 2a may include three first light-emitting elements, and the second light-emitting unit 2b may include three second light-emitting elements.

[0253] In this example, the display board is arranged such that the first light-emitting unit (including three first light-emitting elements arranged along the first direction) and the second light-emitting unit (including three second light-emitting elements arranged along the first direction) are spaced apart in a fourth direction that intersects both the first and second directions. This allows for a rational layout of light-emitting elements with externally placed pixel circuits and light-emitting elements with built-in pixel circuits, thereby achieving an optimal combination of light transmittance and size for the first display area, and improving the performance and user experience of the display board. The remaining details regarding the display board in this example can be found in the description of the previously mentioned embodiment and will not be repeated here.

[0254] Figure 33 is another illustrative diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 33, the light-emitting elements of the first display area may be periodically arranged along a first direction X, with a repeating unit consisting of a light-emitting element that emits a first color of light (e.g., blue light R), a light-emitting element that emits a second color of light (e.g., blue light B), and a light-emitting element that emits a third color of light (e.g., green light G), and in a second direction Y, the light-emitting elements that emit the same color of light may be offset. The light-emitting elements that emit the first color of light in one row of repeating units may be aligned in the second direction with the midline of the light-emitting elements that emit the second color of light and the light-emitting elements that emit the third color of light in the row above. The light-emitting elements in adjacent rows may be offset by 1.5 light-emitting elements in the second direction Y.

[0255] In some examples, as shown in Figure 33, the first sub-area A11 and the second sub-area A12 of the first display area may be spaced apart in the first direction X. The first sub-area A11 may include a plurality of first light-emitting units 2a installed sequentially along the second direction Y, and adjacent first light-emitting units 2a may be offset from each other. The second sub-area A12 may include a plurality of second light-emitting units 2b installed sequentially along the second direction Y, and adjacent second light-emitting units 2b may be offset from each other. The first light-emitting unit 2a may include three first light-emitting elements, and the second light-emitting unit 2b may include three second light-emitting elements.

[0256] In this example, the display board is configured such that the first light-emitting unit (including three first light-emitting elements arranged along the first direction) and the second light-emitting unit (including three second light-emitting elements arranged along the first direction) are spaced apart in the first direction. This allows for a rational layout of light-emitting elements with externally located pixel circuits and light-emitting elements with built-in pixel circuits, thereby achieving an optimal combination of light transmittance and size for the first display area, and improving the performance and user experience of the display board. The remaining details regarding the display board in this example can be found in the description of the previously mentioned embodiment and will not be repeated here.

[0257] FIG. 34 is another exemplary view of the first display area according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 34, a plurality of first light-emitting units 2a and a plurality of second light-emitting units 2b in the first display area may be spaced apart within a plurality of circumferential regions with the center of the first display area as the center of the circle. The first sub-area A11 and the second sub-area A12 may be spaced apart along the direction from the center of the circle towards the edge. The first sub-area A11 may include at least one first light-emitting unit 2a, and the second sub-area A12 may include a plurality of second light-emitting units 2b. Along the direction from the center of the circle towards the edge, the number of first light-emitting units 2a in different first sub-areas A11 may be gradually increased, and the number of first light-emitting units 2b in different second sub-areas A12 may be gradually increased. The first light-emitting unit 2a may include three or four first light-emitting elements, and the second light-emitting unit 2b may include three or four second light-emitting elements. This embodiment does not limit this.

[0258] The display substrate of this example is installed such that the first light-emitting unit and the second light-emitting unit are spaced apart along the direction from the center of the circle towards the edge, so as to rationally layout the light-emitting elements with the pixel circuit externally arranged and the light-emitting elements with the pixel circuit built-in, and realize an optimal combination of the light transmittance and size of the first display area, thereby improving the performance of the display substrate and the user experience. Since the remaining description of the display substrate of this example can refer to the description of the foregoing embodiments, it will not be repeated here.

[0259] FIG. 35 is another exemplary view of the first display area according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 35, the light-emitting elements in the first display area are arranged such that the light-emitting elements that emit a plurality of lights of a third color (e.g., green light G) are arranged in a plurality of rows and a plurality of columns, and the light-emitting elements that emit the light of the first color (e.g., red light R) and the light of the second color (e.g., blue light B) are spaced apart in the row direction and the column direction, and the light-emitting elements that emit the light of the first color and the light-emitting elements that emit the light of the third color are arranged in different rows and different columns.

[0260] In some examples, as shown in FIG. 35, the first light-emitting unit may include one first light-emitting element, and the second light-emitting unit may include the first second light-emitting element. In the first direction X, one first light-emitting unit and one second light-emitting unit are arranged at intervals. In one row of light-emitting elements, the first light-emitting element and the second light-emitting element are arranged at intervals. For example, the first light-emitting element and the second light-emitting element that emit light of the third color (G) are arranged at intervals, the first light-emitting element that emits light of the first color (R) and the second light-emitting element that emits light of the second color (B) are arranged at intervals, or the first light-emitting element that emits light of the second color (B) and the second light-emitting element that emits light of the first color (R) are arranged at intervals.

[0261] In some examples, in the second direction Y, one first light-emitting unit and one second light-emitting unit are arranged at intervals, or two first light-emitting units and two second light-emitting units are arranged at intervals. In one column of light-emitting elements, the first light-emitting element and the second light-emitting element that emit light of the third color (G) are arranged one by one at intervals. In another column of light-emitting elements, two first light-emitting elements (including the first light-emitting element that emits light of the first color (R) and the first light-emitting element that emits light of the first color (B)) and two second light-emitting elements (including the second light-emitting element that emits light of the first color (R) and the first light-emitting element that emits light of the second color (B)) are arranged at intervals.

[0262] The display substrate in this example is arranged such that a single first light-emitting element and a single second light-emitting element are arranged at intervals in the first direction, and a single first light-emitting element and a single first light-emitting element or two first light-emitting elements and two second light-emitting elements are arranged at intervals in the second direction. By doing so, the light-emitting elements with external pixel circuits and the light-emitting elements with built-in pixel circuits are rationally laid out, and an optimal combination of the light transmittance and size of the first display area is realized, thereby improving the performance of the display substrate and the user experience. Since the remaining description of the display substrate in this example can refer to the description of the foregoing embodiments, it will not be repeated here.

[0263] Figure 36 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 36, this embodiment provides a display device including a display substrate 91 and a sensor 92 located on the light-emitting side of a light-emitting structure layer away from the display substrate 91. The sensor 92 may be located on the non-display side of the display substrate 91. The orthographic projection of the sensor 92 on the display substrate 91 may overlap with the first display area A1.

[0264] In some examples, the display board 91 may be a flexible OLED display board, a QLED display board, a Micro-LED display board, or a Mini-LED display board. The display device may be a product having an image display function (including static or dynamic images, where dynamic images may be video). For example, the display device may be any one of the following products: a display, a television, a sign, a digital frame, a laser printer with a display function, a telephone, a mobile phone, a paint screen, a personal digital assistant (PDA), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, an information query device (e.g., a business query device for e-government offices, banks, hospitals, power companies, etc.), a monitor, etc. The display device may also be any one of the following products: a microdisplay, a VR device or AR device including a microdisplay, etc.

[0265] The drawings in this disclosure relate only to the structures relating to this disclosure; for other structures, conventional designs may be referenced. Where there are no conflicts, new embodiments can be obtained by combining the embodiments and features of these embodiments. The embodiments or designs described above are illustrative and not restrictive. Therefore, this disclosure is not limited to what is described in detail herein. Various modifications, substitutions, or omissions can be made to the embodiments and details without departing from the scope of this disclosure. [Explanation of Symbols]

[0266] A1 First display area A2 Second display area 11. First pixel circuit 12. Second Pixel Circuit 21 First light-emitting element 22 Second light-emitting element 2a First light-emitting unit 2b Second light-emitting unit

Claims

1. A display board comprising a base, a plurality of first light-emitting units, a plurality of second light-emitting units, a plurality of first pixel circuits, and a plurality of second pixel circuits, The base includes a first display area and a second display area located on at least one side of the first display area. The plurality of first light-emitting units and the plurality of second light-emitting units are located in the first display area, the first light-emitting unit includes at least one first light-emitting element, the second light-emitting unit includes at least one second light-emitting element, and the first light-emitting unit is adjacent to at least one second light-emitting unit. The plurality of first pixel circuits are located in the first display area, and at least one of the plurality of first pixel circuits is electrically connected to the at least one first light-emitting element and configured to drive the emission of light from the at least one first light-emitting element. A display board wherein the plurality of second pixel circuits are located in the second display area, and at least one of the plurality of second pixel circuits is electrically connected to the at least one second light-emitting element and configured to drive the emission of light from the at least one second light-emitting element.

2. The display board according to claim 1, wherein the plurality of first light-emitting units and the plurality of second light-emitting units are installed at intervals along at least one of the first direction and the second direction, and the first direction intersects the second direction.

3. The display board according to claim 2, wherein in the first direction, one first light-emitting unit and one second light-emitting unit are installed with a gap between them, and in the second direction, one first light-emitting unit and one second light-emitting unit are installed with a gap between them.

4. The plurality of first light-emitting units include a plurality of rows of first light-emitting units, and each row of first light-emitting units includes a plurality of first light-emitting units that are sequentially installed along the second direction. The plurality of second light-emitting units includes a plurality of rows of second light-emitting units, and each row of second light-emitting units includes a plurality of second light-emitting units that are sequentially installed along the second direction. The display board according to claim 2, wherein, in the first direction, a row of first light-emitting units and a row of second light-emitting units are installed with an interval between them.

5. The plurality of first light-emitting units include a plurality of rows of first light-emitting units, and each row of first light-emitting units includes a plurality of first light-emitting units that are sequentially installed along the first direction. The plurality of second light-emitting units includes a plurality of rows of second light-emitting units, and each row of second light-emitting units includes a plurality of second light-emitting units that are sequentially installed along the first direction. The display board according to claim 2, wherein in the second direction, one row of first light-emitting units and one row of second light-emitting units are installed with a gap between them.

6. In the first direction, adjacent first light-emitting units and second light-emitting units are installed in alignment, and in the second direction, adjacent first light-emitting units and second light-emitting units are installed in alignment, Alternatively, the display substrate according to claim 2, wherein adjacent first light-emitting units and second light-emitting units in the second direction are offset from each other.

7. The display substrate according to any one of claims 1 to 6, wherein the ratio of the light-emitting areas of the second light-emitting element and the first light-emitting element that emit light of the same color is less than 1.

8. The display substrate according to any one of claims 1 to 7, wherein the number of first light-emitting elements included in at least one first light-emitting unit is the same as the number of second light-emitting elements included in at least one second light-emitting unit.

9. The at least one first light-emitting unit includes four first light-emitting elements, each of which is a first light-emitting element that emits light of one first color, a first light-emitting element that emits light of one second color, and a first light-emitting element that emits light of two third colors. The display substrate according to claim 8, wherein the at least one second light-emitting unit includes four second light-emitting elements, each second light-emitting element emitting light of one first color, and each second light-emitting element emitting light of two third colors.

10. The plurality of first light-emitting elements and the plurality of second light-emitting elements in the first display area are arranged in multiple rows and multiple columns. In the at least one first light-emitting unit, the two first light-emitting elements that emit the third color of light are arranged in the same row, the first light-emitting element that emits the first color of light and the first light-emitting element that emits the second color of light are arranged in the same row, and the four first light-emitting elements of the first light-emitting unit are arranged in different rows. The display substrate according to claim 9, wherein in at least one second light-emitting unit, the second light-emitting elements that emit the two third colors of light are arranged in the same row, the second light-emitting element that emits the first color of light and the second light-emitting element that emits the second color of light are arranged in the same row, and the four first light-emitting elements of the second light-emitting unit are arranged in different rows.

11. The plurality of first light-emitting elements and the plurality of second light-emitting elements in the first display area are arranged in multiple rows and multiple columns. In the at least one first light-emitting unit, the first light-emitting elements that emit the two third colors of light are installed in the same row, the first light-emitting element that emits the first color of light and the first light-emitting element that emits the second color of light are installed in the same row, and the four first light-emitting elements of the first light-emitting unit are installed in different columns. The display substrate according to claim 9, wherein in at least one second light-emitting unit, the second light-emitting elements that emit the two third colors of light are arranged in the same row, the first light-emitting element that emits the first color of light and the second light-emitting element that emits the second color of light are arranged in the same row, and the four second light-emitting elements of the second light-emitting unit are arranged in different columns.

12. The display substrate according to claim 11, wherein four first light-emitting elements in the first light-emitting unit are electrically connected in a one-to-one correspondence to four first pixel circuits, the four first pixel circuits are sequentially arranged along a first direction, and the orthographic projection of each first pixel circuit on the base at least partially overlaps with the orthographic projection of the connected first light-emitting elements on the base.

13. The display board according to claim 12, wherein the four first pixel circuits are arranged symmetrically with respect to a first midline along the first direction of the four first pixel circuits, the first and second first pixel circuits in the four first pixel circuits are arranged symmetrically with respect to a second midline along the first direction of the two first pixel circuits, and the third and fourth first pixel circuits are arranged symmetrically with respect to a third midline along the first direction of the two first pixel circuits.

14. The display board according to claim 12, wherein the four first pixel circuits are electrically connected to a first power line, and the first power line forms a mesh in the first display area.

15. In a direction perpendicular to the display board, the display board includes a circuit structure layer located at the base, the circuit structure layer includes the plurality of first pixel circuits and the plurality of second pixel circuits, and each pixel circuit in the plurality of first pixel circuits and the plurality of second pixel circuits includes at least one first type transistor, at least one second type transistor and a memory capacitor. The circuit structure layer includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer, which are installed on the base. The first semiconductor layer includes at least the active layer of the first type of transistor of the pixel circuit, The first conductive layer includes at least the gate electrode of the first type of transistor of the pixel circuit and the first electrode of the memory capacitor, The second conductive layer includes at least the second electrode of the memory capacitor of the pixel circuit, The second semiconductor layer includes at least the active layer of the second type of transistor of the pixel circuit, The third conductive layer includes at least the gate electrode of the second type of transistor of the pixel circuit, The fourth conductive layer includes at least a plurality of connecting electrodes, The fifth conductive layer includes at least a plurality of data lines, The display substrate according to claim 12 or 13, wherein the sixth conductive layer includes at least a first power line.

16. The first display area includes a plurality of first sub-areas and a plurality of second sub-areas, wherein at least one first sub-area in the plurality of first sub-areas is provided with at least one first light-emitting unit, and at least one second sub-area in the plurality of second sub-areas is provided with at least one second light-emitting unit. The second conductive layer further includes a first scanning line, a light emission control line, a first reset control line, and a second reset control line electrically connected to the first pixel circuit, wherein the first scanning line, the light emission control line, the first reset control line, and the second reset control line extend along a first direction. The display board according to claim 15, wherein in the second direction, the first scan line and the first reset control line bypass from one side of the second sub-area, the light emission control line and the second reset control line bypass from the other side of the second sub-area, and the second direction intersects with the first direction.

17. The first display area includes a plurality of first sub-areas and a plurality of second sub-areas, wherein at least one first sub-area in the plurality of first sub-areas is provided with at least one first light-emitting unit, and at least one second sub-area in the plurality of second sub-areas is provided with at least one second light-emitting unit. The third conductive layer further includes a first initial signal line, a second initial signal line, a third initial signal line, and a second scan line electrically connected to the first pixel circuit, the first initial signal line, the second initial signal line, the third initial signal line, and the second scan line extend along a first direction. The display board according to claim 15 or 16, wherein in the second direction, the first initial signal line and the second scan line bypass from one side of the second sub-area, the second initial signal line and the third initial signal line bypass from the other side of the second sub-area, and the second direction intersects with the first direction.

18. The display substrate according to any one of claims 1 to 17, wherein the quantity ratio of the first light-emitting unit to the second light-emitting unit in the first display area is 0.8 to 1.

2.

19. The light transmittance of the first display area is greater than the light transmittance of the second display area. The display board further includes a plurality of third light-emitting elements and a plurality of third pixel circuits located in the second display area, wherein at least one third pixel circuit in the plurality of third pixel circuits is electrically connected to at least one third light-emitting element in the plurality of third light-emitting elements and is configured to drive the emission of light from the at least one third light-emitting element. The display board according to any one of claims 1 to 18, wherein the plurality of second pixel circuits are installed with intervals between the plurality of third pixel circuits.

20. The orthogonal projection of the at least one first pixel circuit on its base overlaps with the orthogonal projection of the at least one first light-emitting element on its base. The display substrate according to any one of claims 1 to 19, wherein the at least one second pixel circuit is electrically connected to the at least one second light-emitting element via at least one conductive connecting line, and the orthographic projection of the at least one second pixel circuit on the base does not overlap with the orthographic projection of the at least one second light-emitting element on the base.

21. The display board according to claim 20, wherein the orthographic projection of the at least one conductive connection line on the base coincides with the orthographic projection of the at least one first pixel circuit on the base.

22. A display device comprising a display board according to any one of claims 1 to 21, and a sensor located on the non-display side of the display board, wherein the orthographic projection of the sensor on the display board at least partially overlaps with the first display area of ​​the display board.

Images