Fork seat device

Abstract

Fork seat device. A semiconductor structure comprising a dielectric bar positioned between a first source-drain region and a second source-drain region, physically isolating them; a first silicide liner directly beneath the first source-drain region; and a second silicide liner directly beneath the second source-drain region, wherein the first silicide liner is made of a different material from the second silicide liner.

Description

[Background technology]

[0001] The present invention relates in general to semiconductor structures, and more particularly to a fork seat device structure having dual backside silicides and a dense N2P spacing.

[0002] Complementary metal-oxide-semiconductor (CMOS) technology is commonly used for field-effect transistors (FETs) as part of advanced integrated circuits (ICs) such as central processing units (CPUs), memory, and storage devices. As the demand for reducing the size of transistor devices continues, nanosheet FETs help achieve a reduction in the footprint of FET devices while maintaining the performance of the FET devices. A nanosheet FET comprises multiple stacked nanosheets extending between sets of drain epitaxial regions. The device may be a gate-all-around device or transistor in which the gate surrounds a portion of the nanosheet channel. The nanosheet device comprises one or more layers of semiconductor channel material having a vertical thickness substantially less than its width. [Overview of the project]

[0003] According to one embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include a dielectric bar positioned between a first source-drain region and a second source-drain region, physically isolating them; a first silicide liner directly beneath the first source-drain region; and a second silicide liner directly beneath the second source-drain region, wherein the first silicide liner is made of a different material than the second silicide liner.

[0004] Another embodiment of the present invention provides a semiconductor structure. The semiconductor structure may comprise a first nanosheet device having a first source-drain region, a second nanosheet device having a second source-drain region, a dielectric bar disposed between each of the first and second source-drain regions and physically isolating them, a first silicide liner directly beneath the first source-drain region, and a second silicide liner directly beneath the second source-drain region, wherein the first silicide liner is made of a different material from the second silicide liner.

[0005] According to another embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may comprise an n-type nanosheet device having an n-type source-drain region, a p-type nanosheet device having a p-type source-drain region, a dielectric bar disposed between each of the n-type source-drain regions and each of the p-type source-drain regions to physically isolate them, a first silicide liner directly beneath the first source-drain region, and a second silicide liner directly beneath the second source-drain region, wherein the first silicide liner is made of a different material from the second silicide liner. [Brief explanation of the drawing]

[0006] The following detailed description is provided for illustrative purposes only and is not intended to limit the invention to therein, and will be best understood in conjunction with the accompanying drawings. [Figure 1] This is a cross-sectional view of a semiconductor structure during an intermediate step of a method for fabricating a fork seat device structure according to an exemplary embodiment. [Figure 2] This is a cross-sectional view of a semiconductor structure during an intermediate step of a method for fabricating a fork seat device structure according to an exemplary embodiment. [Figure 3] This is a cross-sectional view of a semiconductor structure during an intermediate step of a method for fabricating a fork seat device structure according to an exemplary embodiment. [Figure 4]This is a cross-sectional view of a semiconductor structure after the formation of a first hard mask according to an exemplary embodiment. [Figure 5] This is a cross-sectional view of a semiconductor structure after the formation of a first hard mask according to an exemplary embodiment. [Figure 6] This is a cross-sectional view of a semiconductor structure after the formation of a first hard mask according to an exemplary embodiment. [Figure 7] This is a cross-sectional view of a semiconductor structure after forming sidewall spacers and patterning the nanosheet layer and substrate, according to an exemplary embodiment. [Figure 8] This is a cross-sectional view of a semiconductor structure after forming sidewall spacers and patterning the nanosheet layer and substrate, according to an exemplary embodiment. [Figure 9] This is a cross-sectional view of a semiconductor structure after forming sidewall spacers and patterning the nanosheet layer and substrate, according to an exemplary embodiment. [Figure 10] This is a cross-sectional view of a semiconductor structure after a dielectric bar has been formed, according to an exemplary embodiment. [Figure 11] This is a cross-sectional view of a semiconductor structure after a dielectric bar has been formed, according to an exemplary embodiment. [Figure 12] This is a cross-sectional view of a semiconductor structure after a dielectric bar has been formed, according to an exemplary embodiment. [Figure 13] This is a cross-sectional view of a semiconductor structure after forming a shallow trench isolation region according to an exemplary embodiment. [Figure 14] This is a cross-sectional view of a semiconductor structure after forming a shallow trench isolation region according to an exemplary embodiment. [Figure 15] This is a cross-sectional view of a semiconductor structure after forming a shallow trench isolation region according to an exemplary embodiment. [Figure 16] This is a cross-sectional view of a semiconductor structure after forming and patterning a sacrificial gate dielectric and a sacrificial gate, forming a gate spacer, removing a portion of the nanosheet stack, and forming an inner spacer, according to an exemplary embodiment. [Figure 17]Cross-sectional view of a semiconductor structure after forming and patterning a sacrificial gate dielectric and a sacrificial gate, forming a gate spacer, removing a portion of a nanosheet stack, and forming an inner spacer, according to an exemplary embodiment. [Figure 18] Cross-sectional view of a semiconductor structure after forming and patterning a sacrificial gate dielectric and a sacrificial gate, forming a gate spacer, removing a portion of a nanosheet stack, and forming an inner spacer, according to an exemplary embodiment. [Figure 19] Cross-sectional view of a semiconductor structure after forming a sacrificial liner, forming a patterning mask, and selectively removing a portion of the sacrificial liner with respect to the patterning mask, according to an exemplary embodiment. [Figure 20] Cross-sectional view of a semiconductor structure after forming a sacrificial liner, forming a patterning mask, and selectively removing a portion of the sacrificial liner with respect to the patterning mask, according to an exemplary embodiment. [Figure 21] Cross-sectional view of a semiconductor structure after forming a sacrificial liner, forming a patterning mask, and selectively removing a portion of the sacrificial liner with respect to the patterning mask, according to an exemplary embodiment. [Figure 22] Cross-sectional view of a semiconductor structure after forming a sacrificial placeholder, according to an exemplary embodiment. [Figure 23] Cross-sectional view of a semiconductor structure after forming a sacrificial placeholder, according to an exemplary embodiment. [Figure 24] Cross-sectional view of a semiconductor structure after forming a sacrificial placeholder, according to an exemplary embodiment. [Figure 25] Cross-sectional view of a semiconductor structure after removing a sacrificial liner and forming a first source / drain region, a second source / drain region, and a dielectric layer, according to an exemplary embodiment. [Figure 26] Cross-sectional view of a semiconductor structure after removing a sacrificial liner and forming a first source / drain region, a second source / drain region, and a dielectric layer, according to an exemplary embodiment. [Figure 27]This is a cross-sectional view of a semiconductor structure according to an exemplary embodiment, after the sacrificial liner has been removed and the first source-drain region, the second source-drain region, and the dielectric layer have been formed. [Figure 28] This is a cross-sectional view of a semiconductor structure after forming the gate structure, source-drain contacts, middle-of-line and back-end, and mounting the carrier wafer, according to an exemplary embodiment. [Figure 29] This is a cross-sectional view of a semiconductor structure after forming the gate structure, source-drain contacts, middle-of-line and back-end, and mounting the carrier wafer, according to an exemplary embodiment. [Figure 30] This is a cross-sectional view of a semiconductor structure after forming the gate structure, source-drain contacts, middle-of-line and back-end, and mounting the carrier wafer, according to an exemplary embodiment. [Figure 31] This is a cross-sectional view of the semiconductor structure after the assembly has been inverted and the substrate has been recessed, according to an exemplary embodiment. [Figure 32] This is a cross-sectional view of the semiconductor structure after the assembly has been inverted and the substrate has been recessed, according to an exemplary embodiment. [Figure 33] This is a cross-sectional view of the semiconductor structure after the assembly has been inverted and the substrate has been recessed, according to an exemplary embodiment. [Figure 34] This is a cross-sectional view of the semiconductor structure after the remaining portion of the substrate has been removed, according to an exemplary embodiment. [Figure 35] This is a cross-sectional view of the semiconductor structure after the remaining portion of the substrate has been removed, according to an exemplary embodiment. [Figure 36] This is a cross-sectional view of the semiconductor structure after the remaining portion of the substrate has been removed, according to an exemplary embodiment. [Figure 37] This is a cross-sectional view of a semiconductor structure after a back surface dielectric layer has been formed, according to an exemplary embodiment. [Figure 38] This is a cross-sectional view of a semiconductor structure after a back surface dielectric layer has been formed, according to an exemplary embodiment. [Figure 39]This is a cross-sectional view of a semiconductor structure after a back surface dielectric layer has been formed, according to an exemplary embodiment. [Figure 40] This is a cross-sectional view of a semiconductor structure after the formation of a first back-side mask according to an exemplary embodiment. [Figure 41] This is a cross-sectional view of a semiconductor structure after the formation of a first back-side mask according to an exemplary embodiment. [Figure 42] This is a cross-sectional view of a semiconductor structure after the formation of a first back-side mask according to an exemplary embodiment. [Figure 43] This is a cross-sectional view of a semiconductor structure after removing the first portion of the sacrificial placeholder to create a first back surface trench, according to an exemplary embodiment. [Figure 44] This is a cross-sectional view of a semiconductor structure after removing the first portion of the sacrificial placeholder to create a first back surface trench, according to an exemplary embodiment. [Figure 45] This is a cross-sectional view of a semiconductor structure after removing the first portion of the sacrificial placeholder to create a first back surface trench, according to an exemplary embodiment. [Figure 46] This is a cross-sectional view of the semiconductor structure after removing the first back-side mask and performing shallow ion implantation, according to an exemplary embodiment. [Figure 47] This is a cross-sectional view of the semiconductor structure after removing the first back-side mask and performing shallow ion implantation, according to an exemplary embodiment. [Figure 48] This is a cross-sectional view of the semiconductor structure after removing the first back-side mask and performing shallow ion implantation, according to an exemplary embodiment. [Figure 49] This is a cross-sectional view of a semiconductor structure after forming a first silicide liner, a first adhesive liner, and a first sacrificial filler according to an exemplary embodiment. [Figure 50] This is a cross-sectional view of a semiconductor structure after forming a first silicide liner, a first adhesive liner, and a first sacrificial filler according to an exemplary embodiment. [Figure 51] This is a cross-sectional view of a semiconductor structure after forming a first silicide liner, a first adhesive liner, and a first sacrificial filler according to an exemplary embodiment. [Figure 52] This is a cross-sectional view of the semiconductor structure after removing the second portion of the sacrificial placeholder according to an exemplary embodiment to create a second back surface trench and performing another shallow ion implantation. [Figure 53] This is a cross-sectional view of the semiconductor structure after removing the second portion of the sacrificial placeholder according to an exemplary embodiment to create a second back surface trench and performing another shallow ion implantation. [Figure 54] This is a cross-sectional view of the semiconductor structure after removing the second portion of the sacrificial placeholder according to an exemplary embodiment to create a second back surface trench and performing another shallow ion implantation. [Figure 55] This is a cross-sectional view of a semiconductor structure after forming a second silicide liner, a second adhesive liner, and a second sacrificial filler according to an exemplary embodiment. [Figure 56] This is a cross-sectional view of a semiconductor structure after forming a second silicide liner, a second adhesive liner, and a second sacrificial filler according to an exemplary embodiment. [Figure 57] This is a cross-sectional view of a semiconductor structure after forming a second silicide liner, a second adhesive liner, and a second sacrificial filler according to an exemplary embodiment. [Figure 58] This is a cross-sectional view of a semiconductor structure after the first and second sacrificial fillers have been removed, the back surface source-drain contacts have been formed, and the back surface wiring layer has been formed, according to an exemplary embodiment. [Figure 59] This is a cross-sectional view of a semiconductor structure after the first and second sacrificial fillers have been removed, the back surface source-drain contacts have been formed, and the back surface wiring layer has been formed, according to an exemplary embodiment. [Figure 60] This is a cross-sectional view of a semiconductor structure after the first and second sacrificial fillers have been removed, the back surface source-drain contacts have been formed, and the back surface wiring layer has been formed, according to an exemplary embodiment.

[0007] The drawings are not necessarily to scale. The drawings are merely schematic representations and are not intended to represent specific parameters of the invention. For clarity and ease of illustration, the scale of elements may be shown larger than they actually are. The drawings are intended to illustrate only typical embodiments of the invention. In the drawings, similar reference numerals represent similar elements. [Modes for carrying out the invention]

[0008] Detailed embodiments of the claimed structure and method are disclosed herein; however, it should be understood that the disclosed embodiments are merely illustrative of the claimed structure and method, which may be embodied in various forms. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the exemplary embodiments described herein. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the embodiments presented.

[0009] References in the specification such as "one embodiment," "one example embodiment," and "one example embodiment" indicate that the embodiments described include certain features, structures, or characteristics, but not all embodiments necessarily include such specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, if certain features, structures, or characteristics are described in relation to one embodiment, it is considered within the knowledge of those skilled in the art that such features, structures, or characteristics will be affected in relation to other embodiments, whether explicitly described or not.

[0010] For the purposes of the following description, the terms “upper,” “downward,” “right,” “left,” “vertical,” “horizontal,” “upper,” and “lower” and their derivatives shall be those of the structure and method disclosed as oriented in the drawings. When an element, such as a layer, region, or substrate, is said to be "on" or "over" another element, it will be understood that it may be directly on that other element, or that there may be an intervening element. In contrast, when an element is said to be "directly on" or "directly over" another element, there is no intervening element. When an element is said to be "connected" or "coupled" to another element, it will also be understood that it may be directly connected or coupled to that other element, or that there may be an intervening element. In contrast, when an element is said to be "directly connected" or "directly coupled" to another element, there is no intervening element. Furthermore, the term "sublithographic" may refer to dimensions or sizes smaller than the current dimensions achievable by the photolithography process, and the term "lithographic" may refer to dimensions or sizes equal to or greater than the current dimensions achievable by the photolithography process. Sublithographic and lithographic dimensions may be determined by a person skilled in the art at the time this application is filed.

[0011] The terms substantially, substantially similar, approximately, or any other terms indicating functionally equivalent similarity refer to cases where differences in length, height, or orientation do not result in actual differences between a clear enumeration (e.g., a phrase without the term substantially similar) and substantially similar derivatives. In one embodiment, substantial (and its derivatives) means differences due to engineering or manufacturing tolerances generally accepted for similar devices, e.g., a maximum deviation of 10% in value or 10 degrees in angle.

[0012] To avoid ambiguity in the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations known in the art may be combined together for presentation and illustrative purposes, and in some cases may not be described in detail. In other cases, some processing steps or operations known in the art may not be described at all. It should be understood that the following description focuses rather on the specific features or elements of various embodiments of the present invention.

[0013] As semiconductor devices continue to shrink in size, it is becoming desirable to provide the distance between the nearest nFET and pFET active regions (i.e., the N2P spacing) on ​​the order of approximately 8 nanometers (nm) to 10 nm. Providing N2P spacings of these dimensions can present challenges to communication between pFET and nFET sections. Specifically, N2P spacings of this order reduce the process window, which can lead to electrical short circuits between contact structures connecting the nFET and pFET sections. While the process window can be widened by positioning contact structures laterally offset from the N2P spacing, this increases the electrical resistance between the contact structures and each pFET and nFET section, thereby offsetting any improvements in the process window and / or electrical characteristics of the multilayer IC device.

[0014] The ongoing trend towards reducing the footprint of FET devices has led to the development of fork-shaped nanosheet semiconductor devices, also known as "fork-sheet devices." Fork-sheet devices implement nanosheets controlled by a trigate fork-like structure. This trigate fork-like structure is realized by forming dielectric bars or dielectric walls between P-type and N-type devices. The dielectric bars physically separate two adjacent devices from each other, enabling much denser N2P spacing, which facilitates superior area and performance scalability compared to conventional nanosheet devices. However, the scalability achieved by fork-sheet devices, along with the introduction of dielectric bars, makes it difficult to maximize the source / drain contact area.

[0015] The present invention relates in general to semiconductor structures, and more particularly to fork-seat device structures having dual back-facing silicides and dense N2P spacing. More specifically, the fork-seat device structures and related methods disclosed herein enable a novel solution for providing dual back-facing silicides with very dense N2P spacing without patterning problems or short circuits between contacts. Exemplary embodiments of the fork-seat device structures having dual back-facing silicides and dense N2P spacing are described in detail below with reference to the accompanying drawings Figures 1 to 60. Those skilled in the art will readily understand that the detailed description given herein with respect to these figures is for illustrative purposes only, for the present invention extends beyond these limiting embodiments.

[0016] Referring here to Figures 1, 2, and 3, a structure 100 in an intermediate step of a method for manufacturing a fork seat device structure according to one embodiment of the present invention is shown. Figure 1 shows a cross-sectional view of the structure 100 shown in Figures 2 and 3, cut along line XX; Figure 2 shows a cross-sectional view of the structure 100 shown in Figure 1, cut along line Y1-Y1; and Figure 3 shows a cross-sectional view of the structure 100 shown in Figure 1, cut along line Y2-Y2.

[0017] The structure 100 shown in Figures 1 to 3 includes a nanosheet layer 102 formed on a substrate 104. The nanosheet layer 102 includes, as shown, a series of alternating silicon germanium (SiGe) sacrificial nanosheets 106 (hereinafter "sacrificial nanosheet 106") and silicon (Si) channel nanosheets 108 (hereinafter "channel nanosheet 108"). Although only a limited number of nanosheet layers (102) are shown, one or more additional nanosheet layers and / or nanosheets can be optionally grown alternately epitaxially, and the properties of any additional nanosheets are the same as those of the corresponding nanosheets described herein.

[0018] In one or more embodiments, the nanosheet layers 102 are formed by epitaxially growing one layer and then the next until a desired number and thickness of each layer is achieved. The epitaxial material can be grown from a gaseous or liquid precursor. The epitaxial material can be grown using vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), or other suitable processes. Epitaxial silicon, silicon germanium, and / or carbon-doped silicon (Si:C) may be undoped or, depending on the type of transistor, may be doped during deposition (in situ-doped) by adding a dopant, an n-type dopant (e.g., phosphorus or arsenic), or a p-type dopant (e.g., boron or gallium). For example, the channel nanosheets 108 of the nanosheet layer 102 may be doped, undoped, or some combination thereof.

[0019] The terms "epitaxial growth and / or deposition" and "epitaxial formation and / or growth" mean that one semiconductor material (crystalline material) grows on the deposition surface of another semiconductor material (crystalline material), where the growing semiconductor material (crystalline overlayer) has substantially the same crystalline properties as the semiconductor material on the deposition surface (seed material). In the epitaxial deposition process, the chemical reactants provided by the source gas are controlled and system parameters are set so that the atoms to be deposited move around on the surface, thereby reaching the deposition surface with enough energy to orient themselves to the crystalline arrangement of the atoms on the deposition surface. Thus, the epitaxially grown semiconductor material has substantially the same crystalline properties as the deposition surface on which the epitaxially grown material is formed. For example, an epitaxially grown semiconductor material deposited on a crystalline surface with a {100} orientation will inherit the {100} orientation. In some embodiments, the epitaxial growth and / or deposition process is selective for formation on semiconductor surfaces and generally does not deposit material on exposed surfaces such as silicon dioxide or silicon nitride surfaces.

[0020] In some embodiments, the gas source for depositing epitaxial semiconductor materials includes silicon-containing gas sources, germanium-containing gas sources, or combinations thereof. For example, an epitaxial silicon layer can be deposited from a silicon gas source selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source selected from the group consisting of german, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. On the other hand, an epitaxial silicon-germanium alloy layer can be formed using a combination of such gas sources. Carrier gases such as hydrogen, nitrogen, helium, and argon may be used.

[0021] The substrate 104 may be a layered semiconductor such as a silicon-on-insulator or a SiGe-on-insulator, where the etching stop layer 110 isolates the base substrate 112 from the upper semiconductor layer 114. Unlike conventional layered semiconductor substrates, the etching stop layer 110 of the substrate 104 may contain any material that affects the desired etching selectivity during subsequent processing. For example, the etching stop layer 110 may be a conventional embedded oxide layer, or it may be a silicon-germanium layer with a specific germanium concentration. In fact, the etching stop layer 110 can be composed of any material that functions as an etching stop layer and supports that function.

[0022] In this embodiment, both the base substrate 112 and the upper semiconductor layer 114 may be any bulk substrate made from any of several known semiconductor materials, such as silicon, germanium, silicon-germanium alloys, and composite (e.g., III-V and II-VI) semiconductor materials. For example, both the base substrate 112 and the upper semiconductor layer 114 may be made from silicon. Additionally, both the etching stop layer 110 and the base substrate 112 are sacrificed and do not remain in the final structure.

[0023] Referring now to Figures 4, 5, and 6, a structure 100 after the formation of the first hard mask 116 according to one embodiment of the present invention is shown. Figure 4 shows a cross-sectional view of the structure 100 shown in Figures 5 and 6, cut along line XX; Figure 5 shows a cross-sectional view of the structure 100 shown in Figure 4, cut along line Y1-Y1; and Figure 6 shows a cross-sectional view of the structure 100 shown in Figure 4, cut along line Y2-Y2.

[0024] The first hard mask 116 is formed by known techniques. Specifically, for example, the first hard mask 116 can be formed by first depositing a hard mask material (e.g., silicon nitride) on the top layer of the nanosheet layer 102 using any technique suitable for dielectric deposition that does not induce physical or chemical changes on the top layer of the nanosheet layer 102, such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or any technique suitable for dielectric deposition that does not induce physical or chemical changes on the top layer of the nanosheet layer 102. The hard mask material is then patterned into multiple hard masks 116 or, alternatively, into individual masks. The patterning of the hard mask material is suitable for the desired footprint and location of the forksheet device structure.

[0025] Referring now to Figures 7, 8, and 9, a structure 100 is shown according to one embodiment of the present invention, after forming a side wall spacer 118 and patterning the nanosheet layer 102 and substrate 104. Figure 7 shows a cross-sectional view of the structure 100 shown in Figures 8 and 9, cut along line XX; Figure 8 shows a cross-sectional view of the structure 100 shown in Figure 7, cut along line Y1-Y1; and Figure 9 shows a cross-sectional view of the structure 100 shown in Figure 7, cut along line Y2-Y2.

[0026] First, a layer of dielectric material may be conformally deposited on the structure 100. Specifically, the layer of dielectric material may be deposited directly on the exposed surfaces of the hard mask 116 and the nanosheet layer 102. In one embodiment, the layer of dielectric material may include, for example, silicon nitride, or silicon oxide, or SiOCN, SiC, TiOx, AlOx, etc. In some cases, it may be preferable to fabricate the sidewall spacer 118 from a material having a substantially different etching rate from the surrounding material to provide good etching selectivity. In one embodiment, the layer of dielectric material may preferably include an oxide, such as silicon oxide. The layer of dielectric material can be deposited by conformal deposition techniques using any known atomic layer deposition technique, molecular layer deposition technique, or other known conformal deposition technique. In one embodiment, the layer of dielectric material may have a substantially conformal and uniform thickness in the range of about 5 nm to about 20 nm, and in the range between therein.

[0027] Next, a directional anisotropic etching technique may be used to remove a portion of the dielectric material layer from the horizontal plane of structure 100, while leaving it on the sidewalls of the first hard mask 116. For example, a reactive ion etching technique may be used to remove a portion of the dielectric material layer from directly above the nanosheet layer 102 and from the upper surface of the first hard mask 116. The portion of the dielectric material layer remaining along the opposing sidewalls of the first hard mask 116 forms a sidewall spacer 118. Furthermore, the first hard mask 116 and the sidewall spacer 118 should each contain material that allows the first hard mask 116 to be selectively removed relative to the sidewall spacer 118. It should be noted that the sidewall spacer 118 shown in the figure is for illustrative purposes only and may have a shape that differs slightly from that generally shown. For example, the sidewall spacer 118 may have rounded corners that can be naturally formed during a directional etching process, as is known in the art.

[0028] The sidewall spacer 118 may have a width in a range substantially equal to the conformal thickness of the layer of dielectric material above. In one embodiment, the width of the sidewall spacer 118 may preferably be smaller than the sublithographic or lithographic minimum dimension. The term “sublithographic” may refer to a dimension or size smaller than the current dimension achievable by the photolithography process, while the terms “lithographic” or “lithographic minimum dimension” may refer to a dimension or size equal to or greater than the current dimension achievable by the photolithography process. Sublithographic and lithographic dimensions may be determined by a person skilled in the art at the time this application is filed. “Lithographic minimum dimension” and “sublithographic dimension” are defined only in relation to lithography tools and typically change with each generation of semiconductor technology, but it is understood that lithographic minimum dimensions and sublithographic dimensions are defined in relation to the best performance of the lithography tools available at the time of semiconductor manufacturing. As of 2015, the lithographic minimum dimension is approximately 20 nm and is expected to shrink in the future. In one embodiment, for example, the sidewall spacer 118 may have a width in the range of about 5 nm to about 15 nm, and in between. The width of the spacer can be adjusted to meet the final technical target dimensions based on etching bias or material loss during the process. The sidewall spacer 118 defines a “fin pattern” or active region that can be subsequently transferred to the underlying layer, which includes the nanosheet layer 102 and the substrate 104. The first hard mask 116 and the sidewall spacer 118, and the associated process, enable the formation of two nanosheet stacks 120 having an N2P spacing 122 smaller than that otherwise possible with typical lithography techniques. According to embodiments of the present invention, the N2P spacing 122 is less than about 10 nm.

[0029] Referring here to Figures 10, 11, and 12, a structure 100 after the dielectric bar 124 has been formed according to one embodiment of the present invention is shown. Figure 10 shows a cross-sectional view of the structure 100 shown in Figures 11 and 12, cut along line XX; Figure 11 shows a cross-sectional view of the structure 100 shown in Figure 10, cut along line Y1-Y1; and Figure 12 shows a cross-sectional view of the structure 100 shown in Figure 10, cut along line Y2-Y2.

[0030] The dielectric bar 124 is formed by known techniques as shown in the illustration. The dielectric bar 124 is formed within the N2P gap 122 between adjacent nanosheet stacks 120. Specifically, the dielectric material is first deposited to substantially fill the N2P gap 122. The dielectric material is then selectively etched using isotropic etch-back so that the dielectric material is recessed below the upper surfaces of the hard mask 116 and sidewall spacers 118, as shown in the illustration.

[0031] Referring now to Figures 13, 14, and 15, a structure 100 after forming a shallow trench isolation region 126 according to one embodiment of the present invention is shown. Figure 13 shows a cross-sectional view of the structure 100 shown in Figures 14 and 15, cut along line XX; Figure 14 shows a cross-sectional view of the structure 100 shown in Figure 13, cut along line Y1-Y1; and Figure 15 shows a cross-sectional view of the structure 100 shown in Figure 13, cut along line Y2-Y2.

[0032] The shallow trench isolation region 126 (hereinafter referred to as "STI region 126") is formed by known techniques. The STI region 126 is formed below the trenches in the substrate 104 formed during the patterning of the nanosheet layer 102. Specifically, by known techniques, dielectric material is deposited below the trenches in the substrate 104 to isolate adjacent devices from each other. The STI region 126 is made of, for example, silicon oxide (SiO₂). x ), or silicon nitride (Si x N y It may be formed from any suitable dielectric material including ).

[0033] Referring here to Figures 16, 17, and 18, a structure 100 is shown according to one embodiment of the present invention, after the sacrificial gate dielectric (not shown) and sacrificial gate 128 have been formed and patterned. Figure 16 shows a cross-sectional view of the structure 100 shown in Figures 16 and 18, cut along line XX; Figure 17 shows a cross-sectional view of the structure 100 shown in Figure 16, cut along line Y1-Y1; and Figure 18 shows a cross-sectional view of the structure 100 shown in Figure 16, cut along line Y2-Y2.

[0034] The sacrificial gate dielectric is deposited directly onto the exposed surface of structure 100 using known techniques. Specifically, as shown in the figure, a relatively thin layer of silicon oxide (SiO2), for example, is first conformally deposited on and around the nanosheet stack 120.

[0035] The sacrificial gate 128 is blanket-deposited on and around the nanosheet stack 120 by known techniques. Specifically, as shown in the figure, a relatively thick layer of amorphous silicon, for example, is blanket-deposited directly onto the sacrificial gate dielectric. In this way, both the sacrificial gate dielectric and the sacrificial gate 128 completely cover the nanosheet stack 120, as shown in the figure.

[0036] As used herein, “conformal” means that a material layer has a continuous or substantially continuous thickness. For example, continuous thickness generally means that a first thickness measured from the bottom surface to the top surface is the same as a second thickness measured from the inner sidewall surface to the outer sidewall surface.

[0037] Next, a gate hard mask 130 (gate mask 130) is formed on the structure 100. The gate mask 130 defines the gate region of the individual device. According to an exemplary embodiment, a selected mask material is deposited on the sacrificial gate 128 and then patterned into a plurality of individual gate masks 130. Next, the patterns created by the individual gate masks 130 are transferred to the sacrificial gate dielectric and the sacrificial gate 128. Specifically, a portion of the sacrificial gate dielectric and the sacrificial gate 128 is selectively etched or removed from the gate mask 130, as shown in the figure. The portion of the sacrificial gate dielectric and the sacrificial gate 128 can be removed using a silicon RIE process.

[0038] Referring further to Figures 16, 17, and 18, a structure 100 after the formation of a gate spacer 132 according to one embodiment of the present invention is shown. Next, the spacer material is conformally deposited directly onto the exposed surface of the structure 100 by known techniques. Specifically, by known techniques, a relatively thin layer of silicon nitride, for example, is conformally deposited, and then a portion of the spacer material is selectively removed or etched from the horizontal plane. In this way, a portion of the nanosheet stack 120, the substrate 104, and the STI region 126 are exposed as shown. The remaining portion of the spacer material forms the gate spacer shown in the figure. In some embodiments, the gate spacer 132, for example, may consist of SiN, SiBCN, SiOCN, SiOC, or any other combination of low-k materials. The term "low-k" as used throughout this application refers to dielectric materials having a dielectric constant of less than 4.0.

[0039] Referring further to Figures 16, 17, and 18, a structure 100 is shown according to one embodiment of the present invention, after a portion of the nanosheet stack 120 has been removed. A portion of the nanosheet stack 120 is etched and removed from between the sacrificial gates 128 by known techniques. Specifically, the pattern created by the gate mask 130 and gate spacers 132 is transferred to the nanosheet stack 120. In this process, as shown, a portion of the sacrificial nanosheets 106 and channel nanosheets 108 is selectively removed relative to the gate mask 130 and gate spacers 132.

[0040] In one embodiment, a portion of the nanosheet stack 120 is removed using anisotropic etching, such as reactive ion etching. This may require a series of etching steps using different etching chemistry, as is well known in the art. The etching is designed to define the source-drain region and expose the edges of individual nanosheet layers. In all cases, as illustrated, the etching continues until the substrate 104 is exposed.

[0041] Referring further to Figures 16, 17, and 18, a structure 100 after the formation of the inner spacer 134 according to one embodiment of the present invention is shown. First, the sacrificial nanosheet 106 is laterally recessed to create space for the inner spacer 134. In one or more embodiments, the sacrificial nanosheet 106 is laterally recessed using an isotropic etching process with hydrogen chloride (HCl) gas that etches silicon germanium without eroding silicon. In other embodiments, the sacrificial nanosheet 106 is laterally recessed using a ClF3 etching process. The space occupied by the removed portion of the sacrificial nanosheet 106 forms a cavity (not shown).

[0042] The inner spacer 134 is formed by first conformally depositing spacer material onto the structure 100 to fill a cavity created by laterally recessing the sacrificial nanosheet 106. The conformal spacer material is then isotropically etched to remove all portions except those remaining in the cavity and forming the inner spacer 134. In one or more embodiments, the inner spacer 134 is made from a nitride-containing material, such as silicon nitride (SiN). The inner spacer 134 shown in Figure 16 is formed from a nitride-containing material, but they can be formed from any material for which subsequent device fabrication operations are not particularly selective. As used in this description, selectivity refers to the tendency of process operations to impact a particular material. One example of low selectivity is a relatively slow etching rate. One example of higher or greater selectivity is a relatively fast etching rate. For the embodiments described, the material for the inner spacer 134 can be selected based on the selectivity of subsequent device fabrication operations for the selected material being below a predetermined threshold.

[0043] The inner spacer 134 is positioned so that subsequent etching processes used to remove the sacrificial nanosheet 106 during device fabrication do not erode the subsequently formed source-drain region.

[0044] Referring here to Figures 19, 20, and 21, a structure 100 according to one embodiment of the present invention is shown after a sacrificial liner 135 has been formed, a patterning mask 136 has been formed, and a portion of the sacrificial liner 135 has been selectively removed from the patterning mask 136. Figure 19 shows a cross-sectional view of the structure 100 shown in Figures 20 and 21, cut along line XX, Figure 20 shows a cross-sectional view of the structure 100 shown in Figure 19, cut along line Y1-Y1, and Figure 21 shows a cross-sectional view of the structure 100 shown in Figure 19, cut along line Y2-Y2.

[0045] First, a sacrificial liner 135 is conformally deposited directly onto the exposed surface of structure 100 using known techniques. Specifically, as shown in the figure, a relatively thin layer of silicon nitride (SiN), for example, is conformally deposited on and around the nanosheet stack 120, sacrificial gate 128, and gate spacer 132.

[0046] Next, a patterning mask 136 is deposited using known techniques and then patterned to expose specific portions of the structure 100. Specifically, as shown in Figures 19 and 21, a portion of the sacrificial liner 135 in the region designated for the back surface source-drain contact is exposed.

[0047] The patterning mask 136 may be an organic planarization layer (OPL) or a layer of material that can be planarized or etched by known techniques. In one embodiment, for example, the patterning mask 136 may be an amorphous carbon layer that can withstand the subsequent processing temperature. Preferably, the patterning mask 136 can have a thickness sufficient to cover the existing structure. After the deposition of the patterning mask 136, a dry etching technique is applied to pattern the patterning mask 136 by known techniques.

[0048] Next, a portion of the sacrificial liner 135 in the region designated for the back-side source-drain contacts is removed using known techniques. Specifically, the exposed portion of the sacrificial liner 135 is removed using known etching techniques suitable for selectively removing silicon nitride from the surrounding material. In one embodiment, a portion of the sacrificial liner 135 is removed using anisotropic etching, such as reactive ion etching. In this process, the exposed portion of the dielectric bar 124 may be etched, as shown in Figure 21, and ultimately recessed or lowered during the etching of the sacrificial liner 135.

[0049] Finally, etching is continued into the substrate 104. Specifically, the exposed portion of the upper semiconductor layer 114 is removed by known techniques and as shown in the illustration. This forms the back surface contact trench 138.

[0050] Referring now to Figures 22, 23, and 24, a structure 100 after the sacrificial placeholder 140 has been formed according to one embodiment of the present invention is shown. Figure 22 shows a cross-sectional view of the structure 100 shown in Figures 23 and 24, cut along line XX; Figure 23 shows a cross-sectional view of the structure 100 shown in Figure 22, cut along line Y1-Y1; and Figure 24 shows a cross-sectional view of the structure 100 shown in Figure 22, cut along line Y2-Y2.

[0051] The back surface contact trench 138 is filled with sacrificial placeholder material by known techniques. Subsequently, the sacrificial placeholder material is recessed by known techniques to create a sacrificial placeholder 140. In one embodiment, the sacrificial placeholder material is SiC, SiOC deposited using, for example, chemical vapor deposition (CVD) or plasma-enhanced CVD (PECVD), and then recessed using, for example, reactive ion etching (RIE). Other suitable deposition and recessing techniques may be used, provided that they do not induce physical or chemical changes in the channel nanosheet 108. Finally, the sacrificial placeholder 140 may also be called a dielectric sacrificial placeholder 140 or dielectric placeholder 140. Finally, the remainder of the patterning mask 136 is removed by known techniques, such as ashing.

[0052] Referring now to Figures 25, 26, and 27, a structure 100 according to one embodiment of the present invention is shown after the sacrificial liner 135 has been removed. Figure 25 shows a cross-sectional view of the structure 100 shown in Figures 26 and 27, cut along line XX; Figure 26 shows a cross-sectional view of the structure 100 shown in Figure 25, cut along line Y1-Y1; and Figure 27 shows a cross-sectional view of the structure 100 shown in Figure 251, cut along line Y2-Y2.

[0053] First, the remaining portion of the sacrificial liner 135 is removed by known techniques. Specifically, the remaining portion of the second sacrificial liner 135 is removed using known etching techniques suitable for selectively removing silicon nitride from the surrounding material. In one embodiment, the remaining portion of the sacrificial liner 135 is removed using anisotropic etching, such as reactive ion etching.

[0054] Referring further to Figures 25, 26, and 27, the structure 100 after the formation of the first source-drain region 142a and the second source-drain region 142b according to one embodiment of the present invention is shown.

[0055] The source-drain regions 142a and 142b are formed by known techniques using an epitaxial layer growth process on the exposed edges of the channel nanosheet 106. Typically, in situ doping is used to dope the source-drain regions 142a and 142b, thereby creating the necessary junctions for the semiconductor device. Virtually all semiconductor transistors are based on the formation of junctions. Junctions allow both blocking and allowing current to flow depending on the applied bias. Junctions are typically formed by bringing two semiconductor regions with opposite polarities into contact with each other. The most common junction is the pn junction, which consists of contact between a hole-rich P-type silicon piece and an electron-rich N-type silicon piece. N-type and P-type devices are formed by using different types of dopants to select regions of the device and form the necessary junctions. For example, N-type devices can be formed by doping with arsenic (As) or phosphorus (P), and P-type devices can be formed by doping with implanted boron (B).

[0056] According to an embodiment of the present invention, as shown in Figure 27, the first source-drain region 142a (on one side of the dielectric bar 124) is of a first type, for example, type P, and the second source-drain region 142b (on the opposite side of the dielectric bar 124) is of a second type, for example, type N.

[0057] Referring further to Figures 25, 26, and 27, a structure 100 after the formation of a dielectric layer 144 according to one embodiment of the present invention is shown. The dielectric layer 144 is formed by blanket deposition of interlayer dielectric material on the structure 100 using known techniques. Specifically, the dielectric layer 144 is formed on source-drain regions 142a and 142b, as shown in the figures, and substantially fills the remaining space between adjacent nanosheet stacks 120.

[0058] The dielectric layer 144 may consist of silicon dioxide, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), spin-on low-k dielectric layer, chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. In another embodiment, a self-planarizing material such as spin-on glass (SOG) or a spin-on low-k dielectric material such as SiLK® may be used as the dielectric layer 144. By using a self-planarizing dielectric material as the dielectric layer 144, the need to perform a subsequent planarization step can be avoided.

[0059] After the dielectric layer 144 is formed, the structure is polished using known techniques, such as chemical mechanical polishing. Specifically, the dielectric layer 144, gate spacer 132, and gate mask 130 are polished until the uppermost surface of the dielectric layer 144 is coplanar or substantially coplanar with the uppermost surfaces of the gate spacer 132 and sacrificial gate 128.

[0060] Referring now to Figures 28, 29, and 30, a structure 100 after the gate structure 146 has been formed according to one embodiment of the present invention is shown. Figure 28 shows a cross-sectional view of the structure 100 shown in Figures 29 and 30, cut along line XX; Figure 29 shows a cross-sectional view of the structure 100 shown in Figure 28, cut along line Y1-Y1; and Figure 30 shows a cross-sectional view of the structure 100 shown in Figure 28, cut along line Y2-Y2.

[0061] The sacrificial gate 128 and sacrificial nanosheet 106 are selectively removed by known techniques.

[0062] First, the sacrificial gate 128 is selectively etched and removed from the gate spacer 132 and the nanosheet stack 120 using known techniques. Next, the sacrificial nanosheet 106 is selectively etched and removed from the channel nanosheet 108 and the inner spacer 134 using known techniques. This is made possible by varying the concentrations of germanium. In this case, the layer containing germanium is selectively removed from the layer without germanium.

[0063] Next, the gate structure 146 is formed by known techniques. First, a gate dielectric (not shown) is directly and conformally deposited on the exposed surface of structure 100 within the gate cavity or opening and in the space remaining after removing the sacrificial gate 128 and sacrificial nanosheet 106, by known techniques. For example, the gate dielectric is conformally deposited on the exposed surfaces of channel nanosheet 108 and inner spacer 134.

[0064] The gate dielectric is composed of any known gate dielectric material, such as oxides, nitrides, and / or oxynitrides. In the example, the gate dielectric may be a high-k material having a dielectric constant greater than silicon dioxide. Exemplary high-k dielectrics include HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, Y2O3, and HfO2. x N y , ZrO x N y, La2O x N y , Al2O x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y2O x N y , SiON, SiN x , including, but not limited to, their silicides and their alloys. Each value of x is independently from 0.5 to 3, and each value of y is independently from 0 to 2. In some embodiments, a multilayer gate dielectric structure including different gate dielectric materials. For example, a silicon dioxide layer and a high-k gate dielectric layer can be formed and used together as the gate dielectric. In at least one embodiment, the gate dielectric is composed of hafnium oxide.

[0065] Next, by known techniques, a work function metal (not shown) is conformally deposited on the first gate dielectric formed in the gate cavity. In at least one embodiment, the work function metal is made of the same conductive material throughout the structure. In at least another embodiment, the first function metal is made of different conductive materials in each of the devices shown in the figure. At that time, different conductive materials are successively deposited according to the design parameters and the desired operating characteristics.

[0066] The work function metal can include any known conductive gate material, such as doped polysilicon, elemental metals (e.g., tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium, and platinum), alloys of at least two elemental metals, elemental metal nitrides (e.g., tungsten nitride, aluminum nitride, and titanium nitride), elemental metal silicides (e.g., tungsten silicide, nickel silicide, and titanium silicide), or titanium carbon (TiC), titanium aluminum (TiAl), titanium aluminum carbon (TiAlC), or multilayer combinations thereof. In some embodiments, the work function metal can include the gate metal of an nFET. In other embodiments, the work function metal can include the gate metal of a pFET. When multiple gate cavities are formed as illustrated herein, embodiments of the present invention explicitly intend to form an nFET in at least one of the gate cavities and a pFET in at least one of the gate cavities.

[0067] In some embodiments, the gate metal or contact metal is deposited directly onto a work function metal to fill the gate cavity. The first gate metal may include any suitable conductive material, such as copper, ruthenium, aluminum, tungsten, cobalt, or alloys thereof. The excess conductive material may then be polished using known techniques.

[0068] Finally, additional interlayer dielectric material is deposited using known techniques. Dielectric layer 144, shown in the figure, contains the additional interlayer dielectric material.

[0069] Referring further to Figures 28, 29, and 30, a structure 100 according to one embodiment of the present invention is shown after the source-drain contact 148 has been formed, the middle-of-line and back-end 150 have been formed, and the carrier wafer 152 has been attached.

[0070] Next, a portion of the dielectric layer 44 is removed, exposing the source-drain regions 142a and 142b. Then, by known techniques, the openings are filled with a conductive material to form the source-drain contacts 148. The source-drain contacts 148 may include any suitable conductive material, such as copper, ruthenium, aluminum, tungsten, cobalt, or alloys thereof. In some embodiments, a metal silicide is formed beneath the contact trenches before they are filled with the conductive material. In some embodiments, the source-drain contacts 148 do not contact the gate spacer 132. In other embodiments, the source-drain contacts 148 self-align with the gate spacer 132 and may therefore be called a self-aligned contact structure.

[0071] Finally, the middle-of-line and back-end layers 150 (hereinafter referred to as MOL / BEOL150) are formed, and the carrier wafer 152 is fixed to the top of the structure 100 according to one embodiment of the present invention. After the source-drain contacts 148 are formed, the MOL / BEOL150 is then formed by known techniques. Next, the carrier wafer 150 is attached to the MOL / BEOL150 or fixed in a removable manner. Generally, although not shown, the carrier wafer 152 may be thicker than the other layers. Temporarily bonding the structure 100 to a thicker carrier provides improved handling and additional support for back-side processing of the thin wafer. After the back-side processing described below, the structure 100 may be peeled off or removed from the carrier wafer 152 by known techniques.

[0072] Referring now to Figures 31, 32, and 33, a structure 100 is shown according to one embodiment of the present invention, after the assembly has been inverted and the substrate 104 has been recessed. Figure 31 shows a cross-sectional view of the structure 100 shown in Figures 32 and 33, cut along line XX; Figure 32 shows a cross-sectional view of the structure 100 shown in Figure 31, cut along line Y1-Y1; and Figure 33 shows a cross-sectional view of the structure 100 shown in Figure 31, cut along line Y2-Y2.

[0073] First, structure 100 is inverted 180 degrees in preparation for back-side processing. Generally, back-side processing involves fabricating or processing the structure 100 on the side opposite to the active device and wiring layers. Next, substrate 104 is recessed by known techniques. Specifically, as shown, the base substrate 112 is recessed or completely removed to expose the etching stop layer 110.

[0074] Referring now to Figures 34, 35, and 36, the structure 100 according to one embodiment of the present invention is shown after the remaining portion of the substrate 104 has been removed. Figure 34 shows a cross-sectional view of the structure 100 shown in Figures 37 and 38, cut along line XX; Figure 35 shows a cross-sectional view of the structure 100 shown in Figure 34, cut along line Y1-Y1; and Figure 36 shows a cross-sectional view of the structure 100 shown in Figure 34, cut along line Y2-Y2.

[0075] First, the etching stop layer 110 and the upper semiconductor layer 114 are selectively removed using known techniques. Specifically, the etching stop layer 110 is selectively removed from the upper semiconductor layer 114, and then the upper semiconductor layer 114 is selectively removed from the STI region 126, the sacrificial placeholder 140, the source-drain regions 142a and 142b, the dielectric bar 124, and the gate structure 146.

[0076] Referring now to Figures 37, 38, and 39, a structure 100 after the formation of the back surface dielectric layer 154 according to one embodiment of the present invention is shown. Figure 37 shows a cross-sectional view of the structure 100 shown in Figures 38 and 39, cut along line XX; Figure 38 shows a cross-sectional view of the structure 100 shown in Figure 37, cut along line Y1-Y1; and Figure 39 shows a cross-sectional view of the structure 100 shown in Figure 37, cut along line Y2-Y2.

[0077] The back surface dielectric layer 154 is formed by blanket deposition of interlayer dielectric material on the structure 100 using known techniques. Specifically, as shown in the figure, the back surface dielectric layer 154 is formed on the source drain regions 142a and 142b, between the STI region 126 and the dielectric bar 124.

[0078] The back dielectric layer 154 may consist of silicon dioxide, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), spin-on low-k dielectric layer, chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. In another embodiment, a self-planarizing material such as spin-on glass (SOG) or a spin-on low-k dielectric material such as SiLK® may be used as the back dielectric layer 154. By using a self-planarizing dielectric material as the back dielectric layer 154, the need to perform a subsequent planarization step can be avoided.

[0079] Referring here to Figures 40, 41, and 42, a structure 100 after the formation of the first back surface mask 156 according to one embodiment of the present invention is shown. Figure 40 shows a cross-sectional view of the structure 100 shown in Figures 41 and 42, cut along line XX; Figure 41 shows a cross-sectional view of the structure 100 shown in Figure 41, cut along line Y1-Y1; and Figure 42 shows a cross-sectional view of the structure 100 shown in Figure 41, cut along line Y2-Y2.

[0080] A first back mask 156 is deposited using known techniques and then patterned to expose a specific portion of the structure 100. The first back mask 156 may be an organic planarization layer (OPL) or a layer of material that can be planarized or etched using known techniques. In one embodiment, for example, the first back mask 156 may be an amorphous carbon layer that can withstand the subsequent processing temperature. The first back mask 156 may preferably have a thickness sufficient to cover the existing structure. After the deposition of the first back mask 156, a dry etching technique is applied to pattern the first back mask 156 using known techniques. Specifically, the first back mask 156 is patterned to expose a portion of the structure 100 that is generally aligned with the first source-drain region 142a on one side of the dielectric bar 124. Some patterning overlays or misalignments are acceptable as long as a portion of the structure 100 that is generally aligned with the second source-drain region 142b on the other side of the dielectric bar 124 remains covered by the first back surface mask 156, as shown in the figure.

[0081] Referring here to Figures 43, 44, and 45, the structure 100 is shown according to one embodiment of the present invention after the first portion of the sacrificial placeholder 140 has been removed to create the first back trench 158. Figure 43 shows a cross-sectional view of the structure 100 shown in Figures 44 and 45, cut along line XX; Figure 44 shows a cross-sectional view of the structure 100 shown in Figure 43, cut along line Y1-Y1; and Figure 45 shows a cross-sectional view of the structure 100 shown in Figure 43, cut along line Y2-Y2.

[0082] A first portion of the sacrificial placeholder 140 is selectively removed by known techniques. Specifically, the first portion of the sacrificial placeholder 140 is selectively etched or removed with respect to the STI region 126, the dielectric bar 124, and the first source-drain region 142a. For example, an anisotropic etching technique, such as reactive ion etching, may be used to remove the first portion of the sacrificial placeholder 140. By removing the first portion of the sacrificial placeholder 140, a first back surface trench 158 is created. Importantly, a portion of the first source-drain region 142a is exposed by the first back surface trench 158, as shown in the figure.

[0083] Referring now to Figures 46, 47, and 48, the structure 100 according to one embodiment of the present invention is shown after the first back-surface mask 156 has been removed and shallow ion implantation has been performed. Figure 46 shows a cross-sectional view of the structure 100 shown in Figures 47 and 48, cut along line XX; Figure 47 shows a cross-sectional view of the structure 100 shown in Figure 46, cut along line Y1-Y1; and Figure 48 shows a cross-sectional view of the structure 100 shown in Figure 46, cut along line Y2-Y2.

[0084] First, the remaining portion of the first back surface mask 156 is removed by a known technique, such as ashing. Next, shallow ion implantation is used to treat the exposed surface of the first source drain region 142a and improve contact resistance.

[0085] Referring here to Figures 49, 50, and 51, a structure 100 is shown according to one embodiment of the present invention, after the formation of the first silicide liner 160, the first adhesive liner 162, and the first sacrificial filler 164. Figure 49 shows a cross-sectional view of the structure 100 shown in Figures 50 and 51, cut along line XX; Figure 50 shows a cross-sectional view of the structure 100 shown in Figure 49, cut along line Y1-Y1; and Figure 51 shows a cross-sectional view of the structure 100 shown in Figure 49, cut along line Y2-Y2.

[0086] First, the first silicide liner 160 is deposited in the first back trench 158 by known techniques. Directional deposition techniques, such as physical vapor deposition, may be preferred to limit the deposition of the first silicide liner 160 to vertical or substantially vertical sidewalls, for example. While tolerances for the deposition thickness of the first silicide liner 160 are not critical, it is necessary that the first silicide liner 160 has sufficient thickness in the z direction to allow for sufficient silicide formation during subsequent processing. The first silicide liner 160 may include any metal or combination of metals suitable for silicide formation on the underside of the first source drain region 142a, as shown in the figure. In one embodiment, the first silicide liner 160 is made from titanium, nickel, cobalt, and nickel platinum. Additional processing may be used to remove excess material of the first silicide liner 160 by known techniques.

[0087] Next, the first adhesive liner 162 is deposited in the first back trench 158 by known techniques. Specifically, a relatively thin layer of titanium nitride or other suitable material is conformally deposited to improve the adhesion of the subsequent deposited material.

[0088] Next, the first sacrificial filler 164 is deposited in the first back trench 158 by known techniques. Specifically, as shown in the figure, the sacrificial material is deposited directly on the first adhesive liner 162 to fill the first back trench 158. According to embodiments of the present invention, the first sacrificial filler 164 may be amorphous silicon or other suitable material that can be selectively removed thereafter.

[0089] Finally, excess material from the first adhesive liner 162 and the first sacrificial filler 164 is removed by known techniques, such as chemical mechanical polishing. Specifically, as shown in the figure, the first adhesive liner 162 and the first sacrificial filler 164 are polished until they are coplanar or substantially coplanar with the STI region 126 and the dielectric bar 124.

[0090] Referring here to Figures 52, 53, and 54, the structure 100 is shown according to one embodiment of the present invention, after removing the second portion of the sacrificial placeholder 140 to create a second back trench 166 and performing another shallow ion implantation. Figure 52 shows a cross-sectional view of the structure 100 shown in Figures 53 and 54, cut along line XX; Figure 53 shows a cross-sectional view of the structure 100 shown in Figure 52, cut along line Y1-Y1; and Figure 54 shows a cross-sectional view of the structure 100 shown in Figure 52, cut along line Y2-Y2.

[0091] The second portion of the sacrificial placeholder 140 is selectively removed by known techniques. Specifically, the second portion of the sacrificial placeholder 140 is selectively etched or removed with respect to the STI region 126, the dielectric bar 124, and the second source-drain region 142b. For example, an anisotropic etching technique, such as reactive ion etching, may be used to remove the second portion of the sacrificial placeholder 140. By removing the second portion of the sacrificial placeholder 140, a second back surface trench 166 is created. Importantly, a portion of the second source-drain region 142b is exposed by the second back surface trench 166, as shown in the figure.

[0092] Similarly to the above, another shallow ion implantation technique is used to treat the exposed surface of the second source-drain region 142b and improve contact resistance.

[0093] Referring here to Figures 55, 56, and 57, a structure 100 is shown according to one embodiment of the present invention, after the formation of the second silicide liner 168, the second adhesive liner 170, and the second sacrificial filler 172. Figure 55 shows a cross-sectional view of the structure 100 shown in Figures 56 and 57, cut along line XX; Figure 56 shows a cross-sectional view of the structure 100 shown in Figure 55, cut along line Y1-Y1; and Figure 57 shows a cross-sectional view of the structure 100 shown in Figure 55, cut along line Y2-Y2.

[0094] First, a second silicide liner 168 is deposited in the second back trench 166 by known techniques. Directional deposition techniques, such as physical vapor deposition, may be preferred to limit the deposition of the second silicide liner 168 to vertical or substantially vertical sidewalls, for example. While tolerances for the deposition thickness of the second silicide liner 168 are not critical, it is necessary that the second silicide liner 168 has sufficient thickness in the z direction to allow for sufficient silicide formation during subsequent processing. The second silicide liner 168 may include any metal or combination of metals suitable for silicide formation on the underside of the second source drain region 142b, as shown in the figure. In one embodiment, the second silicide liner 168 is made from titanium, nickel, cobalt, and nickel platinum. Additional processing may be used to remove excess material of the second silicide liner 168 by known techniques. In some embodiments, the first silicide liner 160 and the second silicide liner 168 are made from materials specifically tailored to fit the source-drain regions on which they are formed. For example, a titanium silicide liner is typically paired with an N-type source-drain region, and a nickel-platinum silicide liner is typically paired with a P-type source-drain region.

[0095] Next, a second adhesive liner 170 is deposited in the second back trench 166 by known techniques. Specifically, a relatively thin layer of titanium nitride or another suitable material is conformally deposited to improve the adhesion of the subsequent deposited material.

[0096] Next, a second sacrificial filler 172 is deposited in the second back trench 166 by known techniques. Specifically, as shown in the figure, the sacrificial material is deposited directly on the second adhesive liner 170 to fill the second back trench 166. According to embodiments of the present invention, the second sacrificial filler 172 may be amorphous silicon or other suitable material that can be selectively removed thereafter.

[0097] Next, excess material from the second adhesive liner 170 and the second sacrificial filler 172 is removed by known techniques, such as chemical mechanical polishing. Specifically, as shown in the figure, the second adhesive liner 170 and the second sacrificial filler 172 are polished until they are coplanar or substantially coplanar with the STI region 126 and the dielectric bar 124.

[0098] Finally, by known techniques, a thermal process, such as annealing, is used to form a first silicide region (not shown) at the interface between the first source-drain region 142a and the first silicide liner 160, and a second silicide region (not shown) at the interface between the second source-drain region 142b and the second silicide liner 168. Specifically, the first silicide region is composed of elements from both the first source-drain region 142a and the first silicide liner 160, and the second silicide region is composed of elements from both the second source-drain region 142b and the second silicide liner 168.

[0099] In one embodiment, for example, annealing may involve placing the structure 100 at a high temperature in the range of approximately 800°C to approximately 1250°C for approximately 1 ns to approximately 500 ms. In yet another embodiment, high-temperature rapid thermal annealing (RTA) techniques, such as high-temperature spike annealing or laser spike annealing, may be used. Typically, high temperatures cannot be used at this stage of fabrication due to the risk of damaging the gate metal or work function metal; however, in this example, the gate metal or work function metal has not yet been fabricated, and therefore high-temperature annealing can be used.

[0100] After annealing, and importantly for the embodiments disclosed herein, portions of the first silicide liner 160 and the second silicide liner 168 remain in the final structure. Furthermore, it should be noted that the specific annealing step described above is not always necessary. In such cases, the silicide is formed during subsequent heat treatment.

[0101] Referring here to Figures 58, 59, and 60, the structure 100 according to one embodiment of the present invention is shown after the first sacrificial filler 164 and the second sacrificial filler 172 have been removed, the back surface source-drain contact 174 has been formed, and the back surface wiring layer 176 has been formed. Figure 58 shows a cross-sectional view of the structure 100 shown in Figures 59 and 60, cut along line XX; Figure 59 shows a cross-sectional view of the structure 100 shown in Figure 58, cut along line Y1-Y1; and Figure 60 shows a cross-sectional view of the structure 100 shown in Figure 58, cut along line Y2-Y2.

[0102] First, both the first sacrificial filler 164 and the second sacrificial filler 172 are recessed and completely removed using known techniques. Specifically, the first sacrificial filler 164 and the second sacrificial filler 172 are selectively etched relative to the first adhesive liner 162 and the second adhesive liner 170.

[0103] Next, the openings created by removing the first sacrificial filling 164 and the second sacrificial filling 172 are then filled with a conductive material by known techniques to form the back-side source-drain contact 174. The back-side source-drain contact 174 may contain any suitable conductive material, such as copper, ruthenium, aluminum, tungsten, cobalt, or alloys thereof. In some embodiments, a metal silicide is formed beneath the back-side trenches 166 before they are filled with the conductive material. Thereafter, as shown in the figures, any excess conductive material can be polished using known techniques until the bottom surface of the back-side source-drain contact 174 is coplanar or substantially coplanar with the bottom surface of the STI region 126 and the back-side dielectric layer 154. After the back-side source-drain contact 174 is formed, the back-side wiring layer 176 is then formed by known techniques.

[0104] Referring again to Figures 58, 59, and 60 according to one embodiment, the structure 100 includes a dielectric bar 124 positioned between a first source-drain region 142a and a second source-drain region 142b, physically isolating them, a first silicide liner 160 directly beneath the first source-drain region 142a, and a second silicide liner 168 directly beneath the second source-drain region 142b, wherein the first silicide liner 160 is made of a different material from the second silicide liner 168.

[0105] Referring again to Figures 58, 59, and 60 according to one embodiment, the structure 100 includes a first nanosheet device including a first source-drain region 142a, a second nanosheet device including a second source-drain region 142b, dielectric bars 124 positioned between each of the first source-drain regions 142a and each of the second source-drain regions 142b to physically isolate them, a first silicide liner 160 directly beneath the first source-drain region 142a, and a second silicide liner 168 directly beneath the second source-drain region 142b, wherein the first silicide liner is made of a different material from the second silicide liner.

[0106] Referring again to Figures 58, 59, and 60 according to one embodiment, the structure 100 includes an n-type nanosheet device including an n-type source-drain region 142a, a p-type nanosheet device including a p-type source-drain region 142b, a dielectric bar 124 positioned between each of the n-type source-drain regions 142a and each of the p-type source-drain regions 142b to physically isolate them, a first silicide liner 160 directly beneath the n-type source-drain region 142a, and a second silicide liner directly beneath the p-type source-drain region 142b, where the first silicide liner 160 is made of a different material from the second silicide liner 168.

[0107] Referring again to Figures 58, 59, and 60, according to one embodiment, the structure 100 further includes a first silicide positioned between a first source-drain region and a first silicide liner and in direct contact with them, and a second silicide positioned between a second source-drain region and a second silicide liner and in direct contact with them.

[0108] Referring again to Figures 58, 59, and 60, according to one embodiment, the structure 100 further includes a first back-surface source-drain contact located directly below and communicating with a first source-drain region, and a second back-surface source-drain contact located directly below and communicating with a second source-drain region.

[0109] Referring again to Figures 58, 59, and 60, according to one embodiment, the structure 100 further includes a first back-surface source-drain contact located directly below and communicating with a first source-drain region, wherein the lowest surface of the first back-surface source-drain contact is substantially coplanar with the lowest surface of the dielectric bar, and a second back-surface source-drain contact located directly below and communicating with a second source-drain region, wherein the lowest surface of the second back-surface source-drain contact is substantially coplanar with the lowest surface of the dielectric bar.

[0110] Referring again to Figures 58, 59, and 60, according to one embodiment, the distance between the first source-drain region and the second source-drain region is less than 10 nm.

[0111] Referring again to Figures 58, 59, and 60, according to one embodiment, the width of the dielectric bar is less than 10 nm.

[0112] Referring again to Figures 58, 59, and 60, according to one embodiment, the sidewall of the first source-drain region and the first silicide liner is in direct contact with the first sidewall of the dielectric bar, and the sidewall of the second source-drain region and the second silicide liner is in direct contact with the second sidewall of the dielectric bar.

[0113] The descriptions of various embodiments of the present invention have been presented for illustrative purposes only and are not intended to be exhaustive or to limit the disclosed embodiments. Many modifications and variations that do not depart from the scope of the invention will be apparent to those skilled in the art. The terms used herein have been selected to best describe the principles of the embodiments, their practical applications, or the technical improvements to the technology available on the market, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

Claims

1. A dielectric bar positioned between the first source-drain region and the second source-drain region, physically separating them; A first silicide liner located directly below the first source drain region; and The second silicide liner is located directly below the second source-drain region. A semiconductor structure comprising the first silicide liner being made of a different material from the second silicide liner.

2. A first silicide positioned between the first source drain region and the first silicide liner and in direct contact with them; and A second silicide is positioned between the second source drain region and the second silicide liner, and is in direct contact with them. The semiconductor structure according to claim 1, further comprising:

3. A first back-surface source-drain contact located directly beneath the first source-drain region and communicating with it; and A second back-side source-drain contact is located directly beneath the second source-drain region and communicates with it. The semiconductor structure according to claim 1, further comprising:

4. A first back-surface source-drain contact located directly below the first source-drain region and communicating with it, wherein the lowest surface of the first back-surface source-drain contact is substantially coplanar with the lowest surface of the dielectric bar; and A second back-surface source-drain contact is located directly below the second source-drain region and communicates with it, wherein the lowest surface of the second back-surface source-drain contact is substantially coplanar with the lowest surface of the dielectric bar. The semiconductor structure according to claim 1, further comprising:

5. The semiconductor structure according to claim 1, wherein the distance between the first source-drain region and the second source-drain region is less than 10 nm.

6. The semiconductor structure according to claim 1, wherein the width of the dielectric bar is less than 10 nm.

7. The first source-drain region and the sidewall of the first silicide liner are in direct contact with the first sidewall of the dielectric bar. The semiconductor structure according to claim 1, wherein the second source-drain region and the sidewall of the second silicide liner are in direct contact with the second sidewall of the dielectric bar.

8. A first nanosheet device having a first source-drain region; A second nanosheet device having a second source-drain region; A dielectric bar positioned between each of the first source-drain regions and each of the second source-drain regions, physically separating them; A first silicide liner located directly below the first source drain region; and The second silicide liner is located directly below the second source-drain region. A semiconductor structure comprising the first silicide liner being made of a different material from the second silicide liner.

9. A first silicide positioned between each of the first source drain regions and the first silicide liner, and in direct contact with them; and A second silicide is positioned between each of the second source drain regions and the second silicide liner, and is in direct contact with them. The semiconductor structure according to claim 8, further comprising:

10. A first back-side source-drain contact located directly beneath each of the first source-drain regions and communicating with them; and A second back-side source-drain contact located directly beneath each of the second source-drain regions, which communicates with them electrically. The semiconductor structure according to claim 8, further comprising:

11. A first back-surface source-drain contact located directly beneath each of the first source-drain regions and communicating with them, wherein the lowest surface of the first back-surface source-drain contact is substantially coplanar with the lowest surface of the dielectric bar; and A second back-surface source-drain contact is located directly beneath each of the second source-drain regions and communicates with them, wherein the lowest surface of the second back-surface source-drain contact is substantially coplanar with the lowest surface of the dielectric bar. The semiconductor structure according to claim 8, further comprising:

12. The semiconductor structure according to claim 8, wherein the distance between each of the first source-drain regions and each of the second source-drain regions is less than 10 nm.

13. The semiconductor structure according to claim 8, wherein the width of the dielectric bar is less than 10 nm.

14. Each of the first source-drain regions and the sidewall of the first silicide liner are in direct contact with the first sidewall of the dielectric bar. The semiconductor structure according to claim 8, wherein each of the second source-drain regions and the sidewall of the second silicide liner are in direct contact with the second sidewall of the dielectric bar.

15. n-type nanosheet device having n-type source-drain regions; p-type nanosheet device having p-type source-drain regions; A dielectric bar is positioned between each of the n-type source-drain regions and each of the p-type source-drain regions, physically separating them; A first silicide liner located directly below the n-type source-drain region; and The second silicide liner is located directly below the p-type source-drain region. A semiconductor structure comprising the first silicide liner being made of a different material from the second silicide liner.

16. A first silicide positioned between the n-type source drain region and the first silicide liner, and in direct contact with them; and A second silicide is positioned between the p-type source drain region and the second silicide liner, and is in direct contact with them. The semiconductor structure according to claim 15, further comprising:

17. A first back-surface source-drain contact located directly beneath the n-type source-drain region and communicating with it; and A second back-side source-drain contact is located directly below the aforementioned p-type source-drain region and communicates with it. The semiconductor structure according to claim 15, further comprising:

18. The semiconductor structure according to claim 15, wherein the distance between each of the n-type source-drain regions and each of the p-type source-drain regions is less than 10 nm.

19. The semiconductor structure according to claim 15, wherein the width of the dielectric bar is less than 10 nm.

20. The n-type source-drain region and the sidewall of the first silicide liner are in direct contact with the first sidewall of the dielectric bar. The semiconductor structure according to claim 15, wherein the p-type source-drain region and the sidewall of the second silicide liner are in direct contact with the second sidewall of the dielectric bar.

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