Self-aligning back-surface contact lenses

Abstract

A semiconductor structure comprising a first transistor having a first placeholder and a first gate pitch, and a second transistor having a second placeholder and a second gate pitch, wherein the first gate pitch is smaller than the second gate pitch, and the first placeholder is smaller than the second placeholder.

Description

[Background technology]

[0001] The present invention generally relates to semiconductor structures, and more particularly to nanosheet transistor structures having self-aligned back-surface contacts.

[0002] Complementary metal-oxide-semiconductor (CMOS) technology is commonly used for field-effect transistors (FETs) as part of advanced integrated circuits (ICs) such as central processing units (CPUs), memory, and storage devices. As the demand for reducing the size of transistor devices continues, nanosheet FETs help achieve a reduction in the footprint of FET devices while maintaining the performance of the FET device. A nanosheet FET comprises multiple stacked nanosheets extending between a pair of source-drain epitaxial regions. The device may be a gate-all-around device or transistor in which the gate surrounds a portion of the nanosheet channel. The nanosheet device comprises one or more layers of semiconductor channel material having a vertical thickness substantially less than its width. [Overview of the project]

[0003] According to embodiments of the present invention, a semiconductor structure is provided. The semiconductor structure may comprise a first transistor having a first placeholder and a first gate pitch, and a second transistor having a second placeholder and a second gate pitch, wherein the first gate pitch is smaller than the second gate pitch, and the first placeholder is smaller than the second placeholder.

[0004] According to another embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may comprise a first array of nanosheet transistors having a first placeholder, and a second array of nanosheet transistors having a second placeholder, wherein the first gate pitch of the first array of nanosheet transistors is smaller than the second gate pitch of the second array of nanosheet transistors, and the bottom surface of each of the second placeholders is below the bottom surface of each of the first placeholders.

[0005] According to another embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may comprise a first array of nanosheet transistors having a first placeholder adjacent to a first back-side source-drain contact, wherein the first array of nanosheet transistors has a first gate pitch, and a second array of second placeholder nanosheet transistors adjacent to a second back-side source-drain contact, wherein the first array of nanosheet transistors has a second gate pitch, wherein the first gate pitch is smaller than the second gate pitch, and the bottom surface of each of the second placeholders is below the bottom surface of each of the first placeholders. [Brief explanation of the drawing]

[0006] The following detailed description is provided for illustrative purposes only and is not intended to limit the invention to therein, and will be best understood in conjunction with the accompanying drawings.

[0007] [Figure 1] The following figures show different cross-sectional views of the semiconductor structure and a top view of the overall structure to provide spatial context for the structural orientation.

[0008] [Figure 2] This is a cross-sectional view of a semiconductor structure during an intermediate step in a method for fabricating a nanosheet transistor structure according to an exemplary embodiment. [Figure 3]A cross-sectional view of a semiconductor structure during an intermediate stage of a method for fabricating a nanosheet transistor structure according to an exemplary embodiment.

[0009] [Figure 4] A cross-sectional view of a semiconductor structure after forming and patterning a sacrificial gate dielectric and a sacrificial gate according to an exemplary embodiment. [Figure 5] A cross-sectional view of a semiconductor structure after forming and patterning a sacrificial gate dielectric and a sacrificial gate according to an exemplary embodiment.

[0010] [Figure 6] A cross-sectional view of a semiconductor structure after selectively removing a second sacrificial nanosheet according to an exemplary embodiment. [Figure 7] A cross-sectional view of a semiconductor structure after selectively removing a second sacrificial nanosheet according to an exemplary embodiment.

[0011] [Figure 8] A cross-sectional view of a semiconductor structure after forming a spacer material according to an exemplary embodiment. [Figure 9] A cross-sectional view of a semiconductor structure after forming a spacer material according to an exemplary embodiment.

[0012] [Figure 10] A cross-sectional view of a semiconductor structure after removing a portion of a nanosheet stack according to an exemplary embodiment. [Figure 11] A cross-sectional view of a semiconductor structure after removing a portion of a nanosheet stack according to an exemplary embodiment.

[0013] [Figure 12] A cross-sectional view of a semiconductor structure after adding a substrate material according to an exemplary embodiment. [Figure 13] A cross-sectional view of a semiconductor structure after adding a substrate material according to an exemplary embodiment.

[0014] [Figure 14] Cross-sectional view of a semiconductor structure after sacrificial spacers, according to an exemplary embodiment. [Figure 15] Cross-sectional view of a semiconductor structure after sacrificial spacers, according to an exemplary embodiment.

[0015] [Figure 16] Cross-sectional view of a semiconductor structure after forming a first opening and a second opening, according to an exemplary embodiment. [Figure 17] Cross-sectional view of a semiconductor structure after forming a first opening and a second opening, according to an exemplary embodiment.

[0016] [Figure 18] Cross-sectional view of a semiconductor structure after enlarging an opening, according to an exemplary embodiment. [Figure 19] Cross-sectional view of a semiconductor structure after enlarging an opening, according to an exemplary embodiment.

[0017] [Figure 20] Cross-sectional view of a semiconductor structure after forming a first placeholder and a second placeholder, according to an exemplary embodiment. [Figure 21] Cross-sectional view of a semiconductor structure after forming a first placeholder and a second placeholder, according to an exemplary embodiment.

[0018] [Figure 22] Cross-sectional view of a semiconductor structure after removing sacrificial spacers, according to an exemplary embodiment. [Figure 23] Cross-sectional view of a semiconductor structure after removing sacrificial spacers, according to an exemplary embodiment.

[0019] [Figure 24] Cross-sectional view of a semiconductor structure after recessing a first placeholder and a second placeholder, according to an exemplary embodiment. [Figure 25]This is a cross-sectional view of a semiconductor structure after the first and second placeholders have been recessed, according to an exemplary embodiment.

[0020] [Figure 26] This is a cross-sectional view of a semiconductor structure after forming a source-drain region, a dielectric layer, a sacrificial gate, and a first sacrificial nanosheet, according to an exemplary embodiment, and after selectively removing the gate structure. [Figure 27] This is a cross-sectional view of a semiconductor structure after forming a source-drain region, a dielectric layer, a sacrificial gate, and a first sacrificial nanosheet, according to an exemplary embodiment, and after selectively removing the gate structure.

[0021] [Figure 28] This is a cross-sectional view of a semiconductor structure after the source-drain contacts, middle-of-line, and back-end have been formed and the carrier wafer has been fixed, according to an exemplary embodiment. [Figure 29] This is a cross-sectional view of a semiconductor structure after the source-drain contacts, middle-of-line, and back-end have been formed and the carrier wafer has been fixed, according to an exemplary embodiment.

[0022] [Figure 30] This is a cross-sectional view of the semiconductor structure after the assembly has been inverted and the substrate has been recessed, according to an exemplary embodiment. [Figure 31] This is a cross-sectional view of the semiconductor structure after the assembly has been inverted and the substrate has been recessed, according to an exemplary embodiment.

[0023] [Figure 32] This is a cross-sectional view of the semiconductor structure after the remaining portion of the substrate has been removed, according to an exemplary embodiment. [Figure 33] This is a cross-sectional view of the semiconductor structure after the remaining portion of the substrate has been removed, according to an exemplary embodiment.

[0024] [Figure 34] This is a cross-sectional view of a semiconductor structure after a back surface dielectric layer has been formed, according to an exemplary embodiment. [Figure 35] This is a cross-sectional view of a semiconductor structure after a back surface dielectric layer has been formed, according to an exemplary embodiment.

[0025] [Figure 36] This is a cross-sectional view of a semiconductor structure after a back surface contact trench has been formed, according to an exemplary embodiment. [Figure 37] This is a cross-sectional view of a semiconductor structure after a back surface contact trench has been formed, according to an exemplary embodiment.

[0026] [Figure 38] This is a cross-sectional view of a semiconductor structure after the placeholder has been removed, according to an exemplary embodiment. [Figure 39] This is a cross-sectional view of a semiconductor structure after the placeholder has been removed, according to an exemplary embodiment.

[0027] [Figure 40] This is a cross-sectional view of a semiconductor structure after the back contact structure and back wiring layer have been formed according to an exemplary embodiment. [Figure 41] This is a cross-sectional view of a semiconductor structure after the back contact structure and back wiring layer have been formed according to an exemplary embodiment.

[0028] The drawings are not necessarily to scale. The drawings are merely schematic representations and are not intended to represent specific parameters of the invention. For clarity and ease of illustration, the scale of elements may be shown larger than they actually are. The drawings are intended to illustrate only typical embodiments of the invention. In the drawings, similar reference numerals represent similar elements. [Modes for carrying out the invention]

[0029] Detailed embodiments of the claimed structure and method are disclosed herein; however, it should be understood that the disclosed embodiments are merely illustrative of the claimed structure and method, which may be embodied in various forms. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the exemplary embodiments described herein. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the embodiments presented.

[0030] References in the specification such as "one embodiment," "one example embodiment," or "one example embodiment" indicate that the described embodiment includes a particular feature, structure, or characteristic, but not all embodiments necessarily include that particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in relation to one embodiment, it is conceivable that, whether explicitly described or not, it would be within the knowledge of those skilled in the art to influence such feature, structure, or characteristic in relation to other embodiments.

[0031] For the purposes of the following description, the terms “upper,” “downward,” “right,” “left,” “vertical,” “horizontal,” “upper,” and “lower” and their derivatives shall be those of the structure and method disclosed as oriented in the drawings. When an element, such as a layer, region, or substrate, is said to be "on" or "over" another element, it will be understood that it may be directly on that other element, or that there may be an intervening element. In contrast, when an element is said to be "directly on" or "directly over" another element, there is no intervening element. When an element is said to be "connected" or "coupled" to another element, it will also be understood that it may be directly connected or coupled to that other element, or that there may be an intervening element. In contrast, when an element is said to be "directly connected" or "directly coupled" to another element, there is no intervening element. Furthermore, the term "sublithographic" may refer to dimensions or sizes smaller than the current dimensions achievable by the photolithography process, and the term "lithographic" may refer to dimensions or sizes equal to or greater than the current dimensions achievable by the photolithography process. Sublithographic and lithographic dimensions may be determined by a person skilled in the art at the time the application is filed.

[0032] The terms substantially, substantially similar, about, or any other terms indicating functionally equivalent similarity refer to cases where differences in length, height, or orientation do not result in actual differences between a clear enumeration (e.g., a phrase without the term substantially similar) and substantially similar derivatives. In one embodiment, substantial (and its derivatives) means differences due to engineering or manufacturing tolerances generally accepted for similar devices, e.g., a maximum deviation of 10% in value or 10 degrees in angle.

[0033] To avoid ambiguity in the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations known in the art may be combined together for presentation and illustrative purposes, and in some cases may not be described in detail. In other examples, some processing steps or operations known in the art may not be described at all. It should be understood that the following description focuses rather on the specific features or elements of various embodiments of the present invention.

[0034] Complementary field-effect transistors, including gate-all-around transistor devices and nanosheet transistor devices, have known advantages over conventional transistor structures in terms of density, performance, power consumption, and integration. However, fabricating device contacts on the back surface of a wafer presents unique challenges. More specifically, conventional placeholder fabrication techniques, for example, introduce undesirable process variations when fabricating transistor arrays with different gate pitches. Such process variations can result in insufficient source / drain growth near the lower channel. Therefore, it is desirable to form self-aligned back-side contacts using placeholders without requiring undesirable process variations.

[0035] The present invention relates in general to semiconductor structures, and more particularly to nanosheet transistor structures having self-aligned back-side contacts. More specifically, the nanosheet transistor structures and related methods disclosed herein enable a novel solution for providing self-aligned back-side device contacts while using placeholder fabrication techniques and avoiding undesirable process variations. Exemplary embodiments of nanosheet transistor structures having self-aligned back-side contacts are described in detail below with reference to the accompanying drawings Figures 1 to 41. Those skilled in the art will readily understand that the detailed description given herein with respect to these figures is for illustrative purposes only, for the present invention extends beyond these limiting embodiments.

[0036] Referring to Figure 1, we see different cross-sectional views of the semiconductor structure shown and described below, as well as a top view of the overall structure to provide spatial context for the structural orientation. Additionally, XYZ Cartesian coordinates may also be shown in each of the drawings to provide further spatial context. As used herein, the terms “vertical,” “vertical direction,” or “vertical height” refer to the Z direction of the Cartesian coordinates shown in the drawings, and as used herein, the terms “horizontal,” “horizontal direction,” or “lateral direction” refer to the X and / or Y directions of the Cartesian coordinates shown in the drawings.

[0037] The overall structure shown in Figure 1 represents a first transistor array and a second transistor array, including fins / stacks and corresponding gate regions positioned perpendicular to the fins / stacks. Figures 1 to 41 represent cross-sectional views oriented as shown in Figure 1.

[0038] Referring now to Figures 2 and 3, we see structure 100 in an intermediate stage of a method for fabricating a stacked transistor structure according to an embodiment of the present invention. Figure 2 shows a cross-sectional view of structure 100 cut along line X1-X1, and Figure 3 shows a cross-sectional view of structure 100 cut along line X2-X2.

[0039] The structure 100 shown in Figures 2-3 includes a nanosheet stack 102 or fin formed from an alternating series of first silicon-germanium (SiGe) sacrificial nanosheets 104 (hereinafter referred to as "first sacrificial nanosheet 104"), silicon (Si) channel nanosheets 106 (hereinafter referred to as "channel nanosheet 106"), and second silicon-germanium (SiGe) sacrificial nanosheets 108 (hereinafter referred to as "second sacrificial nanosheet 108"), as illustrated. The nanosheet stack 102 is formed on a silicon substrate 110. Although only a limited number of nanosheet stacks 102 and nanosheet layers are shown, one or more additional nanosheet stacks and / or nanosheets can be optionally alternately epitaxially grown, and the properties of any additional nanosheets are the same as those of the corresponding nanosheets described herein.

[0040] According to embodiments of this disclosure, the first sacrificial nanosheet 104 has a different germanium concentration than the second sacrificial nanosheet 108. In at least one embodiment, the second sacrificial nanosheet 108 has a higher germanium concentration than the first sacrificial nanosheet 104. More specifically, for example, the second sacrificial nanosheet 108 may have a germanium concentration in the range of about 45 to about 70 percent, while the first sacrificial nanosheet 104 may have a germanium concentration in the range of about 15 to about 40 percent. In all cases, the different germanium concentrations are designed so that the first sacrificial nanosheet 104 and the second sacrificial nanosheet 108 can be selectively etched relative to each other. Thus, other germanium concentrations are explicitly intended.

[0041] In one or more embodiments, the nanosheet stack 102 is formed by epitaxially growing one layer and then the next until a desired number and thickness of each layer is achieved. The epitaxial material can be grown from a gaseous or liquid precursor. The epitaxial material can be grown using vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), or other suitable processes. The epitaxial silicon, silicon germanium, and / or carbon-doped silicon (Si:C) may be undoped or, depending on the type of transistor, may be doped during deposition (in situ doped) by adding a dopant, an n-type dopant (e.g., phosphorus or arsenic), or a p-type dopant (e.g., boron or gallium). For example, in at least one embodiment, each nanosheet stack 102 includes a channel nanosheet 106 which is doped, undoped, or some combination thereof.

[0042] The terms "epitaxial growth and / or deposition" and "epitaxial formation and / or growth" mean that one semiconductor material (crystalline material) grows on the deposition surface of another semiconductor material (crystalline material), where the growing semiconductor material (crystalline overlayer) has substantially the same crystalline properties as the semiconductor material on the deposition surface (seed material). In the epitaxial deposition process, the chemical reactants provided by the source gas are controlled and system parameters are set so that the atoms to be deposited move around on the surface, thereby reaching the deposition surface with enough energy to orient themselves to the crystalline arrangement of the atoms on the deposition surface. Thus, the epitaxially grown semiconductor material has substantially the same crystalline properties as the deposition surface on which the epitaxially grown material is formed. For example, an epitaxially grown semiconductor material deposited on a crystal surface with a {100} orientation will inherit the {100} orientation. In some embodiments, the epitaxial growth and / or deposition process is selective for formation on semiconductor surfaces and generally does not deposit material on exposed surfaces such as silicon dioxide or silicon nitride surfaces.

[0043] In some embodiments, the gas source for depositing epitaxial semiconductor materials includes silicon-containing gas sources, germanium-containing gas sources, or combinations thereof. For example, an epitaxial silicon layer can be deposited from a silicon gas source selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source selected from the group consisting of german, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. On the other hand, an epitaxial silicon-germanium alloy layer can be formed using a combination of such gas sources. Carrier gases such as hydrogen, nitrogen, helium, and argon may be used.

[0044] The substrate 110 may be a layered semiconductor such as a silicon-on-insulator or a SiGe-on-insulator, where an etching stop layer 112 isolates the base substrate 114 from the upper semiconductor layer 116. Unlike conventional layered semiconductor substrates, the etching stop layer 112 of the substrate 110 may contain any material that affects the desired etching selectivity during subsequent processing. For example, the etching stop layer 112 may be a conventional embedded oxide layer, or it may be a silicon-germanium layer with a specific germanium concentration. In fact, the etching stop layer 112 can be composed of any material that functions as an etching stop layer and supports that function.

[0045] In this embodiment, both the base substrate 114 and the upper semiconductor layer 116 may be any bulk substrate made from any of several known semiconductor materials, such as silicon, germanium, silicon-germanium alloys, and composite (e.g., III-V and II-VI) semiconductor materials. For example, both the base substrate 114 and the upper semiconductor layer 116 may be made from silicon. Additionally, both the etching stop layer 112 and the base substrate 114 are sacrificed and do not remain in the final structure.

[0046] Known processing techniques are applied to alternating layers to form the nanosheet stack 102 shown. For example, known processing techniques may include the formation of a hard mask (not shown) on the top layer of the nanosheet stack 102. The hard mask can be formed by first depositing a hard mask material (e.g., silicon nitride) on the top layer of the nanosheet stack 102 using, for example, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or any technique suitable for dielectric deposition that does not induce physical or chemical changes on the top layer of the nanosheet stack 102. According to an exemplary embodiment, the hard mask material is deposited on the upper channel nanosheet 106 of the nanosheet stack 102 and then patterned into a plurality of individual hard masks. The hard mask patterning is suitable for the desired footprint and location of the nanosheet stack 102 shown in Figure 4, which is then used to form the channel region of the semiconductor device disclosed herein. According to an exemplary embodiment, as shown, RIE is used to transfer a hard mask pattern to alternating layers for forming a nanosheet stack 102 and to the substrate 110.

[0047] Next, shallow trench isolation regions (not shown) are formed by known techniques. The shallow trench isolation regions are formed at the bottom of trenches in the substrate 110 formed during the patterning of the nanosheet stack 102. Specifically, dielectric material is deposited at the bottom of trenches in the substrate 110 by known techniques to isolate adjacent devices from each other. The shallow trench isolation regions are made of, for example, silicon dioxide (SiO₂). x ) or silicon nitride (Si x N y It may be formed from any suitable dielectric material including ).

[0048] Referring now to Figures 4 and 5, a structure 100 is shown after forming and patterning a sacrificial gate dielectric (not shown) and a sacrificial gate 120 according to an embodiment of the present invention. Figure 4 shows a cross-sectional view of the structure 100 cut along line X1-X1, and Figure 5 shows a cross-sectional view of the structure 100 cut along line X2-X2.

[0049] The sacrificial gate dielectric is deposited directly onto the exposed surface of structure 100 using known techniques. Specifically, as shown in the figure, a relatively thin layer of silicon oxide (SiO2), for example, is first conformally deposited on and around the nanosheet stack 102.

[0050] The sacrificial gate material is first blanket-deposited on and around the nanosheet stack 102 using known techniques. Specifically, a relatively thick layer of amorphous silicon, for example, is blanket-deposited directly onto the sacrificial gate dielectric as shown in the figure. In this way, both the sacrificial gate dielectric and the sacrificial gate material completely cover the nanosheet stack 102.

[0051] As used herein, “conformal” means that a material layer has a continuous or substantially continuous thickness. For example, continuous thickness generally means that a first thickness measured from the bottom surface to the top surface is the same as a second thickness measured from the inner sidewall surface to the outer sidewall surface.

[0052] Next, a gate hard mask 122 is formed on the structure 100. The gate hard mask 122 defines the gate region of the individual device. According to an exemplary embodiment, the mask material is deposited on the sacrificial gate material and then patterned into a plurality of individual gate hard masks 122. Next, the patterns created by the individual gate hard masks 122 are transferred to the sacrificial gate dielectric and sacrificial gate material. Specifically, a portion of the sacrificial gate dielectric and sacrificial gate material is selectively etched or removed from the gate hard mask 122 to form the sacrificial gate 120 as shown. The portion of the sacrificial gate dielectric and sacrificial gate material may be removed using a silicon RIE process.

[0053] A crucial aspect for embodiments of the present invention is that the first gate pitch (P1) of the first transistor array is different from the second gate pitch (P2) of the second transistor array. As shown in the figure, the first gate pitch (P1) is smaller than the second gate pitch (P2).

[0054] Referring now to Figures 6 and 7, the structure 100 after selective removal of the second sacrificial nanosheet 108 according to an embodiment of the present invention is shown. Figure 6 shows a cross-sectional view of the structure 100 cut along line X1-X1, and Figure 7 shows a cross-sectional view of the structure 100 cut along line X2-X2.

[0055] More specifically, by known techniques, the second sacrificial nanosheet 108 is selectively etched and removed relative to the first sacrificial nanosheet 104 and / or the channel nanosheet 106. This is made possible by varying germanium concentrations. In this case, layers with relatively high germanium concentrations are selectively removed relative to layers with relatively low germanium concentrations.

[0056] Referring now to Figures 8 and 9, the structure 100 after the spacer material 124 has been formed according to an embodiment of the present invention is shown. Figure 8 shows a cross-sectional view of the structure 100 cut along line X1-X1, and Figure 9 shows a cross-sectional view of the structure 100 cut along line X2-X2.

[0057] The spacer material 124 is deposited directly onto the exposed surface of the structure 100 by known techniques. Specifically, a relatively thin layer of silicon nitride, for example, is deposited conformally as shown. In some embodiments, the spacer material 124 may consist of SiN, SiBCN, SiOCN, SiOC, or any other combination of low-k materials. The term “low-k” as used throughout this application refers to dielectric materials having a dielectric constant of less than 4.0. According to embodiments of this disclosure, the spacer material 124 substantially fills the space created by removing the second sacrificial nanosheet 108 and functions to separate the nanosheet stack 102 from the substrate 110. Furthermore, according to embodiments of this disclosure, the spacer material 124 substantially covers the exposed vertical sidewalls of the nanosheet stack 102 and the exposed vertical sidewalls of the sacrificial gate 120, as shown in Figure 13.

[0058] Referring now to Figures 10 and 11, the structure 100 is shown after a portion of the nanosheet stack 102 has been removed according to an embodiment of the present invention. Figure 10 shows a cross-sectional view of the structure 100 cut along line X1-X1, and Figure 11 shows a cross-sectional view of the structure 100 cut along line X2-X2.

[0059] A portion of the nanosheet stack 102 is etched and removed from between the sacrificial gates 120 by known techniques. Specifically, the patterns created by the individual gate hard masks 122 and spacer material 124 are transferred to the nanosheet stack 102. In doing so, a portion of the first sacrificial nanosheet 104 and channel nanosheet 106 is selectively removed from the spacer material 124 as shown in the figure.

[0060] In embodiments, a portion of the nanosheet stack 102 is removed using anisotropic etching, such as reactive ion etching. This may require a series of etching steps using different etching chemistry, as is well known in the art. The etching is designed to create source-drain openings and expose the edges of individual nanosheet layers.

[0061] Next, the exposed portion of the spacer material 124 below the source drain opening is selectively removed by known techniques. Specifically, in embodiments, the exposed portion of the spacer material 124 is removed using anisotropic etching, such as reactive ion etching. By doing so, the substrate 110 is exposed as shown in the figure.

[0062] Referring further to Figures 10 and 11, the structure 100 after the inner spacer 126 has been formed according to an embodiment of the present invention is shown.

[0063] First, the first sacrificial nanosheet 104 is laterally recessed to create space for the inner spacer 126. In one or more embodiments, the first sacrificial nanosheet 104 is laterally recessed using an isotropic etching process with hydrogen chloride (HCl) gas, which etches silicon germanium without eroding silicon. In other embodiments, the first sacrificial nanosheet 104 is laterally recessed using a ClF3 etching process. The space occupied by the removed portion of the first sacrificial nanosheet 104 forms a cavity (not shown).

[0064] The inner spacer 126 is formed by first conformally depositing spacer material onto the structure 100 to fill the cavity created by laterally recessing the first sacrificial nanosheet 104. The conformal spacer material is then isotropically etched to remove all portions except those remaining in the cavity and forming the inner spacer 126. In one or more embodiments, the inner spacer 126 is made from a nitride-containing material, such as silicon nitride (SiN). The inner spacers 126 shown in Figures 10 and 11 are formed from nitride-containing materials, but they can be formed from any material for which subsequent device fabrication operations are not particularly selective. As used in this description, selectivity refers to the tendency of process operations to impact a particular material. One example of low selectivity is a relatively slow etching rate. One example of higher or greater selectivity is a relatively fast etching rate. For the embodiments described, the material for the inner spacer 126 can be selected based on the selectivity of subsequent device fabrication operations with respect to the selected material being below a predetermined threshold.

[0065] The inner spacer 126 is positioned so that a subsequent etching process used to remove the first sacrificial nanosheet 104 during device fabrication does not erode the subsequently formed source drain region.

[0066] Referring now to Figures 12 and 13, the structure 100 after the addition of substrate material according to an embodiment of the present invention is shown. Figure 12 shows a cross-sectional view of the structure 100 cut along line X1-X1, and Figure 13 shows a cross-sectional view of the structure 100 cut along line X2-X2.

[0067] The additional substrate material is added to the upper semiconductor layer 116 by known techniques. Specifically, the additional silicon-based material is epitaxially grown from the upper surface of the upper semiconductor layer 116 exposed within the source-drain opening. In all cases, the additional silicon-based material is grown to a target thickness substantially equal to the thickness of the spacer material 124, as illustrated. The exact thickness of the additional silicon-based material is not critical, but the upper surface of the additional silicon-based material should never extend above the upper surface of the bottom inner spacer 126. In other words, the additional silicon-based material should preferably not contact, cover, or otherwise block the bottom channel nanosheet 106. According to embodiments of the present invention, the silicon-based material may be identical or substantially identical to the material of the upper semiconductor layer 116. For example, in at least one embodiment, both the upper semiconductor layer 116 and the additional silicon-based material are silicon.

[0068] Referring now to Figures 14 and 15, the structure 100 after the sacrificial spacer 128 has been formed according to an embodiment of the present invention is shown. Figure 14 shows a cross-sectional view of the structure 100 cut along line X1-X1, and Figure 15 shows a cross-sectional view of the structure 100 cut along line X2-X2.

[0069] Sacrificial spacers 128 are formed directly on the exposed vertical sidewalls of the source-drain openings by known techniques. Specifically, for example, a relatively thin spacer material is conformally deposited on and around the nanosheet stack 102, the sacrificial gate 120, and the spacer material 124, and then directional RIE is performed on the deposited spacer material. The remainder of the spacer material forms the necessary sacrificial spacers 128 to protect the exposed edges of the channel nanosheet 106 during subsequent processing and prevent damage thereto. According to embodiments of the present invention, the spacer material may include aluminum oxide or titanium oxide, however other known spacer materials that provide suitable etching selectivity may also be used.

[0070] Referring now to Figures 16 and 17, the structure 100 is shown after the first opening 130 and the second opening 132 have been formed in the substrate 100 according to an embodiment of the present invention. Figure 16 shows a cross-sectional view of the structure 100 cut along line X1-X1, and Figure 17 shows a cross-sectional view of the structure 100 cut along line X2-X2.

[0071] The openings 130 and 132 are formed in the upper semiconductor layer 116 below the source-drain openings by known techniques and as shown in the illustration. Specifically, as shown in the illustration, a portion of the upper semiconductor layer 116 is selectively removed from the sacrificial spacer 128, spacer material 124, and gate hard mask 122 using known etching techniques. Etching is continued until the lower surfaces of the openings 130 and 132 are below the lower surface of the spacer material 124. For example, the lower surfaces of the openings 130 and 132 may reach a depth of approximately 10 nm to approximately 30 nm below the lower surface of the spacer material 124, although other depths are explicitly intended.

[0072] In at least one embodiment, a directional dry etching technique, such as reactive ion etching, is used to etch or remove a portion of the upper semiconductor layer 116 to form the openings 130 and 132. Thus, as shown, the openings 130 and 132 are self-aligned with the sacrificial spacer 128. Additionally, the substrate material remains directly beneath the sacrificial spacer 128 due to the directional nature of the selected etching technique. As a result of the etching technique used, the openings 130 and 132 have a continuous tapered profile. More specifically, the openings 130 and 132 have cross-sectional dimensions that decrease with respect to height from top to bottom, as shown. While such a tapered profile is conventional, the tapered profile of the openings 130 and 132 is substantially uniform or continuous from top to bottom. According to embodiments of the present invention, it is explicitly intended that the first opening 130 and the second opening 132 are formed simultaneously using the same etching technique and chemical action in the same processing step.

[0073] Note that since the first pitch (P1) is smaller than the second pitch (P2), the corresponding openings 130 and 132 will be of different sizes. Specifically, the second opening 132 formed in the second transistor array is wider and deeper than the first opening 130 formed in the first transistor array.

[0074] Referring now to Figures 18 and 19, the structure 100 after the openings 130 and 132 have been enlarged according to an embodiment of the present invention. Figure 18 shows a cross-sectional view of the structure 100 cut along line X1-X1, and Figure 19 shows a cross-sectional view of the structure 100 cut along line X2-X2.

[0075] Using known techniques and as illustrated, the openings 130 and 132 formed in the upper semiconductor layer 116 are further enlarged. Specifically, as illustrated, known etching techniques are used to selectively increase both the width and depth of the openings 130 and 132 relative to the sacrificial spacer 128, spacer material 124, and gate hard mask 122. Etching is continued until the sidewalls of the enlarged openings 130 and 132 are below the lower surface of the spacer material 124. For example, as shown, etching enlarges the width of the openings 130 and 132 by approximately 8 nm to approximately 16 nm, but other dimensions are explicitly intended. In other words, the sidewalls of the enlarged openings 130 and 132 may be offset by approximately 4 to 8 nm from the exposed sidewalls of the spacer material 124 on each side of the openings 130 and 132.

[0076] In at least one embodiment, a non-directional wet etching technique, such as ammonia-based wet etching, is used to further enlarge the openings 130 and 132. Thus, the openings 130 and 132 remain self-aligned with the sacrificial spacer 128 and spacer material 124, as shown. As a result of the etching technique used, the side walls and bottom surface of the spacer material 124 are exposed, as shown, and the opening 130 extends laterally beneath the spacer material 124. Furthermore, all remaining substrate material directly beneath the sacrificial spacer 128 is removed due to the non-directional nature of the selected etching technique. It is important that no substrate material remains directly beneath the sacrificial spacer 128, otherwise it may get trapped when the openings 130 and 132 are subsequently filled with placeholder material.

[0077] Note that the second opening 132 formed in the second transistor array is wider and deeper than the first opening 130 formed in the first transistor array, and the same is true after enlargement. In other words, the enlarged second opening 132 formed in the second transistor array is wider and deeper than the enlarged first opening 130 formed in the first transistor array. The enlarged openings 130, 132 further maximize the contact area between the source-drain regions 142a, 142b and the subsequently formed back-surface source-drain contacts. Additionally, the enlarged openings 130, 132 increase the volume of the subsequently formed back-surface source-drain contacts, thereby reducing contact resistance.

[0078] Referring here to Figures 20 and 21, the structure 100 after the first placeholder 134 and the second placeholder 136 have been formed according to an embodiment of the present invention is shown. Figure 20 shows a cross-sectional view of the structure 100 cut along line X1-X1, and Figure 21 shows a cross-sectional view of the structure 100 cut along line X2-X2.

[0079] The openings 130 and 132 are filled with sacrificial material to form placeholders 134 and 136 by known techniques. Specifically, additional silicon-based material is epitaxially grown from the surface of the upper semiconductor layer 116 exposed within the openings 130 and 132. In all cases, as illustrated, the additional silicon-based material is grown to a target thickness sufficient to cover the exposed surface of the spacer material 124 and extend above the bottom surface of the sacrificial spacer 128. The exact thickness or height of the additional silicon-based material is not critical, but the top surface of the additional silicon-based material should generally not extend above the top surface of the bottom channel nanosheet 106.

[0080] According to embodiments of the present disclosure, the placeholders 134 and 136 are made from a material that (a) can be grown from the upper semiconductor layer 116 and (b) can be selectively removed from the upper semiconductor layer 116. For example, in at least one embodiment, the placeholders 134 and 136 are made from silicon germanium that can be easily grown from the upper semiconductor layer 116. Additionally, the germanium concentration allows for desired etching selectivity.

[0081] Note that the enlarged second opening 132 formed in the second transistor array is wider and deeper than the enlarged first opening 130 formed in the first transistor array, so the second placeholder 136 formed in the enlarged second opening 132 is wider and deeper than the first placeholder 134 formed in the enlarged first opening 130. Similarly, as shown in the figure, the top surface of the second placeholder 136 is above the top surface of the first placeholder 134.

[0082] Referring now to Figures 22 and 23, the structure 100 after the removal of the sacrificial spacer 128 according to an embodiment of the present invention is shown. Figure 22 shows a cross-sectional view of the structure 100 cut along line X1-X1, and Figure 23 shows a cross-sectional view of the structure 100 cut along line X2-X2.

[0083] The sacrificial spacer 128 is selectively removed by known techniques. Specifically, the sacrificial spacer 128 is removed using known etching techniques suitable for selectively removing aluminum oxide or titanium oxide from surrounding elements or materials. In embodiments, the sacrificial spacer 128 is removed using isotropic etching, such as dry or wet etching. By removing the sacrificial spacer 128, a stepped opening 138 is created.

[0084] It should be noted that although the second placeholder 136 is wider and deeper than the first placeholder 134, the stepped opening 138 is approximately aligned or at a similar level. In other words, the bottom surface of the stepped opening 138 is substantially coplanar across all of the placeholders 134 and 136. This is possible because the sacrificial spacer 128 is formed on the flat upper surface of the upper semiconductor layer 116, and the bottom surface of the sacrificial spacer 128 was substantially coplanar across both transistor arrays (see Figures 14 to 21). Furthermore, by removing the sacrificial spacer 128, the side walls of the upper portions of the placeholders 134 and 136 are further exposed, as shown.

[0085] Referring now to Figures 24 and 25, the structure 100 after the first placeholder 134 and the second placeholder 136 have been recessed according to an embodiment of the present invention is shown. Figure 24 shows a cross-sectional view of the structure 100 cut along line X1-X1, and Figure 25 shows a cross-sectional view of the structure 100 cut along line X2-X2.

[0086] Next, below the openings 130 and 132, the exposed portions of the first placeholder 134 and the second placeholder 136 are selectively etched by known techniques. Specifically, in embodiments, the exposed surfaces of the first placeholder 134 and the second placeholder 136 are removed using isotropic etching, such as dry or wet etching. By doing so, both the first placeholder 134 and the second placeholder 136 are recessed to a similar level. In other words, as illustrated, although the second placeholder 136 is wider and deeper than the first placeholder 134, the top surfaces of both the first placeholder 134 and the second placeholder 136 become substantially uniform after recessing. As used herein, substantially uniform means that the two surfaces have substantially similar profiles and substantially similar heights. The resulting profiles of placeholders 134 and 136 are made possible because isotropic etching erodes both the exposed side walls and the top surface of placeholders 134 and 136.

[0087] Of particular importance for structures with different gate pitches is that, with the embodiments disclosed herein, the uppermost surfaces of both the first placeholder 134 and the second placeholder 136 are ensured to be substantially uniform. In contrast, without the embodiments disclosed, the uppermost surface of the first placeholder 134 resulting from a single uniform deposition process would be higher than the uppermost surface of the second placeholder 136. Placeholders of different heights can be particularly problematic. Specifically, in dense-pitch devices, placeholders must remain low enough to prevent coating, or otherwise block the bottom channel nanosheet 106, while in loose-pitch devices, placeholders must remain high enough to prevent void formation in the source-drain epitaxy.

[0088] Referring now to Figures 26 and 27, the structure 100 after the source drain region 140 has been formed according to an embodiment of the present invention is shown. Figure 26 shows a cross-sectional view of the structure 100 cut along line X1-X1, and Figure 27 shows a cross-sectional view of the structure 100 cut along line X2-X2.

[0089] The source-drain region 140 is formed by known techniques using an epitaxial layer growth process at the exposed edges of the channel nanosheet 106. Typically, in-situ doping is used to dope the source-drain region 140, thereby creating the required junctions for the semiconductor device. Virtually all semiconductor transistors are based on the formation of junctions. Junctions allow both blocking and allowing current to flow depending on the applied bias. Junctions are typically formed by bringing two semiconductor regions with opposite polarities into contact with each other. The most common junction is the pn junction, which consists of contact between a hole-rich P-type silicon piece and an electron-rich N-type silicon piece. N-type and P-type devices are formed by using different types of dopants to select regions of the device and form the required junctions. For example, N-type devices can be formed by doping with arsenic (As) or phosphorus (P), and P-type devices can be formed by doping with implanted boron (B).

[0090] According to embodiments of the present invention, at least some of the source-drain regions 140 are of a first type, for example, type P, and at least some of the source-drain regions 140 are of a second type, for example, type N.

[0091] Referring further to Figures 26 and 27, the structure 100 is shown after forming the dielectric layer 142, selectively removing the sacrificial gate 120 and the first sacrificial nanosheet 104, and forming the gate structure 144, according to an embodiment of the present invention.

[0092] Using known techniques, a dielectric layer 142 is formed by blanket deposition of interlayer dielectric material on structure 100. Specifically, the dielectric layer 142 is formed on the source-drain region 140, as shown in the figure, and substantially fills the remaining space between the spacer material 124.

[0093] The dielectric layer 142 may consist of silicon dioxide, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), spin-on low-k dielectric layer, chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. In another embodiment, a self-planarizing material such as spin-on glass (SOG) or a spin-on low-k dielectric material such as SiLK® may be used as the dielectric layer 142. By using a self-planarizing dielectric material as the dielectric layer 142, the need to perform a subsequent planarization step can be avoided.

[0094] After the dielectric layer 142 is formed, the structure is polished using known techniques, such as chemical mechanical polishing. Specifically, the dielectric layer 142, the spacer material 124, and the gate hard mask 122 are polished until the uppermost surface of the dielectric layer 142 is coplanar or substantially coplanar with the uppermost surfaces of the spacer material 124 and the sacrificial gate 120.

[0095] Next, the sacrificial gate 120 and the first sacrificial nanosheet 104 are selectively removed by known techniques. First, the sacrificial gate 120 is selectively etched and removed from the spacer material 124 and the nanosheet stack 102 by known techniques. Next, the first sacrificial nanosheet 104 is selectively etched and removed from the channel nanosheet 106 and the inner spacer 126 by known techniques. This is made possible by having different concentrations of germanium. In this case, the layer containing germanium is selectively removed from the layer without germanium.

[0096] Next, the gate structure 144 is formed by known techniques. First, by known techniques, a gate dielectric (not shown) is directly conformally deposited on the exposed surface of the structure 100 within the gate cavity or opening and within the space remaining after removing the sacrificial gate 120 and the first sacrificial nanosheet 104. For example, the gate dielectric is conformally deposited on the exposed surfaces of the channel nanosheet 106 and the inner spacer 126.

[0097] The gate dielectric is composed of any known gate dielectric material, such as oxides, nitrides, and / or oxynitrides. In an example, the gate dielectric may be a high-k material having a dielectric constant greater than that of silicon dioxide. Exemplary high-k dielectrics are HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, Y2O3, HfO x N y 、ZrO x N y 、La2O x N y 、Al2O x N y 、TiO x N y 、SrTiO x N y 、LaAlO x N y 、Y2O x N y 、SiON, SiN x 、including, but not limited to, their silicides, and their alloys. Each value of x is independent from 0.5 to 3, and each value of y is independent from 0 to 2. In some embodiments, a multi-layer gate dielectric structure including different gate dielectric materials. For example, a silicon dioxide layer and a high-k gate dielectric layer can be formed and used together as the gate dielectric. In at least one embodiment, the gate dielectric is composed of hafnium oxide.

[0098] Next, a work function metal (not shown) is conformally deposited onto the gate dielectric formed in the gate cavity using known techniques. In at least one embodiment, the work function metal is made from the same conductive material throughout the entire structure. In at least another embodiment, the work function metal is made from different conductive materials in each of the devices shown in the figure. In doing so, different conductive materials are successively deposited depending on the design parameters and desired operating characteristics.

[0099] The work function metal can include any known conductive gate material, such as doped polysilicon, elemental metals (e.g., tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium, and platinum), alloys of at least two elemental metals, elemental metal nitrides (e.g., tungsten nitride, aluminum nitride, and titanium nitride), elemental metal silicides (e.g., tungsten silicide, nickel silicide, and titanium silicide), or titanium carbon (TiC), titanium aluminum (TiAl), titanium aluminum carbon (TiAlC), or multilayer combinations thereof. In some embodiments, the work function metal can include the gate metal of an nFET. In other embodiments, the work function metal can include the gate metal of a pFET. When multiple gate cavities are formed as illustrated herein, embodiments of the present invention expressly intend to form an nFET in at least one of the gate cavities and a pFET in at least one of the other gate cavities.

[0100] In some embodiments, the gate metal or contact metal is deposited directly onto a work function metal to fill the gate cavity. The first gate metal may include any suitable conductive material, such as copper, ruthenium, aluminum, tungsten, cobalt, or alloys thereof. Any excess conductive material may then be polished off using known techniques.

[0101] Referring now to Figures 28 and 29, the structure 100 is shown after the source-drain contact 146, middle-of-line and back-end 148 have been formed and the carrier wafer 150 has been fixed, according to an embodiment of the present invention. Figure 28 shows a cross-sectional view of the structure 100 cut along line X1-X1, and Figure 29 shows a cross-sectional view of the structure 100 cut along line X2-X2.

[0102] First, additional interlayer dielectric material is deposited using known techniques. Dielectric layer 142, shown in the figure, contains the additional interlayer dielectric material.

[0103] Next, a portion of the dielectric layer 142 is removed to expose the source-drain region 140. Then, by known techniques, the opening is filled with a conductive material to form the source-drain contact 146. The source-drain contact 146 may contain any suitable conductive material, such as copper, ruthenium, aluminum, tungsten, cobalt, or alloys thereof. In some embodiments, a metal silicide is formed beneath the contact trenches before they are filled with the conductive material. In some embodiments, the source-drain contact 146 does not contact the spacer material 124. In other embodiments, the source-drain contact 146 is self-aligned with respect to the spacer material 124 and may therefore be called a self-aligned contact structure.

[0104] Finally, the middle-of-line and back-end layers 148 (hereinafter referred to as MOL / BEOL148) are formed, and the carrier wafer 150 is fixed onto the structure 100 according to an embodiment of the present invention. After the source-drain contacts 146 are formed, the MOL / BEOL148 is then formed by known techniques. Next, the carrier wafer 150 is attached to or removably fixed to the MOL / BEOL148. Generally, although not shown, the carrier wafer 150 may be thicker than the other layers. Temporarily bonding the structure 100 to a thicker carrier improves handling for back-side processing of the thin wafer and provides additional support. After back-side processing as described below, the structure 100 may be peeled off or removed from the carrier wafer 150 by known techniques.

[0105] Referring now to Figures 30 and 31, the structure 100 after the assembly has been inverted and the substrate 110 has been recessed, according to an embodiment of the present invention, is shown. Figure 30 shows a cross-sectional view of the structure 100 cut along line X1-X1, and Figure 31 shows a cross-sectional view of the structure 100 cut along line X2-X2.

[0106] First, structure 100 is inverted 180 degrees to prepare it for back-side processing. Generally, back-side processing involves fabricating or processing structure 100 on the side opposite to the active device and wiring layers. Next, substrate 110 is recessed by known techniques. Specifically, the base substrate 114 is recessed or completely removed to expose the etching stop layer 112 as shown.

[0107] Referring now to Figures 32 and 33, the structure 100 after the remaining portion of the substrate 110 has been removed according to an embodiment of the present invention is shown. Figure 32 shows a cross-sectional view of the structure 100 cut along line X1-X1, and Figure 33 shows a cross-sectional view of the structure 100 cut along line X2-X2.

[0108] First, the etching stop layer 112 and the upper semiconductor layer 116 are selectively removed by known techniques. Specifically, the etching stop layer 112 is selectively removed relative to the upper semiconductor layer 116, and the upper semiconductor layer 116 is selectively removed relative to the placeholders 134, 136 and the spacer material 124. Specific to the disclosed embodiments, due to the presence of the placeholders 134, 136, the source drain region 140 remains intact during the removal of the substrate 110.

[0109] Referring now to Figures 34 and 35, the structure 100 after the back surface dielectric layer 152 has been formed according to an embodiment of the present invention is shown. Figure 34 shows a cross-sectional view of the structure 100 cut along line X1-X1, and Figure 35 shows a cross-sectional view of the structure 100 cut along line X2-X2.

[0110] Using known techniques, the back surface dielectric layer 152 is formed by blanket deposition of interlayer dielectric material on the structure 100. Specifically, as shown in the figure, the back surface dielectric layer 152 is formed on the placeholders 134, 136 and the spacer material 124.

[0111] The back dielectric layer 152 may consist of silicon dioxide, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), spin-on low-k dielectric layer, chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. In another embodiment, a self-planarizing material such as spin-on glass (SOG) or a spin-on low-k dielectric material such as SiLK® may be used as the back dielectric layer 152. By using a self-planarizing dielectric material as the back dielectric layer 152, the need to perform a subsequent planarization step can be avoided.

[0112] Referring now to Figures 36 and 37, the structure 100 after the back surface contact trench 156 has been formed according to an embodiment of the present invention is shown. Figure 36 shows a cross-sectional view of the structure 100 cut along line X1-X1, and Figure 37 shows a cross-sectional view of the structure 100 cut along line X2-X2.

[0113] First, a mask (not shown) is deposited by known techniques and then patterned to expose specific portions of structure 100. The mask may be an organic planarization layer (OPL) or a layer of material that can be planarized or etched by known techniques. In embodiments, for example, the mask may be an amorphous carbon layer capable of withstanding the subsequent processing temperature. The mask may preferably have a thickness sufficient to cover the existing structure. After the deposition of the mask, a dry etching technique is applied to pattern the mask by known techniques.

[0114] Next, according to exemplary embodiments, RIE is used by known art and as illustrated to transfer a mask pattern to the back dielectric layer 152 to form a back contact trench 156. According to embodiments of the present invention, the back contact trench 156 is generally aligned with one or more of the placeholders 134, 136 as illustrated to expose them.

[0115] Referring now to Figures 38 and 39, the structure 100 according to an embodiment of the present invention is shown after the placeholders 134, 136 exposed by the rear contact trench 156 have been removed. Figure 38 shows a cross-sectional view of the structure 100 cut along line X1-X1, and Figure 39 shows a cross-sectional view of the structure 100 cut along line X2-X2.

[0116] Placeholders 134 and 136 exposed by the back surface contact trench 156 are selectively removed by known techniques. Specifically, placeholders 134 and 136 exposed by the back surface contact trench 156 are selectively etched or removed with respect to the spacer material 124 and the source drain region 140, as shown in the figure. For example, anisotropic etching techniques, such as reactive ion etching, may be used to remove placeholders 134 and 136.

[0117] Referring now to Figures 40 and 41, the structure 100 after the back contact structure 158 and back wiring layer 160 have been formed according to an embodiment of the present invention is shown. Figure 40 shows a cross-sectional view of the structure 100 cut along line X1-X1, and Figure 41 shows a cross-sectional view of the structure 100 cut along line X2-X2.

[0118] Next, the back contact trenches 156 are filled with a conductive material by known techniques to form the back contact structure 158. The back contact structure 158 may include any suitable conductive material, such as copper, ruthenium, aluminum, tungsten, cobalt, or alloys thereof. In some embodiments, metal silide is formed beneath the back contact trenches 156 before they are filled with the conductive material. Then, as shown, excess conductive material may be polished using known techniques until the bottom surface of the back contact structure 158 is coplanar or substantially coplanar with the bottom surface of the back dielectric layer 152. It should be noted that the back contact structure 158 may include, for example, back source-drain contacts and back gate contacts, as shown. After the back contact structure 158 is formed, the back wiring layer 160 is then formed by known techniques.

[0119] Referring again to Figures 40 and 41, and according to the embodiment, the structure 100 comprises a first transistor having a first placeholder and a first gate pitch, and a second transistor having a second placeholder and a second gate pitch, wherein the first gate pitch is smaller than the second gate pitch, and the first placeholder is smaller than the second placeholder.

[0120] Referring again to Figures 40 and 41, and according to the embodiment, the structure 100 comprises a first array of nanosheet transistors having a first placeholder, and a second array of nanosheet transistors having a second placeholder, wherein the first gate pitch of the first array of nanosheet transistors is smaller than the second gate pitch of the second array of nanosheet transistors, and the bottom surface of each of the second placeholders is lower than the bottom surface of each of the first placeholders.

[0121] Referring again to Figures 40 and 41, and according to the embodiment, the structure 100 comprises a first array of nanosheet transistors having a first placeholder adjacent to a first back-side source-drain contact, wherein the first array of nanosheet transistors has a first gate pitch, and a second array of nanosheet transistors having a second placeholder adjacent to a second back-side source-drain contact, wherein the second array of nanosheet transistors has a second gate pitch, wherein the first gate pitch is smaller than the second gate pitch, and the bottom surface of each of the second placeholders is below the bottom surface of each of the first placeholders.

[0122] Referring again to Figures 40 and 41, and according to the embodiment, the uppermost surface of the second placeholder is substantially coplanar with the uppermost surface of the first placeholder.

[0123] Referring again to Figures 40 and 41, and according to the embodiment, at least a first portion of the first placeholder is substantially coplanar with the uppermost surface of the back dielectric layer, at least a second portion of the first placeholder extends above the uppermost surface of the back dielectric layer, at least a first portion of the second placeholder is substantially coplanar with the uppermost surface of the back dielectric layer, and at least a second portion of the second placeholder extends above the uppermost surface of the back dielectric layer.

[0124] Referring again to Figures 40 and 41, and according to the embodiment, the first transistor further has a first source-drain region, and the interface between the first placeholder and the first source-drain region is curved, and the second transistor further has a second source-drain region, and the interface between the second placeholder and the second source-drain region is curved.

[0125] Referring again to Figures 40 and 41, and according to the embodiment, the first transistor further has a first source-drain region, and the second transistor further has a second source-drain region, wherein the width of the first source-drain region is smaller than the width of the second source-drain region.

[0126] Referring again to Figures 40 and 41, and according to the embodiment, the first transistor further has a first back-side source-drain contact, the uppermost surface of the first back-side source-drain contact having a profile substantially similar to the uppermost surface of the first placeholder, and the second transistor further has a second back-side source-drain contact, the uppermost surface of the second back-side source-drain contact having a profile substantially similar to the uppermost surface of the second placeholder.

[0127] Referring again to Figures 40 and 41, and according to the embodiment, the first transistor further has a first back-side source-drain contact, where at least a first portion of the first back-side source-drain contact is substantially coplanar with the uppermost surface of the back-side dielectric layer, and at least a second portion of the first back-side source-drain contact extends above the uppermost surface of the back-side dielectric layer. The second transistor further has a second back-side source-drain contact, where at least a first portion of the second back-side source-drain contact is substantially coplanar with the uppermost surface of the back-side dielectric layer, and at least a second portion of the second back-side source-drain contact extends above the uppermost surface of the back-side dielectric layer.

[0128] The descriptions of various embodiments of the present invention have been presented for illustrative purposes only and are not intended to be exhaustive or to limit the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention. The terms used herein have been selected to best describe the principles of the embodiments, their practical applications, or the technical improvements to the technology available on the market, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

Claims

1. A first transistor having a first placeholder and a first gate pitch; and A second transistor having a second placeholder and a second gate pitch; Equipped with, A semiconductor structure in which the first gate pitch is smaller than the second gate pitch, and the first placeholder is smaller than the second placeholder.

2. The semiconductor structure according to claim 1, wherein the uppermost surface of the second placeholder is substantially coplanar with the uppermost surface of the first placeholder.

3. At least a first portion of the first placeholder is substantially coplanar with the uppermost surface of the back dielectric layer, and at least a second portion of the first placeholder extends above the uppermost surface of the back dielectric layer. The semiconductor structure according to claim 1, wherein at least a first portion of the second placeholder is substantially coplanar with the uppermost surface of the back dielectric layer, and at least a second portion of the second placeholder extends above the uppermost surface of the back dielectric layer.

4. The first transistor further has a first source-drain region, and the interface between the first placeholder and the first source-drain region is curved. The semiconductor structure according to claim 1, wherein the second transistor further has a second source-drain region, and the interface between the second placeholder and the second source-drain region is curved.

5. The first transistor further has a first source-drain region, The second transistor further has a second source-drain region, The semiconductor structure according to claim 1, wherein the width of the first source-drain region is smaller than the width of the second source-drain region.

6. The first transistor further has a first back-side source-drain contact, the uppermost surface of the first back-side source-drain contact having a profile substantially similar to the uppermost surface of the first placeholder. The semiconductor structure according to claim 1, wherein the second transistor further has a second back-surface source-drain contact, and the uppermost surface of the second back-surface source-drain contact has a profile substantially similar to that of the uppermost surface of the second placeholder.

7. The first transistor further has a first back-surface source-drain contact, where at least a first portion of the first back-surface source-drain contact is substantially coplanar with the uppermost surface of the back-surface dielectric layer, and at least a second portion of the first back-surface source-drain contact extends above the uppermost surface of the back-surface dielectric layer. The semiconductor structure according to claim 1, wherein the second transistor further has a second back-surface source-drain contact, at least a first portion of the second back-surface source-drain contact is substantially coplanar with the uppermost surface of the back-surface dielectric layer, and at least a second portion of the second back-surface source-drain contact extends above the uppermost surface of the back-surface dielectric layer.

8. A first array of nanosheet transistors having a first placeholder; and A second array of nanosheet transistors having a second placeholder; Equipped with, The first gate pitch of the first array of the nanosheet transistors is smaller than the second gate pitch of the second array of the nanosheet transistors. A semiconductor structure in which the bottom surface of each of the second placeholders is lower than the bottom surface of each of the first placeholders.

9. The semiconductor structure according to claim 8, wherein the uppermost surface of each of the second placeholders is substantially coplanar with the uppermost surface of each of the first placeholders.

10. Each of the first placeholders has at least a first portion that is substantially coplanar with the uppermost surface of the back dielectric layer, and each of the first placeholders has at least a second portion that extends above the uppermost surface of the back dielectric layer. The semiconductor structure according to claim 8, wherein at least a first portion of each of the second placeholders is substantially coplanar with the uppermost surface of the back dielectric layer, and at least a second portion of each of the second placeholders extends above the uppermost surface of the back dielectric layer.

11. The first array of nanosheet transistors further has a first source-drain region, and the interface between each of the first placeholders and each of the first source-drain regions is curved. The semiconductor structure according to claim 8, wherein the second array of nanosheet transistors further has a second source-drain region, and the interface between each of the second placeholders and each of the second source-drain regions is curved.

12. The first array of the nanosheet transistors further has a first source-drain region, The second array of the nanosheet transistors further has a second source-drain region, The semiconductor structure according to claim 8, wherein the width of each of the first source-drain regions is smaller than the width of each of the second source-drain regions.

13. The first array of nanosheet transistors further has first back-side source-drain contacts, and the uppermost surface of each of the first back-side source-drain contacts has a profile substantially similar to the uppermost surface of each of the first placeholders. The semiconductor structure according to claim 8, wherein the second array of nanosheet transistors further has a second back-surface source-drain contact, and the uppermost surface of each of the second back-surface source-drain contacts has a profile substantially similar to that of the uppermost surface of each of the second placeholders.

14. The first array of the nanosheet transistors further has a first back-side source-drain contact, wherein at least a first portion of each of the first back-side source-drain contacts is substantially coplanar with the uppermost surface of the back-side dielectric layer, and at least a second portion of each of the first back-side source-drain contacts extends above the uppermost surface of the back-side dielectric layer. The semiconductor structure according to claim 8, wherein the second array of nanosheet transistors further has a second back-surface source-drain contact, at least a first portion of each of the second back-surface source-drain contacts is substantially coplanar with the uppermost surface of the back-surface dielectric layer, and at least a second portion of each of the second back-surface source-drain contacts extends above the uppermost surface of the back-surface dielectric layer.

15. A first array of nanosheet transistors having a first placeholder adjacent to a first back-side source-drain contact, wherein the first array of nanosheet transistors has a first gate pitch; and A second array of nanosheet transistors having a second placeholder adjacent to a second back-side source-drain contact, wherein the second array of nanosheet transistors has a second gate pitch; Equipped with, The first gate pitch is smaller than the second gate pitch. A semiconductor structure in which the bottom surface of each of the second placeholders is lower than the bottom surface of each of the first placeholders.

16. The semiconductor structure according to claim 15, wherein the uppermost surface of each of the second placeholders is substantially coplanar with the uppermost surface of each of the first placeholders.

17. Each of the first placeholders has at least a first portion that is substantially coplanar with the uppermost surface of the back dielectric layer, and each of the first placeholders has at least a second portion that extends above the uppermost surface of the back dielectric layer. The semiconductor structure according to claim 15, wherein at least a first portion of each of the second placeholders is substantially coplanar with the uppermost surface of the back dielectric layer, and at least a second portion of each of the second placeholders extends above the uppermost surface of the back dielectric layer.

18. The first array of nanosheet transistors further has a first source-drain region, and the interface between each of the first placeholders and each of the first source-drain regions is curved. The semiconductor structure according to claim 15, wherein the second array of nanosheet transistors further has a second source-drain region, and the interface between each of the second placeholders and each of the second source-drain regions is curved.

19. Each of the uppermost surfaces of the first back-surface source-drain contacts has a profile substantially similar to that of each of the uppermost surfaces of the first placeholder. The semiconductor structure according to claim 15, wherein the uppermost surface of each of the second back-surface source-drain contacts has a profile substantially similar to that of the uppermost surface of each of the second placeholders.

20. Each of the first back-surface source-drain contacts has at least a first portion that is substantially coplanar with the uppermost surface of the back-surface dielectric layer, and each of the first back-surface source-drain contacts has at least a second portion that extends above the uppermost surface of the back-surface dielectric layer. The semiconductor structure according to claim 15, wherein at least a first portion of each of the second back surface source-drain contacts is substantially coplanar with the uppermost surface of the back surface dielectric layer, and at least a second portion of each of the second back surface source-drain contacts extends above the uppermost surface of the back surface dielectric layer.

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