Multiple gate dielectrics for monolithic stacked devices
The semiconductor structure with stacked devices and varied gate dielectrics addresses performance and reliability challenges by optimizing dielectric layers for each device type, improving circuit performance and reliability in high-performance computing.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- INTERNATIONAL BUSINESS MACHINE CORPORATION
- Filing Date
- 2024-06-12
- Publication Date
- 2026-07-07
AI Technical Summary
Existing semiconductor technologies face challenges in providing different gate dielectrics for various functional devices like thin oxide devices, thicker oxide devices, SRAMs, high-Vt devices, and low-Vt devices, which are crucial for performance and reliability, especially in high-performance computing for servers, due to impracticality in correcting reliability issues from scratch.
A semiconductor structure with multiple stacked devices featuring different gate dielectrics, including interfacial and high-dielectric-constant layers, optimized for each device type to address performance and reliability requirements, utilizing nanosheet transistors with varying thicknesses and compositions to enhance breakdown voltage and stability.
The solution improves device performance and reliability by optimizing gate stack dielectrics, balancing thickness and composition to meet specific functional needs, enhancing circuit performance and reliability across different device types.
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