Triggering the execution of alternative functions

Abstract

A device (10, 30, 50) comprising a processing circuit (51) that executes instructions and threadlet execution circuits (23, 49, 52) that execute tasks under the control of the processing circuit. The threadlet execution circuits are configured to operate asynchronously with respect to the processing circuit. The threadlet execution circuit starts the execution of a threadlet containing at least one delegated task in response to a start command issued by the processing circuit. In response to a threadlet start instruction, which indicates a request to issue a start command to the threadlet execution circuit, the processing circuit determines, depending on at least one parameter, whether to trigger the execution of an alternative function by the processing circuit instead of issuing a start command to the threadlet execution circuit.

Description

Technical Field

[0001] This technique relates to the field of data processing.

Background Art

[0002] In a data processing system, a processing circuit can be configured to execute various different types of instructions. However, it has been confirmed that using custom hardware or dedicated hardware to execute specific processing tasks can be more efficient than executing those tasks using a processing circuit. For example, a processing circuit can pass a specific type of processing task to a dedicated accelerator, and the dedicated accelerator may be able to execute those tasks more efficiently and / or more quickly.

[0003] However, adding a dedicated circuit such as an accelerator increases the hardware cost for implementing a data processing device, which may be difficult to justify in some situations due to the pressure on the silicon area on the chip. Furthermore, an accelerator can significantly increase the complexity of the device and may consume a significant amount of power.

Summary of the Invention

[0004] Viewed from a first embodiment of this technique, an apparatus comprising a processing circuit that executes instructions, and a threadlet execution circuit that executes tasks under the control of the processing circuit and is configured to operate asynchronously with respect to the processing circuit, the threadlet execution circuit starts the execution of a threadlet including at least one delegated task in response to a start command issued by the processing circuit, and A device is provided in which a processing circuit, in response to a threadlet start instruction, which indicates a request to issue a start command to a threadlet execution circuit, determines, depending on at least one parameter, whether to trigger the execution of an alternative function by the processing circuit instead of issuing a start command to the threadlet execution circuit.

[0005] In another embodiment of this technique, a computer program is provided that includes computer-readable code for manufacturing the aforementioned apparatus. In some embodiments, the computer program may be provided on a computer-readable storage medium that may be temporary or non-temporary.

[0006] Another embodiment of this technique is a method for controlling a threadlet execution circuit to perform a task, and this method is Controlling a threadlet execution circuit, which is configured to operate asynchronously with respect to the processing circuit, to execute a task using a processing circuit. Using a processing circuit, issue a start command to the threadlet execution circuit, causing the threadlet execution circuit to start executing a threadlet containing at least one delegated task, A method is provided which includes a threadlet start instruction, the threadlet start instruction indicating a request to issue a start command to a threadlet execution circuit, and in response to the threadlet start instruction, a processing circuit determines, depending on at least one parameter, whether to trigger the execution of an alternative function by the processing circuit instead of issuing a start command to the threadlet execution circuit.

[0007] Another embodiment of this technique includes a computer program that, when executed by a host data processing device, includes instructions to control the host data processing device to provide an instruction execution environment for executing target program code, wherein the computer program The processing program logic that executes the instructions, A threadlet executable program logic for executing a task under the control of a processing program logic, wherein the threadlet executable program logic is configured to operate asynchronously with respect to the processing program logic, The threadlet execution program logic, in response to a start command issued by the processing program logic, starts the execution of a threadlet that includes at least one delegated task, and A computer program is provided in which processing program logic determines, in response to a threadlet start instruction, which indicates a request to issue a start command to the threadlet execution program logic, whether to trigger the execution of an alternative function by the processing program logic instead of issuing a start command to the threadlet execution program logic, depending on at least one parameter.

[0008] In some embodiments, computer programs may be provided on computer-readable storage media that may be temporary or non-temporary. [Brief explanation of the drawing]

[0009] Further aspects, features, and advantages of this technique will become apparent from the following example description, which should be read in conjunction with the attached drawings. [Figure 1] This paper provides a schematic example of a data processing device that can embody various embodiments of this technique. [Figure 2] This paper provides a schematic example of a data processing device that can embody various embodiments of this technique. [Figure 3] This paper provides a schematic example of a data processing device that can embody various embodiments of this technique. [Figure 4] This is a state diagram illustrating an exemplary set of states, and the extended processing circuit of this technique can transition between these states. [Figure 5]An example of a sequence of code that can be executed according to an embodiment of this technique is illustrated below. [Figure 6] This paper provides a schematic example of a data processing device that can embody various embodiments of this technique. [Figure 7] An example of an AFR setting instruction will be provided. [Figure 8] This flowchart illustrates an example of how to execute a non-blocking threadlet start instruction. [Figure 9] This flowchart illustrates a typical direction for monitoring the execution of instructions by a processing circuit. [Figure 10] This flowchart illustrates an example of how to execute an AFR setting command. [Figure 11] This section provides a general overview of possible simulator implementations. [Modes for carrying out the invention]

[0010] Before considering exemplary implementation configurations with reference to the attached drawings, the following description of exemplary implementation configurations and their associated advantages is provided.

[0011] An embodiment of this technique utilizes a threadlet execution circuit provided in addition to the processing circuit, which can execute specific tasks (e.g., tasks involving data processing operations) under the control of the processing circuit. The threadlet execution circuit operates asynchronously with respect to the processing circuit; for example, it does not operate in a lockstep manner with the processing circuit, meaning that the processing circuit can continue to execute instructions in parallel with the operation of the threadlet execution circuit.

[0012] The processing circuit controls the operation of the threadlet execution circuit to the extent that it can issue a start command to the threadlet execution circuit, causing the threadlet execution circuit to start executing a threadlet containing one or more delegated tasks (e.g., tasks delegated by the processing circuit). In particular, the processing circuit can send a start command to the threadlet execution circuit by executing a threadlet start instruction (also referred to herein as the "XSTART" or "XSTARTS" instruction).

[0013] This technique also considers what happens when the threadlet execution circuit is unavailable at the time the start command is issued. In particular, the inventors of this technique considered the challenge of ensuring that the software does not encounter friction in scenarios where the use of threadlets is desirable, but the persistent availability of the threadlet execution circuit cannot be guaranteed.

[0014] To address this challenge, this technique implements a form of threadlet start instruction that can trigger the execution of an alternative function by a processing circuit (for example, a function whose execution produces a result equivalent to (or at least similar to) the execution of a threadlet by the threadlet execution circuit) if the threadlet execution circuit is determined to be unavailable and / or unsuitable for executing a threadlet. In particular, the processing circuit of this technique is a threadlet start instruction in which the threadlet start instruction indicates a request to issue a start command to the threadlet execution circuit, and in response to the threadlet start instruction, determines, depending on at least one parameter, whether to trigger the execution of an alternative function by the processing circuit instead of issuing a start command to the threadlet execution circuit.

[0015] In this way, the alternative function provides a fallback path that the processing circuit can follow when it is not possible or appropriate to send a start command to the threadlet execution circuit. This avoids the need for the processing circuit to stall execution or trigger an error response when the threadlet execution circuit is unavailable and / or inappropriate, and reduces software thrashing in such scenarios.

[0016] In some embodiments, the processing circuit responds to a determination to issue a start command to the threadlet execution circuit to trigger execution of an alternative function instead of branching execution to the identified instruction.

[0017] For example, the identified instruction can be set to identify the start of the alternative function described above. Thus, this embodiment allows execution to branch to the alternative function when execution by the threadlet execution circuit is not appropriate for a given threadlet. The branch can be triggered by a branch instruction following the threadlet start instruction in some embodiments. The branch instruction can be inserted into the machine code by a compiler, for example, in response to detecting the presence of the threadlet start instruction. The branch instruction can be a linked branch instruction in certain embodiments, and in response thereto, a return address is stored (e.g., in a register such as a link register) so that when execution of the alternative function is complete, execution can return to the point immediately following the threadlet start instruction.

[0018] There are many ways in which the identified instruction can be identified. For example, the identified instruction can be directly identified in the threadlet start instruction (e.g., recording the offset of the first instruction in the alternative function in a field of the branch instruction or the threadlet start instruction).

[0019] However, in some embodiments, an alternative-function register (AFR) is provided, and the processing circuitry responds by deciding to trigger the execution of an alternative function instead of issuing a start command to the threadlet execution circuitry to branch execution to an instruction identified by the address indicated in the AFR.

[0020] The AFR (also referred to herein as the AFR1 register) can take several forms. In some embodiments, the AFR includes either a general-purpose register associated with the processing circuit or a dedicated register associated with the threadlet execution circuit.

[0021] For example, AFR can be one of the general-purpose registers in the register file of a processing circuit, and this register can be identified by the threadlet start (XSTARTS) instruction. For example, the threadlet start instruction can take the following form: XSTARTS<other arguments>, x4 Here, x4 is a general-purpose register in the register file.

[0022] Alternatively, a general-purpose register can be identified in a branch instruction following a threadlet start instruction. For example, the branch instruction may follow immediately after the threadlet start instruction, the two instructions may be merged or fused at the front end, and the branch instruction may be edited to identify the register.

[0023] Alternatively, a dedicated AFR can be provided in association with the threadlet execution circuit. In this case, the AFR does not necessarily need to be identified in the threadlet start instruction, as execution may implicitly branch to an address stored in the AFR as a fallback option. Note that there may be two or more AFRs associated with the threadlet execution circuit, for example, an AFR for each function supported by the threadlet execution circuit. In such cases, it may be beneficial to identify the AFR in the threadlet start instruction. In this embodiment, the AFR provides dedicated hardware support for this technique by providing a dedicated storage location for information identifying alternative functions.

[0024] In some embodiments, the processing circuit, in response to the AFR setting instruction, stores the address pointer specified by the AFR setting instruction in the AFR.

[0025] According to this embodiment, architectural support is provided for a new instruction, namely the AFR setting instruction. The AFR setting instruction can be used to set up an AFR to identify an alternative routine to be used when the threadlet execution circuit is unavailable or unsuitable, avoiding the need to set a specific branch target for the threadlet start instruction, which saves coding space in the threadlet start instruction.

[0026] In some embodiments, the processing circuit, in response to an AFR setting command, records a predetermined value in the AFR's valid field, where the predetermined value indicates that the AFR holds an index of the valid address.

[0027] In this embodiment, the AFR setting instruction is further configured to trigger the setting of the "Valid" field within the AFR. This indicates whether the AFR represents a valid address value and thus reduces the risk of execution branching to an unsafe or otherwise incorrect location.

[0028] In some embodiments, the processing circuit, in response to determining to trigger the execution of an alternative function instead of issuing a start command to the threadlet execution circuit, determines whether the valid field of the AFR holds a predetermined value indicating that the AFR holds a valid index of an address, and in response to determining that the predetermined value does not exist in the valid field of the AFR, initiates an error response.

[0029] Therefore, in this embodiment, the processing circuit branches to the identified location within the AFR only if the valid field (which can be, for example, a single bit) is set to indicate that the address information stored therein is valid. This prevents the code from branching to an incorrect location.

[0030] There are many possible reasons why a threadlet execution circuit may be either unavailable or unsuitable for executing a given threadlet, and at least one of the parameters mentioned above can be set in one of several ways to address these reasons.

[0031] In some embodiments, the processing circuit is configured to determine, as at least one parameter, whether to trigger the execution of an alternative function instead of issuing a start command to the threadlet execution circuit, depending on whether the execution of a previous threadlet by the threadlet execution circuit is in progress.

[0032] For example, a threadlet execution circuit may only be able to execute a given number of threadlets at a time (for instance, a threadlet execution circuit may only be able to execute one threadlet at a time), and in this case, the threadlet execution circuit may not be able to start executing a new threadlet while the previous threadlet is still running. Therefore, it can be useful to set at least one parameter depending on whether the execution of a preceding threadlet is still in progress.

[0033] In some embodiments, the processing circuit, in response to determining that the execution of a previous threadlet by the threadlet execution circuit is in progress, triggers the execution of an alternative function instead of issuing a start command to the threadlet execution circuit.

[0034] Therefore, by setting at least one parameter depending on whether the previous threadlet is being executed, the processing circuit can trigger the execution of an alternative function when the threadlet execution circuit is unavailable for this reason.

[0035] In some embodiments, the threadlet execution circuit is configured to set an abort indicator in response to the completion of the execution of the previous threadlet, and the processing circuit is configured to determine whether the threadlet execution circuit has completed the execution of the previous threadlet, depending on whether the abort indicator has been set.

[0036] For example, the abort indicator can be a signal asserted by the threadlet execution circuit when the execution of a threadlet is complete, or a flag set by the threadlet execution circuit (e.g., in a control register or other storage location) when the execution of a threadlet is complete. Then, at least one parameter may be set depending on whether the abort indicator has been set, enabling the processing circuit to determine whether the execution of the previous threadlet has completed.

[0037] In some embodiments, the processing circuit is configured to determine, as at least one parameter, whether to trigger the execution of an alternative function instead of issuing a start command to the threadlet execution circuit, depending on one or more power and / or thermal requirements.

[0038] Another reason for executing an alternative function instead of issuing a start command to the threadlet execution circuit is that the use of the threadlet execution circuit may be constrained or prohibited by the current power and / or thermal requirements set for the device. For example, since the threadlet execution circuit operates in parallel with the processing circuit (e.g., the threadlet execution circuit and the processing circuit are not synchronized), this can mean that overall power consumption is likely to increase if processing tasks are offloaded to the threadlet execution circuit, at least while a threadlet is running. This can increase the amount of heat generated by the device during that time. Therefore, the current power profile and / or thermal profile set for the device (which may set limits on the power consumption and / or heat generation allowed for the device during a given period) may constrain or prohibit the use of the threadlet execution circuit. Thus, in these cases, the processing circuit may determine not to issue a start command, even if the threadlet execution circuit is currently available and suitable for running a threadlet.

[0039] Therefore, the ability to branch to an alternative function instead can allow processing to continue while still meeting the system's power and thermal requirements.

[0040] In some embodiments, the processing circuit is configured to determine, as at least one parameter, whether to trigger the execution of an alternative function instead of issuing a start command to the threadlet execution circuit, depending on whether at least one delegated task is supported by the threadlet execution circuit.

[0041] A threadlet execution circuit may only support specific types of tasks. In this embodiment, the processing circuit can be configured to determine if a threadlet includes a task involving data processing operations not supported by the threadlet execution circuit, and instead trigger the execution of an alternative function. In this way, the programmer does not need to know which tasks are supported by the threadlet execution circuit at the time of code generation, and the processing circuit does not need to stall or trigger an error response if a threadlet start instruction is executed that relates to a threadlet containing a task not supported by the threadlet execution circuit.

[0042] In some embodiments, the processing circuit is configured to determine, as at least one parameter, whether to trigger the execution of an alternative function instead of issuing a start command to the threadlet execution circuit, depending on whether the granularity of the threadlet satisfies a threshold granularity defined for the threadlet execution circuit.

[0043] Granularity relates to the size or magnitude of the tasks delegated to the threadlet execution circuit. In some embodiments, this is synonymous with the "time" it takes to execute a task, such as measured by the number of clock cycles. Fine granularity in this context means that each offloaded task takes only a few cycles (e.g., a few hundred cycles, while higher granularity may mean thousands of cycles or more).

[0044] There is a relationship between granularity and inference (for example, inference from the CPU's perspective). For instance, encountering relatively costly overheads such as inference barriers or inference misses can result in low threadlet granularity, and these overheads may outweigh any benefits of delegating tasks to threadlet execution circuits. Furthermore, if threadlet execution circuits lack significant inference depth, this can lead to stalls that reduce efficiency.

[0045] These overheads can vary at runtime, and therefore, in some embodiments, a mechanism may exist to determine whether or not it is beneficial to invoke a threadlet. Thus, in this embodiment of the technique, the processing circuit may, in some cases, decide to trigger the execution of an alternative function instead of invoking a threadlet, based on a profitability / cost evaluation.

[0046] In some embodiments, the threadlet execution circuit sets an abort indicator in response to the completion of the execution of an alternative function.

[0047] This can be advantageous because it allows the processing circuit to then respond as if the threadlet execution circuit had just completed the execution of the threadlet. Depending on the contents of the alternative function, this can help ensure that the result of the execution of the alternative function appears to the software as functionally identical to the execution of the threadlet. In certain embodiments, the threadlet execution circuit may have a dedicated set of registers for storing operands and results for data processing operations performed as part of a delegated task. This may be set up by a start command, and an abort indicator may trigger the threadlet execution circuit to buffer the contents of the threadlet execution circuit's registers (e.g., the results of the data processing operations) presented to the data processing circuit.

[0048] In some embodiments, the device includes an alternative function return register for holding an index of a return instruction address, the threadlet execution circuit is configured to monitor the execution of an instruction by the processing circuit and determine, based on the return instruction address, whether the processing circuit has executed the corresponding return instruction, and the threadlet execution circuit sets an abort index in response to the determination that the processing circuit has executed the corresponding return instruction.

[0049] Typically, a function may terminate with a return instruction that indicates that processing returns to a specific point. For example, a return address indicating the point to which processing should return after the execution of a function is complete may be indicated in a register (e.g., a link register), and therefore, the execution of a return instruction may trigger the execution of an instruction identified by the return address. For example, a return address may be stored in a link register in response to the execution of a "branch with link" instruction. In this embodiment, the threadlet execution circuit uses the execution of a return instruction to determine when the execution of the alternative function is complete, and therefore when to set the abort indicator. To enable the threadlet execution circuit to identify that a return instruction has been executed, the device in this embodiment includes an alternative function return register that holds an address indicator corresponding to the function's return address. The threadlet execution circuit can then monitor the operation of the processing circuit and compare the address of the committed instruction with the address stored in the alternative function return register. This allows the threadlet execution circuit to observe when the execution of the alternative function is complete, and if this is observed to have happened, it can set the abort indicator.

[0050] In some embodiments, the device includes an Alternate Function Register (AFR), and in response to the processing circuit determining to trigger the execution of an alternate function instead of issuing a start command to the threadlet execution circuit, the processing circuit branches execution to an instruction identified by the address indicated in the AFR, and in response to an AFR setting instruction, the processing circuit stores the address pointer specified by the AFR setting instruction in the AFR and stores the return instruction address pointer specified by the AFR setting instruction in the Alternate Function Return Register.

[0051] Therefore, in this embodiment, the AFR setting instruction described above can be used to set up both the AFR and the alternate function return register.

[0052] The concepts described herein may be embodied in computer-readable code for the fabrication of devices that embody the described concepts. For example, the computer-readable code can be used in one or more stages of a semiconductor design and fabrication process, including an electronic design automation (EDA) stage, to fabricate an integrated circuit comprising a device that embodies the concepts. The computer-readable code described herein may additionally or alternatively enable the definition, modeling, simulation, verification, and / or testing of devices that embody the concepts described herein.

[0053] For example, computer-readable code for fabricating a device embodying a concept described herein may be embodyed by code that defines a hardware description language (HDL) representation of the concept. For example, the code may define register-transfer-level (RTL) abstractions of one or more logic circuits for defining a device embodying a concept. The code may define HDL representations of one or more logic circuits embodying the device in Verilog, SystemVerilog, Chisel, or VHDL (Very High-Speed ​​Integrated Circuit Hardware Description Language), as well as intermediate representations such as FIRRTL. The computer-readable code may provide definitions that embody the concept using system-level modeling languages ​​such as SystemC and SystemVerilog, or other behavioral representations of the concept that may be interpreted by a computer to enable simulation, functional and / or formal verification, and testing of the concept.

[0054] Additionally or alternatively, computer-readable code may embody computer-readable representations of one or more netlists. These netlists may be generated by applying one or more logic synthesis processes to the RTL representations. Alternatively or additionally, one or more logic synthesis processes may generate bitstreams from the computer-readable code that are loaded into a field-programmable gate array (FPGA) to embody the described concepts. The FPGA may be deployed for verification and testing purposes before being fabricated in an integrated circuit, or the FPGA may be deployed directly in a product.

[0055] Computer-readable code may include a mixture of code representations for the fabrication of a device, for example, a mixture of one or more RTL representations, netlist representations, or other computer-readable definitions used in semiconductor design and fabrication processes for fabricating a device embodying the present invention. Alternatively or additionally, the concept may be defined as a combination of computer-readable definitions used in semiconductor design and fabrication processes for fabricating a device and computer-readable code that defines instructions to be executed by the device once it is fabricated.

[0056] Such computer-readable code may be placed on any known temporary computer-readable medium (such as wired or wireless transmission of code over a network) or on a non-temporary computer-readable medium such as a semiconductor, magnetic disk, or optical disk. An integrated circuit fabricated using computer-readable code may include components such as a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or one or more other components that individually or collectively embody a concept.

[0057] The above-described technology can be implemented in hardware devices having a processing circuit, a threadlet execution circuit, and optionally circuit hardware that implements other hardware features described above (e.g., alternative function registers (AFRs) and alternative function return registers), which support the threadlet start instruction (and optionally the AFR setting instruction) as part of the native instruction set architecture supported by the decoding circuit and the processing circuit.

[0058] However, in another embodiment, the same technique may be implemented in a computer program (e.g., an architecture simulator or model) provided to control a host data processing device to provide an instruction execution environment for executing instructions from target code. The computer program may include processing program logic that emulates the processing circuit described above, and threadlet execution program logic that emulates the threadlet execution circuit described above. The processing program logic includes support for threadlet start instructions having the same functionality as described above for hardware embodiments. Thus, such a simulator computer program can present an instruction execution environment for target code executed on the simulator computer program that is similar to the instruction execution environment that would be provided by an actual hardware device capable of directly executing the target instruction set, even if no actual hardware providing these functions exists on the host computer running the simulator program. This can be useful for executing code written for one instruction set architecture on a host platform that does not actually support that architecture. The simulator can also be useful during the development of software for a new version of an instruction set architecture while software development is being carried out in parallel with the development of hardware devices that support the new architecture. This allows software to be developed and tested on the simulator so that software development can begin before hardware devices supporting the new architecture become available.

[0059] In some embodiments, the program may also include instruction decoding program logic for decoding instructions in the target code in order to control the host data processing device to perform data processing. Thus, the instruction decoding program logic emulates the functionality of the instruction decoder of the hardware device as described above. The instruction decoding program logic may include support for the threadlet start instruction and, optionally, the AFR setting instruction described above. Other instructions described herein may also be supported by the instruction decoding program logic and the processing program logic. In some embodiments, the program may also include register maintenance program logic for maintaining data structures (in the host device's memory or in the architecture registers) that represent (emulate) the architecture registers of the instruction set architecture being simulated by the program. The emulated registers may include any of the registers described in some embodiments above, including the Alternate Function Registers (AFRs) and Alternate Function Return Registers described above.

[0060] The simulator codes described herein may be stored in a computer-readable medium that may be temporary or non-temporary.

[0061] Here, a specific embodiment will be described with reference to the drawings.

[0062] Figure 1 schematically illustrates a data processing device 10 according to several embodiments. The data processing device 10 is schematically shown to have a pipeline configuration, and for brevity and clarity, it is shown here in conceptual form. The illustrated pipeline stages include an instruction cache 11, a fetch stage 12, a decode stage 13, a microoperation cache 14, an issue stage 15, and a register access stage 16. A sequence of instructions is retrieved from memory (not shown) and cached in the instruction cache 11. The fetch stage 12 controls which instructions are retrieved as a sequence of instructions, and these instructions are then decoded in the decode stage 13. This decoding essentially identifies the type of each instruction, as well as any further operands specified by the instruction, and generates control signals to control the rest of the device to perform the data processing operations defined by the instruction. Decoding an instruction may also involve dividing the instruction into one or more microoperations, which can be cached in the microoperation cache 14. The final stage of the pipeline before execution is the issue stage 15, where instructions (or microoperations) are queued, with the availability of the register values ​​they specify as operands and the corresponding functional units in the data processing pipeline that perform the defined operations reserved. Generally, the data processing operations defined by instructions are executed by functional units that form part of the data processing pipeline, namely the load / store unit 17, the execution unit 18, and the execution unit 19. These latter execution units may be, for example, an arithmetic logic unit (ALU) or a floating-point unit (FPU). The functional units that form part of the data processing pipeline perform the data processing operations of the functional units on data values ​​provided from a set of registers (conceptually represented by the register access stage 16 in the figure), and the resulting values ​​of the data processing operations of the functional units are returned to the set of registers.The load / store unit 17 is provided for the purpose of storing values ​​from a set of registers into the memory system, and only the level 1 cache 21 and level 2 cache 22 of the memory system are shown in the figure. The L1 cache 21 is dedicated to the data processing unit 10, while the L2 cache 22 may be shared with another data processing unit when it is part of a broader data processing system. The data processing unit 10 is also shown to include a branching unit 20, which monitors the execution flow of a sequence of instructions and attempts to predict whether or not a given branch will occur based on the previous execution history. The prediction from the branching unit 20 informs the sequence of instructions to be fetched by the fetch stage 12.

[0063] The data processing device 10 further comprises an extension processing circuit 23, which is influential on the data processing operations performed by the data processing device 10 and is provided to support the efficient implementation of one or more defined functions established to be available from anywhere. “Extension processing circuit” is another name for “threadlet execution circuit.” Exemplary functions of this type are known to include tasks or functions such as memcpy, memset, compression, encryption, and string processing, but the technique is not limited to these specific embodiments. The extension processing circuit is closely associated with the data processing pipeline and is configured to implement a defined function (also referred to herein as a delegated task) in response to a delegation signal received from the data processing pipeline. “Delegation signal” is another name for the “start signal” described above. The extension processing circuit 23 is an example of a threadlet extension (TE) by the technique. The sequence of operations that the extension processing circuit 23 performs to implement a defined function is referred to herein as a threadlet. The extension processing circuit 23 is closely associated with the data processing pipeline, but is configured to perform delegated tasks asynchronously with respect to the data processing operations performed by the data processing pipeline. The data processing pipeline may also be referred to herein as the CPU. A threadlet is a set of functions or operations that, once invoked, can be executed asynchronously with respect to other CPU activity. Instructions or commands sent to the extension processing circuit 23 to initiate delegated tasks are generated in response to extension start instructions (also referred to herein as threadlet start instructions), which are defined for this purpose in the set of instructions of the data processing pipeline. Thus, extension start instructions proceed along the data processing pipeline like any other CPU instruction, but once the decoding circuit 13 identifies an extension start instruction, it can signal directly to the extension processing circuit 23.The close integration of the extended processing circuit 23 and the data processing pipeline is illustrated by the fact that the extended processing circuit 23 can directly access the load / store unit 17 and thus share the path to memory for the data processing pipeline. The extended processing circuit 23 can also access a set of registers 16, thereby allowing, for example, an extended start instruction to specify one or more registers as operands, and the values ​​from these registers are then passed directly to the extended processing circuit 23 in connection with the command sent to start the delegated task. Once the task is complete, the result of the delegated task can be returned to the register values ​​via an extended synchronization instruction.

[0064] Figure 2 schematically illustrates a data processing device 30 according to several embodiments. Note that the arrangement of the components of the data processing device 30 is similar to that of the data processing device 10 shown in Figure 1. One difference is that the data processing device 10 in Figure 1 is intended to represent an in-order processor, while the data processing device 30 is an out-of-order processor. As a result, the data processing pipeline of the data processing device 30 includes a rename stage 35, which allows the data processing device 30 to change the order in which it executes instructions in an instruction sequence, so that the instructions in the instruction sequence can be executed in an order determined not by the order in which they appear in the sequence, but by when their operands become available and the availability of functional units. The illustrated pipeline stages include an instruction cache 31, a fetch stage 32, a decode stage 33, a microoperation cache 34, a rename stage 35, an issue stage 36, and a register access stage 37. The instruction sequence is retrieved from memory (not shown) and cached in the instruction cache 31. Instructions pass through the data processing pipeline in the manner described above, referring to the data processing device 10 in Figure 1, and further register renaming is performed by the rename stage 35. The functional units of the data processing pipeline in this embodiment are the load unit 38, the store unit 39, the FPU 41, the integer ALU 42, and the vector unit 43. Since the processing capabilities of the FPU 41, the integer ALU 42, and the vector unit 43 are sufficient, a result cache 44 is provided as an intermediary before the results of their data processing are returned to the register 37. A branch prediction unit 45 is also provided, and its predictions inform the operation of the fetch stage 32.

[0065] The data processing unit 30 further comprises an extension processing circuit ("threadlet extension" or "threadlet execution circuit") 49, which is provided to support the efficient execution of one or more defined functions, these functions influencing the data processing operations performed by the data processing unit 30 and established to be accessible from anywhere. The extension processing circuit 49 is closely associated with the data processing pipeline and is configured to execute the defined functions in response to a delegation signal ("start signal") received from the data processing pipeline. In the embodiment of Figure 2, this delegation signal is shown to originate from the issue queue stage 36. In particular, this issue queue stage 36 is located after the rename stage 35, thereby enabling the extension processing circuit 49 to operate with respect to the physical registers of the set of registers 37 according to the same mapping of architectural registers used for the rest of the device. As in the embodiment of Figure 1, the data processing pipeline (from the instruction cache 31 to the register read stage 37, load / store units 38 and 39, and function units 41-45) may also be referred to as the CPU. The threadlet extension 49, once activated, operates asynchronously with respect to other CPU activity. Instructions or commands sent to the extension processing circuit 49 to start a delegated task are generated in response to an extension start instruction defined for this purpose in the instruction set of the data processing pipeline. The close integration of the extension processing circuit 49 and the data processing pipeline is evident in this embodiment as well, by the fact that the extension processing circuit 49 can directly access the load unit 38 and the store buffer 40, and thus share the path to memory of the data processing pipeline. The extension processing circuit 49 can also access a set of registers 37, thereby, for example, an extension start instruction can specify one or more registers as operands, and the values ​​from these registers are then passed directly to the extension processing circuit 49 in relation to the command sent to start the delegated task. Note that the output of the branch prediction unit 45 is also supplied to the extension processing circuit 49.Once the task is complete, the result of the delegated task can be returned to a register value via an extended synchronization instruction.

[0066] Figure 3 schematically illustrates a data processing device 50 in several embodiments. This embodiment provides a comparison with the embodiments in Figures 1 and 2, in which the extension processing circuits were so closely integrated into the data processing pipeline that their instances could be considered to reside within the CPU. In the exemplary device 50 of Figure 3, the CPU 51 and the extension processing circuit (threadlet extension) 52 are not so closely integrated. This is illustrated, for example, by the fact that each of the CPU 51 and the threadlet extension 52 has its own path to memory, the L1 cache 53 is dedicated to the CPU 51, and the L1 cache 54 is dedicated to the threadlet extension 52. The L1 caches 53 and 54 share the L2 cache 55. Nevertheless, the threadlet extension 52 remains tightly coupled to the CPU 51 and can be quickly invoked when it encounters an extension start instruction in the CPU pipeline that specifies the function to be performed by the threadlet extension 52. The threadlet extension 52 can obtain data directly from CPU registers at the start of its execution. Once completed, the threadlet extension 52 can return a value via an extended synchronization instruction. Figure 3 also shows the threadlet extension 52 having its own dedicated TLB 56, which the threadlet extension 52 can cache the currently used address translation within the dedicated TLB 56. As a preparatory step prior to or associated with the delegation signal, the contents of the TLB 57 in the CPU 51 can be copied to the dedicated TLB 56 to prewarm this cache before the threadlet starts operating.

[0067] Figure 4 is a state diagram illustrating an exemplary set of states to which an extended processing circuit (TE) transitions in several embodiments. Initially, the TE is in the idle state 60. When the data processing pipeline encounters an extended start (XSTART) instruction (threadlet start instruction), the delegate signal (start signal) can cause the TE to switch to the setup state 61. This may also require the assertion of a signal indicating that the XSTART instruction has been committed. In the setup state 61, certain actions necessary to prepare the TE can be performed. For example, in embodiments where the TE has a separate path to memory (as in Figure 3), one setup task is to transfer the relevant entries currently in the CPU's TLB to a dedicated TLB in the TE. This allows the TE to perform translations independently at a faster speed than if it were entirely dependent on the existing translation mechanism in the CPU. If the TE was in a clock-gate or power-gate state while in the idle state 60, the setup state 61 may include a task to terminate the TE from that clock-gate or power-gate state. Once the setup state 61 is complete, the TE can switch to the running state 62. If the TE encounters a memory failure during its processing, the TE asserts a signal that generates an interrupt in the CPU, causing the CPU to stop execution of the main thread and switch to the handler. The TE switches to interrupt state 63. An indicator of the cause of the failure is stored in a special syndrome system register, the address associated with the failure is stored in the failure address system register, and a bit in the Program Status Register (PSR) is set, enabling the handler to quickly determine the cause of the failure. Setting the bit in the PSR simplifies communication of restarting the threadlet because the handler can reset the corresponding bit in the SPSR, and when the CPSR is restored from the SPSR during an exception return, the TE can detect this bit reset and resume execution. The TE also switches to interrupt state 63 if the main thread is replaced, for example, during a context switch initiated by the operating system.In interrupt state 63, the TE may be clock-gated or power-gated unless some other thread invokes a new command targeting it, the associated thread resumes execution, or the handler returns. The TE returns from interrupt state 63 to running state 62 via reload state 64, in which reload state 64 can restore any context or state related to its execution that was previously stored in memory. This may be the case if another thread uses the previously interrupted TE. Finally, when the extension reaches the end of the offloaded granule (delegated task) of computation, it moves to idle state 60. The TE signals the completion of its task, thereby allowing the Extended Synchronization Instruction (XSYNC) to capture its “completion” signal (also referred herein as the “abort” signal or “abort indicator”) and, if necessary, provide a return value to the specified register. If the TE has any residual data in its dedicated cache, these entries may need to be flushed upon completion.

[0068] This section describes an example of using threadlets. The programmer or compiler identifies a function whose execution on custom hardware (extension processing circuitry) satisfies the cost-benefit threshold in those use cases. The command is invoked within the specified CPU extension using an instruction (such as XSTART). A pseudocode example of its use (for such an identified function "funcX") is as follows:

[0069] [Table 1]

[0070] Therefore, within function funcA, the XSTART instruction initializes the CPU extension and transfers the parameters (a, b, c, d) of funcX, located in registers x0, x1, x2, and x3 respectively, to the extension processing circuit. In this embodiment, the XSTART instruction also specifies an immediate value #imm_op that defines the specific function to be executed. For example, there may be only one instance of the extension processing circuit, but this instance may be capable of performing two or more functions, or at least two or more variations of a function, and the immediate value #imm_op can select the desired variation and / or function. In other embodiments, there may be two or more instances of the extension processing circuit, and the immediate value #imm_op can select among them. Depending on the setup, the extension may also automatically obtain a copy of the relevant entry in the TLB. The extension processing circuit then executes the required task (funcX), during which the CPU is free to continue executing other instructions I1, I2, I3, I4, etc. At some point in the future, the CPU executes an extension synchronization instruction (XSYNC) to automatically check whether the extension has completed or not. If not completed, for some variations of the extended synchronization instruction, the CPU waits for the delegated task to complete. Other variations of the extended synchronization instruction (e.g., the XSYNCS variation) allow the CPU to continue executing other code (if there is an alternative routine available) or to stop execution and wait for the extension to complete (typically if there is nothing else to execute in the meantime).

[0071] For example, the three potential variations of the XSYNC instruction can be as follows: 1. XSYNC{x0-x7},#imm This instruction checks whether the TE specified by the immediate field (#imm) has completed execution. If it has, the instruction returns the result in the specified list of registers (x0-x7). A variation of this instruction does not commit if the extension has not completed execution, and effectively stalls until the extension completes and can return a result. 2. XSYNCS{x0-x7},#imm This is a non-blocking variation of the aforementioned XSYNC, which sets one or more flag bits that allow subsequent code to continue execution (for example, by performing some alternative calculation while waiting, perhaps by using a branch instruction that is highly sensitive to the relevant flag bits). 3. XSYNCS{x1-x8},x0 This variation is similar to other XSYNCS variations, but uses register (x0) to check for the completion of the specified TE.

[0072] The XSTART instruction also has several variations, including the following: 4. XSTART{x0-x7},#imm The start command and a variable number of registers (x0-x7) are sent to the TE. These registers contain parameters for configuring the TE to execute the threadlet. Immediate fields are used to identify which TE to activate (if multiple TEs are implemented) and which operation to perform (if multiple types of operation are possible). Variations of this instruction do not commit until the extension can accept the start command, so if the task is already running or execution is unavailable for any other reason, the extension will effectively stall. 5. XSTARTS{x0-x7},#imm Similar to XSTART, but non-blocking. This means that if TE is unavailable, one or more flag bits are set to indicate its status, allowing subsequent code to continue execution, for example, by executing an alternative function as described above. 6. XSTART x0,{x0-x7},#imm This variation of the XSTART instruction returns the identifier of the selected TE in x0, which can be used to send a start command to any available TE when there are multiple TEs that can execute the given command, and can be used later to check for completion.

[0073] The embodiments of this technique also define several additional new instructions, including the following: 7. XEVENT x0 This instruction is useful for reducing the cost of software that polls the status of TEs to determine which ones have completed. It returns the ID of the completed TE (via x0 in this case), and as a result, the threadlet model can be more easily incorporated into event-driven software architectures. 8. XSETAFR x0,x1,#imm This instruction is used to set up the alternative-function register (AFR1) and the alternative-function-return register (AFR2), as will be explained in more detail below.

[0074] Therefore, embodiments of this technique provide architectural support for one or more new instructions added to an instruction set architecture (ISA). Given the limited coding space available within instructions, adding instructions to an ISA is important, and it will be understood that it is not always clear that such new instructions are worth the cost of their implementation. However, the inventors of this technique recognized that the benefits of providing these instructions may outweigh the associated costs. For example, the XSTART and XSYNC instructions (and their variations) enable the functionality of threadlet execution circuits, which can help improve performance for the reasons stated above. The XEVENT instruction is beneficial because it allows threadlet models to be easily incorporated into certain types of architectures. Finally, the XSETAFR instruction is advantageous because it allows the AFR1 and AFR2 registers to be set up (as described below), providing hardware support for the ability to execute alternative functions when threadlet execution circuits are unavailable and / or unsuitable.

[0075] The aforementioned threadlet execution circuits (or "extension processing circuits") can offer several advantages. For example, using threadlet execution circuits can improve CPU performance and efficiency by creating new hardware units that can run asynchronously with respect to the rest of the CPU and can be targeted for offloading certain critical functions. Embodiments of this technique aim to further improve systems that implement threadlet execution circuits and address challenges such as how to limit the friction experienced by software in scenarios where threadlet use (e.g., offloading tasks to threadlet processing circuits) is desirable, but the persistent availability of TEs cannot be guaranteed. In other words, this technique aims to enable code that accesses threadlet functionality to work regardless of whether TEs are available, thus avoiding uncertainty from the programmer's or system developer's perspective.

[0076] Figure 5 shows an example of a code sequence that may typically appear at the invocation point of a threadlet. As shown in the figure, the sequence includes the XSTARTS instruction, which is a non-blocking version of the threadlet start instruction that sets a zero flag if execution fails, as described above. The next instruction in the sequence is the B.NE (Branch if not equal) instruction. Note that this embodiment of the technique is not limited to the B.NE instruction, and other conditions (e.g., other than "not equal") may be used instead. This is an instruction that branches to an identified instruction if a particular condition is not met, and the condition depends on whether the TE is available and / or suitable for the execution of the threadlet. In this embodiment, the label "fallback_zlib_compress_v1.2" identifies a fallback routine (alternative function) that is executed when the TE is unavailable. In this particular embodiment, the fallback routine performs zlib compression. However, the routine selected as the fallback routine will differ depending on the task for which the use of the TE is required. The instruction from which execution branches may be identified in the B.NE instruction, or in the XSTARTS instruction (for example, by identifying the register that stores the instruction's address), or by a dedicated register associated with the TE (it does not necessarily have to be explicitly identified in any of the instructions). Note that other forms of branch instructions (e.g., instructions other than the B.NE instruction) can be used instead. Instructions I1, I2, and I3 are indicated to represent the remaining instructions in the sequence and can be of any type. As described above, offloading a threadlet to the TE means that the processing circuit can continue to execute I1, I2, and I3 in parallel with the execution of the threadlet by the TE. However, if it is decided not to issue a start command, it will be understood that these instructions do not need to be executed until the execution of the alternative function is complete.

[0077] There are several reasons why TE might be unavailable when the XSTARTS instruction is executed. For example, ● TE may still be executing the previous threadlet and therefore cannot be used to initiate execution of any further threadlets associated with the XSTARTS instruction. ● The current power and / or thermal profile set for the CPU may be one that does not allow threadlet execution or restricts it in some way. ● The exact operation requested (e.g., data processing operation contained within a threadlet) may not be supported by TE, for example, because the operation itself is not supported (e.g., a threadlet contains a memcpy function, but TE does not support the memcpy function) or because the parameters associated with the operation are not supported (e.g., requesting a compression level outside the range supported by TE). ● The requested granularity may not meet the internal threshold developed from heuristic methods that depend on the acceptable level of inference for TE.

[0078] Whatever the reason, the processing circuit (CPU) responds to the determination that the TE is unavailable by triggering the execution of an alternative function instead of issuing a start command. As mentioned above, the alternative function can be identified in one of several ways. However, an embodiment of this technique introduces a register associated with the TE that holds an address index that identifies the start of the alternative function.

[0079] Figure 6 shows an embodiment of a dedicated register that may be provided to enable the execution of an alternative function when the TE is unavailable. In this embodiment, the register is located within TE52. However, in other embodiments, the register may be separate from (but associated with) the TE.

[0080] The registers include an alternate function register (AFR1—also called "AFR" in some embodiments) 70 and an alternate function return register (AFR2) 72. The alternate function register (AFR1) 70 holds information indicating the address that indicates the start of an alternate function to be executed by the CPU when the threadlet execution circuit 52 is unavailable. For example, the alternate function register 70 may hold an address pointer to the first instruction of the alternate function. The alternate function return register (AFR2) 72 holds information indicating the address that indicates the end of the alternate function. For example, the alternate function return register 72 may hold an address pointer to the return instruction at the end of the alternate function. Multiple copies of each of AFR1 70 and AFR2 72 may be provided; for example, separate pairs of AFR1 and AFR2 may be provided for each of several different types of operation. The AFR1 and AFR2 registers thus provide hardware support for this technique by providing designated locations for identifying alternate functions to be executed when the TE is unavailable.

[0081] When the AFR1 register 70 is included, the B.NE instruction shown in the sequence in Figure 5 causes the processing circuit to read the AFR1 register 70 and determine where to branch the execution.

[0082] The AFR2 register 72 provides hardware support that enables the threadlet execution circuit 52 to determine when the execution of an alternative function is complete. For example, if the AFR2 register 72 stores a pointer to the function's return address, the threadlet execution circuit 52 can monitor instructions executed by the CPU 51 and compare their instruction addresses with the instruction addresses stored in the AFR2 register. When the TE 52 receives an instruction with an address that matches an address stored in AFR2, it can issue a "complete" signal (abort indicator) to the CPU 51 indicating that the execution of the function is complete. For example, the abort indicator can be a signal asserted by the TE or a flag set by the TE.

[0083] In some embodiments of this technique, the abort indicator set by the TE when it detects that the CPU 51 has completed the execution of the alternative function may be the same as the abort indicator used when the TE completes the execution of the threadlet. This allows the CPU to respond to the completion of the execution of the alternative function in the same way it responded to the completion of the execution of the threadlet. For example, at some later stage, the CPU 51 may execute an XSYNC or XSYNCS instruction as described above.

[0084] Although this embodiment shows the TE as separate from the CPU, please note that this technique can also be implemented in devices arranged as shown in Figures 1 and 2.

[0085] Figure 7 illustrates another new instruction introduced to support this technique. Labelled "XSETAFR," this instruction is an AFR setup instruction used to set up the AFR1 and AFR2 registers described above. The AFR setup instruction shown in Figure 7 has the following fields: ● Field indicating the TE identifier (#imm) - Note that this field may not be necessary if the hardware has only one TE. ● A field that identifies a register (x0) that holds an address pointer to a routine (e.g., an alternative function) that has capabilities matching or similar to those of a given threadlet - this pointer is stored in the AFR1 register of the TE identified when the AFR setting instruction is executed. ● A field that identifies the register (x1) that holds the address of the return instruction within that routine - this address is stored in the AFR2 register of the identified TE when the AFR setting instruction is executed.

[0086] Therefore, the decoding circuit of a device using the corresponding technique may be able to control the processing circuit to decode the AFR setting instruction and store the values ​​held in x0 and x1 in the identified TE's AFR1 and AFR2 registers. Thus, devices of some embodiments of this technique provide architectural support for the AFR setting instruction, thereby facilitating the use of the AFR1 and AFR2 registers.

[0087] Figure 8 is a flowchart illustrating an example of how to execute a non-blocking threadlet start (XSTARTS) instruction. In some embodiments, this method can be performed by the processing circuit described above.

[0088] This method includes determining whether an XSTARTS instruction has been encountered 80, and determining whether, when the instruction has been encountered, a threadlet execution circuit is available, available and suitable for executing a given threadlet 82. If the threadlet execution circuit is determined to be suitable and available, a start command is sent to the threadlet execution circuit 84. On the other hand, if the threadlet execution circuit is determined to be unavailable and / or unsuitable, the processing circuit reads the AFR1 register 86 and determines whether the AFR1 register holds a valid address pointer 88. For example, this may include reading the valid bits / fields of the AFR1 register and determining whether the pointer is set to a value indicating that it is valid. If AFR1 is determined to hold a valid address pointer, this method includes executing a linked branch instruction 90 to branch to the instruction identified by the address pointer in the AFR1 register. On the other hand, if the AFR1 register is determined not to hold a valid address pointer, an error response is triggered 92.

[0089] Figure 9 is a flowchart illustrating a method for monitoring the execution of instructions by a processing circuit. In some embodiments, this method can be implemented by the threadlet execution circuit described in the above embodiment.

[0090] This method begins with step 94, which involves monitoring an instruction to be executed by the processing circuit, and step 96, which involves determining whether the instruction at the address corresponding to the address information stored in the AFR2 register has been executed. Monitoring 94 continues until it is determined that such an instruction has been executed 96, in which case a "complete" signal (or "cancel" signal) is shown to the processing circuit 98.

[0091] Figure 10 is a flowchart illustrating how the AFR setting (XSETAFR) instruction is executed. In some embodiments, this method can be implemented by a processing circuit.

[0092] This method includes a step 100 in which it is determined whether an AFR setting instruction has been encountered. If it is determined that an AFR setting instruction has been encountered, a pointer to the alternative function is stored in the AFR1 register 102, and the valid field is set to indicate that the register stores a valid address pointer. Furthermore, the address of the return instruction in the alternative routine is stored in the AFR2 register 104, and the corresponding valid field is set.

[0093] Figure 11 illustrates possible implementations of a simulator. While the above embodiments implement the present invention in terms of devices and methods for operating specific processing hardware that supports the technology, it is also possible to provide an instruction execution environment according to the embodiments described herein, which are implemented by the use of a computer program. Such a computer program is often called a simulator, insofar as it provides a software-based implementation of a hardware architecture. Various simulator computer programs include emulators, virtual machines, models, and binary translators, including dynamic binary translators. Typically, a simulator implementation may run on a host processor 120, optionally running a host operating system 118 and supporting a simulator program 112. In some configurations, there may be multiple layers of simulation between the hardware and the provided instruction execution environment, and / or multiple different instruction execution environments may be provided on the same host processor. Historically, powerful processors have been required to provide simulator implementations that run at reasonable speeds, but such techniques may be justified in certain circumstances, such as when it is desirable to run native code on a different processor for reasons of compatibility or reuse. For example, a simulator implementation may provide an instruction execution environment with additional functionality not supported by the host processor hardware, or it may provide an instruction execution environment typically associated with a different hardware architecture. An overview of the simulation is described in "Some Efficient Architecture Simulation Techniques," Robert Bedichek, Winter 1990 USENIX Conference, Pages 53-63.

[0094] While embodiments have been described with reference to specific hardware components or features, in simulated embodiments, equivalent functionality may be provided by suitable software components or features. For example, certain circuits may be implemented as computer program logic in simulated embodiments. For instance, the simulator program 112 shown in Figure 11 includes processing program logic 114 that emulates the processing circuit described above, and threadlet execution program logic 116 that emulates the threadlet execution circuit described above. Similarly, memory hardware such as registers or caches may be implemented as software data structures in simulated embodiments. In configurations where one or more of the hardware elements referenced in the embodiments described above reside on host hardware (e.g., host processor 120), some simulated embodiments may, if preferred, utilize the host hardware.

[0095] The simulator program 112 may be stored on a computer-readable storage medium (which may be a non-temporary medium) and provides a program interface (instruction execution environment) to target code 110 (which may include an application, operating system, and hypervisor) that is the same as the interface of the hardware architecture modeled by the simulator program 112. Thus, program instructions of target code 110 that may include one or more of the above-mentioned XSTART, XSTARTS, XSYNC, XSYNCS, XEVENT, and / or XSETAFR instructions may be executed from within the instruction execution environment using the simulator program 112, thereby allowing a host computer 120 that does not actually possess the hardware functions of the device considered above to emulate these functions.

[0096] In this application, the phrase "configured to..." is used to mean that an element of the device has a configuration that enables it to perform a defined operation. In this context, "configuration" means the arrangement or interconnection of hardware or software. For example, the device may have dedicated hardware to provide the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that an element of the device must be modified in any way to provide the defined operation.

[0097] Furthermore, the phrase "including at least one of..." in this application is used to mean that any one of the following options or any combination of the following options is included. For example, "at least one of A, B, and C" is intended to mean A or B or C or any combination of A, B and C (e.g., A or B, or C, or A and B, or A and C, or B and C, or A and B and C).

[0098] This application describes various methods. It will be understood that any of these methods can be implemented in some embodiments by a computer that executes instructions for a computer program. Such a computer program can be stored on a computer-readable storage medium, such as a temporary or non-temporary medium.

[0099] While illustrative embodiments of the present invention are described in detail herein with reference to the accompanying drawings, it will be understood that the present invention is not limited to those exact embodiments, and that various changes and modifications can be made to the embodiments without departing from the scope of the present invention as defined by the appended claims.

Claims

1. It is a device, A processing circuit that executes instructions, A threadlet execution circuit that performs a task under the control of the processing circuit, wherein the threadlet execution circuit is configured to operate asynchronously with respect to the processing circuit, comprising: The threadlet execution circuit, in response to a start command issued by the processing circuit, starts the execution of a threadlet that includes at least one delegated task, and A device wherein, in response to a threadlet start instruction, the processing circuit determines, depending on at least one parameter, whether to trigger the execution of an alternative function by the processing circuit instead of issuing the start command to the threadlet execution circuit, the processing circuit being triggered to execute an alternative function, the processing circuit being triggered to issue the start command to the threadlet execution circuit.

2. The apparatus according to claim 1, wherein the processing circuit, in response to determining that it triggers the execution of the alternative function instead of issuing the start command to the threadlet execution circuit, branches the execution to an identified instruction.

3. Equipped with Alternative Function Registers (AFRs), The apparatus according to claim 2, wherein the processing circuit, in response to determining that it triggers the execution of the alternative function instead of issuing the start command to the threadlet execution circuit, branches the execution to an instruction identified by the address shown in the AFR.

4. The aforementioned AFR is A general-purpose register associated with the processing circuit, or The apparatus according to claim 3, further comprising one of the dedicated registers associated with the threadlet execution circuit.

5. The apparatus according to claim 3 or 4, wherein the processing circuit, in response to an AFR setting instruction, stores the address pointer specified by the AFR setting instruction in the AFR.

6. The apparatus according to claim 5, wherein the processing circuit, in response to the AFR setting command, records a predetermined value in the effective field of the AFR, and the predetermined value indicates that the AFR holds an index of an effective address.

7. In response to the processing circuit determining that it will trigger the execution of the alternative function instead of issuing the start command to the threadlet execution circuit, Determine whether the valid field of the AFR holds a predetermined value indicating that the AFR holds a valid indicator of the address. The apparatus according to any one of claims 3 to 6, which starts an error response in response to determining that there is no predetermined value in the effective field of the AFR.

8. The apparatus according to any one of claims 1 to 7, wherein the processing circuit is configured to determine, as at least one parameter, whether to trigger the execution of the alternative function instead of issuing the start command to the threadlet execution circuit, depending on whether the execution of the previous threadlet by the threadlet execution circuit is in progress.

9. The apparatus according to claim 8, wherein the processing circuit, in response to determining that the execution of the previous threadlet by the threadlet execution circuit is in progress, triggers the execution of the alternative function instead of issuing the start command to the threadlet execution circuit.

10. The threadlet execution circuit is configured to set a abort indicator in response to the completion of the execution of the previous threadlet. The apparatus according to claim 8 or 9, wherein the processing circuit is configured to determine whether the threadlet execution circuit has completed the execution of the previous threadlet, depending on whether the abort indicator is set.

11. The apparatus according to any one of claims 1 to 10, wherein the processing circuit is configured to determine whether to trigger the execution of the alternative function instead of issuing the start command to the threadlet execution circuit, depending on one or more power requirements and / or thermal requirements as the at least one parameter.

12. The apparatus according to any one of claims 1 to 11, wherein the processing circuit is configured to determine, as the at least one parameter, whether to trigger the execution of the alternative function instead of issuing the start command to the threadlet execution circuit, depending on whether the at least one delegated task is supported by the threadlet execution circuit.

13. The apparatus according to any one of claims 1 to 12, wherein the processing circuit is configured to determine, as at least one parameter, whether to trigger the execution of the alternative function instead of issuing the start command to the threadlet execution circuit, in response to a determination of whether the granularity of the threadlet satisfies a threshold granularity defined for the threadlet execution circuit.

14. The apparatus according to any one of claims 1 to 13, wherein the threadlet execution circuit sets a termination indicator in response to the completion of the execution of the alternative function.

15. It has an alternate function return register that holds an index of the return instruction address, The threadlet execution circuit is configured to monitor the execution of instructions by the processing circuit and to determine, based on the return instruction address, whether the processing circuit has executed the corresponding return instruction. The apparatus according to claim 14, wherein the threadlet execution circuit sets the abort index in response to the processing circuit determining that it has executed the corresponding return instruction.

16. Equipped with Alternative Function Registers (AFRs), In response to the processing circuit determining that it will trigger the execution of the alternative function instead of issuing the start command to the threadlet execution circuit, it branches the execution to the instruction identified by the address shown in the AFR, The processing circuit responds to the AFR setting command, The address pointer specified by the AFR setting instruction is stored in the AFR. The apparatus according to claim 15, wherein the return instruction address pointer specified by the AFR setting instruction is stored in the alternative function return register.

17. A computer program including computer-readable code for manufacturing the apparatus according to any one of claims 1 to 16.

18. A method for controlling a threadlet execution circuit to perform a task, wherein the method is Controlling a threadlet execution circuit, which is configured to operate asynchronously with respect to the processing circuit, to execute a task using a processing circuit, Using the processing circuit, a start command is issued to the threadlet execution circuit, causing the threadlet execution circuit to start executing a threadlet that includes at least one delegated task. A method comprising: a threadlet start instruction, wherein the threadlet start instruction indicates a request to issue the start command to the threadlet execution circuit, and in response to the threadlet start instruction, the processing circuit determines, depending on at least one parameter, whether to trigger the execution of an alternative function by the processing circuit instead of issuing the start command to the threadlet execution circuit.

19. A computer program that includes instructions to control the host data processing device to provide an instruction execution environment for executing target program code when executed by the host data processing device, wherein the computer program The processing program logic that executes the instructions, A threadlet execution program logic that executes a task under the control of the processing program logic, wherein the threadlet execution program logic is configured to operate asynchronously with respect to the processing program logic, comprising: The threadlet execution program logic, in response to a start command issued by the processing program logic, starts the execution of a threadlet that includes at least one delegated task. A computer program in which the processing program logic is a threadlet start instruction, the threadlet start instruction indicates a request to issue the start command to the threadlet execution program logic, and in response to the threadlet start instruction, determines, depending on at least one parameter, whether to trigger the execution of an alternative function by the processing program logic instead of issuing the start command to the threadlet execution program logic.

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