Multilayer nanosheet FET with gate dielectric fill
By replacing gate material in the top FET cutout region with a dielectric material and forming a gate cap, the parasitic capacitance issue is mitigated, improving switching speed and performance in stacked nanosheet FETs.
JP2026522207APending Publication Date: 2026-07-07INTERNATIONAL BUSINESS MACHINE CORPORATION
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- INTERNATIONAL BUSINESS MACHINE CORPORATION
- Filing Date
- 2024-05-24
- Publication Date
- 2026-07-07
AI Technical Summary
Technical Problem
In stacked nanosheet field effect transistors (FETs), the top FET cutout region filled with gate material leads to parasitic capacitance, reducing switching speed and affecting performance, especially in multilayer designs where the top FET nanosheets are narrower and surrounded by more gate material.
Method used
Replace a significant amount of work function metal in the top FET cutout region with a dielectric material, particularly one with a low dielectric constant, and form a gate cap with the same work function metal to minimize capacitance and enhance contact flexibility.
Benefits of technology
Reduces parasitic capacitance, improves switching speed, and allows for flexible gate contact placement, thereby enhancing the performance and density of the nanosheet FETs.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure 2026522207000001_ABST
Abstract
The semiconductor cell comprises a top FET containing a first set of silicon nanosheets and a bottom FET containing a second set of silicon nanosheets. The top and bottom FETs form a stacked profile. The semiconductor cell includes a top FET cutout region located laterally to the first set of nanosheets and above a portion of the second set of nanosheets. The semiconductor cell also includes a dielectric fill within the top FET cutout region.
Need to check novelty before this filing date? Find Prior Art