Task delegation

Abstract

Apparatus, data processing method, computer program, and computer-5 readable medium are disclosed. A data processing pipeline performs data processing operations in response to a received instruction sequence. An extension processing circuit is associated with the data processing pipeline and performs a delegated task in response to a delegation signal received from the data processing pipeline. Decoding the received instruction sequence generates a control signal for controlling the data processing pipeline to perform data processing operations. Decoding generates a control signal for controlling the data processing pipeline to delegate the delegated task to the extension processing circuit by issuing a delegation signal to the extension processing circuit in response to an extension start instruction specifying the delegated task. The extension processing circuit performs the delegated task asynchronously with respect to the data processing operations performed by the data processing pipeline.

Description

Technical Field

[0001] This technique relates to an apparatus, a method of operating the apparatus, a computer program, and a computer-readable medium.

[0002] The apparatus may comprise a data processing pipeline configured to perform a data processing operation in response to a received instruction sequence.

[0003] At least some examples in this specification provide an apparatus for data processing, the apparatus comprising a data processing pipeline configured to perform a data processing operation in response to a received instruction sequence, and an extension processing circuit associated with the data processing pipeline and configured to perform a delegated task in response to a delegation signal received from the data processing pipeline. The data processing pipeline comprises a decoding circuit configured to decode the received instruction sequence and generate a control signal for controlling the data processing pipeline to perform a data processing operation. The decoding circuit, in response to an extension start instruction specifying a delegated task, generates a control signal for controlling the data processing pipeline, the data processing pipeline is configured to issue a delegation signal to the extension processing circuit to delegate the delegated task to the extension processing circuit, the extension processing circuit is configured to perform the delegated task asynchronously with the data processing operation performed by the data processing pipeline.

[0004] At least some examples in this specification provide a non-transitory computer-readable medium for storing computer-readable code for manufacturing an apparatus.

[0005] At least some examples in this specification provide a data processing method, the method comprising In response to the received instruction sequence, data processing operations are performed in the data processing pipeline. In response to a delegation signal received from the data processing pipeline, the delegated task is performed in the extended processing circuit associated with the data processing pipeline. This includes decoding a received instruction sequence in a decoding circuit in order to generate control signals for controlling a data processing pipeline to perform data processing operations, Decryption occurs in response to an extended start instruction specifying the delegated task. A delegation signal is issued to the extension processing circuit to generate a control signal that controls the data processing pipeline to delegate the delegated task to the extension processing circuit. The extended processing circuit executes delegated tasks asynchronously with the data processing operations performed by the data processing pipeline.

[0006] At least some examples herein provide computer programs for controlling a host data processing device to provide an instruction execution environment, and the computer programs are A data processing pipeline logic for performing data processing operations according to the received command sequence, Includes extended processing logic associated with data processing pipeline logic and configured to perform delegated tasks in response to delegation signals received from the data processing pipeline logic, The data processing pipeline logic includes decoding logic configured to decode the received instruction sequence and generate control signals to control the data processing pipeline logic to perform data processing operations. The decoding circuit responds to an extended start instruction specifying the delegated task, Generate control signals to control the data processing pipeline logic, The data processing pipeline logic is configured to issue a delegation signal to the extension processing logic, thereby delegating the delegated task to the extension processing logic. The extended processing logic is configured to perform delegated tasks asynchronously with respect to the data processing operations performed by the data processing pipeline logic. [Brief explanation of the drawing]

[0007] This technique will be further explained simply as an example, referring to the embodiment of this technique shown in the attached drawings, in conjunction with the explanation below. [Figure 1] This paper provides a schematic example of a data processing device that can embody various embodiments of this technique. [Figure 2] This paper provides a schematic example of a data processing device that can embody various embodiments of this technique. [Figure 3] This paper provides a schematic example of a data processing device that can embody various embodiments of this technique. [Figure 4] This is a state diagram illustrating an exemplary set of states, and the extended processing circuit of this technique can transition between these states. [Figure 5] Several embodiments schematically illustrate extended start instructions that delegate tasks to extended processing circuits. [Figure 6] This section schematically illustrates an extended start instruction that delegates a task to one of several instances of an extended processing circuit, using several embodiments. [Figure 7] Several embodiments schematically illustrate extension processing circuits that accept delegated tasks. [Figure 8] Several embodiments schematically illustrate extended processing circuits that demonstrate their unavailability for accepting delegated tasks. [Figure 9] This section schematically illustrates an extended start instruction that delegates a task to one of several instances of an extended processing circuit, using several embodiments. [Figure 10] This paper schematically illustrates an extended synchronization instruction that transfers the results of a delegated task from an extended processing circuit to a set of registers belonging to a data processing pipeline, using several embodiments. [Figure 11]This section schematically illustrates an extended start instruction that delegates a task to one of several instances of an extended processing circuit, using several embodiments. [Figure 12] This section schematically illustrates an extended synchronization instruction that transfers the result of a delegated task from one of several instances of an extended processing circuit to a set of registers belonging to a data processing pipeline, using several embodiments. [Figure 13] This section schematically illustrates an extended event instruction that, through several embodiments, causes the identifier of one of several instances of an extended processing circuit that has completed a delegated task to be written to a register belonging to the data processing pipeline. [Figure 14] Several embodiments schematically illustrate extended processing circuits that, upon encountering a memory failure or other processing interruption, signal this event to the data processing pipeline. [Figure 15] This is a flowchart showing the sequence of steps taken in the methods of several embodiments. [Figure 16] This section provides a general overview of possible simulator implementations.

[0008] One example of this specification is a device for data processing, and the device is A data processing pipeline configured to perform data processing operations in response to a received command sequence, The system includes an extended processing circuit associated with a data processing pipeline and configured to perform delegated tasks in response to delegated signals received from the data processing pipeline, The data processing pipeline includes a decoding circuit configured to decode the received instruction sequence and generate control signals to control the data processing pipeline to perform data processing operations. The decoding circuit responds to an extended start instruction specifying the delegated task, Generate control signals to control the data processing pipeline. The data processing pipeline is configured to issue a delegation signal to the expansion processing circuit to delegate the delegated task to the expansion processing circuit. The expansion processing circuit is configured to perform the delegated task asynchronously with respect to the data processing operation performed by the data processing pipeline.

[0009] Devices equipped with a data processing pipeline may be required to perform an infinite variety of data processing operations, as defined by the instruction sequences provided to it. To efficiently perform these data processing operations, the data processing pipeline may consist of various functional units, each possessing a given special type of data processing capability, such as arithmetic logic units (ALUs), floating-point (FP) units, and load / store units. Furthermore, even when such specialized functional units are provided as part of the data processing pipeline, the inventors of this technique have established that in some types of data processing, i.e., in a particular program (i.e., instruction sequence), there may be specific functions that are frequently executed and require a certain amount of processing. As a result, providing dedicated custom hardware to support these functions is valuable because it can significantly impact the overall performance of the device. In identifying such functions, two important characteristics were considered relevant: the ubiquity of the function (i.e., it can be found in many other use cases) and the impact of the function (i.e., the proportion of time spent executing such a function is a significant portion of the total runtime, and as a result, improvements in its execution make a significant difference to the use case as a whole). Such highly impactful and ubiquitous functions have been found to include tasks or functions such as memcpy, memset, compression, encryption, and string processing, but the technique is not limited to these specific embodiments. The technique provides extension processing circuits that are associated with a data processing pipeline and configured to perform such functions (delegated tasks) in response to delegation signals received from the data processing pipeline. Such extension processing circuits may also be referred to herein as threadlet extensions (TEs). The sequence of actions that the extension processing circuit performs to perform a defined function may be referred to herein as a threadlet.The extension processing circuit is closely associated with the data processing pipeline, but is configured to perform delegated tasks asynchronously with respect to the data processing operations performed by the data processing pipeline. The data processing pipeline may also be referred to as the CPU in this specification. A threadlet is a set of functions or operations that, once invoked, can be executed asynchronously with respect to other CPU activity. The asynchronous operation of the extension processing circuit with respect to the data processing pipeline is possible because, unlike some prior art techniques, the extension processing circuit receives instructions or commands from threads currently running on the CPU and performs the necessary operations independently, that is, without requiring a stream of instructions from the CPU that directly controls or affects its internal operations. Thus, the CPU is free to continue executing other code and potentially reduces the overall runtime by overlapping the execution of the instruction stream after the instructions or commands have been sent to the extension processing circuit with the operation of the extension processing circuit. The instructions or commands sent to the extension processing circuit to initiate a delegated task are generated in response to an extension start instruction defined for this purpose in the instruction set of the data processing pipeline. Thus, the decoding circuit, in response to the extension start instruction, issues a delegation signal to the extension processing circuit, thereby delegating the delegated task to the extension processing circuit. Due to the close integration of the expansion processing circuit and the data processing pipeline, the expansion processing circuit can be started up quickly, and its status can be checked in a very short time (e.g., on the order of a few nanoseconds) compared to some conventional techniques that would require a great many CPU cycles to invoke commands or perform synchronous operations.

[0010] In some embodiments, the data processing pipeline includes a set of registers for holding data values ​​on which data processing operations are performed.

[0011] The delegation signal issued to the extension processing circuit to delegate a delegated task can provide various information to the extension processing circuit. In some embodiments, the data processing pipeline is configured to transfer at least one data value from at least one of a set of registers to the extension processing circuit in relation to the delegation signal. The close association between the extension processing circuit (TE) and the data processing pipeline (CPU) means that the TE can directly obtain data from the CPU registers at the start of its execution. Similarly, at completion, a value can be directly returned to the CPU registers. Therefore, there is no need to rely on memory transfers to communicate with the startup thread on the CPU.

[0012] At least one of the set of registers from which at least one data value is transferred can be implicit with respect to the delegated task or the extension processing circuit, or in some embodiments, the extension start instruction specifies at least one of the set of registers, and the decoding circuit generates a control signal for controlling the data processing pipeline to pass at least one data value from at least one of the set of registers to the extension processing circuit in response to the extension start instruction.

[0013] The extension start instruction can take various forms and, in particular, can define one or more operands associated with the instruction. In some embodiments, the extension start instruction further specifies an operation identifier, which identifies at least one of the extension processing circuit identifier and / or the delegated task identifier when the device includes two or more instances of the extension processing circuit. Therefore, the operation identifier can be used to specify a particular instance of the extension processing circuit or a particular delegated task to be executed. In some embodiments, a given instance of the extension processing circuit is configured to execute only one function, while in other embodiments, a given instance of the extension processing circuit can be configured to execute one of several functions selectable by the use of the operation identifier.

[0014] In some embodiments, the extended start instruction specifies a register from which the operation identifier is retrieved, which is part of a set of registers from which the operation identifier is retrieved. In some other embodiments, the extended start instruction specifies the operation identifier as an immediate value.

[0015] A data processing pipeline can delegate delegated tasks to an extension processing circuit and perform its own data processing while the delegated tasks are being executed by the extension processing circuit. However, this configuration still requires that the results of the delegated tasks be available within a limited timeframe (regardless of the asynchronous execution of the delegated tasks) so that they can be integrated into further data processing operations performed by the data processing pipeline without stalling the data processing pipeline while the delegated tasks are completing. To address this, in some embodiments, the data processing pipeline includes a commit stage in which an irreversible change in the state of the device occurs when the executed instructions of the received instruction sequence are committed, and the data processing pipeline is configured to suppress the committing of extension start instructions until the extension processing circuit accepts the delegated tasks.

[0016] Nevertheless, if the extension processing circuit is unable to accept the delegated task, this can itself stall the data processing pipeline; therefore, in some embodiments, the data processing pipeline sets at least one unavailable condition flag in a condition register of a set of registers in response to an unavailable signal from the extension processing circuit regarding the delegated task. This setting of at least one unavailable condition flag can be used as a trigger for an alternative action, for example, by using a branch instruction sensitive to the relevant flag.

[0017] Therefore, in some embodiments, the data processing pipeline, in response to at least one unavailable condition flag being set, (temporarily) deviates from the received instruction sequence to retrieve a fallback instruction set and, depending on the fallback instruction set, executes a fallback data processing operation set.

[0018] In a manner complementary to the initiation of a delegated task in response to an extended start instruction defined for this purpose in the instruction set of the data processing pipeline, extended synchronization instructions may also be defined in the instruction set to make the results of the delegated task available. Therefore, in some embodiments, the decoding circuit responds to the extended synchronization instruction, The extended processing circuit generates a control signal to determine whether it has completed the delegated task. When the extension processing circuit is completing its assigned task, a control signal is generated to control the extension processing circuit so that it passes at least one result data value to at least one result register in the set of registers.

[0019] Extended synchronization instructions can take various forms, and in particular, they can define one or more operands associated with the instruction. In some embodiments, an extended synchronization instruction specifies at least one result register from a set of registers. Similar to extended start instructions, in some forms of extended synchronization instructions, the data processing pipeline is configured not to commit the extended synchronization instruction until the extended processing circuit has completed the task to which it has been delegated. If an extended synchronization instruction is executed before the extended processing circuit has completed the task to which it has been delegated, this can be handled in several ways, but in some embodiments, the data processing pipeline, in response to the determination that the extended processing circuit has not completed the task to which it has been delegated, sets at least one incomplete condition flag in a condition register of the set of registers.

[0020] In situations where an extended synchronization instruction stalls in this manner, the setting of at least one incomplete condition flag can be used as a trigger to allow some subsequent code to continue execution, for example by performing some alternative computation while waiting for the delegated task to complete, for example by using a branch instruction that is sensitive to the relevant incomplete condition flag. Thus, in some embodiments, the data processing pipeline, in response to the setting of at least one incomplete condition flag, (temporarily) deviates from the received instruction sequence, retrieves an alternative set of instructions, and performs a further set of data processing actions according to the alternative set of instructions.

[0021] In embodiments where an extension start instruction initiates a delegated task that can be performed by two or more instances of an extension processing circuit, the extension start instruction may specify a register to which an identifier of the instance of the extension processing circuit to which the delegated task is assigned can be written. This identifier can then be used to check the completion of the delegated task. Thus, in some embodiments, the device further includes multiple instances of an extension processing circuit associated with a data processing pipeline, each instance capable of executing a delegated task in response to a delegation signal received from the data processing pipeline. The extension start instruction specifies the assigned extension register from the set of registers, and the decoding circuit generates a control signal in response to the extension start instruction. Assign the delegated task to a selected instance of the extended processing circuit. The data processing pipeline is controlled to write the identifier of the selected instance of the extended processing circuit to the assigned extended register.

[0022] Therefore, in such an embodiment, the extended synchronization instruction may specify an allocated extended register from a set of registers, and the decoding circuit may generate a control signal in response to the extended synchronization instruction. The selected instance of the extension processing circuit, indicated by the assigned extension register, generates a control signal to determine whether it has completed the delegated task. When a selected instance of the extension processing circuit is completing a delegated task, a control signal is generated to control the selected instance of the extension processing circuit so as to pass at least one result data value to at least one result register of the set of registers.

[0023] Other related instructions may be defined in the instruction set. Thus, in some embodiments, the device includes multiple instances of an extension processing circuit associated with a data processing pipeline, each instance capable of performing a delegated task in response to a delegation signal received from the data processing pipeline. The decoding circuit responds to an extended event instruction that specifies an event instruction register from a set of registers, Generate control signals to control the data processing pipeline to identify instances of the extended processing circuit that have completed their assigned tasks. This instruction generates a control signal that writes the identifier of the extension circuit instance that has completed its delegated task to the event instruction register. This instruction is useful for reducing the cost of software that polls the state of multiple extension circuit instances to determine which one has completed. The instruction returns the identifier of the completed extension circuit instance, and as a result, the threadlet model can be more easily incorporated into event-driven software architectures.

[0024] While the expansion processing circuit is closely associated with the data processing pipeline, the degree of integration between the expansion processing circuit and the data processing pipeline can vary. In some embodiments, the device further comprises a load / store queue and a private cache for the data processing pipeline. The expansion processing circuit is configured to perform memory access via load / store queues and private caches. In other words, the expansion processing circuit relies on the existing infrastructure of the data processing pipeline to access memory.

[0025] In other embodiments, the extended processing circuit is still closely associated with the data processing pipeline, but accesses memory with greater independence, and in some embodiments, the device Extended processing circuit private cache, It further includes an extended processing circuit address translation buffer.

[0026] In some embodiments, the augmented processing circuit is configured to flush the augmented processing circuit private cache upon completion of the delegated task.

[0027] In some embodiments, the device further comprises an address translation buffer configured to cache address translations used by a data processing pipeline. The data processing pipeline is configured to copy the contents of the address translation buffer to the extension processing circuit's address translation buffer when a delegated task is delegated to the extension processing circuit. This "preheats" the extension processing circuit's address translation buffer, allowing it to complete its delegated task more efficiently.

[0028] Here, it is recognized that the extension processing circuit may be interrupted while performing a delegated task, for example, by the extension processing circuit itself encountering a memory failure, or by the main thread running on the data processing pipeline (i.e., the thread that triggered the threadlet) being switched out. This technique proposes the close integration of the extension processing circuit into the exception handling capabilities of the data processing pipeline. Therefore, in some embodiments, the extension processing circuit responds to the interruption of a delegated task by: To indicate the suspension of a delegated task, set the suspension bit in the current program status register, one of the set of registers. If the interruption of a delegated task is caused by a memory failure, an indication of the source of the failure is written to the syndrome system register among the set of registers, and an interrupt signal for the data processing pipeline is asserted. It should be noted that the ability of the extension processing circuit to directly access the set of registers in the data processing pipeline may depend on the tightness of the integration between the extension processing circuit and the data processing pipeline. That is, deeply embedded implementations of the extension processing circuit may be able to access the set of registers essentially without intermediary, while less embedded implementations (e.g., having their own paths to memory) may actually be able to access the set of registers via an intermediary interface.

[0029] Furthermore, in some embodiments, if the interruption of a delegated task is triggered by a context switch in the data processing pipeline, the data processing pipeline is configured to perform further data processing actions defined by a new context instruction sequence. If the interruption of a delegated task is caused by a memory failure, the data processing pipeline is configured to perform further data processing actions defined by an exception handling instruction sequence. When setting up further data processing operations to be performed, the device is configured to copy the current program status register to a stored program status register. When the data processing pipeline returns to the data processing operation defined by the received instruction sequence, the data processing pipeline is configured to clear the interruption bit in the stored program status register and copy the stored program status register to the current program status register. The extended processing circuit resumes the suspended delegated task in response to the cleared suspended bit in the current program status register.

[0030] While expansion processing circuits may be used frequently, there may also be periods when they are idle (i.e., waiting for a newly delegated task) or suspended (i.e., waiting for resolution of a memory failure or return from a context switch). To provide improved power characteristics, in some embodiments, expansion processing circuits are configured to be at least one of clock-gated and / or power-gated when they are not actively performing a delegated task.

[0031] To provide an interface that allows the data processing pipeline to access the results of delegated tasks and to determine the status of the extended processing circuit, in some embodiments, the extended processing circuit includes a data buffer, and the data buffer is, The data processing results of the delegated task, and / or It is configured to hold an extended processing circuit status indicator.

[0032] In one embodiment of this specification, there exists a non-temporary computer-readable medium for storing computer-readable codes for manufacturing any of the apparatuses of the embodiments described above.

[0033] One embodiment of this specification is a data processing method, the method being: In response to the received instruction sequence, data processing operations are performed in the data processing pipeline. In response to a delegation signal received from the data processing pipeline, the delegated task is performed in the extended processing circuit associated with the data processing pipeline. Decoding a received instruction sequence in a decoding circuit in order to generate control signals for controlling a data processing pipeline to perform data processing operations, Decryption occurs in response to an extended start instruction specifying the delegated task. The process involves issuing a delegation signal to an extension processing circuit to generate a control signal that controls the data processing pipeline to delegate the delegated task to the extension processing circuit, and decoding. The data processing operations performed by the data processing pipeline include, asynchronously, the execution of delegated tasks in the extended processing circuit.

[0034] In one embodiment of this specification, there exists a computer program that controls a host data processing device to provide an instruction execution environment, and the computer program is A data processing pipeline logic for performing data processing operations according to the received command sequence, Includes extended processing logic associated with data processing pipeline logic and configured to perform delegated tasks in response to delegation signals received from the data processing pipeline logic, The data processing pipeline logic includes decoding logic configured to decode the received instruction sequence and generate control signals to control the data processing pipeline logic to perform data processing operations. The decoding circuit responds to an extended start instruction specifying the delegated task, Generate control signals to control the data processing pipeline logic, The data processing pipeline logic is configured to issue a delegation signal to the extension processing logic, defining that delegated tasks should be delegated to the extension processing logic. The extended processing logic is configured to perform delegated tasks asynchronously with respect to the data processing operations performed by the data processing pipeline logic.

[0035] Here, several specific embodiments will be described with reference to the figures.

[0036] Figure 1 schematically illustrates a data processing device 10 in several embodiments. The data processing device 10 is schematically shown to have a pipeline configuration, and for brevity and clarity, it is shown conceptually here. The illustrated pipeline stages include an instruction cache 11, a fetch stage 12, a decode stage 13, a microoperation cache 14, an issue stage 15, and a register access stage 16. Instruction sequences are retrieved from memory (not shown) and cached in the instruction cache 11. The fetch stage 12 controls which instructions are retrieved as instruction sequences, and these instructions are then decoded in the decode stage 13. This decoding essentially identifies the type of each instruction, as well as any further operands specified by the instruction, and generates control signals to control the rest of the device to perform the data processing operations defined by the instruction. Decoding an instruction may also involve dividing the instruction into one or more microoperations, which can be cached in the microoperation cache 14. The final stage of the pipeline before execution is the issue stage 15, where instructions (or microoperations) are queued, with the availability of the register values ​​they specify as operands and the corresponding functional units in the data processing pipeline that perform the defined operations reserved. Generally, the data processing operations defined by instructions are executed by functional units that form part of the data processing pipeline, namely the load / store unit 17, the execution unit 18, and the execution unit 19. These latter execution units may be, for example, an arithmetic logic unit (ALU) or a floating-point unit (FPU). The functional units that form part of the data processing pipeline perform the data processing operations of the functional units on data values ​​provided from a set of registers (conceptually represented by the register access stage 16 in the figure), and the resulting values ​​of the data processing operations of the functional units are returned to the set of registers.The load / store unit 17 is provided for the purpose of storing values ​​from a set of registers into the memory system, and only the level 1 cache 21 and level 2 cache 22 of the memory system are shown in the figure. The L1 cache 21 is dedicated to the data processing unit 10, while the L2 cache 22 may be shared with another data processing unit when it is part of a broader data processing system. The data processing unit 10 is also shown to include a branching unit 20, which monitors the execution flow of instruction sequences and attempts to predict whether a given branch will occur based on the previous execution history. The prediction from the branching unit 20 informs the instruction sequence to be fetched by the fetch stage 12.

[0037] The data processing unit 10 further comprises an extension processing circuit 23, which is influential on the data processing operations performed by the data processing unit 10 and is provided to support the efficient implementation of one or more defined functions established to be available from anywhere. Exemplary functions of this type are known to include tasks or functions such as memcpy, memset, compression, encryption, and string processing, but the technique is not limited to these specific embodiments. The extension processing circuit is closely associated with the data processing pipeline and is configured to implement a defined function (also referred to herein as a delegated task) in response to a delegation signal received from the data processing pipeline. The extension processing circuit 23 is an example of a threadlet extension (TE) by the technique. The sequence of operations performed by the extension processing circuit 23 to implement a defined function is referred to herein as a threadlet. Although closely associated with the data processing pipeline, the extension processing circuit 23 is configured to implement the delegated task asynchronously with respect to the data processing operations performed by the data processing pipeline. The data processing pipeline may also be referred to herein as the CPU. A threadlet is a set of functions or actions that, once initiated, can be executed asynchronously with respect to other CPU activity. Instructions or commands sent to the extension processing circuit 23 to initiate a delegated task are generated in response to an extension start instruction defined for this purpose in the instruction set of the data processing pipeline. Thus, while extension start instructions proceed along the data processing pipeline like any other CPU instruction, once the decoding circuit 13 identifies an extension start instruction, it can be directly signaled to the extension processing circuit 23. The close integration of the extension processing circuit 23 and the data processing pipeline is illustrated by the fact that the extension processing circuit 23 can directly access the load / store unit 17 and thus share the data processing pipeline's path to memory.The extended processing circuit 23 can also access a set of registers 16, thereby allowing, for example, an extended start instruction to specify one or more registers as operands, and the values ​​from these registers are then passed directly to the extended processing circuit 23 in connection with the command sent to start the delegated task. Once the task is complete, the result of the delegated task can be returned to the register values ​​via an extended synchronization instruction.

[0038] Figure 2 schematically illustrates a data processing device 30 according to several embodiments. Note that the arrangement of the components of the data processing device 30 is similar to the arrangement of the components of the data processing device 10 shown in Figure 1. One difference is that the data processing device 10 in Figure 1 is intended to represent an in-order processor, while the data processing device 30 is an out-of-order processor. As one result of this, the data processing pipeline of the data processing device 30 includes a rename stage 35, which allows the data processing device 30 to change the order in which it executes instructions in an instruction sequence, so that the instructions in the instruction sequence can be executed in an order determined not by the order in which they appear in the sequence, but by when their operands become available and the availability of functional units. The illustrated pipeline stages include an instruction cache 31, a fetch stage 32, a decode stage 33, a microoperation cache 34, a rename stage 35, an issue stage 36, and a register access stage 37. An instruction sequence is retrieved from memory (not shown) and cached in the instruction cache 31. Instructions pass through the data processing pipeline in the manner described above, referring to the data processing device 10 in Figure 1, and further register renaming is performed by the rename stage 35. The functional units of the data processing pipeline in this embodiment are the load unit 38, the store unit 39, the FPU 41, the integer ALU 42, and the vector unit 43. Since the processing capabilities of the FPU 41, the integer ALU 42, and the vector unit 43 are sufficient, a result cache 44 is provided as an intermediary before the results of their data processing are returned to the register 37. A branch prediction unit 45 is also provided, and its predictions inform the operation of the fetch stage 32.

[0039] The data processing unit 30 further comprises an extension processing circuit ("threadlet extension") 49, which is provided to support the efficient implementation of one or more defined functions established to be influential and ubiquitous to the data processing operations performed by the data processing unit 30. The extension processing circuit 49 is closely associated with the data processing pipeline and is configured to implement the defined functions in response to delegation signals received from the data processing pipeline. In the embodiment of Figure 2, this delegation signal is shown to originate from the issue queue stage 36. In particular, this issue queue stage 36 is located after the rename stage 35, thereby enabling the extension processing circuit 49 to operate with respect to the physical registers of a set of registers 37, according to the same mapping of architectural registers used for the rest of the device. As in the embodiment of Figure 1, the data processing pipeline (from the instruction cache 31 to the register read stage 37, load / store units 38 and 39, and function units 41-45) may also be referred to as the CPU. Once activated, the threadlet extension 49 operates asynchronously with respect to other CPU activity. The instruction or command sent to the extension processing circuit 49 to initiate a delegated task is generated in response to an extension start instruction defined for this purpose in the instruction set of the data processing pipeline. The close integration of the extension processing circuit 49 and the data processing pipeline is evident in this embodiment as well, by the fact that the extension processing circuit 49 can directly access the load unit 38 and the store buffer 40 and thus share the path to the memory of the data processing pipeline. The extension processing circuit 49 can also access a set of registers 37, thereby, for example, an extension start instruction can specify one or more registers as operands, and the values ​​from these registers are then passed directly to the extension processing circuit 49 in connection with the command sent to initiate the delegated task. Note that the output of the branch prediction unit 45 is also supplied to the extension processing circuit 49. Once the task is complete, the result of the delegated task can be returned to a register value via an extension synchronization instruction.

[0040] Figure 3 schematically illustrates a data processing device 50 in several embodiments. This embodiment provides a comparison with the embodiments in Figures 1 and 2, in which the extension processing circuits were so closely integrated into the data processing pipeline that their instances could be considered to reside within the CPU. In the exemplary device 50 of Figure 3, the CPU 51 and the extension processing circuit (threadlet extension) 52 are not so closely integrated. This is illustrated, for example, by the fact that each of the CPU 51 and the threadlet extension 52 has its own path to memory, the L1 cache 53 is dedicated to the CPU 51, and the L1 cache 54 is dedicated to the threadlet extension 52. The L1 caches 53 and 54 share the L2 cache 55. Nevertheless, the threadlet extension 52 remains tightly coupled to the CPU 51 and can be quickly invoked when it encounters an extension start instruction in the CPU pipeline that specifies the function to be performed by the threadlet extension 52. The threadlet extension 52 can obtain data directly from CPU registers at the start of its execution. Once completed, the threadlet extension 52 can return a value via an extended synchronization instruction. Figure 3 also shows the threadlet extension 52 having its own dedicated TLB 56, which the threadlet extension 52 can cache the currently used address translation within the dedicated TLB 56. As a preparatory step prior to or associated with the delegation signal, the contents of the TLB 57 in the CPU 51 can be copied to the dedicated TLB 56 to prewarm this cache before the threadlet starts operating.

[0041] Figure 4 is a state diagram illustrating an exemplary set of states to which an extension processing circuit (TE) transitions in several embodiments. Initially, the TE is in the idle state 60. When the data processing pipeline encounters an extension start (XSTART) instruction, a delegation signal can cause the TE to switch to the setup state 61. This may also require a signal to be asserted indicating that the XSTART instruction has been committed. In the setup state 61, certain actions necessary to prepare the TE can be performed. For example, in embodiments where the TE has a separate path to memory (as in Figure 3), one setup task is to transfer the relevant entries currently in the CPU's TLB to a dedicated TLB in the TE. This allows the TE to perform translations independently at a faster speed than if it were entirely dependent on the existing translation mechanism in the CPU. If the TE was in a clock-gate or power-gate state while in the idle state 60, the setup state 61 may include a task to exit the TE from that clock-gate or power-gate state. Once the setup state 61 is complete, the TE can switch to the running state 62. If the TE encounters a memory failure during its processing, the TE asserts a signal that generates an interrupt in the CPU, causing the CPU to stop execution of the main thread and switch to the handler. The TE switches to interrupt state 63. An indicator of the cause of the failure is stored in a special syndrome system register, the address associated with the failure is stored in the failure address system register, and a bit in the Program Status Register (PSR) is set, enabling the handler to quickly determine the cause of the failure. Setting the bit in the PSR simplifies communication of restarting the threadlet because the handler can reset the corresponding bit in the SPSR, and when the CPSR is restored from the SPSR during an exception return, the TE can detect this bit reset and resume execution. The TE also switches to interrupt state 63 if the main thread is replaced, for example, during a context switch initiated by the operating system.In interrupt state 63, the TE may be clock-gated or power-gated unless some other thread invokes a new command targeting it, the related thread resumes execution, or the handler returns. The TE returns from interrupt state 63 to running state 62 via reload state 64, in which it can restore any context or state related to its execution that was previously stored in memory. This may be the case if another thread uses the previously interrupted TE. Finally, when the extension reaches the end of the offloaded granule (delegated task) of computation, it moves to idle state 60. The TE signals the completion of its task, thereby allowing the extension synchronization instruction (XSYNC) to capture its "complete" signal and, if necessary, provide a return value to the specified register. If the TE has any residual data in its dedicated cache, these entries may need to be flushed upon completion.

[0042] This section describes an example of using threadlets. The programmer or compiler identifies a function whose execution on custom hardware (extension processing circuitry) satisfies the cost-benefit threshold in those use cases. The command is invoked within the specified CPU extension using an instruction (such as XSTART). A pseudocode example of its use (for such an identified function "funcX") is as follows: funcA(){ ... XSTART{x0-x3},#imm_op / / funcX(a,b,c,d); I1 I2 I3 I4 ... XSYNC x0,#imm_op ... }

[0043] Therefore, within function funcA, the XSTART instruction initializes the CPU extension and transfers the parameters (a, b, c, d) of funcX, located in registers x0, x1, x2, and x3 respectively, to the extension processing circuit. In this embodiment, the XSTART instruction also specifies an immediate value #imm_op that defines the specific function to be executed. For example, there may be only one instance of the extension processing circuit, but this instance may be capable of performing two or more functions, or at least two or more variations of a function, and the immediate value #imm_op can select the desired variation and / or function. In other embodiments, there may be two or more instances of the extension processing circuit, and the immediate value #imm_op can select among them. Depending on the setup, the extension may also automatically obtain a copy of the relevant entry in the TLB. The extension processing circuit then executes the required task (funcX), during which the CPU is free to continue executing other instructions I1, I2, I3, I4, etc. At some point in the future, the CPU executes an extension synchronization instruction (XSYNC) to automatically check whether the extension has completed. If not completed, for some variations of the extended synchronization instruction, the CPU waits for the delegated task to complete. Other variations of the extended synchronization instruction (e.g., the XSYNCS variation) allow the CPU to continue executing other code (if there are alternative routines available) or to stop execution and wait for the extension to complete (typically if there is nothing else to execute in the meantime). There are various variations of XSTART and XSYNC proposed herein, which are described in more detail with reference to the following figures.

[0044] Figure 5 schematically illustrates an extended start instruction that delegates a task to an extended processing circuit in several embodiments. Here, the XSTART instruction takes the form XSTART{x0-x7},#imm. Therefore, when the XSTART instruction 100 in this form is decoded by the CPU's decoder 101, it causes the contents of registers x0 to x7 to be retrieved from register 102 and passed to the extended processing circuit 103. In this case, the extended processing circuit 103 can perform multiple types of operations (tasks), and the immediate value #imm (or a signal based on the immediate value #imm) selects one of these.

[0045] Figure 6 schematically illustrates an extension start instruction that delegates a task to one of several instances of an extension processing circuit, according to several embodiments. Here, the XSTART instruction also takes the form XSTART{x0-x7},#imm. However, in this embodiment, there are multiple instances of the extension processing circuit, and the immediate value #imm is used to select among them. Therefore, when this form of the XSTART instruction 105 is decoded by the CPU decoder 106, it causes the contents of registers x0-x7 to be retrieved from register 102. The extension control circuit 108 directs the register values ​​to the selected extension processing circuit 110 based on the immediate value #imm (or a signal based on the immediate value #imm). In this case, the other instances of extension processing circuits 109 and 111 are not activated by this instruction.

[0046] Figure 7 schematically illustrates an extension processing circuit that accepts a delegated task in several embodiments. The data processing pipeline 120 is shown to terminate at a commit stage 121. Instructions passing through this data processing pipeline 120 are ultimately committed if it is definitively known that the instruction should be executed, or canceled if it is established that the instruction should not be executed. For example, when the data processing pipeline follows a prediction about a particular branch made by its branch prediction unit, it can commit any further instructions that were provisionally executed under the assumption that the branch prediction was correct, only when it is determined whether the branch will be taken or not. Here, the XSTART instruction delegates the task to the extension processing circuit 122, but does not commit until the extension processing circuit 122 signals to the data processing pipeline 120 that it has accepted the task. Therefore, if the extension processing circuit is already executing the task or otherwise unavailable, the XSTART instruction effectively stalls.

[0047] Figure 8 schematically illustrates an extension processing circuit that indicates its unavailability to accept a delegated task, in several embodiments. Thus, if the data processing pipeline attempts to delegate a task to the extension processing circuit 130, and the extension processing circuit 130 is already executing the task or is otherwise unavailable, the extension processing circuit 130 indicates its unavailability by setting a flag in a condition register among the set of registers 131. For example, other general-purpose registers 132 that may have provided task parameters if the task had been accepted are not accessed. In some embodiments, the condition register flag may be one or more NZCV flag bits. Setting these bits signals the unavailability of the extension processing circuit 130 to the data processing pipeline, which can then access other code to continue execution, for example, by using a branch instruction sensitive to the relevant flag bits in the condition register 133 to execute a fallback routine. The branch control 134 can then use this input to cause the fetch unit 135 to bypass and access other code for the fallback routine. Therefore, this type of extension start instruction (XSTARTS) is non-blocking and can be committed even if no task has been delegated.

[0048] Figure 9 schematically illustrates an extension start instruction that delegates a task to one of several instances of an extension processing circuit in several embodiments. Here, the XSTART instruction takes the form XSTART{x0-x7},x8. In this embodiment, there are multiple instances of extension processing circuits 154, 155, and 156, and the contents of register x8 are used to select among them. Therefore, when the XSTART instruction 150 in this form is decoded by the CPU's decoder 151, it causes the contents of registers x0-x7 to be retrieved from register 152. Additionally, the contents from register x8 are passed to the extension control circuit 153, which directs the register values ​​x0-x7 to the selected extension processing circuit 156. In this case, the other instances of extension processing circuits 154 and 155 are not activated by this instruction.

[0049] Figure 10 schematically illustrates an extended synchronization instruction (XSYNC) in several embodiments that transfers the results of a delegated task from an extended processing circuit to a set of registers belonging to a data processing pipeline. Here, the XSYNC instruction takes the form XSYNC{x0-x7},#imm. When an XSYNC instruction 100 in this form is decoded by the CPU decoder 161, it first causes the extended control circuit 162 to determine whether a flag 165, which forms part of the result buffer 164 of the extended processing circuit 163, is set to indicate that the extended processing circuit 163 has completed the delegated task and the results are ready. If flag 165 indicates that the task is complete, the extended control circuit 162 causes the results from the result buffer 164 to be passed to registers x0-x7 of the set of registers 166. The use of the immediate value #imm is not explicitly shown in this embodiment, but it can be used to select between multiple instances of the extended processing circuit or to control another aspect of the result collection process. If flag 165 indicates that the task is not complete, the extension control circuit 162 causes the condition register 167 of the set of registers 166 to set the flag, as described above with reference to Figure 8. Thus, the condition register flag can be one or more NZCV flag bits. Setting this flag signals the data processing pipeline that the extension processing circuit 163 has not yet completed the task, and the data processing pipeline can, as a result, access other code to continue execution while waiting, for example by using a branch instruction that is sensitive to the relevant flag bit in the condition register 167. The branch control 168 can then use this input to trigger a branch in the provisional routine of the other code. Thus, this type of extended synchronization instruction (XSYNCS) is non-blocking and can commit even if the task was complete when the instruction was executed.

[0050] Figure 11 schematically illustrates an extension start instruction that delegates a task to one of several instances of an extension processing circuit in several embodiments. Here, the XSTART instruction takes the form XSTART x0,{x1-x7},#imm. In this embodiment, there are multiple instances of extension processing circuits 175, 176, 177, and 178, but the XSTART instruction does not specify which of them should be delegated the task. Instead, register x0 is designated as an indicator of the selected instance of the extension processing circuit to be stored. Thus, when this form of XSTART instruction 170 is decoded by the CPU decoder 171, it causes the contents of registers x1-x7 to be retrieved from register 173. Additionally, the extension control circuit 172 determines which of the instances of the extension processing circuit should receive the task. This can be determined by availability, the relative capabilities of the instances, or other factors. The extension control circuit 172 directs the register values ​​x1 to x7 to the selected extension processing circuit 177 (in this case) and causes the corresponding indicator to be written to register x0 174. The use of the immediate value #imm is not explicitly shown in this embodiment, but it can be used to influence the selection between multiple instances of the extension processing circuit performed by the extension control circuit 172, or to define several aspects of the delegated task.

[0051] Figure 12 schematically illustrates an extended synchronization instruction in several embodiments that transfers the result of a delegated task from one of several instances of an extended processing circuit to a set of registers belonging to a data processing pipeline. Here, the XSYNC instruction takes the form XSYNC x0,{x1-x7}. In this embodiment, there are multiple instances of extended processing circuits 183, 184, and 185, but the XSYNC instruction does not indicate which of them has been delegated the task. Instead, register x0 is designated as the location where an indicator of the selected instance of extended processing circuit 185 is stored. This may have been written there by an XSTART instruction of the type described with reference to Figure 12. Thus, when the XSYNC instruction 180 in this form is decoded by the CPU decoder 181, it causes the contents of register x0 186 to be retrieved from register 187. This tells the extended control circuit 172 which of the instances of the extended processing circuit should be examined to determine which has completed the delegated task. To this end, the extension control circuit 172 checks a flag 188 that the extension processing circuit 185 makes accessible from the outside. If flag 188 indicates that the delegated task is complete, the extension control circuit 182 causes the result to be transferred from buffer 189 to registers x1 to x7 of register set 187. The use of the immediate value #imm in the XSYNC instruction 180 is not shown in this embodiment, but can be added as some form of control over retrieving the delegated task result. Also note that both blocking (XSYNC) and non-blocking (XSYNCS) versions of the instruction in Figure 12 are proposed, and the non-blocking version XSYNCS operates as described with respect to Figure 10.

[0052] Figure 13 schematically illustrates an extended event instruction that, in several embodiments, causes the identifier of one of several instances of an extended processing circuit that has completed a delegated task to be written to a register belonging to the data processing pipeline. This instruction is useful for reducing the cost of software that polls the state of multiple instances of the extended processing circuit to determine which one has completed. Here, the XEVENT instruction takes the form XEVENT x0. Therefore, when the XEVENT instruction 190 in this form is decoded by the CPU decoder 191, it causes the extended control circuit 172 to determine which of the instances of extended processing circuits 193, 194, and 195 has completed the delegated task. To do this, the extension examines the aforementioned flags that each makes available. If one of the instances of extended processing circuits 193, 194, and 195 has completed the delegated task, the extended control circuit 172 returns the identifier of the completed extended processing circuit (in this case, via x0). This makes it easier to incorporate the threadlet model into an event-driven software architecture.

[0053] Figure 14 schematically illustrates an extension processing circuit 202 that, in several embodiments, encounters a memory failure or other processing interruption and signals this event to the data processing pipeline 200. When the illustrated extension processing circuit 202 is in its RUNNING state (see Figure 4), it may encounter an interruption to its processing because the extension processing circuit 202 itself encounters a memory failure during its processing, or because the main thread (executed on the data processing pipeline 200) is switched, for example, during a context switch initiated by the operating system. When such an interruption occurs, the extension processing circuit 202 asserts a signal to the interrupt controller, which generates an interrupt in the CPU (data processing pipeline 200) to cause the CPU to stop the execution of the main thread and switch to the handler. The TE extension processing circuit 202 writes an indication of the cause of the failure to the syndrome register 206 and sets bits in the current program status register (CPSR) 207, enabling the handler to quickly determine the cause of the failure. A handler triggered by an interrupt received from the interrupt controller 205 takes appropriate action to address a memory failure. While the handler is running, or while other switched-in contexts are operating, the contents of the current program status register (CPSR) 207 (since the extension processing circuit 202 was interrupted) are stored in the saved program status register 208. Setting a bit in the CPSR makes it easier to communicate the resumption of the threadlet, as the handler can reset the corresponding bit in the SPSR, and when the CPSR is restored from the SPSR during an exception return, the extension processing circuit 202 can detect this bit reset and resume execution. The extension processing circuit 202 may be clock-gated or power-gated when it is in its INTERRUPTED state, and its control is provided by the clock control 203 and the power control 204.

[0054] Figure 15 is a flowchart showing the sequence of steps taken in the methods of several embodiments. The flow can be considered to begin at step 300, when the data processing pipeline (CPU) enters an ongoing process of fetching, decoding, and executing instruction sequences. In step 301, it is determined whether an extended processing start instruction has been decoded as part of the instruction sequence. If not, the flow simply loops back through step 300. If such an extended processing start instruction is decoded, the flow proceeds to step 302, when the defined processing (defined by the extended processing start instruction) is initiated in the extended processing circuit (here, such an extended processing circuit is assumed to be available to start immediately). Step 303 shows that the extended processing circuit proceeds with its processing asynchronously with respect to the instruction execution of the data processing pipeline. The flow is shown to return to step 300 for the ongoing process of fetching, decoding, and executing instruction sequences for the data processing pipeline to continue. Meanwhile, the asynchronous processing of the extended processing circuit continues until the extended processing circuit completes the task to which it has been delegated.

[0055] Figure 16 schematically illustrates possible implementations of a simulator. While the above embodiments implement the present invention in terms of devices and methods for operating specific processing hardware that supports the technology, it is also possible to provide an instruction execution environment according to the embodiments described herein, which are implemented by the use of a computer program. Such a computer program is often called a simulator, insofar as the computer program provides a software-based implementation of a hardware architecture. Various simulator computer programs include emulators, virtual machines, models, and binary translators, including dynamic binary translators. Typically, a simulator implementation may run on a host processor 515, optionally running a host operating system 510 to support the simulator program 505. In some configurations, there may be multiple layers of simulation between the hardware and the provided instruction execution environment, and / or multiple different instruction execution environments may be provided on the same host processor. Historically, powerful processors have been required to provide simulator implementations that run at reasonable speeds, but such techniques may be justified in certain circumstances, such as when it is desirable to run native code on a different processor for reasons of compatibility or reuse. For example, a simulator implementation may provide an instruction execution environment with additional functionality not supported by the host processor hardware, or it may provide an instruction execution environment typically associated with a different hardware architecture. An overview of the simulation is described in "Some Efficient Architecture Simulation Techniques," Robert Bedichek, Winter 1990 USENIX Conference, Pages 53-63.

[0056] While embodiments have been described with reference to specific hardware components or features, in simulated embodiments, equivalent functionality may be provided by suitable software components or features. For example, certain circuits may be implemented as computer program logic in simulated embodiments. Similarly, memory hardware such as registers or caches may be implemented as software data structures in simulated embodiments. In arrangements where one or more of the hardware elements referenced in the above embodiments reside on host hardware (e.g., host processor 515), some simulated embodiments may, if preferred, utilize the host hardware.

[0057] The simulator program 505 may be stored on a computer-readable storage medium (which may be a non-temporary medium) and provides a program interface (instruction execution environment) to target code 500 (which may include an application, operating system, and hypervisor) that is the same as the interface of the hardware architecture modeled by the simulator program 505. Thus, program instructions of target code 500 can be executed from within the instruction execution environment using the simulator program 505, and for this reason, a host computer 515 that does not actually possess the hardware features of the aforementioned device can emulate these features.

[0058] The concepts described herein may be embodied in computer-readable code for the fabrication of devices that embody the described concepts. For example, the computer-readable code can be used in one or more stages of a semiconductor design and fabrication process, including an electronic design automation (EDA) stage, to fabricate an integrated circuit comprising a device that embodies the concepts. The computer-readable code described herein may additionally or alternatively enable the definition, modeling, simulation, verification, and / or testing of devices that embody the concepts described herein.

[0059] For example, computer-readable code for fabricating a device embodying a concept described herein may be embodyed by code that defines a hardware description language (HDL) representation of the concept. For example, the code may define register-transfer-level (RTL) abstractions of one or more logic circuits for defining a device embodying the concept. The code may define HDL representations of one or more logic circuits embodying the device in Verilog, SystemVerilog, Chisel, or an intermediate representation such as Very High-Speed ​​Integrated Circuit Hardware Description Language (VHDL) and FIRRTL. The computer-readable code may provide definitions that embody the concept using system-level modeling languages ​​such as SystemC and SystemVerilog, or other behavioral representations of the concept that may be interpreted by a computer to enable simulation, functional and / or formal verification, and testing of the concept.

[0060] Additionally or alternatively, computer-readable code may define low-level descriptions of integrated circuit components that embody the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. One or more netlists or other computer-readable representations of integrated circuit components may be generated by applying one or more logic synthesis processes to the RTL representations to generate definitions used for fabricating devices that embody the invention. Alternatively or additionally, one or more logic synthesis processes can generate bitstreams from computer-readable code that are loaded into a field-programmable gate array (FPGA) to configure the FPGA to embody the concepts described herein. The FPGA may be deployed for the purpose of verifying and testing the concept before fabrication in an integrated circuit, or the FPGA may be deployed directly into a product.

[0061] Computer-readable code may include a mixture of code representations for the fabrication of a device, for example, a mixture of one or more RTL representations, netlist representations, or other computer-readable definitions used in semiconductor design and fabrication processes for fabricating a device embodying the present invention. Alternatively or additionally, the concept may be defined as a combination of computer-readable definitions used in semiconductor design and fabrication processes for fabricating a device and computer-readable code that defines instructions to be executed by the device once it is fabricated.

[0062] Such computer-readable code may be placed on any known temporary computer-readable medium (such as wired or wireless transmission of code over a network) or on a non-temporary computer-readable medium such as a semiconductor, magnetic disk, or optical disk. An integrated circuit fabricated using computer-readable code may include components such as a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or one or more other components that individually or collectively embody a concept.

[0063] A concise overall overview discloses an apparatus, a data processing method, a computer program, and a computer-readable medium. The data processing pipeline performs data processing operations in response to an incoming instruction sequence. An extension processing circuit is closely associated with the data processing pipeline and performs a defined task in response to a delegation signal received from the data processing pipeline. Decoding the incoming instruction sequence generates control signals to control the data processing pipeline to perform data processing operations. Decoding, in response to an extension start instruction specifying the delegated task, issues a delegation signal to the extension processing circuit, generating control signals to control the data processing pipeline to delegate the delegated task to the extension processing circuit. The extension processing circuit performs the delegated task asynchronously with respect to the data processing operations performed by the data processing pipeline.

[0064] In this application, the phrase "configured to..." is used to mean that an element of the device has a configuration that enables it to perform a defined operation. In this context, "configuration" means the arrangement or interconnection of hardware or software. For example, the device may have dedicated hardware to provide the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that an element of the device must be modified in any way to provide the defined operation.

[0065] While exemplary embodiments have been described in detail in this specification with reference to the accompanying drawings, it should be understood that the present invention is not limited to embodiments identical thereto, and various changes, additions, and modifications can be made by those skilled in the art without departing from the scope and spirit of the invention as defined in the appended claims. For example, various combinations of the features of the dependent claims can be made together with the features of the independent claims without departing from the scope of the invention.

Claims

1. A device for data processing, A data processing pipeline configured to perform data processing operations in response to a received command sequence, The system includes an extension processing circuit associated with the data processing pipeline and configured to perform a delegated task in response to a delegation signal received from the data processing pipeline, The data processing pipeline includes a decoding circuit configured to decode the received instruction sequence and generate control signals to control the data processing pipeline to perform the data processing operation. The decoding circuit responds to an extended start command specifying the delegated task, The delegation signal is issued to the extension processing circuit to generate the control signal for controlling the data processing pipeline to delegate the delegated task to the extension processing circuit, An apparatus in which the extended processing circuit is configured to perform the delegated task asynchronously with respect to the data processing operations performed by the data processing pipeline.

2. The apparatus according to claim 1, wherein the data processing pipeline comprises a set of registers for holding data values ​​on which the data processing operation is performed.

3. The apparatus according to claim 2, wherein the data processing pipeline is configured to transfer at least one data value from at least one register of the set of registers to the extension processing circuit in connection with the delegation signal.

4. The extension start instruction specifies at least one register from the set of registers, and the decoding circuit responds to the extension start instruction, The apparatus according to claim 3, which generates the control signal for controlling the data processing pipeline to pass the at least one data value from the at least one register of the set of registers to the extension processing circuit.

5. The aforementioned extended start command further specifies an operation identifier, and the operation identifier is Extended processing circuit identifier, and / or The apparatus according to any one of claims 1 to 4, which identifies at least one of the delegated task identifiers.

6. The apparatus according to claim 5, which is dependent on claim 2, wherein the extended start instruction specifies a register among the set of registers from which the operation identifier is extracted.

7. The apparatus according to claim 5, wherein the extended start command specifies the operation identifier as an immediate value.

8. The data processing pipeline includes a commit step in which an irreversible change in the state of the device occurs when the executed instructions from the received instruction sequence are committed, The apparatus according to any one of claims 1 to 7, wherein the data processing pipeline is configured to suppress committing the extension start instruction until the extension processing circuit accepts the delegated task.

9. The apparatus according to claim 2, or according to any one of claims 1 to 8 as dependent on claim 2, wherein the data processing pipeline sets at least one unavailable condition flag in a condition register of the set of registers in response to an unavailable signal from the extended processing circuit relating to the delegated task.

10. The apparatus according to claim 9, wherein the data processing pipeline, in response to the setting of at least one unavailable condition flag, deviates from the received instruction sequence to retrieve a fallback instruction set and performs a fallback data processing operation set according to the fallback instruction set.

11. The decoding circuit responds to the extended synchronization command, The extended processing circuit generates the control signal for determining whether the delegated task has been completed. The apparatus according to claim 2, or according to any one of claims 1 to 10 as dependent on claim 2, wherein when the extension processing circuit has completed the delegated task, the apparatus generates the control signal for controlling the extension processing circuit to pass at least one result data value to at least one result register of the set of registers.

12. The apparatus according to claim 11, wherein the extended synchronization instruction specifies at least one result register from the set of registers.

13. The apparatus according to claim 11 or 12, wherein the data processing pipeline sets at least one incomplete condition flag in a condition register among the set of registers in response to a determination that the extended processing circuit has not completed the delegated task.

14. The apparatus according to claim 13, wherein the data processing pipeline, in response to the setting of at least one incomplete condition flag, deviates from the received instruction sequence to retrieve an alternative instruction set and performs a further set of data processing operations according to the alternative instruction set.

15. The system further includes multiple instances of an extension processing circuit associated with the data processing pipeline, each instance capable of performing the delegated task in response to the delegated signal received from the data processing pipeline. The extension start instruction specifies an allocated extension register from the set of registers, and the decoding circuit responds to the extension start instruction, The delegated task is assigned to a selected instance of the extended processing circuit. The apparatus according to claim 2, or according to any one of claims 1 to 14 as dependent on claim 2, which generates the control signal for controlling the data processing pipeline to write the identifier of the selected instance of the extension processing circuit to the assigned extension register.

16. The extended synchronization instruction specifies the assigned extended register from the set of registers, and the decoding circuit responds to the extended synchronization instruction, The selected instance of the extension processing circuit, indicated by the assigned extension register, generates the control signal for determining whether it has completed the delegated task. The apparatus according to claim 11, or according to any one of claims 1 to 15 as dependent on claim 11, wherein when the selected instance of the extended processing circuit is completing the delegated task, the apparatus generates the control signal for generating the control signal for controlling the selected instance of the extended processing circuit, such that the at least one result data value is passed to the at least one result register of the set of registers.

17. This includes a plurality of instances of an extension processing circuit associated with the data processing pipeline, each instance capable of performing the delegated task in response to the delegated signal received from the data processing pipeline. The decoding circuit responds to an extended event instruction that specifies an event instruction register from the set of registers, The control signals for controlling the data processing pipeline are generated to identify instances of the extended processing circuit that have completed the delegated task, The apparatus according to claim 2, or according to any one of claims 1 to 16 as dependent on claim 2, which generates a control signal for writing an identifier of an instance of the extension processing circuit that has completed the delegated task into the event instruction register.

18. Load / store queue and The system further comprises a private cache for the aforementioned data processing pipeline, The apparatus according to any one of claims 1 to 17, wherein the expansion processing circuit is configured to perform memory access via the load / store queue and the private cache.

19. Extended processing circuit private cache, The apparatus according to any one of claims 1 to 17, further comprising an extended processing circuit address translation buffer.

20. The apparatus according to claim 19, wherein the extension processing circuit is configured to flush the extension processing circuit private cache upon completion of the delegated task.

21. The system further comprises an address translation buffer configured to cache address translations used by the data processing pipeline, The apparatus according to claim 19 or 20, wherein the data processing pipeline is configured to copy the contents of the address translation buffer to the extension processing circuit address translation buffer when the delegated task is delegated to the extension processing circuit.

22. The aforementioned extended processing circuit responds to the interruption of the delegated task, To indicate the interruption of the delegated task, set the interrupt bit in the current program status register of the set of registers: If the interruption of the delegated task is caused by a memory failure, the apparatus according to claim 2, or any one of claims 1 to 21 as dependent on claim 2, writes an indication of the source of the failure to a syndrome system register among the set of registers, and asserts an interrupt signal for the data processing pipeline.

23. If the interruption of the delegated task is caused by a context switch in the data processing pipeline, the data processing pipeline is configured to perform further data processing operations defined by a new context instruction sequence. If the interruption of the delegated task is caused by the memory failure, the data processing pipeline is configured to perform further data processing operations defined by the exception handling instruction sequence. When setting up the further data processing operations to be performed, the device is configured to copy the current program status register to a stored program status register. When the data processing pipeline returns to the data processing operation defined by the received instruction sequence, the data processing pipeline is configured to clear the interrupt bit in the stored program status register and copy the stored program status register to the current program status register. The apparatus according to claim 22, wherein the extension processing circuit resumes the suspended delegated task in response to the cleared suspended bit in the current program status register.

24. When the extended processing circuit is not actively performing the delegated task, the extended processing circuit: Being clock-gated, and / or It is configured to be power-gated, The apparatus according to any one of claims 1 to 23.

25. The aforementioned expansion processing circuit includes a data buffer, and the data buffer is The data processing results of the delegated task, and / or The apparatus according to any one of claims 1 to 24, configured to hold an extended processing circuit status indicator.

26. A non-temporary computer-readable medium for storing computer-readable codes, for the manufacture of the apparatus according to any one of claims 1 to 25.

27. A data processing method, In response to the received instruction sequence, data processing operations are performed in the data processing pipeline. In response to a delegation signal received from the data processing pipeline, the delegated task is performed in the extended processing circuit associated with the data processing pipeline. Decoding the received instruction sequence in a decoding circuit in order to generate a control signal for controlling the data processing pipeline to perform the aforementioned data processing operation, The decoding described above occurs in response to an extended start command specifying the delegated task, Decoding, which involves issuing the delegation signal to the extension processing circuit to generate the control signal for controlling the data processing pipeline to delegate the delegated task to the extension processing circuit, A method comprising performing the delegated task in the extended processing circuit asynchronously with respect to the data processing operations performed by the data processing pipeline.

28. A computer program for controlling a host data processing device to provide an instruction execution environment, A data processing pipeline logic for performing data processing operations according to the received command sequence, Includes extended processing logic associated with the data processing pipeline logic and configured to perform delegated tasks in response to delegation signals received from the data processing pipeline logic, The data processing pipeline logic includes a decoding logic configured to decode the received instruction sequence and generate control signals to control the data processing pipeline logic to perform the data processing operation. The decoding circuit responds to an extended start command specifying the delegated task, The delegation signal is issued to the extended processing logic to generate a control signal for controlling the data processing pipeline logic to delegate the delegated task to the extended processing logic, A computer program in which the extended processing logic is configured to perform the delegated task asynchronously with respect to the data processing operations performed by the data processing pipeline logic.

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