An integrated circuit (IC) package and related manufacturing method employing a metal block in which metal interconnects thermally bond the die to an interposer substrate in order to dissipate the die's thermal energy.

Abstract

Embodiments disclosed in “Modes for Carrying Out the Invention” include an integrated circuit (IC) package employing a metal block in which metal interconnects thermally bond the die to an interposer substrate in order to dissipate thermal energy within the semiconductor die ("die"). The die is bonded to a package substrate that provides a signal routing path to the die. To facilitate the stacking of additional dies within the IC package as a three-dimensional (3D) IC (3DIC) package, the IC package also includes an interposer substrate adjacent to the die. The interposer substrate supports providing additional signal routing paths to the package substrate. The interposer substrate also comprises a plurality of metal layers and includes a metal block thermally bonded to the die and the metal interconnects (one or more) in the interposer substrate in order to dissipate thermal energy from the die via the metal block and via bonded metal interconnects (one or more).

Description

Technical Field

[0001] (Priority Application) This application claims priority to U.S. Patent Application No. 18 / 330,435, filed Jun. 7, 2023, entitled "INTEGRATED CIRCUIT (IC) PACKAGE EMPLOYING A METAL BLOCK WITH METAL INTERCONNECTS THERMALLY COUPLING A DIE TO AN INTERPOSER SUBSTRATE FOR DISSIPATING THERMAL ENERGY OF THE DIE, AND RELATED FABRICATION METHODS", the entire disclosure of which is incorporated herein by reference.

Background Art

[0002] I. Field of the Disclosure The field of the present disclosure relates to integrated circuit (IC) packages, and more particularly, to the design and fabrication of IC packages for dissipating thermal energy from semiconductor die(s) within the IC package.

[0003] II. Background Integrated circuits (ICs) are the foundation of electronic devices. ICs are packaged in IC packages, also called “semiconductor packages” or “chip packages.” An IC package contains one or more semiconductor dies ("dies" or “dice") mounted on a package substrate that provides physical support and an electrical interface to the dies(s) and electrically coupled. The package substrate contains one or more metallization layers, including metal interconnects (e.g., metal traces, metal wires), and vias provide an electrical interface between dies(s) by coupling metal interconnects together between adjacent metallization layers. Dies(s) are electrically interfaced to metal interconnects exposed in the upper or outer metallization layers of the package substrate in order to electrically couple the dies(s) to the metal interconnects of the package substrate. For example, the package substrate may include a laminate or embedded trace substrate (ETS) layer electrically coupled adjacent to the die to provide a signal routing path to the die. Metal interconnects in the outer metallization layer of the package substrate are coupled to other metal interconnects in other lower metallization layers within the package substrate to provide a signal routing path to the coupled die.

[0004] Some IC packages are known as “hybrid” IC packages, which include multiple die packages, each with its own die for a different purpose or application. For example, a hybrid IC package may contain an application die, such as a communication modem or processor (including a system). A hybrid IC package may also include one or more memory dies that provide memory to support data storage and data access by the application die. Multiple dies can be arranged within a single die layer and positioned adjacent to each other horizontally on the package substrate within the IC package. Multiple dies can also be provided within their own die packages, stacked on top of each other in a three-dimensional (3D) configuration as an overall 3DIC package. Dies within a die layer are typically housed in an epoxy molding compound (EMC) to protect them. 3DIC packages may be desirable to reduce the package cross-sectional area. In a 3DIC package, a first bottom die, directly supported on the package substrate, is electrically coupled to the metallization layer of the package substrate via die interconnects to provide signal routing paths for the dies within the package substrate. Other stacked dies within a 3DIC package that are not directly adjacent to the package substrate can be electrically coupled to the package substrate by wire bonds and / or intermediate interposers to provide die-to-die (D2D) connections between multiple stacked dies. In addition to protecting the dies, EMC provides some thermal dissipation of the thermal energy generated by the first bottom die.

[0005] Currently, dies within IC packages are improving in both functionality and operating speed. As die functionality / speed improves, the thermal energy generated within the die typically increases, potentially exceeding the heat dissipation capacity of the IC package. Improved die functionality or speed leads to the need to dissipate the thermal energy generated within the die. Efficient dissipation of thermal energy can be particularly important in 3DIC packages, which contain multiple stacked dies, each generating heat. [Overview of the project] [Means for solving the problem]

[0006] Embodiments disclosed in “Modes for Carrying Out the Invention” include an integrated circuit (IC) package employing a metal block in which metal interconnects thermally bond the die to an interposer substrate in order to dissipate thermal energy within the semiconductor die ("die"). Related manufacturing methods are also disclosed. The IC package includes a die layer containing a die bonded to a package substrate to provide signal routing paths to the die. For example, to facilitate the stacking of additional dies within the IC package as a three-dimensional (3D) IC (3DIC) package, the IC package also includes an interposer substrate adjacent to the die. The interposer substrate supports providing additional signal routing paths to the package substrate for external connections and / or die-to-die (D2D) connections. In exemplary embodiments, the interposer substrate also includes a metal block comprising a plurality of metal layers and thermally bonded to the die and metal interconnects (one or more) (e.g., metal traces, metal pads, metal wires, metal plates) within the interposer substrate. In this way, when thermal energy is generated within the die, this thermal energy is dissipated from the die through the metal block and through the connected metal interconnects (one or more) to the outside of the interposer substrate. Therefore, metal interconnects and metal layers, which are structures available in the interposer substrate manufacturing process, are provided to provide heat dissipation to the die within the IC package.

[0007] In this regard, in one exemplary embodiment, an IC package is provided. The IC package comprises a first package substrate and an interposer substrate extending in a first direction. The interposer substrate includes a first side surface and a second side surface opposite to the first side surface in a second direction perpendicular to the first direction. The interposer substrate also includes a metal block comprising a plurality of metal layers, a plurality of first metal interconnects adjacent to the first side surface and coupled to the metal block, and a plurality of second metal interconnects adjacent to the second side surface and coupled to the first package substrate. The IC package also comprises a first die, coupled to the first package substrate, between the first package substrate and the second side surface of the interposer substrate in a second direction. In one embodiment, the metal block may be coupled to the metal interconnects via metal vias. In another embodiment, the plurality of metal layers are sufficient to directly couple the metal block to the metal interconnects.

[0008] In another embodiment, a method for manufacturing an IC package is provided. The method for manufacturing an integrated circuit (IC) package includes forming a first package substrate; forming an interposer substrate having a first side surface extending in a first direction and having a second side surface opposite to the first side surface in a second direction perpendicular to the first direction. Forming the interposer substrate includes forming a metal block having a plurality of metal layers; forming a plurality of first metal interconnects adjacent to the first side surface and coupled to the metal block; and forming a plurality of second metal interconnects adjacent to the second side surface and coupled to the first package substrate. The method for manufacturing an IC package further includes arranging a first die coupled to the first package substrate between the first package substrate and the second side surface of the interposer substrate in a second direction. [Brief explanation of the drawing]

[0009] [Figure 1]This is a side view of an integrated circuit (IC) package including a die and an interposer substrate having a core layer adjacent to the die. The core layer includes a metal block, and a first metal interconnect thermally bonds the die to the interposer substrate in order to dissipate the thermal energy of the die. [Figure 2A] This is a side view of an IC package, in which the interposer substrate includes a core layer comprising a metal block having a metal layer coupled to a first metal interconnect via metal vias to dissipate the thermal energy of the die. [Figure 2B] This is an enlarged side view of the IC package in Figure 2A, along the cutting line A1-A2 in Figure 2A. [Figure 2C] This is an enlarged side view of Figure 2B, showing measurements of the structure within the core layer. [Figure 3A] This is a side view of an IC package, in which the core layer includes a metal block having multiple metal layers directly bonded to a first metal interconnect to dissipate the thermal energy of the die. [Figure 3B] This is an enlarged side view of the IC package in Figure 3A along the cutting line B1-B2. [Figure 3C] This is an enlarged side view of Figure 2B, showing multiple metal layers of a metal block. [Figure 4] This flowchart illustrates an exemplary manufacturing process for producing an IC package that includes an interposer substrate, thermally coupled to a first die via a metal block to dissipate thermal energy within the first die, as shown in Figures 1, 2A-2C, and 3A-3C. [Figure 5A] This flowchart shows another exemplary manufacturing process for producing an interposer substrate having multiple metal layers and including a metal block directly bonded to a first metal interconnect to dissipate the thermal energy of the die. [Figure 5B] This flowchart shows another exemplary manufacturing process for producing an interposer substrate having multiple metal layers and including a metal block directly bonded to a first metal interconnect to dissipate the thermal energy of the die. [Figure 5C]This flowchart shows another exemplary manufacturing process for producing an interposer substrate having multiple metal layers and including a metal block directly bonded to a first metal interconnect to dissipate the thermal energy of the die. [Figure 5D] This flowchart shows another exemplary manufacturing process for producing an interposer substrate having multiple metal layers and including a metal block thermally bonded to a first metal interconnect to dissipate the thermal energy of the die. [Figure 5E] This flowchart shows another exemplary manufacturing process for producing an interposer substrate having multiple metal layers and including a metal block thermally bonded to a first metal interconnect to dissipate the thermal energy of the die. [Figure 6A] Figures 5A to 5C show exemplary manufacturing stages during the production of an interposer substrate, according to the manufacturing process. [Figure 6B] Figures 5A to 5C show exemplary manufacturing stages during the production of an interposer substrate, according to the manufacturing process. [Figure 6C] Figures 5A to 5C show exemplary manufacturing stages during the production of an interposer substrate, according to the manufacturing process. [Figure 6D-1] Figures 5A to 5C show exemplary manufacturing stages during the production of an interposer substrate, according to the manufacturing process. [Figure 6E-1] Figures 5A to 5C show exemplary manufacturing stages during the production of an interposer substrate, according to the manufacturing process. [Figure 6F-1] Figures 5A to 5C show exemplary manufacturing stages during the production of an interposer substrate, according to the manufacturing process. [Figure 6G-1] Figures 5A to 5C show exemplary manufacturing stages during the production of an interposer substrate, according to the manufacturing process. [Figure 6H-1] Figures 5A to 5C show exemplary manufacturing stages during the production of an interposer substrate, according to the manufacturing process. [Figure 6I-1] Figures 5A to 5C show exemplary manufacturing stages during the production of an interposer substrate, according to the manufacturing process. [Figure 6D-2]Exemplary manufacturing stages during the manufacturing of an interposer substrate according to the manufacturing process of FIGS. 5D to 5E. [Figure 6E-2] Exemplary manufacturing stages during the manufacturing of an interposer substrate according to the manufacturing process of FIGS. 5D to 5E. [Figure 6F-2] Exemplary manufacturing stages during the manufacturing of an interposer substrate according to the manufacturing process of FIGS. 5D to 5E. [Figure 6G-2] Exemplary manufacturing stages during the manufacturing of an interposer substrate according to the manufacturing process of FIGS. 5D to 5E. [Figure 7A] A flowchart showing an exemplary assembly process for assembling an IC package that employs a metal block in which metal interconnects thermally couple a die to an interposer substrate to dissipate the die's thermal energy. [Figure 7B] A flowchart showing an exemplary assembly process for assembling an IC package that employs a metal block in which metal interconnects thermally couple a die to an interposer substrate to dissipate the die's thermal energy. [Figure 7C] A flowchart showing an exemplary assembly process for assembling an IC package that employs a metal block in which metal interconnects thermally couple a die to an interposer substrate to dissipate the die's thermal energy. [Figure 8A] Exemplary assembly stages during the assembly process of the IC package of FIGS. 7A to 7C. [Figure 8B] Exemplary assembly stages during the assembly process of the IC package of FIGS. 7A to 7C. [Figure 8C] Exemplary assembly stages during the assembly process of the IC package of FIGS. 7A to 7C. [Figure 8D] Exemplary assembly stages during the assembly process of the IC package of FIGS. 7A to 7C. [Figure 8E] Exemplary assembly stages during the assembly process of the IC package of FIGS. 7A to 7C. [Figure 8F]Figures 7A to 7C show exemplary assembly stages in the IC package assembly process. [Figure 9] This is a block diagram of an exemplary wireless communication device, including, but not limited to, the IC packages shown in Figures 1, 2A, 2C and 3A, 3C, by exemplary manufacturing and assembly processes shown in Figures 4, 5A-5E, 6A-6G-2, 7A-7C and 8A-8F, and including radio-frequency (RF) components deployed within an IC package employing an interposer substrate that includes a metal block, where metal interconnects thermally bond the die to the interposer substrate in order to dissipate the thermal energy of the die. [Figure 10] This is a block diagram of an exemplary processor-based system, including, but not limited to, the IC packages of Figures 1, 2A, 2C and 3A, 3C, manufactured and assembled according to the exemplary manufacturing and assembly processes of Figures 4, 5A-5E, 6A-6G-2, 7A-7C and 8A-8F, and including components deployed within an IC package employing an interposer substrate that includes a metal block, where metal interconnects thermally bond the die to the interposer substrate in order to dissipate the thermal energy of the die. [Modes for carrying out the invention]

[0010] Next, several exemplary embodiments of this disclosure will be described with reference to the drawings. The term “exemplary” is used herein to mean “serving as an example, case, or illustration.” No embodiment described herein as “exemplary” should be construed as necessarily preferable or advantageous to any other embodiment.

[0011] Embodiments disclosed in “Modes for Carrying Out the Invention” include an integrated circuit (IC) package employing a metal block in which metal interconnects thermally bond the die to an interposer substrate in order to dissipate thermal energy within the semiconductor die ("die"). Related manufacturing methods are also disclosed. The IC package includes a die layer containing a die bonded to a package substrate to provide signal routing paths to the die. For example, to facilitate the stacking of additional dies within the IC package as a three-dimensional (3D) IC (3DIC) package, the IC package also includes an interposer substrate adjacent to the die. The interposer substrate supports providing additional signal routing paths to the package substrate for external connections and / or die-to-die (D2D) connections. In exemplary embodiments, the interposer substrate also includes a metal block comprising a plurality of metal layers and thermally bonded to the die and metal interconnects (one or more) (e.g., metal traces, metal pads, metal wires, metal plates) within the interposer substrate. In this way, when thermal energy is generated within the die, this thermal energy is dissipated from the die through the metal block and through the connected metal interconnects (one or more) to the outside of the interposer substrate. Therefore, metal interconnects and metal layers, which are structures available in the interposer substrate manufacturing process, are provided to provide heat dissipation to the die within the IC package.

[0012] In this regard, Figure 1 is a side view of an integrated circuit (IC) package 100, which includes a die 102 and an interposer substrate 104 adjacent to the die 102, having a core layer 106. The core layer 106 includes a metal block 108, and a first metal interconnect 110 thermally bonds the die 102 to the interposer substrate 104 in order to dissipate the heat energy of the die 102. The metal block 108 and the first metal interconnect 110, as well as the manner in which the metal block 108 is bonded to the first metal interconnect 110, will be described in more detail in connection with the description of Figures 2 and 3.

[0013] As used in this application, “adjacent” objects refer to objects that are adjacent to another object, on another object, or next to another object with an intervening space between them. Adjacent objects may not be physically connected to one another. Directly adjacent objects mean that such objects are directly adjacent to one another, and no other object is intervening or positioned between them. Indirectly adjacent objects mean that such objects are not directly adjacent to one another, and no other object is intervening or positioned between them.

[0014] The interposer substrate 104 extends in a first horizontal direction (one or more) (X-axis direction and / or Y-axis direction (one or more)) and includes a first side surface 112 and a second side surface 114 opposite to the first side surface 112 in a second direction (Z-axis direction) perpendicular to the first direction. The first metal interconnect 110 is adjacent to the first side surface 112 of the interposer substrate 104. When thermal energy is generated in the die 102, this thermal energy is dissipated through the metal block 108 and the first metal interconnect 110.

[0015] Outside the periphery of the metal block 108 (shown to the left and right of the metal block 108 within the core layer 106 in Figure 1), the interposer substrate 104 includes metal layers 116, each using routing metal interconnects (e.g., metal traces, metal wires, metal pads) for providing signal and / or power routing through the interposer substrate 104. The metal layers 116 include metal interconnects 117 on a first side surface 112 of the interposer substrate 104 and metal interconnects 118 on a second side surface 114 of the interposer substrate 104. Signal and / or power routing between indirectly adjacent metallization layers within the interposer substrate 104 is provided by metal vias (not shown), which are vertical metal interconnects extending in a second vertical direction (Z-axis direction). The interposer substrate 104 is electrically coupled to a first die layer 122, which includes a die 102 bonded to a package substrate 120 via metal interconnects 117 and 118.

[0016] For example, the package substrate 120 may be a laminate substrate or an embedded trace substrate (ETS). The package substrate 120 includes a plurality of metallization layers (not shown), each of which includes a respective metal interconnect (e.g., metal traces, metal wires, metal pads) (not shown) to provide signal routing to a die 102 in a first die layer 122 coupled to the package substrate 120. The metallization layers are parallel to each other, directly adjacent to each other, and extend in a first horizontal direction (one or more) (X-axis direction and / or Y-axis direction (one or more)). The die 102 is located between the package substrate 120 and the interposer substrate 104, extends in a first horizontal direction (one or more) (X-axis direction and / or Y-axis direction (one or more)), and is electrically coupled to the package substrate 120 by a die interconnect 124. The package substrate 120 is configured to provide signal routing and / or power routing paths to the IC package 100 through the coupling of its metal interconnects in its respective metallization layers between the die 102 and the external interconnects 126 (e.g., solder balls, ball grid array (BGA) interconnects, etc.).

[0017] As shown in Figure 1, the external interconnect 126 is located on the land side surface 128 of the package substrate 120. The IC package 100 is also positioned to provide electrical coupling between the interposer substrate 104 and the package substrate 120. This is to allow, for example, in the IC package 100, signal routing to be provided between one or more second dies 130A-130D coupled to the interposer substrate 104 and the package substrate 120 and / or the external interconnect 126. In this regard, vertical interconnects 132 (e.g., metal posts, metal pillars, metal balls) are located within the lower first die layer 122, surrounded by a molding compound 134, and coupled to (not shown) metal vias in the interposer substrate 104 and the package substrate 120 to provide electrical coupling between the interposer substrate 104 and the package substrate 120.

[0018] Continuing to refer to Figure 1, the external interconnectors 136A-136L (e.g., metal posts, metal pillars, metal balls) connect the package 138 to the interposer substrate 104. The package 138 includes the package substrate 140. In this example, the external interconnectors 136A-136C and 136J-136L, including the metal layer 116 and the vertical interconnector 132, electrically route signal lines and / or power lines from the second die(s) 130A-130D to the package substrate 120 via the interposer substrate 104. The external interconnectors 136A-136C and 136J-136L are also referred to as routing balls in this specification. On the other hand, the external interconnects 136D to 136I are directly connected to the first metal interconnect 110 and are thermally coupled to the metal block 108 without carrying signal or power lines; these are referred to herein as dummy balls. Furthermore, the dummy balls 136D to 136I are connected to the package 138. As used herein, the term “thermally coupled” means that thermal energy is drawn from a heat source to a heat sink, or from an intermediate conduit for thermal energy to a heat sink.

[0019] Figure 2A is a side view of the IC package 200, in which the interposer substrate 104 includes a core layer 202. The core layer 202 includes a metal block 204 having a metal layer 206 coupled to a first metal interconnect 110 via metal vias 208 to dissipate thermal energy from the die 102. Common elements between the IC package 200 in Figures 2A-2C and the IC package 100 in Figure 1 are indicated by common element numbers.

[0020] Figure 2B is an enlarged side view of the IC package 200 of Figure 2A along the cutting line A1-A2 of Figure 2A.

[0021] Figure 2C is an enlarged side view of Figure 2B showing measurements of the structure of the core layer 202. The core layer 202 includes metal layer 1 210 and metal layer 2 212. Metal layer 1 210 includes metal pads, metal traces, and metal wires. The metal block 204 includes portions of metal layer 2 212 that are directly adjacent to portions of metal layer 1 210 in a second vertical direction (Z-axis direction). The core layer 202 also includes insulating openings 214A and 214B within the insulating layer 216, which are directly adjacent to metal interconnects 218 (e.g., metal pads) within the metal layer 1 210. The insulating opening 214A has a width W1 and is 0.21 millimeters (millimeters, mm). The width W2 between insulating opening 214A and insulating opening 214B, also known as the pitch, is 0.35 mm. The metal interconnect 218 has a width W3, which is 0.15 to 0.25 mm. The metal post 220 is directly adjacent to the metal interconnect 218 in a second vertical direction (Z-axis direction) and has a width W4. The width W4 is generally 0.02 mm smaller than W3. The metal layer 6 222 includes metal pads such as the metal pad 224 and the first metal interconnect 110, metal traces, and metal wires. The insulating layer 228 is directly adjacent to the metal layer 6 222 in a second vertical direction (Z-axis direction) and includes openings 230A to 230F having a width W5. The insulating openings 230D-230F directly adjacent to the first metal interconnect 110 in the second vertical direction (Z-axis direction) have the same width W5 as the insulating openings 230A-230C directly adjacent to the metal pad 224 in the second vertical direction (Z-axis direction) for arranging dummy balls during the assembly process, as described in relation to Figure 6. The width W5 is 0.23 mm. The width W6 between consecutive insulating openings 230A-230F, such as between insulating opening 230B and insulating opening 230C, is also known as the pitch and is 0.40 mm. Metal vias 232 and 208 connect structures in metal layer 6 222 to structures in metal layer 2 212. Metal vias 232 connect metal interconnects 117, such as the metal pad 224, to metal interconnects 118 via metal posts 220.Once the core layer 202 is deployed within the IC package 200, the metal vias 232 electrically couple the second die 130 to the first package substrate 120 via metal interconnects 118, including vertical interconnects 132 and metal interconnects 218. The metal vias 208 couple the first metal interconnect 110 to the metal block 204. The metal vias 232 and 208 have a length L1, which is between 0.015 mm and 0.03 mm.

[0022] Figure 3A is a side view of the IC package 300, in which the core layer 302 includes a metal block 304 having multiple metal layers 306 that are directly bonded to the first metal interconnect 110 in order to dissipate the thermal energy of the die 102. Common elements between the IC package 300 in Figures 3A to 3C and the elements of the IC package 100 in Figure 1 and the IC package 200 in Figures 2A to 2C are indicated by common element numbers.

[0023] Figure 3B is an enlarged side view of the IC package in Figure 3A along the cutting line B1-B2.

[0024] Figure 3C is an enlarged side view of the core layer 302 of Figure 3B, showing multiple metal layers 306 of the metal block 304. In addition to metal layer 1 210 and metal layer 2 210, the metal layers 306 of the metal block 304 include metal layer 3 308, metal layer 4 310, and metal layer 5 312. The core layer 302 also includes insulating openings 314A, 314B within the insulating layer 316, which are directly adjacent to the metal interconnects 318 (e.g., metal pads) in metal layer 1 210. Metal posts 320 are directly adjacent to the metal interconnects 318 (e.g., metal pads) in a second vertical direction (Z-axis direction). Metal vias 332 connect metal interconnects 117, such as metal pads 324, to metal interconnects 118, such as metal interconnects 318, via metal posts 320. Once the core layer 302 is deployed within the IC package 300, the metal vias 332 electrically couple the second die 130 to the first package substrate 120 via metal interconnects 118, including the vertical interconnect 132 and the metal interconnect 318.

[0025] Interposer substrates including core layers 106, 202, and 302 in the related IC packages 100, 200, and 300 in Figures 1, 2A-2C, and 3A-3C, respectively, which employ a metal block thermally bonded to the first die to dissipate the thermal energy of the first die, can be manufactured using different manufacturing processes. In this regard, Figure 4 is a flowchart illustrating an exemplary manufacturing process 400 for manufacturing an IC package including an interposer substrate 104 thermally bonded to the first die 102 via a metal block 108 to dissipate thermal energy within the first die 102, as an example, including the interposer substrate 104 in Figures 1, 2A-2C, and 3A-3C.

[0026] The manufacturing process 400 in Figure 4 is described in conjunction with the interposer substrate 104 in Figures 1, 2A-2C, and 3A-3C, but it should be noted that this description is not limiting. In this regard, the first exemplary step in the manufacturing process 400 in Figure 4 may include forming the first package substrate 120 (block 402). The next step in the manufacturing process 400 may include forming the interposer substrate 104 (block 404), which extends in a first direction and has a first side surface 112 and a second side surface 114 opposite to the first side surface 112 in a second direction perpendicular to the first direction. Forming the interposer substrate includes forming metal blocks 108, 204, 304 having a plurality of metal layers 206, 306 (block 406), forming a plurality of first metal interconnects 110 adjacent to the first side surface 112 of the interposer substrate 104 and coupled to the metal blocks 108, 204, 304 (block 408), and forming a plurality of second metal interconnects 118 adjacent to the second side surface 114 of the interposer substrate 104 and coupled to the first package substrate 120 (block 410). The next step of the manufacturing process 400 may include positioning the first die 102 between the first package substrate 120 and the second side surface 114 of the interposer substrate 104 in a second direction (block 412), the first die 102 being coupled to the first package substrate 120.

[0027] Other manufacturing processes may also be employed to produce an interposer substrate having a core layer, including, but not limited to, the core layers 106, 202, and 302 and associated IC packages 100, 200, and 300, respectively, as shown in Figures 1, 2A-2C, and 3A-3C, and including the use of a metal block thermally bonded to the first die to dissipate the thermal energy of the first die. In this regard, Figures 5A-5E are flowcharts of another exemplary manufacturing process 500 for producing an interposer substrate 104 having a core layer, including, but not limited to, the core layers 106, 202, and 302 and associated IC packages 100, 200, and 300, respectively, as shown in Figures 1, 2A-2C, and 3A-3C, and including a metal block thermally bonded to the first die to dissipate the thermal energy of the first die. Figures 6A to 6I-1 show exemplary manufacturing stages 600A to 600I1 during the manufacturing of the core layer 202 according to the manufacturing process 500 shown in Figures 5A to 5C. Figures 6A to 6C and Figures 6D-2 to 6G-2 show exemplary manufacturing stages 600A to 600C, 600D2 to 600G2 during the manufacturing of the core layer 302 according to the manufacturing process 500 shown in Figures 5A, 5D, and 5E. The manufacturing process 500 shown in manufacturing stages 600A to 600I1 of Figures 6A to 6I-1 pertains to the core layer 202 and associated IC package 200 of Figures 2A to 2C, and is therefore described with reference to the core layer 202 and IC package 200 of Figure 2A. The manufacturing processes 500 shown in Figures 5A, 5D, and 5E, which are manufacturing stages 600A to 600C and 600D-2 to 600G-2, relate to the core layer 302 and associated IC package 300 of Figures 3A to 3C, and are therefore described with reference to the core layer 302 and IC package 300 of Figure 3A.

[0028] In this regard, as shown in manufacturing stage 600A of Figure 6A, an exemplary step of manufacturing process 500 is to coat the carrier 602 with an insulating layer 604 and a very thin metal seed layer 606 to form the beginning portion of the interposer substrate 104 (block 502 in Figure 5A). As shown in manufacturing stage 600B of Figure 6B, the next step of manufacturing process 500 may include plating a metal layer 1 210 onto the metal seed layer 606 and patterning and etching a notch 608 from the metal layer 1 210 (block 504 in Figure 5A). As shown in manufacturing stage 600C in Figure 6C, the next step in manufacturing process 500 may include plating metal layer 2 212 onto metal layer 1 210, patterning and etching notches 610 from metal layer 2 212 to form metal interconnects 118, 218, 318 and metal posts 220, 320 (block 506 in Figure 5A). Metal layer 2 212 is wider than metal layer 1 210 in the second Z-axis direction. As shown in manufacturing stage 600D1 in Figure 6D-1, the next step in manufacturing process 500 may include depositing insulator 612 and seed layer 614 on top of metal layer 1 210 and metal layer 2 212 (block 508 in Figure 5B). As shown in manufacturing stage 600E1 in Figure 6E-1, the next step in manufacturing process 500 may include drilling the insulator 612 down to the metal layer 2212 to form an opening 616 in the insulator 612 (block 510 in Figure 5B). As shown in manufacturing stage 600F1 in Figure 6F-1, the next step in manufacturing process 500 may include depositing metal in the opening 616 of the insulator 612 to form metal vias 232, 208. Furthermore, the next step may include patterning and etching the deposited metal to form metal interconnects 110 and 117 (block 512 in Figure 5B). As shown in manufacturing stage 600G1 in Figure 6G-1, the next step in manufacturing process 500 may include removing the carrier 602 (block 514 in Figure 5C).As shown in manufacturing stage 600H1 in Figure 6H-1, the next step in manufacturing process 500 may include depositing insulating layers 618, 620 on the top and bottom of the interposer substrate 104 to form the first side 112 and the second side 114, thereby completing the core layer 202 (block 516 in Figure 5C). As shown in manufacturing stage 600I1 in Figure 6I-1, the next step in manufacturing process 500 may include depositing solder balls 136 on the first side 112 of the interposer substrate 104 in preparation for assembling the interposer substrate 104 into the package 138 (block 518 in Figure 5C).

[0029] Branching from block 506 in Figure 5A to block 520 in Figure 5D, manufacturing process 500 initiates a specific process for forming the core layer 302. In block 520, as shown in manufacturing step 600D2 in Figure 6D-2, the next step of manufacturing process 500 includes plating, patterning, and etching the metal layers, including metal layer 3 308, metal layer 4 310, and metal layer 5 312, to form a metal block 304 (block 520 in Figure 5D). As shown in manufacturing step 600E2 in Figure 6E-2, the next step of manufacturing process 500 may include adding insulators 622 and seed layer 624 on top of / above metal layers 210, 212, 308, 310, and 312 (block 522 in Figure 5D). As shown in manufacturing stage 600F2 in Figure 6F-2, the next step in manufacturing process 500 may include drilling the insulator 622 down to the metal layer 2212 to form an opening, depositing metal in the opening in the insulator 622 to form metal vias 232, patterning and etching the deposited metal to form metal interconnects 110, 117 to form the core layer 302, and depositing insulating layers 626 and 628 on the top and bottom of the interposer substrate 104 to form the first side surface 112 and the second side surface 114 to complete the core layer 302 (block 524 in Figure 5D). As shown in manufacturing stage 600G2 in Figure 6G-2, the next step in manufacturing process 500 may include depositing solder balls 136 on the first side surface 112 of the core layer 302 (block 526 in Figure 5E) in preparation for assembling the interposer substrate 104 into the package 138.

[0030] Including, but not limited to, the IC packages 100, 200, and 300 shown in Figures 1, 2A to 2C, and 3A to 3C, an interposer substrate 104 having a core layer 106 employing a metal block 108 thermally bonded to the first die to dissipate the thermal energy of the first die may be assembled using different assembly processes.

[0031] In this regard, Figures 7A to 7C are flowcharts illustrating an exemplary assembly process 700 for assembling an IC package that employs a metal block 108 to thermally bond the first die to an interposer substrate 104 in order to dissipate the thermal energy of the first die, including, but not limited to, the IC packages 100, 200, and 300 of Figures 1, 2A to 2C, and 3A to 3C as examples. The assembly process 700 of Figures 7A to 7C is described, for example, in conjunction with the interposer substrate 104, the first die layer 122, and the package substrate 120 of Figure 1.

[0032] In this regard, as shown in assembly stage 800A of Figure 8A, an exemplary initial step of the assembly process 700 begins with providing the first die 102 coupled to the package substrate 120 (block 702 in Figure 7A). As also shown in manufacturing stage 800B of Figure 8B, the next step of the assembly process 700 may include adding a thermal interface material 802 to the back surface 804 of the first die 102 (block 704 in Figure 7A). The thermal interface material 802 is available in various forms and may be added according to those forms. For example, the thermal interface material 802 may be a thermal paste that is added to the first die 102 by brushing a paste onto the back surface 804 of the first die 102 (this is also known as a dispensing process). In another example, the thermal interface material 802 may be in the form of a film that is attached to the back surface 804 of the first die 102. As also shown in manufacturing stage 800C in Figure 8C, the next step in assembly process 700 may include bonding the interposer substrate 104 to the package substrate 120 via thermal compression (block 706 in Figure 7B). As also shown in manufacturing stage 800D in Figure 8D, the next step in assembly process 700 may include adding molding compound 803 to fill the space between the interposer substrate 104, the first die 102, and the package substrate 120 (block 708 in Figure 7B). As also shown in manufacturing stage 800E in Figure 8E, the next step in assembly process 700 may optionally include mounting external interconnects, such as solder balls 806, on the land sides of the package substrate 120 and mounting external capacitors 808 (block 710 in Figure 7C). As also shown in manufacturing stage 800F in Figure 8F, the next step in assembly process 700 may include mounting the second package 138 to the interposer substrate 104 using solder balls 136. Although the solder balls 136 are shown in Figure 8F as pre-mounted on the package 138, the solder balls 136 may be pre-mounted on the interposer substrate 104 before mounting the package 138, as shown in Figures 6I-1 and 6G-2.

[0033] IC packages including, but not limited to, the IC packages 100, 200, and 300 of Figures 1, 2A-2C, and 3A-3C, as disclosed herein and by exemplary manufacturing and assembly processes shown in Figures 4 and 5A-5E, and including an interposer substrate 104 having a core layer 106 that employs a metal block 108 thermally bonded to the first die to dissipate the thermal energy of the first die, may be provided in or incorporated into any processor-based device or wireless device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cell phones, smartphones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health trackers or fitness trackers, eyewear, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, and avionics systems.

[0034] In this regard, Figure 9 shows an exemplary wireless communication device 900 including radio frequency (RF) components formed from one or more ICs 902, any of which may include an IC package employing an interposer substrate including a metal block in which metal interconnects thermally bond the die to the interposer substrate in any embodiment disclosed herein to dissipate the thermal energy of the die. The wireless communication device 900 may, for example, include any of the devices mentioned above, or may be provided within any of those devices. As shown in Figure 9, the wireless communication device 900 includes a transceiver 904 and a data processor 906. The data processor 906 may include memory for storing data and program code. The transceiver 904 includes a transmitter 908 and a receiver 910 that support bidirectional communication. Generally, the wireless communication device 900 may include any number of transmitters 908 and / or receivers 910 for any number of communication systems and frequency bands. The transceiver 904, in whole or in part, may be mounted on one or more analog ICs, RF ICs, mixed-signal ICs, etc.

[0035] The transmitter 908 or receiver 910 may be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal is frequency-converted between RF and baseband in multiple stages; for example, in receiver 910, the signal is frequency-converted from RF to intermediate frequency (IF) in one stage, and then from IF to baseband in another stage. In a direct conversion architecture, the signal is frequency-converted between RF and baseband in one stage. Superheterodyne and direct conversion architectures may use different circuit blocks and / or have different requirements. In the wireless communication device 900 in Figure 9, the transmitter 908 and receiver 910 are implemented using a direct conversion architecture.

[0036] In the transmission path, the data processor 906 processes the data to be transmitted and provides the transmitter 908 with an I analog output signal and a Q analog output signal. In an exemplary wireless communication device 900, the data processor 906 includes digital-to-analog converters (DACs) 912(1), 912(2) to convert the digital signals generated by the data processor 906 into an I analog output signal and a Q analog output signal, for example, an I output current and a Q output current, for further processing.

[0037] Within the transmitter 908, low-pass filters 914(1) and 914(2) filter the I analog output signal and the Q analog output signal, respectively, to remove undesirable signals generated by the preceding digital-to-analog conversion. Amplifiers (AMPs) 916(1) and 916(2) amplify the signals from the low-pass filters 914(1) and 914(2), respectively, to provide the I baseband signal and the Q baseband signal. The upconverter 918 upconverts the I baseband signal and the Q baseband signal via mixers 920(1) and 920(2) using the I TX LO signal and the Q TX LO signal from the transmit (TX) local oscillator (LO) signal generator 922 to provide the upconverted signal 924. Filter 926 filters the upconverted signal 924 to remove undesirable signals generated by frequency upconversion, as well as noise in the receiving frequency band. A power amplifier (PA) 928 amplifies the upconverted signal 924 from the filter 926 to obtain a desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 930 and transmitted via antenna 932.

[0038] In the receiving path, antenna 932 receives signals transmitted by the base station and provides a received RF signal, which is routed through a duplexer or switch 930 and supplied to a low-noise amplifier (LNA) 934. The duplexer or switch 930 is designed to operate with specific RX vs. TX duplexer frequency separation so that the receive (RX) signal is separated from the TX signal. To obtain the desired RF input signal, the received RF signal is amplified by the LNA 934 and filtered by a filter 936. Down-conversion mixers 938(1) and 938(2) mix the output of the filter 936 with the I RX LO signal and Q RX LO signal (i.e., LO_I and LO_Q) from the RX LO signal generator 940 to generate the I baseband signal and the Q baseband signal. To obtain the I analog input signal and the Q analog input signal provided to the data processor 906, the I baseband signal and the Q baseband signal are amplified by AMPs 942(1) and 942(2) and further filtered by low-pass filters 944(1) and 944(2). In this example, the data processor 906 includes analog-to-digital converters (ADCs) 946(1) and 946(2) to convert the analog input signals into digital signals that will be further processed by the data processor 906.

[0039] In the wireless communication device 900 shown in Figure 9, the TX LO signal generator 922 generates the I TX LO signal and the Q TX LO signal used for frequency upconversion, while the RX LO signal generator 940 generates the I RX LO signal and the Q RX LO signal used for frequency downconversion. Each LO signal is a periodic signal with a specific fundamental frequency. The TX phase-locked loop (PLL) circuit 948 receives timing information from the data processor 906 and generates a control signal used to adjust the frequency and / or phase of the TX LO signal from the TX LO signal generator 922. Similarly, the RX PLL circuit 950 receives timing information from the data processor 906 and generates a control signal used to adjust the frequency and / or phase of the RX LO signal from the RX LO signal generator 940.

[0040] Regarding exemplary processor-based devices, Figure 10 shows an example of a processor-based system 1000 including circuits that may be provided within IC packages 1002, 1002(1) to 1002(7). Any of the IC packages 1002, 1002(1) to 1002(7) may include, but are not limited to, the core layers 106, 202, 302 of the related IC packages 100, 200, 300, and 3A-3C, as well as the core layers 106, 202, 302 of Figures 1, 2A-2C, and 3A-3C, by any embodiment disclosed herein and by exemplary manufacturing and assembly processes of Figures 4, 5A-5E, 6A-6G-2, 7A-7C, and 8A-8F, as well as the interposer substrate which includes a core layer having a metal block in which metal interconnects thermally bond the die to the interposer substrate in order to dissipate the thermal energy of the die. In this example, the processor-based system 1000 may be formed as an IC 1004 in an IC package 1002 and as a system-on-a-chip (SoC) 1006. The processor-based system 1000 includes a central processing unit (CPU) 1008, which includes one or more processors 1010, which may also be called CPU cores or processor cores. The CPU 1008 may have a cache memory 1012 coupled to it for quick access to temporarily stored data. The CPU 1008 is coupled to a system bus 1014, which can interconnect master and slave devices included in the processor-based system 1000. As is well known, the CPU 1008 communicates with these other devices by exchanging address information, control information, and data information via the system bus 1014. For example, the CPU 1008 can communicate bus transaction requests to a memory controller 1016, which is an example of a slave device. Although not shown in Figure 10, it is possible to provide multiple system buses 1014, each system bus 1014 comprising a different fabric.

[0041] Other master and slave devices can be connected to the system bus 1014. As shown in Figure 10, these devices may include, for example, a memory system 1020 which may be located in a separate IC package 1002(4) and include a memory controller 1016 and one or more memory arrays 1018, one or more input devices 1022 which may be located in a separate IC package 1002(6), one or more output devices 1024 which may be located in a separate IC package 1002(7), one or more network interface devices 1026 which may be located in a separate IC package 1002(5), and one or more display controllers 1028 which may be located in a separate IC package 1002(2). Each of the memory system 1020, one or more input devices 1022, one or more output devices 1024, one or more network interface devices 1026, and one or more display controllers 1028 can be provided in the same or different IC package 1002(5). The input devices (one or more) 1022 may include, but are not limited to, input keys, switches, voice processors, etc., and may include any type of input device. The output devices (one or more) 1024 may include, but are not limited to, audio indicators, video indicators, other visual indicators, etc., and may include any type of output device. The network interface devices (one or more) 1026 may be any device configured to enable data exchange with the network 1030.Network 1030 can be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth® networks, and the Internet. Network interface devices 1026 (one or more) can be configured to support any desired type of communication protocol.

[0042] The CPU 1008 may also be configured to access a display controller(s) 1028 via the system bus 1014 to control the information sent to one or more displays 1032. The display controller(s) 1028 sends the information to be displayed to the displays(s) 1032 via one or more video processors 1034, and the one or more video processors 1034 process the information to be displayed into a format suitable for the displays(s) 1032. The display controller(s) 1028 and the video processor(s) 1034 may, for example, be included as ICs in the same or different IC package 1002(5) and as ICs in the same or different IC package 1002(1) that includes the CPU 1008. The display(s) 1032 may include, but is not limited to, any type of display, such as a cathode ray tube (CRT), liquid crystal display (LCD), plasma display, or light-emitting diode (LED) display.

[0043] Those skilled in the art will further understand that various exemplary logic blocks, modules, circuits, and algorithms described in relation to the embodiments disclosed herein may be implemented as electronic hardware, as instructions stored in memory or another computer-readable medium, where any such instruction is executed by a processor or other processing device, or a combination of both. The memory disclosed herein may be of any type and size and may be configured to store any desired type of information. To clearly demonstrate this compatibility, various exemplary components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the system as a whole. Those skilled in the art may implement the described functionality in various ways for specific applications, but such implementation decisions should not be construed as causing a departure from the scope of this disclosure.

[0044] Various exemplary logic blocks, modules, and circuits described in relation to the embodiments disclosed herein may be implemented or run using processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate logic or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors working with a DSP core, or any other such configuration).

[0045] The embodiments disclosed herein may be embodied in hardware, or in instructions stored within hardware, which may reside, for example, in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable media known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integrated with the processor. The processor and storage medium may reside within an ASIC. The ASIC may reside within a remote station. Alternatively, the processor and storage medium may reside as separate components within a remote station, base station, or server.

[0046] Furthermore, it should be noted that the operational steps described in any of the exemplary embodiments of this specification are described for the purpose of providing examples and explanations. The operations described may be performed in many different orders other than those shown in the illustrations. Moreover, an operation described in a single operational step may actually be performed in several different steps. Furthermore, one or more operational steps described in the exemplary embodiments may be combined. It should be understood that the operational steps shown in the flowcharts may be subjected to many different modifications, as will be readily apparent to those skilled in the art. It will also be understood that information and signals may be represented using a wide variety of techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips which may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0047] The above description in this disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to this disclosure will be readily apparent to a person skilled in the art, and the general principles defined herein may be applicable to other variations. Accordingly, this disclosure is not intended to be limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

[0048] Implementation examples are described in the following numbered clauses.

[0049] Clause 1. Integrated circuit (IC) package, The first package substrate and A substrate extending in a first direction and including a first side surface and a second side surface opposite to the first side surface in a second direction perpendicular to the first direction, A metal block containing multiple metal layers, A plurality of first metal interconnects adjacent to the first side surface and coupled to the metal block, A substrate including a plurality of second metal interconnects adjacent to the second side and bonded to the first package substrate, An IC package comprising: a first die, which is coupled to the first package substrate, between the first package substrate and a second side surface of the substrate in a second direction; and a first die.

[0050] Clause 2. The substrate is The IC package according to Clause 1, further comprising one or more metal vias connecting a plurality of first metal interconnects to a metal block.

[0051] Clause 3. The IC package according to Clause 1, wherein the plurality of metal layers comprises at least three metal layers, and the plurality of first metal interconnects are directly bonded to a metal block.

[0052] Clause 4. A plurality of solder balls, wherein at least one first solder ball among the plurality of solder balls is positioned on a plurality of first metal interconnects, further comprising: A metal block is thermally bonded to a first die in order to dissipate thermal energy through a plurality of first metal interconnects and at least one of the plurality of solder balls. An IC package as described in any one of Clauses 1 to 3.

[0053] Clause 5. The IC package according to Clause 4, wherein at least one second solder ball among a plurality of solder balls is electrically coupled to a plurality of second metal interconnects.

[0054] Clause 6. Further comprising a plurality of vertical interconnections electrically coupling the first package substrate to the substrate, the substrate The present invention further comprises at least one metal via that electrically connects the second die to the first package substrate via a plurality of vertical interconnects and a plurality of second metal interconnects. The IC package as described in Clause 5.

[0055] Clause 7. Further comprising a second package substrate, the second die is disposed on the second package substrate and electrically coupled via at least a second solder ball among a plurality of solder balls. The IC package described in Clause 6.

[0056] Clause 8. An IC package according to any one of Clauses 1 to 7, wherein the first package substrate further includes a plurality of external interconnects disposed on the land side surface of the first package substrate.

[0057] Clause 9. An IC package as described in any one of Clauses 1 to 8, wherein the width of the multiple first metal interconnects is 0.23 millimeters (mm) or less.

[0058] Clause 10. A method for manufacturing an integrated circuit (IC) package, To form the first package substrate, Forming a substrate that extends in a first direction and includes a first side surface and a second side surface opposite to the first side surface in a second direction perpendicular to the first direction, Forming a metal block containing multiple metal layers, To form a plurality of first metal interconnections adjacent to the first side surface and connected to the metal block, Forming a substrate, including forming a plurality of second metal interconnects adjacent to the second side surface and bonded to the first package substrate, A method comprising arranging a first die, which is coupled to the first package substrate, between the first package substrate and a second side of the substrate in a second direction.

[0059] Clause 11. Forming a substrate The method according to clause 10, further comprising forming one or more metal vias that connect a plurality of first metal interconnects to a metal block.

[0060] Clause 12. The method according to Clause 10, wherein the plurality of metal layers comprises at least three metal layers, and the plurality of first metal interconnects are directly bonded to a metal block.

[0061] Clause 13. Further includes forming a plurality of solder balls, wherein at least a first solder ball among the plurality of solder balls is positioned on a plurality of first metal interconnects, A metal block is thermally bonded to a first die in order to dissipate thermal energy through a plurality of first metal interconnects and at least the first solder balls among a plurality of solder balls. The method described in any one of Clauses 10 to 12.

[0062] Clause 14. The method according to Clause 13, wherein at least a second solder ball among a plurality of solder balls is electrically coupled to a plurality of second metal interconnects.

[0063] Clause 15. Further includes forming a plurality of vertical interconnections that electrically couple the first package substrate to a substrate, and forming the substrate The invention further includes forming at least one metal via that electrically connects the second die to the first package substrate via a plurality of vertical interconnects and a plurality of second metal interconnects. The method described in Article 14.

[0064] Clause 16. Further comprising forming a second package substrate, wherein a second die is disposed on the second package substrate and electrically coupled via at least a second solder ball of a plurality of solder balls. The method described in Article 15.

[0065] Clause 17. The method according to any one of Clauses 10 to 16, wherein the first package substrate further includes an external interconnect portion disposed on the land side of the first package substrate.

[0066] Clause 18. The method according to any one of Clauses 10 to 17, wherein the width of the multiple first metal interconnects is 0.23 millimeters (mm) or less. [Explanation of Symbols]

[0067] 100, 200 IC packages 102 Die 104 Interposer substrate 110 First metal interconnect 118 Second metal interconnect 120 Package Substrates 108, 204 Metal Blocks 116, 206 metal layer 208 Metal Via

Claims

1. An integrated circuit (IC) package, The first package substrate and A substrate extending in a first direction and including a first side surface and a second side surface opposite to the first side surface in a second direction perpendicular to the first direction, A metal block containing multiple metal layers, A plurality of first metal interconnecting parts adjacent to the first side surface and coupled to the metal block, A substrate including a plurality of second metal interconnects adjacent to the second side surface and bonded to the first package substrate, An IC package comprising: a first die, which is coupled to the first package substrate, between the first package substrate and the second side surface of the substrate in the second direction; and a first die.

2. The aforementioned substrate, The IC package according to claim 1, further comprising one or more metal vias for connecting the plurality of first metal interconnects to the metal block.

3. The IC package according to claim 1, wherein the plurality of metal layers include at least three metal layers, and the plurality of first metal interconnects are directly bonded to the metal block.

4. The present invention further comprises a plurality of solder balls, wherein at least one first solder ball among the plurality of solder balls is positioned on the plurality of first metal interconnects, The metal block is thermally bonded to the first die in order to dissipate thermal energy through the plurality of first metal interconnects and at least one of the plurality of solder balls. The IC package according to claim 1.

5. The IC package according to claim 4, wherein at least one second solder ball among the plurality of solder balls is electrically coupled to the plurality of second metal interconnects.

6. The first package substrate further comprises a plurality of vertical interconnection parts that electrically connect to the substrate, and the substrate is The device further comprises at least one metal via that electrically connects the second die to the first package substrate via the plurality of vertical interconnections and the plurality of second metal interconnections. The IC package according to claim 5.

7. The present invention further comprises a second package substrate, wherein the second die is disposed on the second package substrate and is electrically coupled via at least the second solder ball among the plurality of solder balls. The IC package according to claim 6.

8. The IC package according to claim 1, wherein the first package substrate further includes a plurality of external interconnection portions disposed on the land side surface of the first package substrate.

9. The IC package according to claim 1, wherein the width of the plurality of first metal interconnection portions is 0.23 millimeters (mm) or less.

10. A method for manufacturing an integrated circuit (IC) package, To form the first package substrate, Forming a substrate that extends in a first direction and includes a first side surface and a second side surface opposite to the first side surface in a second direction perpendicular to the first direction, Forming a metal block containing multiple metal layers, To form a plurality of first metal interconnection parts adjacent to the first side surface and coupled to the metal block, Forming a substrate, which includes forming a plurality of second metal interconnection portions adjacent to the second side surface and bonded to the first package substrate, A method comprising arranging a first die, which is coupled to the first package substrate, between the first package substrate and the second side surface of the substrate in the second direction.

11. Forming the aforementioned substrate The method according to claim 10, further comprising forming one or more metal vias that connect the plurality of first metal interconnects to the metal block.

12. The method according to claim 10, wherein the plurality of metal layers comprises at least three metal layers, and the plurality of first metal interconnects are directly bonded to the metal block.

13. The invention further includes forming a plurality of solder balls, wherein at least one of the plurality of solder balls is positioned on the plurality of first metal interconnects, The metal block is thermally bonded to the first die in order to dissipate thermal energy through the plurality of first metal interconnects and at least the first solder balls among the plurality of solder balls. The method according to claim 10.

14. The method according to claim 13, wherein at least a second solder ball among the plurality of solder balls is electrically coupled to the plurality of second metal interconnects.

15. The process further includes forming a plurality of vertical interconnection portions that electrically connect the first package substrate to the substrate, and forming the substrate is The further includes forming at least one metal via that electrically connects the second die to the first package substrate via the plurality of vertical interconnections and the plurality of second metal interconnections. The method according to claim 14.

16. The further includes forming a second package substrate, wherein the second die is disposed on the second package substrate and is electrically coupled via at least the second solder ball of the plurality of solder balls. The method according to claim 15.

17. The method according to claim 10, wherein the first package substrate further includes an external interconnection portion disposed on the land side surface of the first package substrate.

18. The method according to claim 10, wherein the width of the plurality of first metal interconnecting portions is 0.23 millimeters (mm) or less.

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