High-current, low-dropout driver circuit

Abstract

It provides a high-current, low-dropout driver circuit. [Solution] A high-current, low-dropout driver circuit is disclosed. This circuit includes a decoder configured to decode a plurality of control bits to generate a plurality of control signals, and a current source having a plurality of devices. The current source is configured to activate at least a subset of the plurality of devices using the control signals and to provide load current to a load circuit such as a light-emitting diode (LED) using the activated devices and control voltages among the plurality of devices. The control circuit is configured to generate a control voltage based on the load current and a reference current.

Description

Technical Field

[0001] The present disclosure relates to electronic circuits, and more particularly, to circuits for driving light emitting diodes (LEDs) and other load circuits.

Background Art

[0002] LED driver circuits are used, for example, to drive LEDs used in displays for different types of devices. Different types of LEDs can be driven by corresponding LED driver circuits. For example, white LEDs can be driven by a circuit using pulse width modulation (PWM) without constantly supplying current to the LEDs. The frequency of the pulses used may be such that the non-constant current is not perceptible to the naked eye, while the brightness of such LEDs may vary with the width of the pulses (wider pulses correspond to an increase in brightness). Recently, colored LEDs have been used in some types of displays. These LEDs may be driven by a circuit that provides a constant current instead of using a PWM circuit.

Summary of the Invention

[0003] A high-current, low-dropout driver circuit is disclosed. In one embodiment, the circuit includes a decoder configured to decode a plurality of control bits to generate a plurality of control signals, and a current source having a plurality of devices. The current source is configured to activate at least a subset of the plurality of devices using the control signals and provide a load current to a load circuit, such as a light emitting diode (LED), using the activated devices among the plurality of devices and a control voltage. The control circuit is configured to generate the control voltage based on the load current and a reference current.

[0004] In one embodiment, the control circuit includes a replica device (e.g., a transistor) having substantially the same dimensions and electrical characteristics as one of the multiple devices. Therefore, the current through each individual device of the multiple devices is substantially the same as the current through the replica device. Furthermore, the load current at any given time is the number of active devices in the current source multiplied by the reference current. [Brief explanation of the drawing]

[0005] For a detailed explanation, please refer to the attached diagrams briefly described below.

[0006] [Figure 1] This is a block diagram of one embodiment of a driver circuit.

[0007] [Figure 2] This is a schematic diagram of one embodiment of a driver circuit.

[0008] [Figure 3] This is a schematic diagram of another embodiment of the driver circuit.

[0009] [Figure 4] This is a schematic diagram of another embodiment of the driver circuit.

[0010] [Figure 5A] This is a schematic diagram of another embodiment of the driver circuit.

[0011] [Figure 5B] This is a schematic diagram of another embodiment of the driver circuit.

[0012] [Figure 5C] This is a schematic diagram of another embodiment of the driver circuit.

[0013] [Figure 6] This is a flowchart of one embodiment of a method for operating a driver circuit.

[0014] [Figure 7] This is a flowchart of another embodiment of how to operate the driver circuit.

[0015] [Figure 8] This is a block diagram of one embodiment of an exemplary system. [Modes for carrying out the invention]

[0016] A driver circuit is used to supply current to a load circuit. An exemplary load circuit is, for example, an LED in a display. Previous solutions for LED driver circuits were designed for white LEDs that consume low power / current and can be controlled through circuits implementing techniques such as pulse width modulation (PWM). However, these circuits are not suitable for LEDs that have become more frequently used. More specifically, the current use of LEDs for displays and other applications is trending towards LEDs that are high-power colored LEDs that operate using constant current instead of current pulses according to the PWM scheme. Other requirements for driver circuits used with these types of LEDs are low dropout, high current capability, high dimming ratio, monotonicity, and low quiescent current.

[0017] The present disclosure thus relates to driver circuits, such as LED driver circuits, suitable for use with high-power LEDs. The circuit includes a current DAC (including a number of devices), an equalizer circuit, a regulator circuit, and a decoder. The decoder can activate or deactivate various devices (e.g., transistors) of the current DAC based on an input code. When an LED is used as a load circuit, the device draws current from the cathode of the LED. The regulator generates a control voltage provided to the gate terminal of a replica device as well as the gate terminals of the devices of the current DAC via corresponding switches controlled by the decoder (the replica device has the same characteristics as the devices of the current DAC). The equalizer circuit equalizes the drain voltage from the devices of the current DAC to the drain voltage of the replica device. As a result, the terminal voltage of the replica device is equal to each of the active devices of the current DAC. There are N devices in the current DAC, and thus the current drawn through the LED can be any of 0 to N times the drain-source current of the replica device.

[0018] The driver circuit of the present disclosure can thus provide a constant (continuous) current with a very low dropout and a high dimming ratio, suitable for use in LED applications as well as other applications where a current driver is desired. The current can be varied monotonically, while the quiescent current is low, making it suitable for use in portable (battery-driven) devices.

[0019] Further details are explained further below. The description begins with a discussion of various embodiments of a driver circuit that can be used to drive an LED, among other applications. Next, a method of operating the driver circuit is explained, followed by a description of an exemplary system in which an instance of the driver circuit according to the present disclosure can be implemented. Embodiments of the driver circuit:

[0020] FIG. 1 is a block diagram of an embodiment of a driver circuit coupled to drive an LED. In the illustrated embodiment, driver circuit 100 includes a control circuit 110, a current source 115, and a decoder 105. Driver circuit 100 is coupled to LED 117 and is configured to draw a load current I_load and drive the LED to emit light. LED 117 can be, for example, one of several LEDs in a display on a mobile device, but this exemplary use is not intended to limit the present disclosure. Similarly, driver circuit 100 can be used for applications other than driving an LED, and more generally, for any application where it is desirable for a circuit to draw current in the manner described herein.

[0021] Current source 115 in the illustrated embodiment includes a plurality of devices (e.g., transistors such as NMOS devices) that can be activated to generate current through the cathode of LED 117. In an alternative embodiment, current source 115 can be connected to the anode of LED 117, and the polarities of the other devices are reversed accordingly. Control of the amount of current generated by current source 115 can be partially controlled by, at least, selecting a subset of the devices that are activated. In this embodiment, decoder 105 can control, via a control signal, which of the plurality of devices in current source 115 are activated. Decoder 105 can generate a control signal based on control bits including an input code.

[0022] Control circuit 110 can also affect the amount of current generated by current source 115 based on a control voltage Vctrl provided to each of the devices. In one embodiment, the control voltage is provided to the gate terminals of some of the NMOS or PMOS transistors that make up current source 115. The control voltage generated by control circuit 110 is at least partially based on load current I_load. A reference current source I_ref can also be used in the generation of the control voltage.

[0023] Figure 2 is a schematic diagram of one embodiment of a driver circuit. In the illustrated embodiment, the driver circuit 200 is configured to drive an LED 217, but other loads are also possible and intended. The LED 217 is coupled via its anode to a power supply 203 that generates a regulated supply voltage V_in, but a reverse polarity embodiment (as described above) is also possible and intended. The power supply 203 may be a buck converter, a boost converter, a low-dropout (LDO) voltage regulator, or any other suitable type of power supply. The LED 217 is provided here as an example of a load circuit, but this disclosure is not intended to limit it to this type of load.

[0024] The LED driver circuit 200 in the illustrated embodiment includes a control circuit 210, a decoder 205, and a current source 215. The control circuit 210 includes an equalizer 214, a replica regulator 213, and a reference current source 211. The replica regulator 213 in the illustrated embodiment includes an operational transconductance amplifier 1 (OTA1), a device M0 (e.g., an NMOS transistor), and a reference current resistor R_ref and a feedback resistor R_fb. The equalizer 214 includes OTA0 and devices M1 and M2. In various embodiments, the OTA can perform a comparator function in which the magnitude of each output signal changes in proportion to the voltage difference applied to each input.

[0025] The current source 215 includes multiple devices MN0 (e.g., NMOS transistors), each of which can be activated or deactivated using a corresponding switch S1 coupled to it. A control signal output from the decoder 205 can be used to selectively activate various devices among the devices of the current source 215. Thus, the load current I_Load is the sum of the currents through the individual active devices of the current source 215. Therefore, control of the amount of load current depends in part on the number of active devices in the current source 215, which depends on the input code provided to the decoder 205. The input code can be provided as a binary code, a thermometer (or thermometric) code, or a combination thereof (e.g., the most significant bit is thermometer, the least significant bit is binary).

[0026] In the illustrated embodiment, the voltage V_out on the cathode of LED 217 is provided to the non-inverting input of OTA0. This arrangement allows OTA0 to monitor V_out. The inverting input of OTA0 is coupled in a feedback configuration to the terminal of M2 (for example, the drain terminal of the PMOS device in this embodiment). Thus, based on the configuration shown herein, OTA0 generates an output voltage substantially proportional to V_out. In practice, OTA0 acts as a comparator comparing the drain voltage on the device of current source 215 with the drain voltage of device M0. Since both V_out and I_Load are taken from the same terminal (the cathode of LED 217 in this embodiment), these values ​​correspond to each other. Thus, through the comparison operation of OTA0, the voltage V_out on the drain terminal of the device in current source 215 is effectively repeated to the drain terminal of M0, and at the same time, a replica current I_M0 is also generated through M0.

[0027] In the illustrated embodiment, M2 and M1 effectively act as current mirrors. The replica current I_M0 flowing through M2 and M0 is mirrored to M1 to generate I_M1. In one embodiment, the mirroring of current to M1 via M2 / M0 is performed at a 1:1 ratio, and therefore I_M0 and I_M1 are substantially equal. Using the current I_M1, R_fb generates a voltage supplied to the inverting input of OTA1. Using the reference current, R_ref generates a reference voltage supplied to OTA1. Using these voltages, OTA1 acts as a comparator to generate a control voltage V_ctrl. The control voltage generated by the comparating operation of OTA1 is supplied to the gate terminal of M0, and to the active device in the current source 215 (via the corresponding closed switch). In the illustrated embodiment, the device MN0 in the current source 215 is equal in size to each other and to M0 (e.g., the same length and width). Therefore, the current I_M0 is substantially equal to the current through any one active device MN0 of the current source 215. Thus, the total current I_Load is the product of the current I_M0 through M0 multiplied by the number of active devices of the current source 215, and this current is regulated by OTA1.

[0028] The arrangement of the driver circuit 200 in the illustrated embodiment provides several mechanisms for controlling the load current or the possible range of load currents that can be provided. One such mechanism is to adjust or change the reference current I_ref provided by the reference current source 211. This changes the voltage to the non-inverting input of OTA1 and, therefore, the control voltage V_ctrl output from there. Another mechanism for controlling the load current is to change the number of active devices in the current source 215 by changing the input code to the decoder 205. If the current source 215 is modeled as a single transistor, changing the number of active devices may be equivalent to modulating the width of the modeled single device. Another mechanism for controlling the load current is to control the ratio of the respective resistances provided by R_ref and R_fb and, therefore, control the respective input voltages provided to OTA1 and, therefore, change the control voltage V_ctrl. Changing the size ratio of M1 and M2 may be used as a mechanism for controlling the load current, as it results in a change in the ratio of the individual drain currents in these devices.

[0029] In the illustrated embodiment, OTA0 may be implemented with a low offset to ensure good matching between the load current and the replica current I_M0. This amplifier can also be implemented with a wider common-mode voltage to have a higher bandwidth than OTA1, thereby obtaining a higher phase margin and thus improving overall stability. OTA0 can respond to transients faster than OTA1 because its respective bandwidths do not overlap. By isolating its respective bandwidths, OTA0 controls the voltage at the drain terminal of M0 (forming a follower with M2), while OTA1 controls the current on the same node. In the case of OTA1, the common-mode voltage is not significant and can be defined by the product of the reference current I_ref and the resistance of resistor R_ref. Although the bandwidth of OTA1 is lower than that of OTA0, OTA1 may have a higher driving capability.

[0030] Figure 3 is a schematic diagram of another embodiment of the driver circuit. In the illustrated embodiment, the driver circuit 300 is coupled to the LED 317 and configured to drive the LED 317. In this particular embodiment, the current source that generates the current through the LED 317 is N * It is implemented as a single device M5 sized to be M0. The equalizer 314 and replica regulator 313 are arranged similarly to their counterparts in the embodiment shown in Figure 2.

[0031] In the embodiment shown in Figure 3, the driver circuit 300 varies the load current I_Load through variations in the reference current I_ref. This is achieved via a decoder 305 that changes the current generated by the reference current source 311 via the I_ctrl signal. The I_ctrl signal is generated by the decoder 305 based on the received input code. Changing the input code, and therefore changing the reference current I_ref, changes the voltage applied to the non-inverting input of OTA1, and therefore changes the control voltage V_ctrl applied to the gates of M0 and M5, respectively. This changes the replica current and therefore the load current.

[0032] Figure 4 is a schematic diagram of another embodiment of the driver circuit. In the illustrated embodiment, the driver circuit 400 is configured to generate a current for driving the LED 417. The driver circuit 400 combines features of the embodiments illustrated in Figures 2 and 3. In the illustrated embodiment, the load current I_load can be adjusted by changing the reference current and / or by changing the number of active devices in the current source 415. In this embodiment, the reference current can be adjusted by changing the four least significant bits of the input code, which is provided to the decoder 405-1, which then generates a current control signal I_ctrl, which is provided to the reference current source 411. In this embodiment, the most significant bit is provided to the decoder 405-2, which generates a control signal used to activate the various devices in the current source 415.

[0033] The input codes provided to decoders 415-1 and 415-2 may be binary codes, thermometer codes, or any other suitable type. In one embodiment, the least significant bits (bits 3:0) of the input code are provided to decoder 415-1 as a binary code, and the most significant bits (bits M-1:4) are provided to decoder 405-2 as a thermometer code. However, both or any of the groups of code bits may be binary, thermometer, or any other suitable code.

[0034] Figure 5A is a schematic diagram of another embodiment of the driver circuit. In this embodiment, the driver circuit 500 generates a current to drive the LED 517. In this embodiment, additional control of the current may be provided via a switch S2 in the equalizer 514. Switch S2 (which may be controlled by a control circuit not shown here) can select one of transistors M2A or M2B to be active at a given time. These devices may be of different sizes, and therefore, changing between one and the other changes the size ratio between the devices in different legs of the control circuit 510. For example, M2A may be the same size as M1, and M2B may be twice the size of M1. This changes the current mirrored to M1 and therefore changes the control voltage generated by OTA1. In this approach, the current of the current source 515 can be adjusted while maintaining the common mode of OTA1. Further embodiments are possible and contemplated that include additional devices to allow a wider range of adjustment, finer control of individual adjustments, or both. For example, embodiments having a device that supports 16 possible current mirror configurations are possible and intended. Embodiments that add additional devices to the M1 positions with different weights (e.g., configurations including M1A devices, M1B devices, etc.) are also possible and intended. In general, the embodiments shown in Figure 5A intend a configurable current mirror that can be controlled and selected using various switches.

[0035] Figure 5B is a schematic diagram of yet another embodiment of the driver circuit. In this embodiment, the replica regulator and equalizer functions of the driver circuit 550 are combined into a single circuit, replica regulator / equalizer 557, which includes OTA0 and M0. This circuit includes two control loops, one using OTA0 and the other using OTA_HV.

[0036] A first control loop utilizing OTA0 can force a proportional current through transistor M0 based on a reference current from I_Ref1 561 and the voltage difference between the input terminals of OTA0. This difference is based on the drain voltage of M0 and the active device of current source 565. This can then force a proportional current to flow through the active device of current source 565. The active device is selected based on a control signal generated by decoder 555, which is activated or deactivated based on the received input code.

[0037] A second control loop utilizing OTA_HV and M5 (high-voltage transistor) adjusts the voltage on each drain terminal of the current source 565 device to a substantially fixed voltage. This fixed voltage is partially determined by the voltage V_IDAC generated using the current source I_ref2 562 and resistor R_IDAC. In this particular configuration, the first control loop is isolated from the second control loop, which is implemented in the high-voltage region. This allows the current source 565 device to operate in a lower voltage region. The illustrated embodiment can offer significant area savings because the devices M0 and current source 565 may be smaller than their higher-voltage counterparts.

[0038] Figure 5C is one possible variation of the embodiment shown in Figure 5B. In this embodiment, the driver circuit 570 includes a current mirror formed by devices M6 and M7, and a third control loop is added, including OTA1, M8, R56, R57, and I_ref 561. In this embodiment, the LSB current increment (or size), and therefore the full-scale current, can be changed by changing the values ​​of various circuit elements. Changing the resistance value of either R56 or R57 (and thus changing the ratio between the two) can change the LSB size. Similarly, changing the ratio of the device sizes between M6 and M7 can also change the LSB size. The third loop added here generates the current I_MO using the current mirror of M6 and M7, the reference current from OTA1, M8, I_ref 561, and the voltage generated by the currents through R56 and R57. Therefore, the embodiment shown in Figure 5C allows for high flexibility in adjusting the LSB size, which in turn allows for the adaptation of extra features such as DC precision trimming and LSB range in an exponential order.

[0039] Other variations of the embodiments illustrated in Figures 5B and 5C are possible and intended. In one possible alternative embodiment, a reference voltage is applied, for example, to the inverting input of the OTA in the replica regulator. In such an embodiment, the loop containing the OTA of the replica regulator operates independently of the high-voltage OTA (e.g., OTA_HV in Figure 5C). This helps maintain the stability of the OTA in the replica regulator by avoiding interaction with the high-voltage OTA. The reference voltage of the high-voltage OTA can be obtained from the drain of the replica device M0. As a result, such an embodiment offers the advantage that it never saturates, regardless of the high-voltage loop driving the LED.

[0040] In yet another embodiment, the two control loops may be further separated by generating two independent reference voltages, one for the replica regulator's OTA and the other for the high-voltage OTA used in the loop driving the LEDs. The two reference voltages may be trimmed to the same value. This further separation of the control loops can achieve even greater operational stability.

[0041] Another embodiment can improve DC accuracy by eliminating the current mirror. Such an embodiment may implement a second high-voltage OTA, the added OTA located in the loop that generates the replica current. A reference current sink to ground may also be provided (e.g., coupled to the non-inverting input of the second high-voltage OTA). Since the bandwidth of the loop including the second high-voltage OTA does not affect the overall transient response of the circuit, the bandwidth of the control loop may be isolated to prevent interaction with the low-voltage loop (including the replica regulator). Method Flowchart

[0042] Figure 6 is a flowchart of one embodiment of a method for operating a driver circuit. Method 600 can be carried out by various embodiments of the circuit embodiments described above with reference to Figures 1 to 5. While Method 600 can be carried out, circuit embodiments not explicitly disclosed herein may also be considered to be within the scope of this disclosure.

[0043] Method 600 includes generating a plurality of control signals, the generation comprising decoding a plurality of control bits using a decoder circuit (block 605), and activating at least a subset of a plurality of devices of a current source based on the plurality of control signals (block 610). The method further includes providing a load current to a load circuit based on a control voltage provided to the activated device among the plurality of devices (block 615), and using a control circuit to generate a control voltage based on the load current and a reference current (block 620).

[0044] In various embodiments, the method includes generating a copy of the load current using an equalization circuit, and further including generating a control voltage using a regulator circuit and the copy of the load current. Generating a copy of the load current includes, in one embodiment, a comparator in the equalization circuit that generates a comparison voltage by comparing the drain voltage on the control device of the regulator circuit with the drain voltage on the activated device of the plurality of devices. Generating the control voltage includes performing a comparison between the copy of the load current and the reference current using a comparator in the regulator circuit. The comparator in one embodiment may be an operational transconductance amplifier that can generate an output signal whose magnitude changes in proportion to the voltage applied to its input. The method also includes providing the control voltage to the gate terminal of the control device, so that the current through the control device is substantially equal to the current through the individual devices of the plurality of devices. In various embodiments, the equalization circuit includes a current mirror, and therefore, the method for operating such embodiments further includes changing the ratio of the current mirror.

[0045] Some circuit embodiments may utilize two decoders for generating a reference current and activating the devices of the current source. In operation of such embodiments, the method further includes the decoder circuit providing a first subset of a plurality of control signals to a reference current generator configured to generate a reference current, and providing a second subset of a plurality of control signals to control the activation of some of a plurality of devices.

[0046] Figure 7 is a flowchart of another embodiment of a method for operating a driver circuit. Method 700 can be applied to various of the driver circuits described above with reference to Figures 1 to 5. Driver circuits capable of performing Method 700, although not expressly disclosed herein, are also considered to fall within the scope of this disclosure.

[0047] Method 700 includes monitoring the output voltage of the DAC at the cathode of the LED (block 705). The DAC may be a current source as shown in Figure 7, which includes several different devices. The device may be activated using a control signal generated by a decoder circuit based on a digital input code. Thus, the decoder and current source effectively convert the code into an output current having a specific voltage corresponding to the drain voltage of the activated device.

[0048] Method 700 further includes generating a replica current based on the output voltage (block 710). Again, using the embodiment of Figure 2 as an example, the output voltage may be transmitted to the device through which the replica current passes via an OTA in the equalizer circuit. The replica current may also be mirrored to another device. Using the mirrored replica current and reference current to generate their respective voltage inputs, another OTA in the replica circuit may generate a control voltage (block 715). Based on the control voltage output from the OTA and the number of active devices in the current source, a load current is generated (block 720). Exemplary System

[0049] Referring next to Figure 8, a block diagram of one embodiment of system 800 is shown, which can incorporate and / or utilize the methods and mechanisms described herein. In the illustrated embodiment, system 900 includes at least one instance of system on chip (SoC) 806, which may include multiple types of processing units such as a central processing unit (CPU), a graphics processing unit (GPU), or other methods, a communication fabric, and interfaces to memory and input / output devices. In some embodiments, one or more processors within the SoC 806 include multiple execution lanes and instruction issue queues. In various embodiments, the SoC 806 is coupled to external memory 802, peripherals 804, and a power supply 808.

[0050] A power supply 808 is also provided, which supplies a supply voltage to the SoC 806 and one or more supply voltages to the memory 802 and / or peripheral devices 804. In various embodiments, the power supply 808 represents a battery (e.g., a rechargeable battery for a smartphone, laptop or tablet computer, or other device). In some embodiments, two or more instances of the SoC 806 are included (and two or more external memories 802 are also included).

[0051] Memory 802 is any type of memory, including dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM such as mDDR3 and / or low-power versions such as LPDDR2), Rambus DRAM (RDRAM), and static RAM (SRAM). One or more memory devices are coupled to a circuit board to form memory modules such as single inline memory modules (SIMMs) and dual inline memory modules (DIMMs). Alternatively, the devices are mounted on an SoC or integrated circuit in a chip-on-chip, package-on-package, or multi-chip module configuration.

[0052] The system 800 in the illustrated embodiment may implement one or more of the driver circuits described above with respect to Figures 1 to 5. For example, the system 800 may include at least one LED display having various driver circuits used to adjust its brightness by changing the load current. Other applications of the driver circuits described herein are also possible and intended.

[0053] The peripheral device 804 includes any desired circuit configuration depending on the type of system 800. For example, in one embodiment, the peripheral device 804 includes devices for various types of wireless communication, such as Wi-Fi, Bluetooth, cellular, and global positioning systems. In some embodiments, the peripheral device 804 also includes additional storage, such as RAM storage, solid-state storage, or disk storage. The peripheral device 804 includes user interface devices such as a display screen, including a touch display screen or a multi-touch display screen, a keyboard or other input devices, a microphone, and a speaker.

[0054] As illustrated, system 800 is shown to be applicable to a wide range of areas. For example, system 800 may be used as part of a chip, circuit, or component in a desktop computer 810, a laptop computer 820, a tablet computer 830, a cellular or mobile phone 840, or a television 850 (or a set-top box coupled to a television). A smartwatch and a health monitoring device 860 (or more generally, a wearable device) are also shown. In some embodiments, the smartwatch 860 may include a variety of general-purpose computing-related functions. For example, the smartwatch 860 may provide access to email, mobile phone services, a user calendar, etc. In various embodiments, the health monitoring device may be a dedicated medical device or may otherwise include dedicated health-related functions. For example, the health monitoring device may monitor the user's vital signs, track the user's proximity to other users for epidemiological social distancing, perform contact tracing, and provide communication to emergency services in the event of a health crisis. In various embodiments, the smartwatch described above may or may not include some or any of the health monitoring-related functions. Other wearable devices, such as devices worn around the neck, implantable devices in the human body, and glasses designed to provide augmented and / or virtual reality experiences, are also intended.

[0055] System 800 may be further used as part of a cloud-based service(s) 870. For example, the aforementioned devices and / or other devices may access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Furthermore, System 800 may be used in one or more devices in a home other than those described above. For example, household appliances may monitor and detect conditions of note. For example, various household devices (e.g., refrigerators, cooling systems, etc.) may monitor the status of the devices and alert the homeowner (or repair facility) if a particular event is detected. Alternatively, a thermostat may monitor the temperature in the home and automate the adjustment of the heating / cooling system based on the homeowner's response history to various conditions. Figure 8 also shows the application of System 800 to various modes of transport. For example, System 800 may be used in control and / or entertainment systems for aircraft, trains, buses, rental cars, private cars, ships ranging from privately owned boats to cruise ships, and scooters (rented or owned). In various cases, System 800 may be used to provide automatic guidance (e.g., autonomous vehicles), general system control, and other methods. Many other embodiments of these are possible and contemplated. Note that the devices and applications illustrated in Figure 8 are illustrative and not intended to be limiting. Other devices are possible and contemplated.

[0056] While the circuits described above are implemented using NMOS and PMOS transistors, it should be noted that this disclosure is not intended to limit the embodiments within its scope to these types of devices. Therefore, in addition to the various MOSFET types described above, this disclosure also intends to include embodiments using non-planar devices such as FinFETs and GAAFETs (Gate All Around FETs), among other types. Embodiments implemented using bipolar devices are also possible and intended. This disclosure further intends to include, but is not limited to, technologies that are speculative at the time of writing this specification, which may be used to implement the devices in various embodiments of the circuits described herein. These technologies include, but are not limited to, graphene transistors, carbon nanotube transistors, and gallium arsenide transistors. The use of memristors in specific circuit structures is also intended. ***

[0057] This disclosure includes references to “one embodiment” or a group of “embodiments” (e.g., “several embodiments” or “various embodiments”). Embodiments are different implementations or examples of the disclosed concept. References to “one embodiment,” “one embodiment,” “a particular embodiment,” etc., do not necessarily refer to the same embodiment. Numerous possible embodiments, including those specifically disclosed, and modifications or substitutions within the spirit or scope of this disclosure are intended.

[0058] This disclosure may discuss the potential benefits that may arise from the disclosed embodiments. Not all implementations of these embodiments necessarily demonstrate any or all of the potential benefits. Whether a benefit is realized for a particular implementation depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an implementation within the claims may not exhibit some or all of any disclosed benefits. For example, a particular implementation may include other circuits outside the scope of this disclosure that, together with one of the disclosed embodiments, negate or reduce one or more of the disclosed benefits. Furthermore, suboptimal design execution of a particular implementation (e.g., implementation technique or tool) may also negate or reduce the disclosed benefits. Even assuming skilled execution, the realization of benefits may still depend on other factors, such as the environmental conditions in which the implementation is deployed. For example, the inputs supplied to a particular implementation may prevent one or more of the problems addressed in this disclosure from occurring on certain occasions, and as a result, the benefits of the solution may not be realized. Given the existence of possible external factors of this disclosure, it is expressly intended that any potential benefits described herein should not be construed as limitations on claims that must be satisfied to demonstrate infringement. Rather, the identification of such potential benefits is intended to illustrate the type(s) of improvements available to designers who have an interest in this disclosure. The acceptable description of such benefits (e.g., the statement that a particular benefit "may occur") is not intended to convey any doubt as to whether such benefits can actually be realized, but rather to acknowledge the technical reality that the realization of such benefits often depends on additional factors.

[0059] Unless otherwise specified, the embodiments are non-limiting. That is, even if only a single embodiment describes a particular feature, the disclosed embodiments are not intended to limit the scope of claims made based on this disclosure. The disclosed embodiments are intended to be illustrative, not limiting, unless there is a statement to the contrary in this disclosure. The foregoing is intended to enable claims that cover not only the disclosed embodiments but also alternatives, modifications, and equivalents that would be obvious to a person skilled in the art who would benefit from this disclosure.

[0060] For example, the features of this application can be combined in any preferred manner. Therefore, new claims can be formulated for any such combination of features during the examination of this application (or an application claiming priority to this application). In particular, referring to the attached claims, features from dependent claims can be combined with features from other dependent claims, including claims dependent on other independent claims, as appropriate. Similarly, features from each independent claim can be combined as appropriate.

[0061] Accordingly, each of the attached dependent claims may be constructed to depend on a single other claim, but additional dependencies are also contemplated. Any combination of features in the dependent claims that are consistent with the present disclosure is contemplated and may be claimed in this application or another application. In summary, the combinations are not limited to those specifically enumerated in the attached claims.

[0062] Where appropriate, claims prepared in one format or legal type (e.g., apparatus) are intended to also support corresponding claims in another format or legal type (e.g., method). ***

[0063] As this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. The following paragraphs, and the definitions provided through this disclosure, are hereby publicly noted as being used in interpreting the claims made pursuant to this disclosure.

[0064] References to singular items (i.e., nouns or noun phrases preceded by "a," "an," or "the") are intended to mean "one or more" unless explicitly stated in the context. Therefore, references to "items" in the claims do not, without context, preclude additional instances of an item. "Multiple" items refer to a set of two or more items.

[0065] In this specification, the word "may" is used in an allowable sense (i.e., possible, feasible) and not in an obligatory sense (i.e., not required).

[0066] The terms and forms "comprising" and "including" are open-ended and mean "to include, but not to limit."

[0067] When the term “or” is used in this disclosure in relation to a list of options, it will generally be understood to be used in an inclusive sense unless otherwise explicitly stated in the context. Thus, the enumeration of “x or y” is equivalent to “x or y, or both,” and therefore includes 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, the phrase “either x or y, but not both” clarifies that “or” is used in an exclusive sense.

[0068] The enumerations "w, x, y, z, or any combination thereof" or "...at least one of w, x, y, and z" are intended to cover all possibilities, including single elements, up to the total number of elements in the set. For example, in the set [w, x, y, z], these expressions cover any single element in the set (e.g., w, but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. Thus, the phrase "...at least one of w, x, y, and z" refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in this list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0069] In this disclosure, various “labels” may precede nouns or noun phrases. Unless otherwise explicitly stated in the context, the various labels used for features (e.g., “first circuit,” “second circuit,” “specific circuit,” “given circuit,” etc.) refer to different examples of the feature. Furthermore, when applied to features, the labels “first,” “second,” and “third” do not imply any type of order (e.g., spatial, temporal, logical, etc.) unless otherwise specified.

[0070] The phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the decision; that is, the decision may be based on the specified factor alone, or on the specified factor plus other unspecified factors. Consider the phrase "determine A based on B." This phrase identifies B as a factor used to determine A or that influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factor, such as C. This phrase is intended to cover even one embodiment in which A is determined based solely on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0071] The phrases “in response to” and “in response to” describe one or more factors that trigger an effect. This phrase does not preclude the possibility that additional factors may influence, or otherwise trigger, the effect, either in conjunction with or independently of a specific factor. That is, the effect may depend on these factors alone, or on the specified factor and other unspecified factors. Consider the phrase “perform A in response to B.” This phrase means that B is a factor that triggers the performance of A, or a specific outcome with respect to A. This phrase does not preclude the performance of A from also being in response to other factors, such as C. This phrase also does not preclude the performance of A from being in response to both B and C. This phrase is intended to include embodiments in which A is performed solely in response to B. As used herein, the phrase “in response to” is synonymous with the phrase “in response to at least partially.” Similarly, the phrase “in response to” is synonymous with the phrase “in at least partially.” ***

[0072] Within this disclosure, various entities (which may be referred to as “units,” “circuits,” or other components, etc.) may be described or claimed to be “configured” to perform one or more tasks or operations. The expression “configured to perform one or more tasks” is used herein to refer to structures (i.e., physical things). More specifically, the expression is used to indicate that the structure is arranged to perform one or more tasks while in operation. A structure may be said to be “configured” to perform some task even when the structure is not currently in operation. Thus, entities described or explained as “configured” to perform some task refer to physical things such as devices, circuits, and systems having a processor unit and memory storing program instructions that can be executed to perform the task. This phrase is not used herein to refer to intangible things.

[0073] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. Even if not specifically stated, it is understood that those entities are "configured" to perform those tasks / operations.

[0074] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA is not considered "configured" to perform a particular function. However, this unprogrammed FPGA may be "configurable" to perform that function. After proper programming, the FPGA can then be said to be "configured" to perform a particular function.

[0075] For the purposes of a U.S. patent application based on this disclosure, to state in the claims that the structure is “configured” to perform one or more tasks is not intended to expressly invoke Section 112(f) of the U.S. Patent Act with respect to that claim. not present If the applicant wishes to invoke Section 112(f) of the U.S. Patent Application under this Disclosure during the examination process, it would use “means for” to perform the function to describe the elements of the claim.

[0076] This disclosure may describe various “circuits.” These circuits or “circuit configurations” constitute hardware that includes various types of circuit elements, such as combinational logic, clock memory devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), and programmable logic arrays. Circuits may be custom designed or obtained from standard libraries. In various implementations, circuit configurations may include digital components, analog components, or a combination of both, as needed. Certain types of circuits may generally be referred to as “units” (e.g., decoding units, arithmetic logic units (ALUs), function units, memory management units (MMUs), etc.). Such units also refer to circuits or circuit configurations.

[0077] The disclosed circuits / units / components and other elements shown in the drawings and described herein include hardware elements such as those described in the preceding paragraphs. Often, the internal arrangement of hardware elements within a particular circuit can be specified by describing the function of that circuit. For example, a particular “decoder unit” may be described as performing the function of “processing the opcode of an instruction and routing the instruction to one or more of several functional units,” meaning that the decoder unit is “configured” to perform this function. The detail of this function is sufficient to imply to a person skilled in the art of computer technology a set of possible structures of the circuit.

[0078] In various embodiments, as discussed in the preceding paragraph, circuits, units, and other elements may be defined by the function or operation they are configured to perform. The arrangement of such circuits / units / components relative to each other and the way they interact generates a microarchitecture definition of hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA, forming a physical implementation of the microarchitecture definition. Thus, a microarchitecture definition is recognized by those skilled in the art as a structure from which many physical implementation forms can be derived, all of which belong to the broader structure described by the microarchitecture definition. That is, a person skilled in the art, presented with the microarchitecture definitions provided pursuant to this disclosure, can implement the structure by coding the circuit / unit / component description in a hardware description language (HDL), such as Verilog or VHDL, using ordinary art without excessive experimentation. The HDL description is often expressed in a form that appears to be functional. However, to those skilled in the art, this HDL description is a method used to translate the structure of a circuit, unit, or component into the next level of implementation detail. Such HDL descriptions can take the form of operation-level code (typically not synthesizable), register transfer language (RTL) code (typically synthesizable, in contrast to operation-level code), or structure code (e.g., a netlist specifying logic gates and their connections). The HDL description may be synthesized against a library of cells designed for a given integrated circuit manufacturing technique, modified for timing, power, and other reasons, resulting in a final design database that can be sent to a foundry, generating a mask, and ultimately manufacturing the integrated circuit. Some hardware circuits, or parts thereof, can also be custom-designed in a schematic editor and incorporated into the integrated circuit design along with the synthesized circuits.An integrated circuit may further include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, and inductors), as well as interconnects between transistors and circuit elements. Some embodiments may implement multiple integrated circuits connected integrally to realize a hardware circuit, and / or, in some embodiments, separate elements may be used. Alternatively, the HDL design may be integrated into a programmable logic array such as a field programmable gate array (FPGA), and may be implemented on an FPGA. This decoupling between the design of this group of circuits and the subsequent low-level implementation of these circuits generally leads to scenarios where the circuit or logic designer does not specify any particular set of structures for low-level implementation forms other than a description of how the circuit is configured, because this process is performed at different stages of the circuit implementation process.

[0079] The fact that the same specifications of a circuit can be implemented using many different low-level combinations of circuit elements results in a multitude of equivalent structures for that circuit. As mentioned above, these low-level circuit implementation forms can vary depending on changes in manufacturing technology, the foundry chosen to manufacture the integrated circuit, the library of cells provided for a particular project, and so on. Often, the choice made by different design tools or methods to generate these different implementation forms can be arbitrary.

[0080] Furthermore, in a given embodiment, a single implementation of a specific functional specification of a circuit typically involves a large number of devices (e.g., millions of transistors). Therefore, given this sheer volume of information, it is impractical to fully enumerate the low-level structures used to implement a single embodiment, let alone a vast number of equivalent possible implementations. For this reason, this disclosure describes the circuit structure using functional omissions commonly used in the industry.

[0081] If the above disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. The following claims are intended to be interpreted as encompassing all such variations and modifications.

Claims

1. It is a device, A decoder configured to decode multiple bits and generate multiple control signals, A current source comprising multiple devices, wherein the current source is Using the plurality of control signals, activate at least a subset of the plurality of devices, A current source configured to supply load current to a light-emitting diode (LED) using the activated device and control voltage among the plurality of devices, An apparatus comprising: a control circuit configured to generate the control voltage based on the load current and a reference current.

2. The apparatus according to claim 1, wherein the control circuit includes an equalization circuit configured to generate a copy of the load current, and a regulator circuit configured to generate the control voltage using the copy of the load current.

3. The apparatus according to claim 2, wherein the equalization circuit includes a comparator circuit configured to generate a comparison voltage corresponding to the load current, and the copy of the load current is generated based on the comparison voltage.

4. The apparatus according to claim 3, wherein, when generating the comparison voltage, the comparator circuit is configured to compare a first drain voltage present on the control device of the regulator circuit with a second drain voltage present on the drain terminal of each of the plurality of devices.

5. The aforementioned regulator circuit is A comparator circuit configured to generate the control voltage by comparing the copy of the load current with the reference current, The apparatus according to claim 2, further comprising a control device having a gate terminal coupled to receive the control voltage, wherein the control device and some of the plurality of devices have substantially equal electrical characteristics.

6. The apparatus according to claim 5, wherein the load current is substantially equal to the current passing through the control device multiplied by the number of active devices among the plurality of devices.

7. The apparatus according to claim 2, wherein the equalization circuit includes a current mirror and a switch, wherein when the switch is in a first position, the current mirror is configured to mirror the current according to a first ratio, and when the switch is in a second position, the current mirror is configured to mirror the current according to a second ratio.

8. The apparatus according to claim 1, wherein the decoder is configured to provide a first subset of the plurality of bits to a reference current circuit configured to generate the reference current, and to provide a second subset of the plurality of bits to generate the plurality of control signals.

9. The apparatus according to claim 1, wherein the current source comprises an M-bit thermometric current digital-to-analog converter (IDAC) and an N-bit binary IDAC.

10. The apparatus according to claim 1, wherein the decoder is configured to use the least significant subset of bits used to generate the reference current and to use the most significant subset of bits used to generate the plurality of control signals.

11. It is a method, The process of generating multiple control signals, wherein the generation includes the decoding of multiple control bits by a decoder circuit. Activating at least a subset of the devices of the current source based on the aforementioned plurality of control signals, To provide a load current to a load circuit based on a control voltage provided to the activated device among the plurality of devices, A method comprising using a control circuit to generate the control voltage based on the load current and the reference current.

12. Using an equalization circuit, a copy of the load current is generated, The control voltage is generated using the regulator circuit and the copy of the load current, The method according to claim 11, further comprising:

13. The method of claim 12, wherein generating the copy of the load current comprises a comparator in the equalization circuit that generates a comparison voltage by comparing the drain voltage on the control device of the regulator circuit with the drain voltage on the activated device among the plurality of devices.

14. The control voltage is generated by comparing the copy of the load current with the reference current using the comparator of the regulator circuit, A control device, wherein the current passing through the control device is substantially equal to the current passing through each of the plurality of devices, and the control voltage is provided to the gate terminal of the control device. The method according to claim 12, further comprising:

15. The method according to claim 12, wherein the equalization circuit comprises a current mirror, and the method further comprises changing the ratio of the current mirror.

16. The method according to claim 11, further comprising the decoder circuit providing a first subset of the plurality of control signals to a reference current generator configured to generate the reference current, and providing a second subset of the plurality of control signals to control the activation of some of the plurality of devices.

17. It is a system, A current source configured to drive a load circuit with load current, wherein the current source includes a plurality of devices, A decoder circuit configured to selectively activate some of the multiple devices based on an input code, A control circuit configured to generate a control voltage supplied to the gate terminals of a replica device and a corresponding device among the plurality of devices, wherein the control circuit is configured to generate the control voltage based on a reference current, and the replica device and the plurality of devices of the current source have substantially equal electrical characteristics, comprising: A system in which the replica device is configured to generate a replica current, and the current source is configured to generate the load current based on the replica current and the number of the multiple devices that are active.

18. The aforementioned control circuit is An equalization circuit, wherein the equalization circuit is configured to generate a copy of the load current, The system according to claim 17, further comprising a regulator circuit configured to generate the control voltage based on the copy of the load current and the reference current.

19. The system according to claim 17, wherein the decoder circuit is a thermometric decoder configured to generate a plurality of bits based on an input code, to use a first subset of the plurality of bits to control the reference current, and to use a second subset of the plurality of bits to control the number of active devices among the plurality of devices.

20. The system according to claim 17, wherein the load circuit is a colored light-emitting diode (LED).

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