Sense amplifier and its control method, memory array structure, and memory

Abstract

The present invention provides a sense amplifier and a method for controlling the same, a memory array structure, and a memory, relating to the technology of memory. The sense amplifier comprises a first signal amplification unit in which a first terminal and a second terminal are used to electrically connect to a first voltage terminal and a second voltage terminal, respectively, and a third terminal and a fourth terminal function as a first node and a second node, respectively, and a second signal amplification unit in which a first terminal, a second terminal and a third terminal are used to electrically connect to a third voltage terminal, a fourth voltage terminal and a bit line, respectively, and a fourth terminal is electrically connected to the first node. The sense amplifier is configured to amplify the voltage of the first node to a first voltage or a second voltage in the first signal amplification stage, and to write the second voltage or the first voltage back to the memory unit in the second signal amplification stage. The structure of the sense amplifier according to the embodiment of the present disclosure can replace an edge reference array, thus eliminating the need for an additional reference array, further reducing the chip size and chip cost.

Description

Technical Field

[0001] The present disclosure relates to the technical field of memory, and specifically relates to a sense amplifier and its control method, a memory array structure, and a memory.

Background Art

[0002] Currently, most DRAMs (Dynamic Random Access Memories) reduce the chip cost by reducing the chip size using an open bit line structure open BL mode.

[0003] However, in the open bit line structure, the reference voltage of each bit line is supplied from the other adjacent memory unit on the other side, and a reference voltage is required every time the signal of the bit line is detected and amplified. The drawback of such an existing structure is that an additional reference array needs to be set at the edge of each memory unit in the memory array structure and controlled by a control logic corresponding to the reference array. As a result, the area of the entire chip becomes large and the chip size increases.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present disclosure provides a sense amplifier and its control method, a memory array structure, and a memory for the drawbacks of the prior art, thereby solving the technical problem that the chip size in the prior art increases due to setting an additional reference array.

Means for Solving the Problems

[0005] In a first aspect, an embodiment of the present disclosure is a sense amplifier, wherein A first signal amplification unit in which the first terminal and the second terminal are used to electrically connect to the first voltage terminal and the second voltage terminal, respectively, and the third terminal and the fourth terminal function as the first node and the second node, wherein the first voltage terminal is used to output the first voltage, the second voltage terminal is used to output the second voltage, and the first voltage is greater than the second voltage, A second signal amplification unit comprising: a first terminal, a second terminal, and a third terminal used to electrically connect to a third voltage terminal, a fourth voltage terminal, and a bit line, respectively, and the fourth terminal being electrically connected to a first node, wherein the voltage of the third voltage terminal is the same as the voltage of the first voltage terminal, the voltage of the fourth voltage terminal is the same as the voltage of the second voltage terminal, and the bit line is used to electrically connect to a memory unit of a memory array structure; The sense amplifier is configured to amplify the voltage at the first node to a first voltage or a second voltage by turning on the first terminal, first node, and second terminal of the first signal amplification unit in the first signal amplification stage, and to amplify the voltage of the bit line to a second voltage or a first voltage by turning on the first and third terminals of the second signal amplification unit, or by turning on the second and third terminals, thereby writing the second voltage or a first voltage back to the memory unit.

[0006] In a second aspect, an embodiment of the present disclosure is a memory array structure comprising a plurality of bit lines, a plurality of word lines, a plurality of memory units arranged in a matrix, and a plurality of sense amplifiers as described in the first aspect. One bit line is electrically connected to a corresponding row of memory units. One word line is electrically connected to a corresponding row of memory units. Each bit line is electrically connected to the third terminal of the second signal amplification unit of a sense amplifier, providing a memory array structure.

[0007] In a third aspect, an embodiment of the present disclosure provides a dynamic random access memory comprising the memory array structure described in the second aspect.

[0008] In a fourth aspect, an embodiment of the present disclosure provides an electronic device comprising the memory array structure described in the second aspect or the dynamic random access memory described in the third aspect.

[0009] In the fifth aspect, an embodiment of the present disclosure is a control method applied to the sense amplifier described in the first aspect, The first signal amplification step involves controlling the first terminal, first node, and second terminal of the first signal amplification unit to be ON, thereby amplifying the voltage at the first node to a first voltage or a second voltage. The present invention provides a control method comprising: a second signal amplification step, which involves controlling the first and third terminals of a second signal amplification unit to be turned ON, or by controlling the second and third terminals to be turned ON, thereby amplifying the voltage of a bit line to a second voltage or a first voltage, and writing the second voltage or first voltage back to a memory unit of a memory array structure. [Effects of the Invention]

[0010] The beneficial technical effects of the technical solutions provided in the embodiments of this disclosure are as follows:

[0011] The sense amplifier according to the embodiment of this disclosure can, in the first signal amplification stage, amplify the voltage of the first node to a first voltage or a second voltage via the first signal amplification unit, and in the second signal amplification stage, amplify the voltage of the bit line correspondingly to a second voltage or a first voltage via the second signal amplification unit, thereby writing the second voltage or first voltage back to the memory unit and improving the data write-back effect. The embodiment of this disclosure designs a new sense amplifier that can achieve signal detection amplification based on the first and second signal amplification units of the sense amplifier, and when the sense amplifier is applied to a memory, it eliminates the need to set a reference array at the edge of the memory array structure of the memory, significantly reducing the overhead of the reference array area required at the edge of the open bit line structure, thereby reducing the chip size. Furthermore, the embodiment of this disclosure can add a second signal amplification unit to an existing sense amplifier, optimizing the structure of the sense amplifier to replace the edge reference array, further reducing the chip size and chip cost.

[0012] Additional aspects and benefits of this disclosure are partially described in the following description and may be apparent from the following description or may be understood through the implementation of this disclosure. [Brief explanation of the drawing]

[0013] The above and / or additional aspects and advantages of this disclosure will become apparent and readily apparent from the description of the embodiments with reference to the following drawings. [Figure 1] Figure 1 is a schematic diagram of the structure of a first type sense amplifier according to an embodiment of the present disclosure. [Figure 2] Figure 2 is a schematic diagram of the structure of a second type sense amplifier according to an embodiment of the present disclosure. [Figure 3] Figure 3 is a schematic diagram of the structure of a third type sense amplifier according to an embodiment of the present disclosure. [Figure 4] Figure 4 is a schematic diagram of the structure of a fourth type sense amplifier according to an embodiment of the present disclosure. [Figure 5]FIG. 5 is a structural schematic diagram of a fifth type of sense amplifier according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a structural schematic diagram of a sixth type of sense amplifier according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a structural schematic diagram of a seventh type of sense amplifier connected to a memory unit according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a structural schematic diagram of a seventh type of sense amplifier connected to a memory unit and a port according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is a structural schematic diagram of a memory array structure according to an embodiment of the present disclosure. [Figure 10] FIG. 10 is a flowchart of a control method according to an embodiment of the present disclosure. [Figure 11] FIG. 11 is a flowchart of another control method according to an embodiment of the present disclosure. [Figure 12] FIG. 12 is a flowchart of another control method according to an embodiment of the present disclosure. [Figure 13] FIG. 13 is a timing control diagram of a sense amplifier according to an embodiment of the present disclosure. [Figure 14] FIG. 14 is a schematic diagram when the timing control diagram of FIG. 13 is divided into five stages. [Figure 15] FIG. 15 is a timing control diagram of another sense amplifier according to an embodiment of the present disclosure. [Figure 16] FIG. 16 is a schematic diagram when the timing control diagram of FIG. 15 is divided into seven stages.

DETAILED DESCRIPTION OF THE INVENTION

[0014] The present disclosure is described in detail below, and the drawings illustrate examples of embodiments of the present disclosure. In the accompanying drawings, identical or similar reference numerals indicate identical or similar components, or components having identical or similar functions, throughout the entire disclosure. Detailed descriptions of the prior art are omitted where unnecessary to the features of the present disclosure. The embodiments described below with reference to the drawings are illustrative and are for interpretation purposes only, and do not limit the present disclosure.

[0015] Unless otherwise defined in a manner understandable to those skilled in the art, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art in which this disclosure pertains. Furthermore, terms defined in general dictionaries, etc., have the same meaning as in the context of the prior art and, unless specifically defined herein, should not be interpreted as idealized or overly formal.

[0016] As those skilled in the art will understand, unless otherwise specified, the singular forms “one,” “one,” “the said,” and “the said” as used herein also include the plural forms. Furthermore, it should be understood that the term “including” as used in this disclosure means that the features, integers, steps, operations, elements, and / or assemblies exist, but do not exclude the existence or addition of one or more other features, integers, steps, operations, elements, assemblies, and / or groups thereof. It should be understood that when it is stated that one element is “connected” or “joined” to another element, it may be directly connected or joined to the other element, or there may be intermediate elements. Also, “connected” or “joined” as used herein may include wireless connection or wireless coupling. The term “and / or” as used herein includes all or any one unit of one or more related enumeration items, and all combinations thereof.

[0017] The following describes in detail the technical solutions of this disclosure and how they solve the above-mentioned technical problems, with specific examples.

[0018] Embodiments of the present disclosure provide a sense amplifier, the sense amplifier 10 comprising a first signal amplification unit 110 and a second signal amplification unit 120, as shown in Figure 1.

[0019] The first and second terminals of the first signal amplification unit 110 are used to electrically connect to the first voltage terminal and the second voltage terminal, respectively. The third and fourth terminals of the first signal amplification unit 110 function as the first node A and the second node B, respectively. The first voltage terminal is used to output the first voltage, and the second voltage terminal is used to output the second voltage, with the first voltage being greater than the second voltage.

[0020] Selectively, as shown in Figure 1, the voltage signal output from the first voltage terminal is RTO, and the voltage signal output from the second voltage terminal is SB. The first and second voltage terminals are power supply terminals and supply two power supply signals. A switch device may be provided between the first voltage terminal and the first terminal of the first signal amplification unit 110. When the switch device is turned on, the first voltage terminal turns on and the unit is in operation. Similarly, a switch device may be provided between the second terminal and the second voltage terminal of the first signal amplification unit 110. When the switch device is turned on, the second voltage terminal turns on and the unit is in operation.

[0021] Selectively, RTO has a voltage of 0.5V in the non-operating state and a voltage of 1.0V in the operating state, while SB has a voltage of 0.5V in the non-operating state and a voltage of 0V in the operating state. In the operating state, the first voltage may be 1V, and the second voltage may be 0V.

[0022] The first, second, and third terminals of the second signal amplification unit 120 are used to electrically connect to the third voltage terminal, the fourth voltage terminal, and the bit line, respectively. The fourth terminal of the second signal amplification unit 120 is electrically connected to the first node A. The voltage at the third voltage terminal is the same as the voltage at the first voltage terminal, and the voltage at the fourth voltage terminal is the same as the voltage at the second voltage terminal.

[0023] As shown in Figures 1 and 7, the bit line BL (Bit-line, abbreviated BL) is used to electrically connect to the memory unit 20 of the memory array structure. The bit line may also be used for data transmission and location identification. The bit line BL is further used to electrically connect to the second node B.

[0024] Selectively, as shown in Figure 1, the voltage signal output from the third voltage terminal is RTO1, and the voltage signal output from the fourth voltage terminal is SB1. The third and fourth voltage terminals correspond to and are similar to the first and second voltage terminals, respectively, and are also power supply terminals, supplying two power supply signals. Selectively, like the RTO, RTO1 has a voltage of 0.5V in the non-operating state and a voltage of 1.0V in the operating state, the voltage at the third voltage terminal becomes the first voltage in the operating state and may be 1V, and SB1 is 0V.

[0025] The sense amplifier 10 is configured to amplify the voltage at the first node A to the first voltage or the second voltage by turning on the first terminal, first node A, and second terminal of the first signal amplification unit 110 in the first signal amplification stage, and to amplify the voltage of the bit line to the second voltage or the first voltage by turning on the first and third terminals of the second signal amplification unit 120, or by turning on the second and third terminals, thereby writing the second voltage or the first voltage back to the memory unit 20.

[0026] Specifically, the first and third terminals or the second and third terminals of the second signal amplification unit 120 are turned on by the control of the first node A, and the voltage of the first node A is the second voltage or the first voltage, which can be used to control whether the first and third terminals of the second signal amplification unit 120 are turned on or the second and third terminals are turned on accordingly.

[0027] For example, the sense amplifier 10 may be configured to amplify the voltage at the first node A to a first voltage by turning on the first terminal, first node A, and second terminal of the first signal amplification unit 110 in the first signal amplification stage, and to amplify the voltage of the bit line to a second voltage by turning on the second terminal and third terminal of the second signal amplification unit 120 in the second signal amplification stage, thereby writing the second voltage back to the memory unit 20.

[0028] Currently, DRAM size units have a 1T1C structure, resulting in a large area ratio and a complex manufacturing process. Sense amplifiers generally use a simple MOS transistor (Metal Oxide Semiconductor Field Effect Transistor) structure, making them easy to manufacture and resulting in a small area. Because the DRAM's open BL requires a reference voltage each time it performs detection amplification, typical DRAMs require a reference array at the edge to serve as the detection reference during reading and writing of the memory unit. The sense amplifier 10 according to the embodiment of this disclosure features a novel structural design that enables detection amplification using only a single sense amplifier 10, eliminating the need to manufacture an additional reference array and thus reducing the chip area.

[0029] The sense amplifier 10 according to the embodiment of this disclosure can amplify the voltage of the first node A to a first voltage or a second voltage via the first signal amplification unit 110 in the first signal amplification stage, and amplify the voltage of the bit line to a second voltage or a first voltage via the second signal amplification unit 120 in the second signal amplification stage, thereby writing the second voltage or first voltage back to the memory unit 20 and improving the data write-back effect. The embodiment of this disclosure designs a new sense amplifier 10 that can achieve signal detection amplification based on the first signal amplification unit 110 and the second signal amplification unit 120 of the sense amplifier. When the sense amplifier is applied to a memory, it is not necessary to set up a reference array at the edge of the memory array structure of the memory, and the overhead of the reference array area required at the edge of the open bit line structure is greatly reduced, thereby reducing the chip size. Furthermore, the embodiment of this disclosure can add the second signal amplification unit 120 to an existing sense amplifier, optimizing the structure of the sense amplifier 10 to replace the edge reference array, further reducing the chip size and chip cost.

[0030] Similarly, the sense amplifier 10 may be configured to further amplify the voltage at the first node A to the second voltage by turning on the first terminal, first node A, and second terminal of the first signal amplification unit 110 in the first signal amplification stage, and to amplify the voltage of the bit line to the first voltage by turning on the first terminal and third terminal of the second signal amplification unit 120 in the second signal amplification stage, thereby writing the first voltage back to the memory unit 20.

[0031] In some embodiments, as shown in Figure 2, the fifth and sixth terminals of the first signal amplification unit 110 function as the third node C and the fourth node D, respectively.

[0032] The sense amplifier 10 further includes a third signal amplification unit 130.

[0033] The first, second, and third terminals of the third signal amplification unit 130 are used to electrically connect to the fifth voltage terminal, the sixth voltage terminal, and the first data signal line, respectively. The fourth terminal of the third signal amplification unit 130 is electrically connected to the third node C. The voltage of the fifth voltage terminal is the same as the voltage of the first voltage terminal, the voltage of the sixth voltage terminal is the same as the voltage of the second voltage terminal, and the first data signal line is used to electrically connect to the port.

[0034] As shown in Figure 2, the voltage signal output from the fifth voltage terminal is RTO2, and the voltage signal output from the sixth voltage terminal is SB2. The fifth and sixth voltage terminals correspond to and are similar to the first and second voltage terminals, respectively, and are also power supply terminals, supplying two power supply signals. Selectively, RTO2, like RTO, has a voltage of 0.5V in the non-operating state and a voltage of 1.0V in the operating state. The voltage at the fifth voltage terminal becomes the first voltage in the operating state and may be 1V, and the voltage at the sixth voltage terminal becomes the second voltage in the operating state and may be 0V.

[0035] The sense amplifier 10 is further configured to amplify the voltage at the third node C to the second or first voltage by turning on the first terminal, third node C, and second terminal of the first signal amplification unit 110 in the first signal amplification stage, and to amplify the voltage of the first data signal line to the first or second voltage by turning on the first and third terminals of the third signal amplification unit 130, or by turning on the second and third terminals, thereby outputting the first or second voltage to the port.

[0036] Specifically, the first and third terminals or the second and third terminals of the third signal amplification unit 130 are turned on by the control of the third node C, and the voltage of the third node C is the second voltage or the first voltage, which can be used to control whether the first and third terminals or the second and third terminals of the third signal amplification unit 130 are turned on accordingly.

[0037] For example, the sense amplifier 10 may be configured to amplify the voltage at the third node C to a second voltage by turning on the first terminal, third node C, and second terminal of the first signal amplification unit 110 in the first signal amplification stage, and to amplify the voltage of the first data signal line to a first voltage by turning on the first terminal and third terminal of the third signal amplification unit 130 in the second signal amplification stage, thereby outputting the first voltage to the port.

[0038] Specifically, the structures of the third signal amplification unit 130 and the second signal amplification unit 120 are identical, and the third signal amplification unit 130 and the second signal amplification unit 120 correspond to two inverter structures for data recovery.

[0039] Selectively, as shown in Figure 2, the third signal amplification unit 130 and the second signal amplification unit 120 are installed on either side of the first signal amplification unit 110 in a symmetrical structure. Considering that the loads at both ends of the bit line BL and the first data signal line BLB on either side of the first signal amplification unit 110 are different, the bit line BL is connected to the memory unit 20, but the first data signal line BLB is not connected to the memory unit 20. In order to prevent data errors due to interference during reading, the small voltage difference between the bit line BL and the first data signal line BLB is sensed during the first signal amplification and amplified to the first node A and the third node C. Then, during the second signal amplification, the voltage signals of the bit line BL and the first data signal line BLB are amplified via the second signal amplification unit 120 and the third signal amplification unit 130, thereby ensuring the reliability of the amplification process.

[0040] Similarly, the sense amplifier 10 is configured to further amplify the voltage at the third node C to a first voltage by turning on the first terminal, third node C, and second terminal of the first signal amplification unit 110 in the first signal amplification stage, and to amplify the voltage of the first data signal line to a second voltage by turning on the second terminal and third terminal of the third signal amplification unit 130 in the second signal amplification stage, thereby outputting the second voltage to the port.

[0041] In some embodiments, as shown in Figure 3, the sense amplifier 10 further comprises a first isolation unit 140.

[0042] The control terminal of the first isolation unit 140 is used to electrically connect to the first isolation signal line, and the first and second terminals of the first isolation unit 140 are used to electrically connect to the first reference voltage terminal and the first data signal line, respectively.

[0043] The first isolation unit 140 is configured to amplify the voltage of the first data signal line by turning off its first and second terminals during the second signal amplification stage.

[0044] As an example, the first isolation unit 140 may be configured to amplify the voltage of the first data signal line to the first voltage or the second voltage by turning off its first and second terminals during the second signal amplification stage. As shown in Figure 7, during the first detection amplification process at SABL (first node A), the voltage on SABL will be different depending on whether 0 or 1 is stored in the memory unit 20. If 0 is stored, the voltage on SABL will be the first voltage (RTO), and in the second signal amplification, the voltage written back by the bit line BL will be the voltage of SB1. Conversely, if 1 is stored in the memory unit 20, the voltage on SABL will be the second voltage (SB), and in the second detection amplification, the voltage written back by BL will be the RTO1 voltage.

[0045] As shown in Figure 3, the control signal received by the first isolation signal is ISO3, and the reference voltage at the first reference voltage terminal is V BLEP ISO3 can control the on / off state of the first and second terminals of the first isolation unit 140, and when the first and second terminals of the first isolation unit 140 are turned off, the voltage of the first data signal line BLB is the reference voltage V of the first reference voltage terminal. BLEP Insulated from, reference voltage V BLEP By eliminating the influence of this, the problem with the edge reference voltage signal is resolved. The first reference voltage terminal may be a 0.5V power supply, i.e., VBLEP It can also be 0.5V.

[0046] In some embodiments, as shown in Figure 4, the sense amplifier 10 further comprises a second isolation unit 150.

[0047] The control terminal and first terminal of the second isolation unit 150 are used to electrically connect to the second isolation signal line and bit line, respectively, and the second terminal of the second isolation unit 150 is electrically connected to the second node B. The second isolation unit 150 is configured to turn on its first and second terminals when operating and to turn off its first and second terminals when non-operating.

[0048] As shown in Figure 4, the control signal received by the second isolated signal line is ISO2, which can control the on / off state of the first and second terminals of the second isolated unit 150. When the first and second terminals of the second isolated unit 150 are turned off, the bit line and the second node B are turned off, the sense amplifier 10 is disconnected from the port, the port load effect is blocked, and the impact on the read / write effect is avoided.

[0049] In some embodiments, as shown in Figure 4, the sense amplifier 10 further comprises a third isolation unit 160.

[0050] The control terminals of the third isolation unit 160 are used to electrically connect to the third isolation signal line, the first and second terminals of the third isolation unit 160 are electrically connected to the first data signal line and the fourth node D, respectively, and the third isolation signal line is electrically connected to the second isolation signal line. The third isolation unit 160 is configured to turn on its first and second terminals when operating and to turn off its first and second terminals when non-operating.

[0051] As shown in Figure 4, the setting principle of the third isolation unit 160 is the same as that of the second isolation unit 150. The control signal received by the third isolation signal line is ISO2, which can control the on / off state of the first and second terminals of the third isolation unit 160. When the first and second terminals of the third isolation unit 160 are turned off, the first data signal line and the fourth node D are also turned off. Since both the bit line and the first data signal line are connected to the port, and the IO and the inverted IO signal IOB are output, the control signal ISO2 can disconnect the sense amplifier 10 from the port, blocking the port load effect and avoiding any impact on the read / write effect.

[0052] In some embodiments, as shown in Figure 5, the sense amplifier 10 further comprises a first precharge unit 170, a second precharge unit 180, and a fourth isolation unit 190.

[0053] The control terminal of the first precharge unit 170 is used to electrically connect to the first signal line, the first terminal of the first precharge unit 170 is used to electrically connect to the first reference voltage terminal, the second terminal of the first precharge unit 170 is electrically connected to the third node C, and the first reference voltage terminal is used to output the first reference voltage. The control terminals of the second precharge unit 180 are used to electrically connect to the second signal line, and the first and second terminals of the second precharge unit 180 are electrically connected to the first node A and the third node C, respectively. The control terminals of the fourth isolation unit 190 are used to electrically connect to the fourth isolation signal line, and the first, second, third, and fourth terminals of the fourth isolation unit 190 are electrically connected to the second node B, the third node C, the first node A, and the fourth node D, respectively.

[0054] As shown in Figure 5, the reference voltage output from the first reference voltage terminal is V BLEPThe control signal output from the first signal line is PRE, the control signal output from the second signal line is EQ, and the control signal output from the fourth isolated signal line is ISO1. PRE can control the on / off state of the first and second terminals of the first precharge unit 170, EQ can control the on / off state of the first and second terminals of the second precharge unit 180, and ISO1 can control the on state of the first and second terminals, third and fourth terminals, and the off state of the first and second terminals, third and fourth terminals of the fourth isolated unit 190.

[0055] The sense amplifier 10 is further configured to precharge the first node A, the third node C, the bit line, and the first data signal line to a predetermined voltage by controlling the first and second terminals of the first precharge unit 170 to turn on, the first and second terminals of the second precharge unit 180 to turn on, the first and second terminals of the fourth isolation unit 190 to turn on and the third and fourth terminals to turn on, and the first and second terminals of the first isolation unit 140 to turn on.

[0056] The sense amplifier 10 is further configured to perform charge sharing between a predetermined voltage of the bit line and the capacitor of the memory unit 20 by controlling the first and second terminals of the first precharge unit 170 to be turned off during the charge sharing stage, and by controlling the first and second terminals of the second precharge unit 180 to be turned off.

[0057] Specifically, the specified voltage is the reference voltage, V BLEP It can also be 0.5V.

[0058] Specifically, as shown in Figure 7, each memory unit 20 in the memory array structure is configured with a 1T1C structure, and a control signal WL that controls the word line can be used to control charge sharing between the bit line BL and the capacitor of the memory unit 20. Charge is exchanged between the load capacitance on the bit line BL and the storage capacitance of the memory unit 20, and the voltage stored internally is shared on the bit line BL. After charge sharing, the bit line BL will no longer be 0.5V, and if 0V is stored in the memory unit 20, the voltage of the bit line BL will be lower than 0.5V, and if 1V is stored in the memory unit 20, the voltage of the bit line BL will be higher than 0.5V.

[0059] The sense amplifier 10 is further configured to amplify the voltage at the third node C to a first voltage or a second voltage by controlling the first and second terminals of the fourth isolation unit 190 to the off and the third and fourth terminals to the off and controlling the first terminal, third node C and second terminals of the first signal amplification unit 110 to the on in the first signal amplification stage, and by controlling the first and second terminals of the first isolation unit 140 to the off and the first and second terminals of the fourth isolation unit 190 to the on and the third and fourth terminals to the on and controlling the first and third terminals of the third signal amplification unit 130 of the sense amplifier 10 to the on or the second and third terminals to the on in the second signal amplification stage, thereby amplifying the voltage at the first data signal line to a second voltage or a first voltage, and thereby outputting the second voltage or a first voltage to the port.

[0060] Selectively, the sense amplifier 10 is configured to further control, in the second precharge stage, to turn off the first terminal, first node A and second terminal of the first signal amplification unit 110, to turn off the first terminal, third node C and second terminal of the first signal amplification unit 110, to turn off the first and third terminals of the second signal amplification unit 120 and to turn off the second and third terminals, to turn off the first and third terminals of the third signal amplification unit 130 and to turn off the second and third terminals, to disconnect the electrical connection between the bit line and the memory unit 20, to turn on the first and second terminals of the first precharge unit 170, and to turn on the first and second terminals of the second precharge unit 180, thereby precharging the first node A, third node C, bit line and first data signal line to a predetermined voltage. The second precharge stage prepares for the next data read.

[0061] In some embodiments, as shown in Figure 6, the sense amplifier 10 further comprises an offset removal unit 1100.

[0062] The control terminals of the offset removal unit 1100 are used to electrically connect to the offset removal signal line, and the first, second, third, and fourth terminals of the offset removal unit 1100 are electrically connected to the second node B, the first node A, the third node C, and the fourth node D, respectively.

[0063] As shown in Figure 6, the control signal output from the offset removal signal line is OC, which can control the on-turn-on and off-turn-off of the first and second terminals, third and fourth terminals of the offset removal unit 1100.

[0064] As another example, the sense amplifier 10 is further configured to precharge the first node A, the third node C, the bit line and the first data signal line to a predetermined voltage by controlling the first and second terminals of the first precharge unit 170 of the sense amplifier 10 to turn on, controlling the first and second terminals of the second precharge unit 180 of the sense amplifier 10 to turn on, controlling the first and second terminals and the third and fourth terminals of the offset removal unit 1100 of the sense amplifier 10 to turn on, and controlling the first and second terminals of the first isolation unit 140 of the sense amplifier 10 to turn on.

[0065] The sense amplifier 10 is further configured to remove the offset of the threshold voltage of the switch devices at terminals 4 and 6 of the first signal amplification unit 110 by controlling the first and second terminals of the first precharge unit 170 to the OFF position, the first and second terminals of the second precharge unit 180 to the OFF position, the first and second terminals of the first isolation unit 140 to the OFF position, the first terminal, first node A and second terminal of the first signal amplification unit 110 to the ON position, and the first terminal, third node C and second terminal of the first signal amplification unit 110 to the ON position.

[0066] The sense amplifier 10 is further configured to precharge the first node A and the third node C to a predetermined voltage in the fourth precharge stage by controlling the first and second terminals of the offset removal unit 1100 to the OFF position and the third and fourth terminals to the OFF position, controlling the first and second terminals of the first precharge unit 170 to the ON position, and controlling the first and second terminals of the second precharge unit 180 to the ON position.

[0067] In some embodiments, as shown in Figure 7, the second signal amplification unit 120 includes a first switch module 121 and a second switch module 122.

[0068] The control terminals of the first switch module 121 and the second switch module 122 both function as the fourth terminals of the second signal amplification unit 120. The first terminal of the first switch module 121 functions as the first terminal of the second signal amplification unit 120. The second terminal of the second switch module 122 functions as the second terminal of the second signal amplification unit 120. The second terminal of the first switch module 121 and the first terminal of the second switch module 122 both function as the third terminal of the second signal amplification unit 120.

[0069] Selectively, the first switch module 121 includes a first switch device T1, and the second switch module 122 includes a second switch device T2, wherein the gate of the first switch device T1 is the control terminal of the first switch module 121, the source and drain electrodes of the first switch device T1 are the first and second terminals of the first switch module 121, the gate of the second switch device T2 is the control terminal of the second switch module 122, and the source and drain electrodes of the second switch device T2 are the first and second terminals of the second switch module 122. Specifically, the configuration of the switch devices is done according to the actual circuit requirements.

[0070] For example, the first switch device T1 may be a PMOS, the second switch device T2 may be an NMOS, the first terminal of the first switch module 121 is the source electrode of the PMOS, the second terminal of the first switch module 121 is the drain electrode of the PMOS, the first terminal of the second switch module 122 is the drain electrode of the NMOS, and the second terminal of the second switch module 122 is the source electrode of the NMOS.

[0071] In some embodiments, as shown in Figure 7, the third signal amplification unit 130 includes a third switch module 131 and a fourth switch module 132. The control terminals of the third switch module 131 and the fourth switch module 132 both function as the fourth terminals of the third signal amplification unit 130. The first terminal of the third switch module 131 functions as the first terminal of the third signal amplification unit 130. The second terminal of the fourth switch module 132 functions as the second terminal of the third signal amplification unit 130. The second terminal of the third switch module 131 and the first terminal of the fourth switch module 132 both function as the third terminal of the third signal amplification unit 130.

[0072] Selectively, as shown in Figure 7, the third switch module 131 includes the third switch device T3, and the fourth switch module 132 includes the fourth switch device T4, with the gate of the third switch device T3 being the control terminal of the third switch module 131, the source and drain electrodes of the third switch device T3 being the first and second terminals of the third switch module 131, the gate of the fourth switch device T4 being the control terminal of the fourth switch module 132, and the source and drain electrodes of the fourth switch device T4 being the first and second terminals of the fourth switch module 132. Specifically, the circuit connections are made according to the actual circuit requirements.

[0073] For example, the third switch device T3 may be a PMOS, the fourth switch device T4 may be an NMOS, the first terminal of the third switch module 131 is the source electrode of the PMOS, the second terminal of the third switch module 131 is the drain electrode of the PMOS, the first terminal of the fourth switch module 132 is the drain electrode of the NMOS, and the second terminal of the fourth switch module 132 is the source electrode of the NMOS.

[0074] In some embodiments, as shown in Figure 7, the first signal amplification unit 110 includes a fifth switch module 111, a sixth switch module 112, a seventh switch module 113, and an eighth switch module 114.

[0075] The first terminal of the fifth switch module 111 and the first terminal of the sixth switch module 112 both function as the first terminal of the first signal amplification unit 110. The second terminal of the fifth switch module 111 and the first terminal of the seventh switch module 113 both function as the third terminal of the first signal amplification unit 110, and the second terminal of the sixth switch module 112 and the first terminal of the eighth switch module 114 both function as the fifth terminal of the first signal amplification unit 110. The second terminal of the seventh switch module 113 and the second terminal of the eighth switch module 114 both function as the second terminal of the first signal amplification unit 110. The control terminal of the fifth switch module 111 is electrically connected to the third node C, and the control terminal of the sixth switch module 112 is electrically connected to the first node A. The control terminal of the seventh switch module 113 functions as the fourth terminal of the first signal amplification unit 110, and the control terminal of the eighth switch module 114 functions as the sixth terminal of the first signal amplification unit 110.

[0076] As an example, as shown in Figure 7, the fifth switch module 111 includes the fifth switch device T5, the sixth switch module 112 includes the sixth switch device T6, the seventh switch module 113 includes the seventh switch device T7, and the eighth switch module 114 includes the eighth switch device T8. The fifth switch device T5 and the sixth switch device T6 may be PMOS, and the seventh switch device T7 and the eighth switch device T8 may be NMOS. Specifically, the configuration of the switch devices is done according to the actual circuit requirements.

[0077] Selectively, the gates of the fifth switch device T5, the sixth switch device T6, the seventh switch device T7, and the eighth switch device T8 are the control terminals of the fifth switch module 111, the sixth switch module 112, the seventh switch module 113, and the eighth switch module 114, respectively, and the source and drain electrodes of the fifth switch device T5, the sixth switch device T6, the seventh switch device T7, and the eighth switch device T8 are correspondingly the first and second terminals of the fifth switch module 111, the sixth switch module 112, the seventh switch module 113, and the eighth switch module 114.

[0078] In some embodiments, as shown in Figure 7, the fourth isolation unit 190 includes a ninth switch module 191 and a tenth switch module 192. The control terminals of the 9th switch module 191 and the 10th switch module 192 both function as control terminals of the 4th isolation unit 190. The first and second terminals of the ninth switch module 191 function as the second and first terminals of the fourth isolation unit 190, respectively. The first and second terminals of the tenth switch module 192 function as the third and fourth terminals of the fourth isolation unit 190, respectively.

[0079] As an example, as shown in Figure 7, the ninth switch module 191 includes the ninth switch device T9, and the tenth switch module 192 includes the tenth switch device T10, and the ninth switch device T9 and the tenth switch device T10 may be NMOS. The gates of the ninth switch device T9 and the tenth switch device T10 are the control terminals of the ninth switch module 191 and the tenth switch module 192, respectively, and the source and drain electrodes of the ninth switch device T9 and the tenth switch device T10 are the first and second terminals of the ninth switch module 191 and the tenth switch module 192, respectively.

[0080] In some embodiments, as shown in Figure 7, the offset removal unit 1100 includes an 11th switch module 1101 and a 12th switch module 1102. The control terminals of the 11th switch module 1101 and the 12th switch module 1102 both function as control terminals for the offset removal unit 1100. The first and second terminals of the 11th switch module 1101 function as the second and first terminals of the offset removal unit 1100, respectively. The first and second terminals of the 12th switch module 1102 function as the third and fourth terminals of the offset removal unit 1100, respectively.

[0081] As an example, as shown in Figure 7, the 11th switch module 1101 includes the 11th switch device T11, the 12th switch module 1102 includes the 12th switch device T12, and the 11th switch device T11 and the 12th switch device T12 may be NMOS. The gates of the 11th switch device T11 and the 12th switch device T12 are the control terminals of the 11th switch module 1101 and the 12th switch module 1102, respectively, and the source and drain electrodes of the 11th switch device T11 and the 12th switch device T12 are the first and second terminals of the 11th switch module 1101 and the 12th switch module 1102, respectively.

[0082] As shown in Figure 7, the first isolation unit 140 includes the 13th switch device T13, the second isolation unit 150 includes the 14th switch device T14, and the third isolation unit 160 includes the 15th switch device T15. The gates of the 13th switch device T13, the 14th switch device T14, and the 15th switch device T15 are the control terminals of the first isolation unit 140, the second isolation unit 150, and the third isolation unit 160, respectively. The source and drain electrodes of the 13th switch device T13, the 14th switch device T14, and the 15th switch device T15 are the first and second terminals of the first isolation unit 140, the second isolation unit 150, and the third isolation unit 160, respectively.

[0083] Figure 8 shows a schematic diagram of the structure of the memory unit 20 and the sense amplifier connected to the port. IOB is the inverted signal of IO and is output to the port. RTO1 and SB1 connected to the second signal amplification unit 120, and RTO2 and SB2 connected to the third signal amplification unit 130 provide IO and IOB, respectively. When performing a data read operation at the stage when RTO1 and SB1 and RTO2 and SB2 are turned on simultaneously, RTO1 and SB1 and RTO2 and SB2 can improve the data transmission effect at the port. Even after turning on the switch device CSL, data stability at IO and IOB can be ensured. Turning on the switch device CSL provides data read functionality, and turning off the switch device CSL blocks the impact of IO load on read / write performance.

[0084] Based on the same inventive concept, embodiments of the present disclosure provide a memory array structure, as shown in Figure 9, the memory array structure comprises a plurality of bit lines, a plurality of word lines, a plurality of memory units 20 arranged in a matrix, and a plurality of sense amplifiers 10 as described in embodiments of the present disclosure. One bit line is electrically connected to a corresponding row of memory units 20. One word line is electrically connected to a corresponding row of memory units 20. Each bit line is electrically connected to the third terminal of the second signal amplification unit 120 of a sense amplifier 10.

[0085] As shown in Figures 7 to 9, the memory unit 20 includes a switch device 16 and a capacitor. The control terminal of the switch device 16 is electrically connected to the word line, and the connection and disconnection between the memory unit 20 and the bit line BL are controlled by controlling the on / off state of the switch device 16 with an output control signal WL that controls the word line.

[0086] It should be noted that the circuit connection method described herein is merely one example of a sense amplifier according to the embodiments of this disclosure. Each switch device can be selected from different transistors such as PMOS or NMOS as needed, and the electrical connection method of each element in the sense amplifier according to the embodiments of this disclosure can be adaptively adjusted. The adaptively adjusted electrical connection method still falls within the scope of protection of the embodiments of this disclosure.

[0087] Based on the same inventive concept, embodiments of the present disclosure provide a dynamic random access memory comprising a memory array structure.

[0088] Based on the same inventive concept, embodiments of the present disclosure provide electronic devices comprising a memory array structure or a dynamic random access memory as described in embodiments of the present disclosure.

[0089] Electronic devices may include mobile devices such as smartphones, laptops, digital radio receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), and in-car terminals (e.g., in-car navigation terminals), as well as fixed terminals such as smart TVs and desktop computers.

[0090] Based on the same inventive concept, embodiments of the present disclosure provide a control method applicable to a sense amplifier 10 according to embodiments of the present disclosure, as shown in Figure 10, the control method is The first signal amplification stage S1001 amplifies the voltage at the first node A to the first voltage or the second voltage by controlling the first terminal, first node A, and second terminal of the first signal amplification unit 110 to be ON, The system includes a second signal amplification step S1002 which controls the first and third terminals of the second signal amplification unit 120 to be turned ON, or controls the second and third terminals to be turned ON to amplify the voltage of the bit line to a second voltage or a first voltage, thereby writing the second voltage or first voltage back to the memory unit 20 of the memory array structure.

[0091] In some embodiments, before the first signal amplification step, A first pre-charge stage is performed by controlling the first and second terminals of the first pre-charge unit 170 of the sense amplifier 10 to ON, controlling the first and second terminals of the second pre-charge unit 180 of the sense amplifier 10 to ON, controlling the first and second terminals of the fourth isolation unit 190 of the sense amplifier 10 and controlling the third and fourth terminals to ON, and controlling the first and second terminals of the first isolation unit 140 of the sense amplifier 10 to ON, thereby pre-charging the first node A, the third node C, the bit line and the first data signal line to a predetermined voltage smaller than the first voltage, The system further includes a charge sharing step in which the first and second terminals of the first precharge unit 170 are controlled to be turned off, and the first and second terminals of the second precharge unit 180 are controlled to be turned off, thereby enabling charge sharing between a predetermined voltage of the bit line and the capacitor of the memory unit 20.

[0092] In some embodiments, in the first signal amplification step, The method further includes controlling the first and second terminals of the fourth isolation unit 190 to be off, and controlling the third and fourth terminals to be off, while controlling the first terminal, third node C, and second terminal of the first signal amplification unit 110 to be on, thereby amplifying the voltage at the third node C to the second voltage or the first voltage. In the second signal amplification stage, The further includes controlling the first and second terminals of the first isolation unit 140 to the OFF state, controlling the first and second terminals of the fourth isolation unit 190 to the ON state and controlling the third and fourth terminals to the ON state, and controlling the first and third terminals of the third signal amplification unit 130 of the sense amplifier 10 to the ON state, or controlling the second and third terminals to the ON state, thereby amplifying the voltage of the first data signal line to a first voltage or a second voltage, and thereby outputting the first voltage or a second voltage to a port.

[0093] In some embodiments, after the second signal amplification stage, The process further includes a second pre-charge step in which the first node A, third node C, bit line, and first data signal line are pre-charged to a predetermined voltage by controlling the first terminal, first node A, and second terminal of the first signal amplification unit 110 to the OFF position, controlling the first terminal, third node C, and second terminal of the first signal amplification unit 110 to the OFF position, controlling the first terminal and third terminal of the second signal amplification unit 120 to the OFF position and controlling the second terminal and third terminal of the third signal amplification unit 130 to the OFF position, controlling the electrical connection between the bit line and the memory unit 20 to the OFF position, controlling the first terminal and second terminal of the first pre-charge unit 170 to the ON position, and controlling the first terminal and second terminal of the second pre-charge unit 180 to the ON position.

[0094] As an example, as shown in Figure 11, a first type of control method, The first pre-charge stage S1101 involves controlling the first and second terminals of the first pre-charge unit 170 of the sense amplifier 10 to be ON, controlling the first and second terminals of the second pre-charge unit 180 of the sense amplifier 10 to be ON, controlling the first and second terminals of the fourth isolation unit 190 of the sense amplifier 10 and controlling the third and fourth terminals to be ON, and controlling the first and second terminals of the first isolation unit 140 of the sense amplifier 10 to be ON, thereby pre-charging the first node A, the third node C, the bit line and the first data signal line to a predetermined voltage smaller than the first voltage, Charge sharing step S1102 is performed by controlling the first and second terminals of the first precharge unit 170 to be turned off, and controlling the first and second terminals of the second precharge unit 180 to be turned off, thereby sharing charge between a predetermined voltage of the bit line and the capacitor of the memory unit 20. The first signal amplification stage S1103 involves controlling the first terminal, first node A, and second terminal of the first signal amplification unit 110 to turn on, thereby amplifying the voltage at the first node A to a first voltage or a second voltage; controlling the first and second terminals and third and fourth terminals of the fourth isolation unit 190 to turn off, and controlling the first terminal, third node C, and second terminal of the first signal amplification unit 110 to turn on, thereby amplifying the voltage at the third node C to a second voltage or a first voltage. The second signal amplification stage S1104 controls the voltage of the bit line to a second voltage or a first voltage by controlling the first and third terminals of the second signal amplification unit 120 to be ON, or by controlling the second and third terminals to be ON, thereby writing the second voltage or the first voltage back to the memory unit 20 of the memory array structure, and controls the first and second terminals of the first isolation unit 140 to be OFF, controls the first and second terminals of the fourth isolation unit 190 to be ON and controls the third and fourth terminals to be ON, and controls the voltage of the first data line to a first voltage or a second voltage by controlling the first and third terminals of the third signal amplification unit 130 of the sense amplifier 10 to be ON, or by controlling the second and third terminals to be ON, thereby outputting the first voltage or the second voltage to the port. The present invention provides a first type of control method, which includes a second pre-charge step S1105 in which the first terminal, the first node A and the second terminal of the first signal amplification unit 110 are controlled to be off, the first terminal, the third node C and the second terminal of the first signal amplification unit 110 are controlled to be off, the first terminal and the third terminal of the second signal amplification unit 120 are controlled to be off and the second and third terminals are controlled to be off, the first terminal and the third terminal of the third signal amplification unit 130 are controlled to be off and the second and third terminals are controlled to be off, the electrical connection between the bit line and the memory unit 20 is interrupted, the first terminal and the second terminal of the first pre-charge unit 170 are controlled to be on, and the first terminal and the second terminal of the second pre-charge unit 180 are controlled to be on, thereby pre-charging the first node A, the third node C, the bit line and the first data signal line to a predetermined voltage.

[0095] As an example, the first control method includes a first signal amplification step in which the voltage at the first node A is amplified to a first voltage by controlling the first terminal, first node A, and second terminal of the first signal amplification unit 110 to turn on, the first terminal and second terminal of the fourth isolation unit 190 is turned off, and the third and fourth terminals are turned off, and the voltage at the third node C is amplified to a second voltage by controlling the first terminal, third node C, and second terminal of the first signal amplification unit 110 to turn on, and The process may also include a second signal amplification step in which the voltage of the bit line is amplified to a second voltage by controlling the second and third terminals of the second signal amplification unit 120 to turn on, thereby writing the second voltage back to the memory unit 20 of the memory array structure; the first and second terminals of the first isolation unit 140 are turned off, the first and second terminals of the fourth isolation unit 190 are turned on and the third and fourth terminals are turned on, and the voltage of the first data signal line is amplified to a first voltage by controlling the first and second terminals of the third signal amplification unit 130 of the sense amplifier 10 to turn on, thereby outputting the first voltage to the port.

[0096] Similarly, the first control method includes a first signal amplification step in which the voltage at the first node A is amplified to the second voltage by controlling the first terminal, first node A, and second terminal of the first signal amplification unit 110 to be ON, the first terminal and second terminal of the fourth isolation unit 190 to be OFF, and the third terminal and fourth terminal to be OFF, and the voltage at the third node C is amplified to the first voltage by controlling the first terminal, third node C, and second terminal of the first signal amplification unit 110 to be ON, The system further includes a second signal amplification step in which the voltage of the bit line is amplified to a first voltage by controlling the first and third terminals of the second signal amplification unit 120 to be ON, thereby writing the first voltage back to the memory unit 20 of the memory array structure; the voltage of the first data line is amplified to a second voltage by controlling the first and second terminals of the first isolation unit 140 to be OFF, the first and second terminals of the fourth isolation unit 190 to be ON and the third and fourth terminals to be ON, and the voltage of the first data line is amplified to a second voltage by controlling the second and third terminals of the third signal amplification unit 130 of the sense amplifier 10, thereby outputting the second voltage to the port.

[0097] In some embodiments, before the first signal amplification step, A third pre-charge stage is performed by controlling the first and second terminals of the first pre-charge unit 170 of the sense amplifier 10 to ON, controlling the first and second terminals of the second pre-charge unit 180 of the sense amplifier 10 to ON, controlling the first and second terminals of the offset removal unit 1100 of the sense amplifier 10 and controlling the third and fourth terminals to ON, and controlling the first and second terminals of the first isolation unit 140 of the sense amplifier 10 to ON, thereby pre-charging the first node A, third node C, bit line and first data signal line to a predetermined voltage. An offset removal step is performed by controlling the first and second terminals of the first precharge unit 170 to the OFF position, controlling the first and second terminals of the second precharge unit 180 to the OFF position, controlling the first and second terminals of the first isolation unit 140 to the OFF position, controlling the first terminal, first node A and second terminal of the first signal amplification unit 110 to the ON position, and controlling the first terminal, third node C and second terminal of the first signal amplification unit 110 to the ON position, thereby removing the offset of the threshold voltage of the switch devices at the fourth and sixth terminals of the first signal amplification unit 110. A fourth pre-charge step involves controlling the first and second terminals of the offset removal unit 1100 to be off and the third and fourth terminals to be off, controlling the first and second terminals of the first pre-charge unit 170 to be on, and controlling the first and second terminals of the second pre-charge unit 180 to be on, thereby pre-charging the first node A and the third node C to a predetermined voltage. The system further includes a charge sharing step in which the first and second terminals of the first precharge unit 170 are controlled to be turned off, and the first and second terminals of the second precharge unit 180 are controlled to be turned off, thereby enabling charge sharing between a predetermined voltage of the bit line and the capacitor of the memory unit 20.

[0098] As an example, as shown in Figure 12, a second type of control method is, The third pre-charge stage S1201 pre-charges the first node A, third node C, bit line, and first data signal line to a predetermined voltage by controlling the first and second terminals of the first pre-charge unit 170 of the sense amplifier 10 to turn on, controlling the first and second terminals of the second pre-charge unit 180 of the sense amplifier 10 to turn on, controlling the first and second terminals of the offset removal unit 1100 of the sense amplifier 10 and controlling the third and fourth terminals to turn on, and controlling the first and second terminals of the first isolation unit 140 of the sense amplifier 10 to turn on, Offset removal step S1202 removes the offset of the threshold voltage offset of the switch devices at terminals 4 and 6 of the first signal amplification unit 110 by controlling the first and second terminals of the first precharge unit 170 to the OFF position, controlling the first and second terminals of the second precharge unit 180 to the OFF position, controlling the first and second terminals of the first isolation unit 140 to the OFF position, controlling the first terminal, first node A and second terminal of the first signal amplification unit 110 to the ON position, and controlling the first terminal, third node C and second terminal of the first signal amplification unit 110 to the ON position. A fourth pre-charge step S1203 pre-charges the first node A and the third node C to a predetermined voltage by controlling the first and second terminals of the offset removal unit 1100 to the OFF position and the third and fourth terminals to the OFF position, controlling the first and second terminals of the first pre-charge unit 170 to the ON position, and controlling the first and second terminals of the second pre-charge unit 180 to the ON position. A charge sharing step S1204 is performed by controlling the first and second terminals of the first precharge unit 170 to be turned off, and controlling the first and second terminals of the second precharge unit 180 to be turned off, thereby sharing charge between a predetermined voltage of the bit line and the capacitor of the memory unit 20. The first signal amplification stage S1205 involves controlling the first terminal, first node A, and second terminal of the first signal amplification unit 110 to turn on, thereby amplifying the voltage at the first node A to a first voltage or a second voltage; controlling the first and second terminals of the fourth isolation unit 190 to turn off, and controlling the third and fourth terminals to turn off, thereby amplifying the voltage at the third node C to a second voltage or a first voltage by controlling the first terminal, third node C, and second terminal of the first signal amplification unit 110 to turn on, The second signal amplification stage S1206 controls the first and third terminals of the second signal amplification unit 120 to be turned ON, or controls the second and third terminals to be turned ON, thereby amplifying the voltage of the bit line to a second voltage or a first voltage, and thereby writing the second voltage or a first voltage back to the memory unit 20 of the memory array structure, controls the first and second terminals of the first isolation unit 140 to be kept OFF, controls the first and second terminals of the fourth isolation unit 190 to be turned ON and controls the third and fourth terminals to be turned ON, and controls the first and third terminals of the third signal amplification unit 130 of the sense amplifier 10 to be turned ON, or controls the second and third terminals to be turned ON, thereby amplifying the voltage of the first data signal line to a first voltage or a second voltage, and thereby outputting the first voltage or a second voltage to the port. The present invention provides a second type of control method, which includes a second pre-charge step S1207 in which the first terminal, the first node A and the second terminal of the first signal amplification unit 110 are controlled to be off, the first terminal, the third node C and the second terminal of the first signal amplification unit 110 are controlled to be off, the first terminal and the third terminal of the second signal amplification unit 120 are controlled to be off and the second and third terminals of the third signal amplification unit 130 are controlled to be off, the electrical connection between the bit line and the memory unit 20 is interrupted, the first terminal and the second terminal of the first pre-charge unit 170 are controlled to be on, and the first terminal and the second terminal of the second pre-charge unit 180 are controlled to be on, thereby pre-charging the first node A, the third node C, the bit line and the first data signal line to a predetermined voltage.

[0099] Figures 13 and 14 show the timing diagrams of the first type of control method, which is divided into five stages: a first precharge stage, a charge sharing stage, a first signal amplification stage, a second signal amplification stage, and a second precharge stage, corresponding to states 1, 2, 3, 4, and 5, respectively. The first type of control method eliminates overclocking (OC) and performs signal amplification twice, and in order to achieve the effect of reading data from the memory unit 20 using the timing control method shown in Figure 13, this method disables the OC enablement and allows the data stored in the memory unit 20 to be read normally.

[0100] As shown in Figures 7 and 14, the first type of control method is Turn on EQ, ISO1, ISO2, ISO3, and PRE, V BLEP This involves a first pre-charge stage in which SABL and SABLB, and BL and BLB, are all pre-charged to 0.5V, With EQ and PRE turned off, and WL and ISO1, ISO2, and ISO3 kept on, a charge sharing phase is performed. The first signal amplification stage involves turning off ISO1, keeping WL, ISO2, and ISO3 on, and turning on RTO and SB, and performing the first signal amplification using sense amplifier SA for SABL and SABLB. The second signal amplification stage involves turning off ISO3, isolating it from the reference power supply, turning on WL, ISO1, and ISO2 to perform a second signal detection amplification, turning on RTO1 and SB1 and RTO2 and SB2 to enable the data write-back function, turning on CSL to provide the data read function, and This includes a second pre-charge phase in which WL is turned off, then RTO, RTO1, RTO2 and SB, SB1, SB2 are turned off, then EQ and PRE are enabled, and BL and BLB and SABL and SABLB are charged to 0.5V to return the DRAM to an ideal state and prepare it for the next read / write.

[0101] Figures 15 and 16 show the timing diagrams for the second type of control method. The second type of control method maintains OC and performs signal amplification twice, and is divided into seven stages: a third precharge stage, an offset removal stage, a fourth precharge stage, a charge sharing stage, a first signal amplification stage, a second signal amplification stage, and a second precharge stage, corresponding to states 1, 2, 3, 4, 5, 6, and 7, respectively.

[0102] As shown in Figures 7 and 16, the second type of control method is The third pre-charge stage involves turning on EQ, ISO2, ISO3, PRE, and OC, and pre-charging SABL and SABLB, as well as BL and BLB, to 0.5V using VBLEP. The offset removal stage involves turning off EQ and PRE, turning on OC and SB, and RTO, and then executing the mismatch removal process. This includes a fourth pre-charge stage in which OC is turned off, EQ and PRE are turned on, and SABL and SABLB are pre-charged to 0.5V, The charge sharing stage, first signal amplification stage, second signal amplification stage, and second pre-charge stage of the first control method are performed, and during the execution process, ISO3 must always be kept off and isolated from the reference power supply.

[0103] The second type of control method is a method of reading data in the memory unit 20 using the timing control method shown in Figure 15. In this method, the OC enable mode is maintained, and by using this method, the mismatch voltage of the two amplified NMOS (switch devices T7 and T8) can be detected correctly, improving detection accuracy and allowing the data stored in the memory unit 20 to be read correctly.

[0104] As those skilled in the art will understand, the steps, measures, and solutions in the various operations, methods, and processes considered in this disclosure are substituted, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes considered in this disclosure are also substituted, modified, rearranged, disassembled, combined, or deleted. Furthermore, steps, measures, and solutions in the various operations, methods, and processes disclosed in the prior art are also substituted, modified, rearranged, disassembled, combined, or deleted.

[0105] The terms “First” and “Second” are for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly representing the number of technical features shown. Thus, features limited by “First” and “Second” may explicitly or implicitly include one or more such features. In this disclosure, unless otherwise specified, “multiple” means two or more.

[0106] In this specification, specific features, structures, materials, or properties can be combined in an appropriate manner in any one or more embodiments or examples.

[0107] While the steps in the flowcharts shown in the diagrams are displayed sequentially as indicated by arrows, it should be understood that these steps are not necessarily performed in the order indicated by the arrows. Unless expressly stated herein, there are no strict order constraints on the execution of these steps, and they may be performed in other orders. Furthermore, at least some steps in the flowcharts shown in the diagrams may include multiple substeps or stages, and these substeps or stages do not necessarily have to be completed simultaneously, may be performed at different times, and their execution order is not necessarily sequential, but may be performed sequentially with other steps, or at least some of the substeps or stages in other steps, or alternately.

[0108] The above description represents only a limited set of embodiments of the Disclosure, and it should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the Disclosure, and such improvements and modifications will also be within the scope of protection of the Disclosure. [Explanation of symbols]

[0109] 10 Sense Amplifier 110 First signal amplification unit 111 Fifth Switch Module 112. 6th Switch Module 113. 7th Switch Module 114. 8th Switch Module 120 Second signal amplification unit 121 First Switch Module 122 Second Switch Module 130 Third Signal Amplifier Unit 131 Third Switch Module 132 4th Switch Module 140 First Insulation Unit 150 Second Insulation Unit 160 Third Insulation Unit 170 First Precharge Unit 180 Second Precharge Unit 190 Fourth Insulation Unit 191 9th Switch Module 192 10th Switch Module 1100 Offset Removal Unit 1101 11th Switch Module 1102 12th Switch Module A First node B Second node C 3rd node D 4th node 20 memory units

Claims

1. It is a sense amplifier, A first signal amplification unit in which a first terminal and a second terminal are used to electrically connect to a first voltage terminal and a second voltage terminal, respectively, and a third terminal and a fourth terminal function as a first node and a second node, wherein the first voltage terminal is used to output a first voltage, the second voltage terminal is used to output a second voltage, and the first voltage is greater than the second voltage, A second signal amplification unit comprising: a first terminal, a second terminal, and a third terminal used to electrically connect to a third voltage terminal, a fourth voltage terminal, and a bit line, respectively, the fourth terminal being electrically connected to a first node, wherein the voltage of the third voltage terminal is the same as the voltage of the first voltage terminal, the voltage of the fourth voltage terminal is the same as the voltage of the second voltage terminal, and the bit line is used to electrically connect to a memory unit of a memory array structure; The sense amplifier is configured to, in the first signal amplification stage, amplify the voltage at the first node to the first voltage or the second voltage by turning on the first terminal, first node, and second terminal of the first signal amplification unit, and in the second signal amplification stage, amplify the voltage of the bit line to the second voltage or the first voltage by turning on the first and third terminals of the second signal amplification unit, or by turning on the second and third terminals, thereby writing the second voltage or the first voltage back to the memory unit. A sense amplifier characterized by the following features.

2. The fifth and sixth terminals of the first signal amplification unit function as the third and fourth nodes, respectively. The aforementioned sense amplifier, A third signal amplification unit having a first terminal, a second terminal, and a third terminal used to electrically connect to a fifth voltage terminal, a sixth voltage terminal, and a first data signal line, respectively, and a fourth terminal electrically connected to a third node, wherein the voltage of the fifth voltage terminal is the same as the voltage of the first voltage terminal, the voltage of the sixth voltage terminal is the same as the voltage of the second voltage terminal, and the first data signal line is used to electrically connect to a port, further comprising a third signal amplification unit, The sense amplifier is further configured to amplify the voltage at the third node to the second voltage or the first voltage by turning on the first terminal, third node, and second terminal of the first signal amplification unit in the first signal amplification stage, and to amplify the voltage of the first data signal line to the first voltage or the second voltage by turning on the first and third terminals of the third signal amplification unit, or by turning on the second and third terminals, thereby outputting the first voltage or the second voltage to the port. The sense amplifier according to claim 1.

3. The system further comprises a first isolation unit, the first and second terminals of which are used to electrically connect to a first isolated signal line and a first reference voltage terminal and a first data signal line, respectively. The first isolation unit is configured to amplify the voltage of the first data signal line by turning off its first and second terminals during the second signal amplification stage. The sense amplifier according to claim 2.

4. The system further comprises a second isolation unit, the control terminal and the first terminal of which are used to electrically connect to the second isolated signal line and the bit line, respectively, and the second terminal of which is electrically connected to the second node. The second isolation unit is configured to turn on its first and second terminals when operating and to turn off its first and second terminals when not operating. The sense amplifier according to claim 3.

5. A third isolation unit having a control terminal used to electrically connect to a third isolation signal line, and a first terminal and a second terminal electrically connected to a first data signal line and a fourth node, respectively, further comprising a third isolation unit to which the third isolation signal line is electrically connected to the second isolation signal line. The third isolation unit is configured to turn on its first and second terminals when operating and to turn off its first and second terminals when not operating. The sense amplifier according to claim 4.

6. The second signal amplification unit includes a first switch module and a second switch module, The control terminals of the first switch module and the control terminals of the second switch module both function as the fourth terminals of the second signal amplification unit. The first terminal of the first switch module functions as the first terminal of the second signal amplification unit. The second terminal of the second switch module functions as the second terminal of the second signal amplification unit. The second terminal of the first switch module and the first terminal of the second switch module both function as the third terminal of the second signal amplification unit. The sense amplifier according to claim 1.

7. The third signal amplification unit includes a third switch module and a fourth switch module, The control terminals of the third switch module and the control terminals of the fourth switch module both function as the fourth terminals of the third signal amplification unit. The first terminal of the third switch module functions as the first terminal of the third signal amplification unit. The second terminal of the fourth switch module functions as the second terminal of the third signal amplification unit. The second terminal of the third switch module and the first terminal of the fourth switch module both function as the third terminal of the third signal amplification unit. The sense amplifier according to claim 2.

8. The first signal amplification unit includes a fifth switch module, a sixth switch module, a seventh switch module, and an eighth switch module. The first terminal of the fifth switch module and the first terminal of the sixth switch module both function as the first terminal of the first signal amplification unit. The second terminal of the fifth switch module and the first terminal of the seventh switch module both function as the third terminal of the first signal amplification unit, and the second terminal of the sixth switch module and the first terminal of the eighth switch module both function as the fifth terminal of the first signal amplification unit. The second terminal of the seventh switch module and the second terminal of the eighth switch module both function as the second terminal of the first signal amplification unit. The control terminal of the fifth switch module is electrically connected to the third node, and the control terminal of the sixth switch module is electrically connected to the first node. The control terminal of the seventh switch module functions as the fourth terminal of the first signal amplification unit, and the control terminal of the eighth switch module functions as the sixth terminal of the first signal amplification unit. The sense amplifier according to claim 2.

9. A first precharge unit having a control terminal used for electrically connecting to a first signal line, a first terminal used for electrically connecting to a first reference voltage terminal, and a second terminal used for electrically connecting to a third node, wherein the first reference voltage terminal is used for outputting a first reference voltage, A second precharge unit, in which a control terminal is used to electrically connect to a second signal line, and the first and second terminals are electrically connected to a first node and a third node, respectively, The present invention further comprises a fourth isolation unit, the control terminal of which is used to electrically connect to the fourth isolation signal line, and the first, second, third, and fourth terminals of which are electrically connected to the second, third, first, and fourth nodes, respectively. A sense amplifier according to any one of claims 3 to 5.

10. The system further comprises an offset removal unit in which control terminals are used to electrically connect to offset removal signal lines, and the first, second, third, and fourth terminals are electrically connected to the second, first, third, and fourth nodes, respectively. The sense amplifier according to claim 9.

11. The fourth isolation unit includes a ninth switch module and a tenth switch module, The control terminals of the ninth switch module and the tenth switch module both function as control terminals of the fourth isolation unit. The first and second terminals of the ninth switch module function as the second and first terminals of the fourth isolation unit, respectively. The first and second terminals of the 10th switch module function as the third and fourth terminals of the 4th isolation unit, respectively. The sense amplifier according to claim 9.

12. The offset removal unit includes an 11th switch module and a 12th switch module, The control terminals of the 11th switch module and the control terminals of the 12th switch module both function as control terminals of the offset removal unit. The first and second terminals of the 11th switch module function as the second and first terminals of the offset removal unit, respectively. The first and second terminals of the 12th switch module function as the third and fourth terminals of the offset removal unit, respectively. The sense amplifier according to claim 10.

13. A memory array structure, The system comprises multiple bit lines, multiple word lines, multiple memory units arranged in a matrix, and multiple sense amplifiers according to any one of claims 1 to 12. One of the bit lines is electrically connected to a corresponding row of the memory units. One of the word lines is electrically connected to a corresponding row of the memory unit. Each bit line is electrically connected to the third terminal of the second signal amplification unit of one of the sense amplifiers. A memory array structure characterized by the following features.

14. The memory array structure is provided as described in claim 13. A dynamic random access memory characterized by the following features.

15. The memory array structure is as described in claim 13 or the dynamic random access memory is as described in claim 14. An electronic device characterized by the following features.

16. A control method applicable to a sense amplifier according to any one of claims 1 to 12, A first signal amplification step involves controlling the first terminal, first node, and second terminal of the first signal amplification unit to be ON, thereby amplifying the voltage at the first node to a first voltage or a second voltage. The second signal amplification step includes controlling the first and third terminals of the second signal amplification unit to turn on, or by controlling the second and third terminals to turn on, the voltage of the bit line is amplified to the second voltage or the first voltage, thereby writing the second voltage or the first voltage back to the memory unit of the memory array structure. A control method characterized by the following:

17. Before the first signal amplification stage, A first pre-charge step involves controlling the first and second terminals of the first pre-charge unit of the sense amplifier to be turned ON, controlling the first and second terminals of the second pre-charge unit of the sense amplifier to be turned ON, controlling the first and second terminals of the fourth isolation unit of the sense amplifier to be turned ON and controlling the third and fourth terminals to be turned ON, and controlling the first and second terminals of the first isolation unit of the sense amplifier to be turned ON, thereby pre-charging the first node, third node, bit line, and first data signal line to a predetermined voltage smaller than the first voltage, The process further includes a charge sharing step in which the first and second terminals of the first precharge unit are controlled to be turned off, and the first and second terminals of the second precharge unit are controlled to be turned off, thereby enabling charge sharing between a predetermined voltage of the bit line and the capacitor of the memory unit. The control method according to claim 16.

18. In the first signal amplification stage, The method further includes controlling the first and second terminals of the fourth isolation unit to be turned off and the third and fourth terminals to be turned off, and controlling the first terminal, third node and second terminal of the first signal amplification unit to be turned on, thereby amplifying the voltage at the third node to the second voltage or the first voltage. In the second signal amplification stage, The method further includes controlling the first and second terminals of the first isolation unit to be OFF, controlling the first and second terminals of the fourth isolation unit to be ON and controlling the third and fourth terminals to be ON, and controlling the first and third terminals of the third signal amplification unit of the sense amplifier to be ON, or controlling the second and third terminals to be ON, thereby amplifying the voltage of the first data signal line to the first voltage or the second voltage, and thereby outputting the first voltage or the second voltage to the port. The control method according to claim 17.

19. After the second signal amplification stage, The process further includes a second pre-charge step in which the first node, third node, bit line, and first data signal line are pre-charged to a predetermined voltage by controlling the first terminal, first node, and second terminal of the first signal amplification unit to turn off; controlling the first terminal, third node, and second terminal of the first signal amplification unit to turn off; controlling the first terminal and third terminal of the second signal amplification unit to turn off and the second terminal and third terminal of the third signal amplification unit to turn off; controlling the electrical connection between the bit line and the memory unit to be interrupted; controlling the first terminal and second terminal of the first pre-charge unit to turn on; and controlling the first terminal and second terminal of the second pre-charge unit to turn on. The control method according to claim 18.

20. Before the first signal amplification stage, A third pre-charge step involves controlling the first and second terminals of the first pre-charge unit of the sense amplifier to be turned ON, controlling the first and second terminals of the second pre-charge unit of the sense amplifier to be turned ON, controlling the first and second terminals of the offset removal unit of the sense amplifier to be turned ON and controlling the third and fourth terminals to be turned ON, and controlling the first and second terminals of the first isolation unit of the sense amplifier to be turned ON, thereby pre-charging the first node, third node, bit line, and first data signal line to a predetermined voltage. An offset removal step is performed by controlling the first and second terminals of the first precharge unit to be turned off, controlling the first and second terminals of the second precharge unit to be turned off, controlling the first and second terminals of the first isolation unit to be turned off, controlling the first terminal, first node and second terminal of the first signal amplification unit to be turned on, and controlling the first terminal, third node and second terminal of the first signal amplification unit to be turned on, thereby removing the offset of the threshold voltage of the switch devices of the fourth and sixth terminals of the first signal amplification unit. A fourth pre-charge step in which the first and third nodes are pre-charged to a predetermined voltage by controlling the first and second terminals of the offset removal unit to be off and the third and fourth terminals to be off, controlling the first and second terminals of the first pre-charge unit to be on, and controlling the first and second terminals of the second pre-charge unit to be on, The process further includes a charge sharing step in which the first and second terminals of the first precharge unit are controlled to be turned off, and the first and second terminals of the second precharge unit are controlled to be turned off, thereby enabling charge sharing between a predetermined voltage of the bit line and the capacitor of the memory unit. The control method according to claim 16.

21. After the second signal amplification stage, The process further includes a second pre-charge step in which the first node, third node, bit line, and first data signal line are pre-charged to a predetermined voltage by controlling the first terminal, first node, and second terminal of the first signal amplification unit to turn off; controlling the first terminal, third node, and second terminal of the first signal amplification unit to turn off; controlling the first terminal and third terminal of the second signal amplification unit to turn off and the second terminal and third terminal of the third signal amplification unit to turn off; controlling the electrical connection between the bit line and the memory unit to be interrupted; controlling the first terminal and second terminal of the first pre-charge unit to turn on; and controlling the first terminal and second terminal of the second pre-charge unit to turn on. The control method according to claim 20.

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