Coordination between changes in the power state of the system basis chip and changes in the power state of the PHY transceiver implemented by the system basis chip.

Abstract

The method includes the steps of: providing a system basis chip that supports at least two power states, a sleep state and an awake state; monitoring power state information via a hardware interface that enables communication between a physical layer (PHY) transceiver implemented on the system basis chip and a PHY controller implemented on a microcontroller, and a communication interface that enables communication between the system basis chip and the microcontroller; and coordinating changes in the power state of the system basis chip, at least in part, based on the reception of power state information via the hardware interface and the communication interface.

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims the benefit of U.S. Provisional Patent Application No. 63 / 512,229, filed on July 6, 2023, under 35 U.S.C. § 119(e), the disclosure of which is incorporated herein by reference in its entirety.

[0002] (Field of the Invention) Embodiments generally relate to system basis chips and system basis chips implementing physical layer devices.

Background Art

[0003] A system basis chip (SBC) is an integrated circuit (IC) that combines multiple functions required for the operation of an electronic system. ICs and SBCs are utilized in various operating situations.

Brief Description of the Drawings

[0004] To easily identify any consideration of a particular element or action, the most significant digit of the reference number refers to the figure number in which the element was first introduced. [Figure 1] A block diagram of a system implementing, among other things, a 10SPE PHY according to one or more embodiments. [Figure 2] A block diagram showing a system basis chip portion according to one or more embodiments. [Figure 3] A state diagram showing transitions between wake and sleep states managed by the FSM of an SBC according to one or more embodiments. [Figure 4] A state diagram showing a step - by - step change in power states from wake to sleep and from sleep to wake managed by the FSM of an SBC according to one or more embodiments. [Figure 5]This document illustrates exemplary processes for changing the power state of a system basis chip implementing a PHY transceiver of a PHY having a split PHY architecture, using one or more embodiments. [Figure 6] This flowchart shows the process of coordinating changes in the power state of an SBC implementing a PHY transceiver with changes in the power state of the PHY transceiver, according to one or more embodiments. [Figure 7] This document illustrates exemplary processes for changing the power state of a system basis chip, a PHY transceiver implemented by the system basis chip, or both, using one or more embodiments. [Figure 8] This is a block diagram of a circuit that may be used to implement various functions, operations, actions, processes, or methods disclosed herein in some embodiments. [Modes for carrying out the invention]

[0005] The following detailed description refers to the accompanying drawings, which form part of this specification and illustrate specific examples of embodiments that may carry out the disclosure. These embodiments are described in sufficient detail to enable those skilled in the art to carry out the disclosure. However, other embodiments may be used, and the structure, materials, and processes may be modified without departing from the scope of the disclosure.

[0006] The illustrative diagrams presented herein are not intended to be actual diagrams of any particular method, system, device, or structure, but are merely idealized representations used to illustrate embodiments of the disclosure. The drawings presented herein are not necessarily drawn to scale. Similar structures or components in various drawings may retain the same or similar numbering for the convenience of the reader. However, similarity in numbering does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other characteristics.

[0007] The following description may include examples to help enable those skilled in the art to carry out the disclosed examples. The use of the terms “exemplary,” “as an example,” and “for example” means that the relevant description is illustrative, and the scope of this disclosure is intended to encompass examples and legal equivalents, and the use of such terms is not intended to limit the examples or the scope of this disclosure to specified components, steps, features, functions, etc.

[0008] It will be readily apparent that the components of the embodiments described herein and illustrated in the drawings can be arranged and designed in a wide variety of different configurations. Therefore, the following descriptions of various embodiments are not intended to limit the scope of this disclosure, but merely to illustrate various embodiments. Various aspects of the embodiments may be presented in the drawings, which are not necessarily drawn to scale unless specifically indicated.

[0009] Furthermore, the specific implementations illustrated and described are merely examples and should not be construed as the only way to implement this disclosure unless otherwise specified herein. Elements, circuits, and functions may be shown in block diagram form to avoid obscuring this disclosure with unnecessary details. Conversely, the specific implementations illustrated and described are merely illustrative and should not be construed as the only way to implement this disclosure unless otherwise specified herein. Additionally, the block definitions and partitioning of logic between various blocks are examples of specific implementations. It will be readily apparent to those skilled in the art that this disclosure can be implemented by numerous other partitioning solutions. For the most part, details such as timing considerations are omitted, as such details are not necessary for a full understanding of this disclosure and are within the capabilities of those skilled in the art.

[0010] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. Some drawings may illustrate a signal as a single signal for clarity in presentation and explanation. Those skilled in the art will understand that a signal can represent a bus of signals, which can have various bit widths, and that this disclosure can be implemented with any number of data signals, including a single data signal.

[0011] The various illustrative logic blocks, modules, and circuits described in relation to the embodiments disclosed herein may be implemented or run using general-purpose processors, dedicated processors, digital signal processors (DSPs), integrated circuits (ICs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, separate gate or transistor logic, separate hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but instead, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors working in conjunction with a DSP core, or any other such configuration. A general-purpose computer including a processor is considered a dedicated computer while that general-purpose computer is executing computing instructions (e.g., software code) related to the embodiments of this disclosure.

[0012] Examples may be described in relation to processes depicted as flowcharts, flow diagrams, structural diagrams, or block diagrams. While flowcharts may describe actions as sequential processes, many of these actions can be performed in separate sequences, concurrently, or substantially simultaneously. In addition, the order of actions can be rearranged. Processes may, but are not limited to, methods, threads, functions, procedures, subroutines, or subprograms. Furthermore, methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, functions may be stored or transmitted as one or more instructions or codes in a computer-readable medium. Computer-readable mediums include both computer storage media and communication media, including any medium that facilitates the transfer of computer programs from one location to another.

[0013] Any reference to elements in this specification using notations such as "first," "second," etc., does not limit the number or order of those elements unless such limitation is expressly stated. Rather, these notations may be used in this specification as a convenient way to distinguish two or more elements or examples of elements. Thus, references to the first and second elements do not mean that only two elements may be used, or that the first element must precede the second element in any manner. In addition, unless otherwise specified, a set of elements may include one or more elements.

[0014] As used herein, the term “substantially” when referring to a given parameter, characteristic, or condition means and includes the extent to which a person skilled in the art would understand that the given parameter, characteristic, or condition is within a small variation, such as within an acceptable manufacturing tolerance. For example, depending on the particular parameter, characteristic, or condition to be substantially satisfied, the parameter, characteristic, or condition may be satisfied at least 90%, at least 95%, or even at least 99%.

[0015] As used herein, any relative terms such as “over,” “under,” “on,” “underlying,” “upper,” and “lower” are used for clarity and convenience in understanding this disclosure and the accompanying drawings, and do not imply, or rely on, any particular preference, orientation, or order, unless the context clearly indicates otherwise.

[0016] In this description, the term “combined” and its derivatives may be used to indicate that two elements cooperate with or interact with each other. When one element is described as “combined” with another, those elements may be in direct physical or electrical contact, but there may be an intervening element or layer between them. In contrast, when one element is described as “directly combined” with another, there is no intervening element or layer. The term “connected” may be used interchangeably with the term “combined” herein and has the same meaning unless otherwise expressly indicated or the context indicates to those skilled in the art in another way.

[0017] As used herein, the terms “assert,” “de-assert,” and their derivatives, used in reference to a pin, mean to assert or de-assert a signal associated with a pin (e.g., a signal specifically assigned to a pin, or a signal to which a pin is specifically assigned), respectively.

[0018] A system basis chip (SBC) is an integrated circuit (IC) that combines multiple functions for the operation of an electronic system. Typically, an SBC integrates various different functions onto a single chip. Examples of such functions include, but are not limited to, power management functions for managing the system's power supply, such as voltage regulators, power switches, or protection circuits; communication interfaces such as CAN (Controller Area Network), LIN (Local Interconnect Network), SPI (Serial Peripheral Interface), or I2C (Inter-Integrated Circuit); embedded systems for controlling and coordinating tasks, such as state machines or microprocessors; analog functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), temperature sensors, and other signal conditioning circuits; and, but are not limited to, diagnostic and safety functions such as monitoring and adjusting voltage levels, temperature, or fault conditions.

[0019] SBCs are found in a variety of operating environments, including automotive and industrial applications. A non-exclusive example of an automotive application of SBCs is the 10SPE (i.e., 10 Mbps Single Pair Ethernet) network (also known as a "10BASE-T1S network"). 10SPE is a network technology defined in clauses 147 and 148 of IEEE 802.3. 10SPE is designed to provide collision-free deterministic transmission over multidrop networks.

[0020] In some cases, as a non-limiting example, since the transceiver (xcvr) and the controller of a 10SPE physical layer device (PHY) may be located on different dies, each die may be subject to different processing conditions. Such an architecture is referred to herein as a "split PHY" architecture. In a split PHY architecture, the digital blocks of the PHY controller that are vulnerable to damage during a high-voltage high-temperature process (the high-voltage high-temperature process is also referred to herein as the "high-voltage temperature process") may be located on a first die that does not undergo the high-voltage high-temperature process. The analog and digital blocks of the PHY transceiver that are less vulnerable to damage during the high-voltage temperature process or that require such a high-voltage temperature process may be located on a second die that undergoes such a high-voltage temperature process.

[0021] The 10SPE transceiver interface standard currently under specification development by the Technology Committee 14 of the Open Alliance (hereinafter referred to as "TC14") defines a 3-pin hardware interface for communication between the PHY transceiver and the PHY controller.

[0022] In a PHY having a split PHY architecture, the 10SPE controller function is implemented in a microcontroller (MCU), and the 10SPE transceiver function is implemented in an SBC. In addition to the 10SPE transceiver function, the SBC can implement non-transceiver functions, that is, but not limited to, functions of an electronic system such as power management, watchdog circuit, monitor, sensor, general purpose input / output (GPIO), etc. Therefore, in 10SPE, the roles of the SBC may include, but are not limited to, a communication transceiver, a low-voltage power supply, observability / control of a high-voltage domain, and a functional safety mechanism for the MCU to reach a safe state.

[0023] Furthermore, TC14 describes the low-power (sleep-wake) behavior of the PHY transceiver for partial networking. Partial networking refers to the feature that enables selective power management and communication capabilities within the network. Partial networking allows a particular network node or device to enter a low-power state or sleep state while still maintaining basic communication functions. In an Ethernet network, partial networking can be utilized to optimize (e.g., limit, but not limited to, reduce) power consumption, especially in automotive or industrial applications. Enabling selected devices to enter a low-power state or sleep state can, among other things, reduce overall power consumption, extend battery life, or improve energy efficiency.

[0024] The SBC may implement a 10 SPE PHY transceiver, and furthermore, it can manage power supply and other functions such as watchdog for the MCU, PHY controller, and other devices (such as, but not limited to, sensors). The driver that implements the PHY transceiver and commands (such as, but not limited to, firmware, configurable state machine, logic circuit, or hardware) is typically separate (such as, but not limited to, a different data path) and asynchronous from the driver that implements other SBC functions.

[0025] In the case of power state management (such as, but not limited to, the PHY transceiver and MCU), the lack of coordination can cause inefficiencies, increased power consumption, and operational anomalies such as unintended wake-up or incorrect entry into the low-power state.

[0026] Therefore, in a split PHY architecture where the PHY transceiver and PHY controller are separately implemented in different components (such as, but not limited to, the SBC and MCU), it is difficult to manage coordinated power states and / or coordinated power state transitions.

[0027] One or more embodiments generally relate to an SBC that can coordinate changes in the power state of the SBC with changes in the power state of a PHY transceiver implemented by the SBC.

[0028] In one or more embodiments, the SBC implements at least a portion of the hardware interface between the PHY transceiver and the PHY controller (e.g., a 3-pin hardware interface, but not limited to one) and implements the PHY transceiver, so the SBC is aware of power state information (e.g., power management commands and status information, but not limited to one) transmitted via the hardware interface, at least generally. In a non-limiting embodiment, wakes are handled exclusively by the PHY transceiver, but information regarding the wake source status is transmitted via the hardware interface. Thus, the SBC is generally aware of the power state of the PHY transceiver and changes in the power state. Furthermore, the supply of power to the MCU and the PHY controller implemented by the MCU is at least partially managed via information and commands transmitted between the SBC and the MCU via a communication interface (e.g., an I2C bus, but not limited to one).

[0029] In one or more embodiments, the SBC executes power management commands only when a matching power management command is received via a hardware interface (e.g., a TC14-compliant 3-pin hardware interface enabling communication between the PHY controller and the PHY transceiver) and the I2C bus. This ensures that the power states of the SBC and the PHY transceiver are changed simultaneously. For example, the SBC instructs the power states of the driver controlling the SBC's power functions and the driver implementing the PHY transceiver to be changed substantially simultaneously. In some embodiments, the SBC may include logic circuits (e.g., a finite-state-machine (FSM)) that perform the changes in the power states of the SBC and the transceiver in a stepwise manner.

[0030] Therefore, if the power management command is a sleep command, the power will not be turned off in the SBC unless the power state management logic determines that both the PHY transceiver and the PHY controller are (or will be) in a sleep state. Thus, changes in the SBC's power state depend at least in part on the power state of the PHY transceiver and PHY controller or the planned power state.

[0031] Figure 1 is a block diagram of one or more embodiments of a system 100 that implements a 10SPE PHY.

[0032] System 100 comprises an MCU 102 and an SBC 108. The MCU 102 includes a PHY controller 104 and an I2C bus controller 106. The SBC 108 includes a stepped low-power input / output FSM 110 and a PHY transceiver 112. The PHY controller 104 and the PHY transceiver 112 form a 10 SPE PHY. The PHY controller 104 and the PHY transceiver 112 communicate via a hardware interface 114 which includes connections for carrying signals associated with transmission signaling (TX connection), energy sensing signaling (ED connection), and receive signaling (RX connection). The SBC and MCU communicate via the I2C bus, as well as command connections, control connections, and management connections (the command connections, control connections, and management connections are represented by connections INTn and RSTn, which in particular indicate operations required by the MCU, but are not intended to limit this disclosure in any way).

[0033] The PHY controller 104 is responsible for managing the digital aspects of 10BASE-T1S PHY communication. The PHY controller 104 handles tasks such as encoding, decoding, and managing the link layer protocol. The I2C bus controller 106 manages communication over the I2C bus and facilitates the exchange of commands, control, and data between the MCU and SBC. In the particular embodiment shown in Figure 1, the logic managing communication between command connections, control connections, and management connections (e.g., INTn and RSTn, but not limited to these) is shown by the same block representing the I2C bus controller 106, but may be in different logical partitions.

[0034] The SBC108 implements or manages the functions of the PHY transceiver 112, the MCU 102, the sensors (sensors are not shown but should be assumed to be optional), and its own internal functions (SBC functions). Vuc is the supply voltage supplied from the SBC to the MCU. Vsen is the supply voltage supplied to one or more sensors, if sensors are present. Vsup is the supply voltage supplied to the SBC and can be used, for example, directly or as a modified version of Vsup, to generate Vuc and Vsen. GPIOs are general-purpose input / output connections. Transmission / receive connections, common mode chokes (CMCs), and connectors are physical circuits that connect the SBC108 to a physical transmission medium, such as twisted pair, but are not limited to it. WAKEIN is an input connection used exclusively to receive power management signals (e.g., wake or sleep, but are not limited to it) from an external source (e.g., outside of system 100, but are not limited to it).

[0035] In one or more embodiments, the SBC108 coordinates two or more power states and power state changes among the SBC108, MCU102, PHY controller 104, and PHY transceiver 112. As described later, the SBC108 includes a logic circuit, in this case FSM110, which manages changes in the SBC's power state in a stepwise manner (to prevent sudden changes that could lead to system instability or increased power consumption, for example, but not limited to).

[0036] The FSM110 receives power state information (e.g., command or status information, but not limited to) via both the hardware interface 114 and the I2C bus, and uses this power state information to ensure that changes in the power state of the SBC108 occur in synchronization with the power state of the PHY transceiver 112. The FSM110 acts as control logic that directs overall power state changes of the SBC108 and the PHY transceiver 112. Based on the state and inputs it receives, the FSM110 issues commands to the driver 116 (including the SBC driver and the driver implementing the PHY transceiver 112). The driver 116 executes the detailed commands issued by the FSM110. For example, the SBC108 driver 116 adjusts hardware settings, manages power adjustments, and ensures that system components follow instructions from the FSM110 precisely.

[0037] During the period between when the power state information indicates that the SBC 108 should change its power state and when the power state information indicates that the PHY transceiver 112 should change its power state, the SBC 108 or the PHY transceiver 112 may, depending on the circumstances, process events such as wake events that occur during that period, but are not limited to those events.

[0038] In some embodiments, the SBC108 may include at least one regulating voltage source, the sleep state of the SBC indicates that at least one regulating voltage source is off, and the awake state of the SBC108 indicates that at least one regulating voltage source is on.

[0039] Figure 2 is a block diagram representing a system basis chip portion 200 in one or more embodiments. The system basis chip portion 200 is a non-limiting example of a part of the SBC108 in Figure 1.

[0040] The system basis chip portion 200 includes a logic circuit 202, an SBC driver 204, and a PHY transceiver driver 206.

[0041] The logic circuit 202 monitors the hardware interface (e.g., hardware interface 114 in Figure 1, but not limited to this) and the communication interface (e.g., the I2C bus communication interface in Figure 1, but not limited to this) with respect to power state information, and receives power state information received via the hardware interface 208 and power state information received via the communication interface 210.

[0042] The power state information received via the hardware interface 208 may, in a non-limiting embodiment, include commands from the PHY controller 104 to the PHY transceiver 112 related to the power state of the PHY transceiver 112, as well as other information indicating the power state of the PHY transceiver 112 or a change in its power state. For example, a sleep command may be communicated from the PHY controller 104 to the PHY transceiver 112 via the hardware interface 114, and the power state information received via the hardware interface 208 may include a sleep command.

[0043] The power status information received via the communication interface 210 may, in a non-limiting embodiment, include commands that cause the SBC, including the system basis chip portion 200, to enter a low-power state or a sleep state.

[0044] The SBC driver 204 ("first driver") implements the functions of the system basis chip, including, but not limited to, the execution of instructions 212 from the logic circuit 202 (or FSM), such as adjusting hardware settings, handling communication through specific connections, and managing power regulation. The PHY transceiver driver 206 ("second driver") implements the functions of the PHY transceiver, including, but not limited to, the execution of instructions 214 from the logic circuit 202.

[0045] The timing of instructions 212 and 214, which include power state information and specific instructions for changing the power state or intermediate state, may occur substantially simultaneously. Here, "substantially simultaneously" when discussing the provision of power state information, or more generally instructions, to the SBC driver 204 and the PHY transceiver driver 206 means a time window, typically on the order of microseconds, that ensures appropriately synchronized state changes to maintain system stability and power efficiency.

[0046] Figure 3 is a state diagram showing the transition between the wake state and sleep state managed by the FSM110 of the SBC108 in one or more embodiments.

[0047] The awake state (WAIT_SLEEP) is the initial active state in which the system is fully powered and operational. In this state, both the PHY transceiver and the MCU are awake and perform normal communication and processing tasks. While in the awake state, the FSM110 monitors for sleep commands from either the hardware interface (PHY transceiver) or the I2C bus (MCU).

[0048] Upon receiving a sleep command, the FSM110 initiates a transition to the sleep state (from WAIT_SLEEP to SLEEP) when it receives both a sleep command from the reception signaling (RX) and a sleep command from the I2C bus (this condition is represented in Figure 3 by the expression SLEEP_CMD_RX && SLEEP_CMD_I2C). As discussed below, the transition from the awake state to the sleep state involves several intermediate stages (transitions through various intermediate states between WAIT_SLEEP and SLEEP) to ensure a controlled reduction in power consumption and prevent abrupt changes that could cause instability. In this particular embodiment, the FSM110 waits for a general waiting period (duration) before it completes the transition, waiting for the low-dropout regulator (LDO) to turn off (WAIT_LDO_OFF) (these conditions are represented in Figure 3 by the expression WAIT_LDO_OFF && WAIT_SLEEP). Waiting for the LDO to turn off and waiting for the general waiting period to end is optional, and any conditions added to or different from these two conditions are not beyond the scope of this disclosure.

[0049] In sleep mode, power consumption is minimized, and the SBC108, or more generally, system 100, is ready to wake up in response to a wake event. When a wake event occurs (e.g., receiving a wake command, though not limited to one), the FSM110 reverses the steps performed to transition the system to the awake state (WAIT_SLEEP). The FSM110 initiates the transition to the awake state (from SLEEP to WAIT_SLEEP) when it receives either a wake command from the receive signaling (RX) or a wake command from the I2C bus (this condition is represented in Figure 3 by the expression WAKE_CMD_RX || WAKE_CMD_I2C). In this particular embodiment, the FSM110 waits for the LDO to turn on (WAIT_LDO_ON) and for a general waiting period before completing the transition to the awake state (these conditions are represented in Figure 3 by the expression WAIT_LDO_ON && WAIT_WAKE). Waiting for the LDO to turn on and waiting for the general waiting period to end are optional, and any conditions added to or different from these two conditions are not beyond the scope of this disclosure.

[0050] Figure 4 is a state diagram showing the power state changes performed in stages from wake to sleep and from sleep to wake, managed by the FSM110 of the SBC108, in one or more embodiments.

[0051] The power state transitions performed in stages from awake to sleep include the following states (identified by circles): WAIT_SLEEP (i.e., awake state), XCR_CTL, ISO_CTRL, LDO_CTL, WAIT_LDO_OFF, ACT_DET_CTL, and WAIT_WAKE (i.e., sleep state). Transitions between states are represented by arrows pointing from one state to the next. The conditions or events that trigger a particular transition are identified next to the arrows.

[0052] In the transceiver control state (XCR_CTL), the FSM configures the PHY transceiver 112 with control settings to prepare for low-power mode. In the isolation control state (ISO_CTL), the FSM110 isolates certain circuits to reduce power draw during the awake-to-sleep transition and reintegrates the isolated circuits into the system's power domain during the sleep-to-awake transition. In the low-dropout regulator control state (LDO_CTL), the FSM110 adjusts the power regulation settings to reduce power consumption. In the wait for LDO to turn off state (WAIT_LDO_OFF), the FSM110 waits for confirmation that the LDO has successfully reduced or turned off its output. In the active detection control state (ACT_DET_CTL), the FSM110 maintains a state where any necessary monitoring regarding wake or sleep events is functioning and ensures that detection circuits are activated as needed. In low-power sleep mode (WAIT_WAKE), the FSM110 waits for a wake event. In wait for the LDO to turn on (WAIT_LDO_ON), ​​the FSM waits for the LDO to stabilize and provide the voltage level necessary for normal operation.

[0053] The stepwise transition from wake to sleep includes the following sequence of states: WAIT_SLEEP, XCR_CTL, ISO_CTL, LDO_CTL, WAIT_LDO_OFF, ACT_DET_CTL, and WAIT_WAKE.

[0054] The stepwise transition from sleep to wake includes the following sequence of states: WAIT_WAKE, ACT_DET_CTL, WAIT_LDO_ON, ISO_CTRL, CVR_CTRL, and WAIT_SLEEP.

[0055] These sequences ensure smooth and coordinated power state transitions, preventing abrupt changes that could lead to instability or increased power consumption. The FSM 110 manages these stepwise transitions, ensuring that each intermediate state completes normally before moving to the next state.

[0056] Figure 5 illustrates an exemplary process 500 for changing the power state of a system basis chip implementing a PHY transceiver of a PHY having a split PHY architecture, in one or more embodiments. While the exemplary process 500 shows a specific sequence of operations, the sequence can be modified without departing from the scope of the disclosure. For example, some of the operations shown may be performed in parallel or in different sequences that do not materially affect the functionality of process 500. In other embodiments, different components of the exemplary device or system implementing process 500 may function substantially simultaneously or in specific sequences. Some or all of the operations of process 500 may be performed by system 100 or system basis chip portion 200, in non-limiting embodiments.

[0057] According to one or more embodiments, process 500 may include the step of providing a system basis chip that supports at least two power states, a sleep state and an awake state, in operation 502.

[0058] According to one or more embodiments, process 500 may include the step of monitoring power state information via a hardware interface and via a communication interface, wherein the hardware interface enables communication between a physical layer (PHY) transceiver implemented on a system basis chip and a PHY controller implemented on a microcontroller in operation 504, and the communication interface enables communication between the system basis chip and the microcontroller.

[0059] According to one or more embodiments, process 500 may include, in operation 506, coordinating changes in the power state of a system basis chip, at least in part, based on receiving power state information via hardware interfaces and communication interfaces.

[0060] Figure 6 is a flowchart of process 600 in which changes in the power state of an SBC implementing a PHY transceiver are coordinated with changes in the power state of the PHY transceiver, in one or more embodiments. While exemplary process 600 shows a specific sequence of operations, the sequence can be modified without departing from the scope of the disclosure. For example, some of the operations shown may be performed in parallel or in different sequences that do not materially affect the functionality of process 600. In other embodiments, different components of the exemplary device or system implementing process 600 may function substantially simultaneously or in specific sequences. Some or all of the operations of process 600 may be performed by system 100 or system basis chip portion 200, in non-limiting embodiments.

[0061] According to one or more embodiments, the method includes the step of receiving a first power management command, which is received via a hardware interface in operation 602.

[0062] According to one or more embodiments, the method includes the step in operation 604 of decoding a first power management command from a signal received via a hardware interface.

[0063] According to one or more embodiments, the method includes receiving a second power management command in operation 606, the second power management command being received via a communication interface.

[0064] According to one or more embodiments, the method includes the step in operation 608 of decoding a second power management command from a signal received via a communication interface.

[0065] According to one or more embodiments, the method includes the step of coordinating changes in the power state of the system basis chip in operation 610, at least in part, based on the reception of both a first power management command and a second power management command.

[0066] Figure 7 illustrates an exemplary process 700 for changing the power state of a system basis chip, a PHY transceiver implemented by the system basis chip, or both, in one or more embodiments. While the exemplary process 700 shows a specific sequence of operations, the sequence can be modified without departing from the scope of the disclosure. For example, some of the operations shown may be performed in parallel or in different sequences that do not materially affect the functionality of process 700. In other embodiments, different components of the exemplary device or system implementing process 700 may function substantially simultaneously or in specific sequences. Some or all of the operations of process 700 may be performed by system 100 or system basis chip portion 200, in non-limiting embodiments.

[0067] According to one or more embodiments, process 700 may include, in operation 702, a step of performing a stepwise change in the power state of the system basis chip from a first state to a second state through a plurality of intermediate states.

[0068] According to one or more embodiments, process 700 may include in operation 704 a state in which one of the first or second state is an awake state and the other of the first or second state is a sleep state.

[0069] According to one or more embodiments, process 700 may include in operation 706 a plurality of intermediate states, including a transceiver control state, an isolation control state, a low dropout regulator (LDO) control state, a waiting state until the LDO is turned off, and an active detection control state.

[0070] Those skilled in the art will understand that the functional elements (e.g., functions, operations, actions, processes, and / or methods) of the embodiments disclosed herein can be implemented in any suitable hardware, software, firmware, or combination thereof. Figure 8 illustrates non-limiting embodiments of implementations of the functional elements disclosed herein. In some embodiments, some or all of the functional elements disclosed herein may be performed by hardware capable of executing the functional elements.

[0071] Figure 8 is a block diagram of a circuit 800 that may be used to implement various functions, operations, actions, processes, or methods disclosed herein in several embodiments. The circuit 800 includes one or more processors 802 (which may be referred to herein as "processors 802") operably coupled to one or more data storage devices 804 (which may be referred to herein as "storage devices 804"). The storage devices 804 include machine-executable code 806 stored therein, and the processors 802 include logic circuits 808. The machine-executable code 806 includes functional elements that describe information that can be implemented (e.g., performed) by the logic circuits 808. The logic circuits 808 are adapted to implement (e.g., perform) the functional elements described by the machine-executable code 806. When the circuit 800 executes the functional elements described by the machine-executable code 806, it should be considered dedicated hardware for executing the functional elements disclosed herein. In some embodiments, the processor 802 may perform the functional elements described by the machine-executable code 806 sequentially, simultaneously (for example, on one or more different hardware platforms), or in one or more parallel process streams.

[0072] When implemented by the logic circuit 808 of the processor 802, the machine-executable code 806 adapts the processor 802 to perform the operations of the embodiments disclosed herein. In a non-limiting embodiment, the machine-executable code 806 may adapt the processor 802 to perform some or all of the operations of one or more of the processes 500, 600, or 700, or the processes that implement state diagram 300 or state diagram 400.

[0073] In addition, as a non-limiting embodiment, machine executable code 806 may adapt processor 802 to perform some or all of the features, functions, or operations disclosed herein with respect to one or more of the system 100, system basis chip portion 200, state diagram 300, or state diagram 400. More specifically, features, functions, or operations disclosed herein for coordinating changes in power states.

[0074] The processor 802 may include a general-purpose processor, a dedicated processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. A general-purpose computer including a processor is considered a dedicated computer while the general-purpose computer is executing functional elements corresponding to machine-executable code 806 (e.g., software code, firmware code, hardware description) related to the embodiments of this disclosure. Note that the general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but instead, the processor 802 may include any conventional processor, controller, microcontroller, or state machine. Processor 802 can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0075] In some embodiments, the storage device 804 includes volatile data storage devices (e.g., random-access memory (RAM)) and non-volatile data storage devices (e.g., flash memory, hard disk drives, solid-state drives, erasable programmable read-only memory (EPROM)). In some embodiments, the processor 802 and the storage device 804 may be implemented in a single device (e.g., a semiconductor device product, a system on a chip (SOC)), but not limited to these. In some embodiments, the processor 802 and the storage device 804 may be implemented in separate devices.

[0076] In some embodiments, machine-executable code 806 may include computer-readable instructions (e.g., software code, firmware code). In a non-limiting embodiment, computer-readable instructions may be stored in memory device 804, directly accessed by processor 802, and executed by processor 802 using at least logic circuit 808. Also in a non-limiting embodiment, computer-readable instructions may be stored in memory device 804, transferred to a memory device (not shown) for execution, and executed by processor 802 using at least logic circuit 808. Thus, in some embodiments, logic circuit 808 includes an electrically configurable logic circuit 808.

[0077] In some embodiments, machine-executable code 806 may describe hardware (e.g., circuits) implemented within logic circuits 808 to perform functional elements. This hardware may be described at any of the various levels of abstraction, from low-level transistor layouts to high-level description languages. At high levels of abstraction, hardware description languages ​​(HDLs), such as the IEEE standard hardware description language (HDL), may be used. Non-limiting examples include VERILOG®, SYSTEMVERILOG®, or very large-scale integration (VLSI) hardware description languages ​​(VHDL).

[0078] An HDL description can be translated into a description at any of several other levels of abstraction, as desired. As an unspecified example, a high-level description can be translated into a logic-level description such as a register-transfer language (RTL), gate-level (GL) description, layout-level description, or mask-level description. In an unspecified embodiment, the microoperations performed by the hardware logic circuits of logic circuit 808 (e.g., gates, flip-flops, registers, etc.) may be described in RTL and then translated into a GL description by a synthesis tool, which can then be translated into a layout-level description by a placement and routing tool, which corresponds to the physical layout of an integrated circuit of programmable logic devices, separate gate or transistor logic, separate hardware components, or combinations thereof. Thus, in some embodiments, machine-executable code 806 may include HDL, RTL, GL descriptions, mask-level descriptions, other hardware descriptions, or any combination thereof.

[0079] In embodiments where the machine-executable code 806 includes a hardware description (at any level of abstraction), the system (including a storage device 804, not shown) implements the hardware description described by the machine-executable code 806. In non-limiting embodiments, the processor 802 may include a programmable logic device (e.g., an FPGA or PLC), and the logic circuit 808 may be electrically controlled to implement circuits corresponding to the hardware description in the logic circuit 808. Also in non-limiting embodiments, the logic circuit 808 may include hardwired logic manufactured by a manufacturing system (including a storage device 804, not shown) according to the hardware description of the machine-executable code 806.

[0080] Regardless of whether the machine-executable code 806 includes computer-readable instructions or hardware descriptions, the logic circuit 808 is adapted to perform the functional elements described by the machine-executable code 806 when implementing those functional elements. Note that while hardware descriptions do not have to directly describe functional elements, they indirectly describe the functional elements that the hardware elements described by them can perform.

[0081] When used in this disclosure, the terms “module” or “component” may refer to a specific hardware implementation for performing actions of a module or component and / or software object or software routine that are stored in and / or executed by general-purpose hardware of a computing system (e.g., computer-readable media, processing devices, etc.). In some embodiments, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes that run on a computing system (e.g., as separate threads). While some of the systems and methods described in this disclosure are generally described as being implemented in software (stored in and / or executed in general-purpose hardware), specific hardware implementations, or combinations of software and specific hardware implementations, are also possible and intended.

[0082] When used in this disclosure, the term “combination” referring to multiple elements may include any combination of all elements or any various different subcombinations of some elements. For example, the phrase “A, B, C, D, or any combination thereof” may refer to A, B, C, or D; any combination of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or any one of C and D.

[0083] The terms used in this disclosure, and in particular in the appended claims (e.g., the text of the appended claims, but not limited to them), are generally intended to be “open” terms (for example, “including” should be interpreted as “including, but not limited to,” “having” should be interpreted as “at least having,” and “includes” should be interpreted as “including, but not limited to,” but not limited to). As used herein, “each” means “part or whole.” As used herein, “each and all” means “whole.”

[0084] Additionally, if a specific number of introduced claims is intended, such intention will be explicitly enumerated in the claims; if there is no such enumeration, such intention does not exist. For example, to aid understanding, the attached claims below may include the use of the introductory phrases “at least one” and “one or more” to introduce a claim enumeration. However, the use of such phrases should not be interpreted as the introduction of a claim description with the indefinite article “a” or “an” limiting any particular claim containing such introduced claims to only one embodiment containing such description (for example, “a” and / or “an” should be interpreted as meaning “at least one” or “one or more,” although this is not a limitation). The same applies to the use of definite articles used to introduce a claim enumeration.

[0085] In addition, even if a specific number is explicitly stated in the introduced claims, a person skilled in the art will recognize that such a statement should be interpreted as meaning at least the number stated (for example, the explicit statement “recitations” without other modifiers means, but not limited to, at least two statements or two or more statements). Furthermore, where conventions similar to “at least one of A, B, and C” or “not limited to, one or more of A, B, and C” are used, such structures are generally intended to include, but not limited to, A only, B only, C only, A and B together, A and C together, B and C together, or A, B, and C together.

[0086] Furthermore, any separating words or phrases that present two or more alternative terms should be understood, whether in the specification, claims, or drawings, as intended to include the possibility of including one of the terms, either of the terms, or both of the terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B".

[0087] Further non-limiting embodiments include: Example 1: A method comprising the steps of: providing a system basis chip that supports at least two power states, a sleep state and an awake state; monitoring power state information via a hardware interface that enables communication between a physical layer (PHY) transceiver implemented on the system basis chip and a PHY controller implemented on a microcontroller, and a communication interface that enables communication between the system basis chip and the microcontroller; and coordinating changes in the power state of the system basis chip, at least in part, based on the reception of power state information via the hardware interface and the communication interface.

[0088] Example 2: The method according to Example 1, wherein the step of monitoring power status information includes monitoring power management commands and status information related to the power status.

[0089] Example 3: The method according to Examples 1 and 2, wherein the step of coordinating changes in the power state of the system basis chip is to coordinate changes in the power state of the system basis chip with changes in the power state of the PHY transceiver.

[0090] Example 4: The method according to Examples 1 to 3, wherein the step of coordinating a change in the power state of a system basis chip with a change in the power state of a PHY transceiver includes substantially simultaneously providing first power state information to one or more drivers managing the power state of the system basis chip and second power state information to one or more drivers managing the power state of the PHY transceiver.

[0091] Example 5: The method according to Examples 1 to 4, comprising the steps of receiving a first power management command received via a hardware interface, receiving a second power management command received via a communication interface, and coordinating changes in the power state of a system basis chip at least in part based on the reception of both the first and second power management commands.

[0092] Example 6: The method according to Examples 1 to 5, comprising the steps of decoding a first power management command from a signal received via a hardware interface and decoding a second power management command from a signal received via a communication interface.

[0093] Example 7: The method according to Examples 1 to 6, wherein the power state of the system basis chip does not change in response to only one of the first power management command or the second power management command.

[0094] Example 8: The method according to Examples 1 to 7, wherein both the first power management command and the second power management command each include a wake command or a sleep command.

[0095] Example 9: The method according to Examples 1 to 8, wherein the communication interface is separate from the hardware interface.

[0096] Example 10: The method according to Examples 1 to 9, wherein the PHY transceiver and PHY controller are combined to form a 10SPE PHY having a split PHY architecture.

[0097] Example 11: The method according to Examples 1 to 10, comprising the step of performing a stepwise change in the power state of a system basis chip from a first state to a second state through a plurality of intermediate states, wherein one of the first or second state is an awake state and the other of the first or second state is a sleep state.

[0098] Example 12: The method according to Examples 1 to 11, wherein the multiple intermediate states include a transceiver control state, an isolation control state, a low dropout regulator (LDO) control state, a standby state until the LDO is turned off, and an active detection control state.

[0099] Example 13: The method according to Examples 1-12, wherein the hardware interface for communication between the PHY transceiver and the PHY controller is integrated into the microcontroller.

[0100] Example 14: A device comprising: a first driver for implementing the functionality of a PHY transceiver on a system basis chip; a second driver for implementing the functionality of the system basis chip, which is different from the first driver; and a logic circuit for coordinating changes in the power state of the system basis chip with changes in the power state of the PHY transceiver via commands issued to the first driver and the second driver.

[0101] Example 15: The apparatus according to Example 14, wherein the system basis chip supports at least two power states: sleep and awake.

[0102] Example 16: The apparatus according to Examples 14 and 15, wherein the logic circuit monitors power state information via a hardware interface that enables communication between a PHY transceiver implemented on a system basis chip and a PHY controller implemented on a microcontroller, and a communication interface that enables communication between the system basis chip and the microcontroller, and coordinates changes in the power state of the system basis chip with changes in the power state of the PHY transceiver, at least partially based on the reception of power state information via both the hardware interface and the communication interface.

[0103] Example 17: The apparatus according to Examples 14-16, wherein the monitored power status information includes power management commands and status information relating to the power status.

[0104] Example 18: The apparatus according to Examples 14-17, wherein the logic circuit comprises a finite state machine (FSM) for initiating a change in the power state of a system basis chip, at least partially based on power state information indicating coordinated power state changes of PHY transceivers received via a hardware interface and a communication interface.

[0105] Example 19: The apparatus according to Examples 14-18, wherein the logic circuit comprises a finite state machine (FSM) for stepwise performing a change in the power state of a system basis chip from a first state to a second state through a plurality of intermediate states, wherein one of the first or second state is an awake state and the other of the first or second state is a sleep state.

[0106] Example 20: A system comprising a microcontroller and a system basis chip supporting at least two power states, a sleep state and an awake state, wherein the system basis chip monitors power state information via a hardware interface enabling communication between a PHY transceiver implemented on the system basis chip and a PHY controller implemented on the microcontroller, and a communication interface enabling communication between the system basis chip and the microcontroller, and coordinates changes in the power state of the system basis chip, at least in part, based on the reception of power state information via both the hardware interface and the communication interface.

[0107] While this disclosure is described herein with respect to certain illustrated embodiments, those skilled in the art will recognize and understand that the invention is not limited thereto. Rather, numerous additions, deletions, and modifications can be made to the illustrated and described embodiments without departing from the scope of the invention as claimed below, together with their legal equivalents. In addition, features of one embodiment can be combined with features of another disclosed embodiment, as conceived by the inventors, but still remain within the scope of this disclosure.

Claims

1. It is a method, The steps include providing a system basis chip that supports at least two power states: a sleep state and an awakened state, A hardware interface that enables communication between a physical layer (PHY) transceiver implemented on the system basis chip and a PHY controller implemented on the microcontroller, and a communication interface that enables communication between the system basis chip and the microcontroller, to monitor power status information. A method comprising the step of coordinating changes in the power state of the system basis chip, at least in part, based on the reception of power state information via the hardware interface and the communication interface.

2. The method according to claim 1, wherein the step of monitoring power status information includes monitoring power management commands and status information relating to the power status.

3. The step of coordinating the changes in the power state of the system basis chip is: The method according to claim 1, further comprising the step of coordinating the change in the power state of the system basis chip with the change in the power state of the PHY transceiver.

4. The step of coordinating the change in the power state of the system basis chip with the change in the power state of the PHY transceiver is: First power state information for one or more drivers that manage the power state of the system basis chip, The method according to claim 3, comprising the step of providing substantially simultaneously a second power state information to one or more drivers that manage the power state of the PHY transceiver.

5. The steps include receiving a first power management command received via the hardware interface, The steps include receiving a second power management command received via the aforementioned communication interface, The method according to claim 1, further comprising the step of coordinating changes in the power state of the system basis chip based at least in part on the reception of both the first power management command and the second power management command.

6. The steps include decoding the first power management command from the signal received via the hardware interface, The method according to claim 5, comprising the step of decoding a second power management command from a signal received via the communication interface.

7. The method according to claim 5, wherein the power state of the system basis chip does not change in response to only one of the first power management command or the second power management command.

8. The method according to claim 5, wherein both the first power management command and the second power management command each include a wake command or a sleep command.

9. The method according to claim 1, wherein the communication interface is separate from the hardware interface.

10. The method according to claim 1, wherein the PHY transceiver and the PHY controller together form a 10SPE PHY having a split PHY architecture.

11. The process includes a step of gradually changing the power state of the system basis chip from a first state to a second state through a plurality of intermediate states, The method according to claim 1, wherein one of the first state or the second state is an awake state, and the other of the first state or the second state is a sleep state.

12. The aforementioned multiple intermediate states are, The method according to claim 11, comprising a transceiver control state, an isolation control state, a low dropout regulator (LDO) control state, a standby state until the LDO is turned off, and an active detection control state.

13. The method according to claim 1, wherein the hardware interface for communication between the PHY transceiver and the PHY controller is integrated into the microcontroller.

14. It is a device, A first driver for implementing the functionality of a PHY transceiver on the system basis chip, A second driver for implementing the functions of the system basis chip, which is different from the first driver, A device comprising: a logic circuit for coordinating changes in the power state of the system basis chip with changes in the power state of the PHY transceiver via commands issued to the first driver and the second driver.

15. The apparatus according to claim 14, wherein the system basis chip supports at least two power states: a sleep state and an awake state.

16. The aforementioned logic circuit is A hardware interface that enables communication between the PHY transceiver implemented on the system basis chip and the PHY controller implemented on the microcontroller, and a communication interface that enables communication between the system basis chip and the microcontroller, are used to monitor power status information. The apparatus according to claim 14, for coordinating the changes in the power state of the system basis chip with the changes in the power state of the PHY transceiver, at least in part on receiving power state information via both the hardware interface and the communication interface.

17. The apparatus according to claim 16, wherein the monitored power status information includes a power management command and status information relating to the power status.

18. The aforementioned logic circuit is The apparatus according to claim 16, further comprising a finite state machine (FSM) for initiating a change in the power state of the system basis chip based at least in part on power state information indicating a coordinated change in the power state of the PHY transceiver, received via the hardware interface and the communication interface.

19. The aforementioned logic circuit is The system includes a finite state machine (FSM) for stepwise implementing a change in the power state of the system basis chip from a first state to a second state through multiple intermediate states, The apparatus according to claim 16, wherein one of the first state or the second state is an awake state, and the other of the first state or the second state is a sleep state.

20. It is a system, Microcontroller and The system comprises a system basis chip that supports at least two power states: a sleep state and an awake state, and the system basis chip is A hardware interface that enables communication between the PHY transceiver implemented on the system basis chip and the PHY controller implemented on the microcontroller, and a communication interface that enables communication between the system basis chip and the microcontroller, are used to monitor power status information. A system for coordinating changes in the power state of the system basis chip, at least partially based on receiving power state information via both the hardware interface and the communication interface.

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