Method, apparatus, medium for removing wafer surface defects, and wafer manufacturing method

Abstract

Embodiments of the present application disclose a method, apparatus, medium, and wafer manufacturing method for removing wafer surface defects, the method for removing wafer surface defects comprising: obtaining related defect types having a quantitative correlation with linear defects; determining the causative defects of the linear defects from among the related defect types, wherein the causative defects are the primary cause of the formation of the linear defects; obtaining a secondary cause of the linear defects during the wafer processing process; and generating a first removal measure to reduce the quantity of the causative defects and a second removal measure to instruct a change in processing parameters during the wafer processing process for the first and second causes, respectively, wherein the first and second removal measures can reduce the quantity of linear defects on the wafer surface.

Description

Technical Field

[0001] Cross-reference to Related Applications This application claims the priority of Chinese Patent Application No. 202311076184.5, filed in China on August 24, 2023, the entire content of which is incorporated herein by reference. The embodiments of this application relate to the technical field of semiconductor processing, and in particular, to a method, apparatus, medium, and wafer manufacturing method for removing defects on the wafer surface.

Background Art

[0002] With the continuous progress of the semiconductor manufacturing process, the impact of defects on the wafer on device performance has become increasingly significant. Therefore, strict management and control of wafer defects are of great importance.

[0003] Surface defects of wafers directly affect the quality and reliability of semiconductor manufacturing processes, such as photolithography processes, thin film deposition, etching processes, and metal electrode fabrication in semiconductor manufacturing. However, with the continuous development of the manufacturing process, the existing means of managing and controlling surface defects of wafers are no longer sufficiently effective, and more precise and strict means are required to control wafer surface defects.

Summary of the Invention

Problems to be Solved by the Invention

[0004] In view of this, the embodiments of this application aim to provide a method, apparatus, medium, and wafer manufacturing method for removing wafer surface defects that can reduce the occurrence of small-size defects on the silicon wafer surface and improve the quality and reliability of the wafer.

Means for Solving the Problems

[0005] The technical aspects of the embodiments of this application are realized as follows.

[0006] In the first aspect, an embodiment of the present application is a method for removing wafer surface defects, the method being To obtain related defect types that have a quantitative correlation with linear defects, The process involves determining the causative defect of the linear defect from among the aforementioned related defect types, wherein the causative defect is the primary cause of the formation of the linear defect. To obtain the second cause of the linear defect during the wafer processing process, The present invention provides a method for removing wafer surface defects, comprising generating a first removal measure to reduce the number of the causative defects and a second removal measure to instruct a change in processing parameters during the wafer processing process for the first and second causative causes, wherein the first and second removal measures can reduce the number of linear defects on the wafer surface.

[0007] In some cases, within a pair of defect types, there is a positive correlation between the number of linear defects and the number of causative defects.

[0008] In some cases, the causative defect is a residual defect.

[0009] In some cases, determining the causative defect of the linear defect from among the aforementioned related defect types is possible. The wafer polishing process includes determining the residual defects as the causative defects of the linear defects, in which the filler material present in microcracks at localized locations on the wafer surface reacts chemically and physically with the microcracks due to the high temperature generated during polishing, thereby forming linear defects.

[0010] In some cases, obtaining the secondary cause of the aforementioned linear defect during the wafer processing process is possible. The wafer polishing process includes determining the second cause of occurrence as the coincidence between the direction of motion of polishing particles at the wafer edge and the direction of linear defects.

[0011] In some cases, for the first and second causes of occurrence described above, a first removal measure to reduce the number of the causative defects and a second removal measure to instruct the wafer processing parameters to be changed are generated, respectively. Depending on the first cause of occurrence, it is determined that the first removal measure is to reduce the amount of residual organic matter on the wafer surface, thereby reducing the residual defect. This includes determining that the second removal measure, depending on the second cause of occurrence, is to change the trajectory of the polishing particles at the wafer edge.

[0012] In some cases, the second removal measure is, The wafer polishing process involves polishing the wafer surface using spherically shaped polishing particles to alter the trajectory of the polishing particles at the wafer edge.

[0013] In the second aspect, an embodiment of the present application is an apparatus for removing wafer surface defects, the apparatus is This includes the first acquisition portion, the finalization portion, the second acquisition portion, and the countermeasure generation portion, of which, The first acquisition unit is configured to acquire related defect types that have a quantitative correlation with linear defects, The determination portion is configured to determine the causative defect of the linear defect from among the related defect types, and of these, the causative defect becomes the first cause of the formation of the linear defect. The second acquisition unit is configured to acquire the second cause of the linear defect during the wafer processing process. The countermeasure generation unit is configured to generate a first removal countermeasure to reduce the number of the causative defects and a second removal countermeasure to instruct the wafer processing parameters to be changed for the first and second causative causes, respectively, and the first and second removal countermeasures provide a wafer surface defect removal device that can reduce the number of linear defects on the wafer surface.

[0014] In a third aspect, embodiments of the present application provide a computing device including a processor and memory, wherein the processor is for executing instructions stored in the memory so as to realize the method for removing wafer surface defects described in the first aspect and any one example in the first aspect.

[0015] In the fourth aspect, an embodiment of the present application is a computer storage medium storing at least one instruction, the at least one instruction being to be executed by a processor to realize a method for removing wafer surface defects as described in the first aspect and any one example in the first aspect.

[0016] In the fifth aspect, embodiments of the present application provide a computer program product including a computer instruction, wherein the computer instruction is stored in a computer-readable storage medium, and a processor of an electronic device reads the computer instruction from the computer-readable storage medium and executes the computer instruction, thereby enabling the electronic device to perform the method for removing wafer surface defects described in the first aspect and any one example in the first aspect.

[0017] In the sixth aspect, an embodiment of the present application is a wafer manufacturing method, the method being Determine the first and second removal measures for removing linear defects according to the method for removing wafer surface defects described in the first phase and any one example in the first phase, In the wafer processing process, a wafer manufacturing method is provided, which includes removing straight-line defects on the wafer surface by using the first removal measure and the second removal measure.

Advantages of the Invention

[0018] The embodiments of the present application provide a method, an apparatus, a medium, and a wafer manufacturing method for removing wafer surface defects. The root causes of straight-line defects are determined based on the quantity correlation, and the quantity of straight-line defects is reduced by reducing the quantity of root cause defects. Accordingly, the processing parameters in the wafer processing process are changed according to the generation mechanism of straight-line defects in the wafer processing process. Through the combination of the above two measures, the occurrence quantity of small-size defects on the wafer surface is reduced, and the processing quality of the wafer is improved.

Brief Description of the Drawings

[0019] [Figure 1] FIG. 1 is a flow schematic diagram of a method for removing wafer surface defects according to an embodiment of the present application. [Figure 2] FIG. 2 is a schematic diagram of the aggregated statistics of defects of multiple polishing wafers according to an embodiment of the present application. [Figure 3] FIG. 3 is a schematic diagram of the quantity correlation of two types of defects according to an embodiment of the present application. [Figure 4] (A) and (B) of FIG. 4 are schematic diagrams of residue defects according to an embodiment of the present application. [Figure 5] FIG. 5 is a distribution schematic diagram of straight-line defects according to an embodiment of the present application. [Figure 6] FIG. 6 is a schematic diagram of the configuration of a polishing device according to an embodiment of the present application. [Figure 7] FIG. 7 is a schematic diagram of the movement direction of polishing particles according to an embodiment of the present application. [Figure 8] FIG. 8 is a topography schematic diagram of discontinuous straight-line defects according to an embodiment of the present application. [Figure 9] FIG. 9 is a schematic diagram of spherical-shaped polishing particles according to an embodiment of the present application. [Figure 10] Figure 10 is a schematic diagram of the configuration of an apparatus for removing wafer surface defects according to an embodiment of the present application. [Figure 11] Figure 11 is a schematic diagram of the structure of a computing device according to an embodiment of the present invention. [Figure 12] Figure 12 is a schematic flowchart of a wafer manufacturing method according to an embodiment of the present application. [Modes for carrying out the invention]

[0020] The technical proposal in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this application.

[0021] Regarding control measures for defects on the wafer surface, it is possible to prevent relatively large defects from existing on the wafer surface. However, to meet the reliability requirements of advanced manufacturing processes, it is necessary to control wafer surface defects using more precise and rigorous methods. Improving the control of small defects on the wafer surface is one way to achieve this.

[0022] Regarding small-sized defects on the wafer surface, the embodiment of this application attempts to determine removal measures for small-sized defects on the wafer surface by combining the quantitative correlation between defects and the defect generation mechanism during the wafer processing process. As a result, the number of small-sized defects appearing on the wafer surface is reduced, and the processing quality of the wafer is improved.

[0023] Based on this, with reference to Figure 1, a method for removing wafer surface defects according to an embodiment of the present application is shown, which is applicable to computing equipment, and the method includes the following steps S101 to S104.

[0024] Step S101 is to obtain related defect types that have a quantitative correlation with linear defects. Typically, wafer defects need to be detected after wafer processing is complete but before shipment. Taking polished wafers as an example, the final processing step is the cleaning process. After the cleaning process is complete, it is possible to use a scanning electron microscope (SEM) to detect the surface of the polished wafer to be inspected and obtain an image of the polished wafer surface. Subsequently, it is possible to determine the location of defects on the image of the polished wafer surface. Next, at the locations where defects exist, the type of defect present at each defect location is determined and the quantity of each type of defect is statistically calculated using methods such as machine learning models and classification algorithms, according to image features corresponding to different defect types (e.g., aspect ratio, edge slope, circularity, group statistics of slope variance).

[0025] For each polished wafer after the cleaning process is completed, defects are detected as described above, and the detection results are aggregated and statistically analyzed. Common surface defects found on polished wafer surfaces include particle defects, line jut defects, fat jut defects, mechanical pit defects, residual defects, and scratch defects. In some cases, the above defects from multiple polished wafers are aggregated and statistically analyzed, and the results are shown in Figure 2. As can be seen from Figure 2, the main defect type present on the polished wafer surface is line jut defects.

[0026] In some cases, when the defect type and quantity were statistically analyzed individually for each polished wafer, as shown in Figure 3, using defect detection performed on 13 polished wafers as an example, a positive correlation was found between the number of line jut defects and the number of residual defects. That is, the more line jut defects there were, the more residual defects there were, and conversely, as the number of line jut defects decreased, the number of residual defects also decreased.

[0027] Step S102 is to determine the causative defect of the linear defect from among the related defect types. Of these, the aforementioned causative defect becomes the primary cause of the formation of the linear defect.

[0028] In the embodiments of this application, linear defects and residual defects exhibit a quantitative correlation, which can be shown to indicate that both types of defects are caused by the same faulty process. Furthermore, a certain degree of causal relationship exists between defects that exhibit quantitative correlation; that is, if the quantity of one type of defect (e.g., defect A) is reduced, the quantity of the other type of defect (e.g., defect B) will also decrease accordingly, even if no separate treatment is performed on the other type of defect (e.g., defect B). Based on this, the causal defect becomes defect A, and the linear defect becomes defect B. In some examples, this causal relationship can be determined according to the defect formation mechanism, and it becomes known that residual defects are the causal defects of linear defects. For specific determination processes, refer to the subsequent descriptions of implementation methods and examples of this step.

[0029] Step S103 is to obtain the second cause of the linear defect during the wafer processing process. In the embodiments of this application, the cause of linear defects is not limited to one factor. In addition to the residue defects described in the steps above, the processing processes and means used in the wafer processing process can also contribute to the occurrence of linear defects. In some examples, it is possible to determine a secondary cause of linear defects in the wafer processing process based on the distribution of linear defects on the wafer surface image, the processing trajectory during the wafer processing process, and the resulting physical and chemical changes. In some examples, the process for determining the secondary cause can be similarly described in subsequent descriptions of implementation methods and examples of this step.

[0030] Step S104 involves generating a first removal measure to reduce the number of causative defects and a second removal measure to instruct the wafer processing parameters to be changed for the first and second causative causes, respectively, of which the first and second removal measures can reduce the number of linear defects on the wafer surface.

[0031] In the embodiments of the present application, in some cases, the number of causal defects can be reduced based on the causal relationship between causal defects and linear defects, depending on the first cause of occurrence obtained in S102 above. As a result, the number of linear defects also decreases, and consequently, the number of both types of defects can be effectively and significantly reduced with only one countermeasure, thereby improving wafer quality.

[0032] In some examples, depending on the second cause of occurrence obtained in S103 above, processing parameters such as the processing process and means in the wafer processing process can be changed in order to remove linear defects that occurred during the wafer processing process. In this example, when changing the processing parameters, it is not necessary to consider the causative defect, and only the generation mechanism of the linear defect during the processing process needs to be considered. The coupling between the two removal measures is reduced, and it is avoided that a separate defect will be introduced when the two generated removal measures are executed.

[0033] Regarding the above technical embodiment, the causative defects of linear defects are determined based on quantitative correlation, and the number of linear defects is reduced by decreasing the number of causative defects. In addition, processing parameters in the wafer processing process are changed according to the mechanism of linear defect generation in the wafer processing process. By combining these two measures, the number of small defects appearing on the wafer surface is reduced, and the processing quality of the wafer is improved.

[0034] Based on the aforementioned technical embodiments, in several possible implementation methods, determining the causative defect of the linear defect from among the aforementioned related defect types is: The wafer polishing process includes determining the residual defects as the causative defects of the linear defects, in which the filler material present in microcracks at localized locations on the wafer surface reacts chemically and physically with the microcracks due to the high temperature generated during polishing, thereby forming linear defects.

[0035] Regarding the above implementation method, specifically, during the wafer polishing process, dislocations are generated on the silicon wafer surface. These dislocations propagate and accumulate to form large linear cracks. Of these cracks, the majority are the expansion of microcracks that occurred after exceeding the critical fracture size, ultimately leading to surface fracture at that point. Furthermore, smaller cracks, due to impurities or pinning effects between cracks, do not reach the critical size, and therefore do not expand into microcracks. As a result, these smaller cracks can remain in their corresponding local locations.

[0036] During the polishing process, silicon debris mixed into the polishing slurry, additives in the polishing slurry such as pH adjusters, and other organic media fill these small cracks. As the polishing process progresses, the localized high temperatures generated during polishing cause a reaction between the filler and the cracks at these small crack locations, thereby increasing the adhesion of the filler. Referring to the schematic diagrams of residual defects shown in Figures 4(A) and (B), respectively, based on the above description, there is a similarity between the morphology of the defects in the images and the morphology of linear defects. Therefore, there is a positive correlation between the number of residual defects and the number of linear defects; that is, the more residual material, such as organic residue, there is more organic material entering the cracks, and thus more linear defects are formed.

[0037] Based on the above description, for a pair of defect types consisting of a residual defect and a linear defect, the residual defect is one of the causes of the formation of the linear defect, and therefore the causative defect is the residual defect.

[0038] Based on the aforementioned technical embodiments, in several possible implementation methods, obtaining the second cause of the linear defect during the wafer processing process is: The wafer polishing process includes determining the second cause of occurrence as the coincidence between the direction of motion of polishing particles at the wafer edge and the direction of linear defects.

[0039] Regarding the above implementation method, when combined with the previously mentioned implementation method, the characteristic of cracks with fillers should be that they are uniformly distributed on the wafer surface, and in other words, linear defects should also be uniformly distributed on the wafer surface. However, as can be seen by referring to the schematic distribution diagram in the image of linear defects shown in Figure 5, linear defects do not exhibit the characteristic of being uniformly distributed, but rather exhibit the characteristic of being few in number at the wafer center and many at the wafer edge. On the other hand, linear defects at the edge have a regularity in that their direction relatively coincides with the tangential direction of the wafer edge, whereas the direction of linear defects closer to the wafer center loses the above directional regularity.

[0040] In order to analyze the schematic distribution diagram of the linear defects described above, it is first necessary to analyze the polishing process. In the embodiment of this application, as can be seen by referring to the schematic configuration diagram of the polishing equipment shown in Figure 6, the polishing equipment may generally include an upper platen 61, a carrier 62 on which the wafer is placed, and a lower platen 63. The upper platen 61 and the lower platen 63 rotate in opposite directions to each other, and the polishing slurry flows down from the cavities 64 uniformly distributed in the upper platen 61. The wafer surface is polished by the relative rotation of the upper and lower plates and the polishing slurry, so that mechanical damage and defects on the wafer surface can be removed.

[0041] Based on the above brief description of the polishing equipment, since the cavities 64 on the upper platen 61 are uniformly distributed, the polishing slurry should also be uniformly distributed on the wafer surface. However, during the polishing process, the direction of motion of the polishing particles in the polishing slurry is determined by the direction of the combined velocity of the centrifugal velocity v1 and the linear velocity v2 of the relative rotation of the upper and lower platens. As shown in Figure 7, if we start timing from the moment the platen begins to rotate, in the first stage, when the rotation time of the platen is less than the set critical time 1 / w, v2 becomes smaller than v1, and at this time, the direction of the combined velocity (i.e., the direction of motion of the polishing particles) is biased towards the linear velocity v2. In the second stage, when the rotation time of the platen becomes longer than the critical time, the direction of the combined velocity (i.e., the direction of motion of the polishing particles) is biased towards the centrifugal velocity v1. Therefore, after polishing begins, polishing particles closer to the wafer center have sufficient time to complete the change in direction of the synthesis rate in both of the above stages, whereas polishing particles closer to the wafer edge are thrown out of the wafer by centrifugal force after the first stage of the change in direction of the synthesis rate. As a result, the direction of motion of polishing particles at the wafer edge is along the tangential direction at the edge where they are located.

[0042] When the direction of motion of the polishing particles does not coincide with the direction of the cracks with fillers, the cracks with fillers (i.e., linear defects) are removed by lapping, resulting in fewer linear defects closer to the wafer center. The discontinuous topography of linear defects shown in Figure 8 supports this characteristic. In Figure 8, the linear defects are divided into multiple defects. This is because the direction of motion of the polishing particles is not parallel to the direction of the linear defects. Although the defects were removed by lapping the polishing particles laterally, the polishing particles were not densely distributed and there were gaps between them. As a result, the linear defects were not completely removed by lapping, ultimately leading to the discontinuous topography.

[0043] When the direction of motion of the polishing particles coincides with the direction of the cracks with filler, linear defects in the gaps between the polishing particles are not removed by lapping. As a result, linear defects are distributed along the tangent to the wafer edge. In other words, most linear defects on the wafer surface that do not coincide with the direction of motion of the polishing particles are removed by lapping, while linear defects located at the wafer edge and along the tangential direction are not removed by lapping.

[0044] In summary, the agreement between the direction of motion of polishing particles at the wafer edge and the direction of linear defects may be established as another cause of the presence of linear defects.

[0045] Based on the above embodiment and its implementation method, in several possible implementation methods, for the first and second causes of occurrence described above, a first removal measure to reduce the number of the causative defects and a second removal measure to instruct the wafer processing parameters to be changed are generated, respectively. Depending on the first cause of occurrence, it is determined that the first removal measure is to reduce the amount of residual organic matter on the wafer surface, thereby reducing the residual defect. This includes determining that the second removal measure, depending on the second cause of occurrence, is to change the trajectory of the polishing particles at the wafer edge.

[0046] Regarding the above example, it should be explained that after identifying the cause of linear defects using the above method, it is possible to determine countermeasures for eliminating linear defects based on the cause. As a first countermeasure for the first cause, in order to reduce the amount of organic matter remaining on the wafer surface, the waiting time of the wafer from the completion of the polishing process (the last process in wafer machining) to the cleaning process may be reduced. This reduces the amount of organic matter remaining on the wafer surface and does not give enough time for the organic matter to fill the cracks.

[0047] As a second removal measure against the second cause of defects, the consistency of the directional distribution may be disrupted by selectively modifying the shape of the polishing particles to change their motion trajectory. This makes it possible to uniformly lap and remove linear defects in each direction on the wafer surface. In some examples, during the wafer polishing process, the wafer surface may be polished using polishing particles with mismatched end face areas to change the motion trajectory of the polishing particles at the wafer edge. Taking the black spherical-shaped polishing particles shown in Figure 9 as an example, these spherical-shaped polishing particles have different end faces at both ends. At one end, a large contact surface is generated, resulting in a large frictional force, which causes the polishing particle itself to rotate. This changes the direction of motion of the polishing particle, and further changes the direction of motion of the polishing particle at the wafer edge. Furthermore, if one end with a large contact surface randomly contacts the upper or lower platen, a large number of polishing particles will simultaneously be present moving in the opposite direction. In this way, the direction of motion of the polishing particles can be disrupted, resulting in the effect of more uniform lapping and removal of defects. Moreover, for example, conical and frustoconical polishing particles are polishing particles with mismatched end face areas, but this will not be elaborated on in the embodiments of this application.

[0048] In some examples, the area of ​​the larger end face represents the magnitude of the frictional force that can be obtained by the polishing particle and determines its rotational speed, thus resulting in different removal effects for linear defects. In the specific implementation process, polishing particles with different end face areas may be designed and blended, thereby achieving a better linear defect removal effect.

[0049] Based on the same inventive concept as described above, with reference to Figure 10, the figure shows an apparatus 100 for removing wafer surface defects according to an embodiment of the present application, and the apparatus 100 may include a first acquisition portion 1001, a confirmation portion 1002, a second acquisition portion 1003, and a countermeasure generation portion 1004, of which, The first acquisition unit 1001 is configured to acquire related defect types that have a quantitative correlation with linear defects, The determination portion 1002 is configured to determine the causative defect of the linear defect from among the related defect types, and of these, the causative defect becomes the first cause of the formation of the linear defect. The second acquisition unit 1003 is configured to acquire the second cause of occurrence of the linear defect during the wafer processing process. The countermeasure generation unit 1004 is configured to generate a first removal countermeasure to reduce the number of the causative defects and a second removal countermeasure to instruct the wafer processing parameters to be changed, depending on the first cause and the second cause of occurrence, and of these, the first removal countermeasure and the second removal countermeasure can reduce the number of linear defects on the wafer surface.

[0050] In some cases, within a pair of defect types, there is a positive correlation between the number of linear defects and the number of causative defects.

[0051] In some examples, in the pair of defect types, the causative defect is a residue defect.

[0052] In some examples, the definite portion 1002 is In the wafer polishing process, the filler material present in microcracks at localized locations on the wafer surface reacts chemically and physically with the microcracks due to the high temperature generated during polishing, forming linear defects. The system is configured to identify these residual defects as the causative defects of the linear defects.

[0053] In some examples, the second acquisition portion 1003 is In the wafer polishing process, the system is configured to determine the second cause of occurrence by determining the coincidence between the direction of motion of polishing particles at the wafer edge and the direction of linear defects.

[0054] In some examples, the countermeasure generation unit 1004 is Depending on the first cause of occurrence, the first removal measure is determined to reduce the amount of residual organic matter on the wafer surface, thereby reducing the residual defect. Depending on the second cause of occurrence, the second removal measure is configured to be determined to involve altering the trajectory of the polishing particles at the wafer edge.

[0055] In some cases, the second removal measure is, The wafer polishing process involves polishing the wafer surface using polishing particles with mismatched edge surface areas, thereby altering the trajectory of the polishing particles at the wafer edge.

[0056] Referring to Figure 11, the figure shows a structural block diagram of a computing device according to one exemplary embodiment of the present invention. The computing device in the present invention may include one or more processors 1110 and memory 1120.

[0057] Selectively, the processor 1110 connects various parts of the entire computing device using various interfaces and lines, and performs various functions of the computing device and processes data by operating or executing instructions, programs, code sets or instruction sets stored in memory 1120, and by retrieving data stored in memory 1120. Selectively, the processor 1110 may be implemented by employing at least one hardware form from among Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 1110 may integrate one or more combinations from among a Central Processing Unit (CPU), Graphics Processing Unit (GPU), Neural-network Processing Unit (NPU), and baseband chip, etc. Of these components, the CPU primarily handles the operating system, user interface, and application programs, while the GPU is responsible for rendering and drawing content that needs to be displayed on the touch screen. The NPU is for implementing artificial intelligence (AI) functions, and the baseband chip is for handling wireless communication. The baseband chip may be implemented separately on a single chip rather than being integrated into the processor 1110.

[0058] The memory 1120 may include random access memory (RAM) or read-only memory (ROM). Optionally, the memory 1120 may include a non-transitory computer-readable storage medium. The memory 1120 can be used to store instructions, programs, code, code sets, or instruction sets. The memory 1120 may include a program storage area and a data storage area, the program storage area capable of storing instructions for implementing an operating system, instructions for at least one function (e.g., touch function, audio playback function, image playback function, etc.), instructions for implementing each of the above-described embodiments, etc. The data storage area can store data created in accordance with the use of the computing device, etc.

[0059] Furthermore, as those skilled in the art will understand, the structure of the computing device shown in the above drawings does not constitute a limitation on the computing device, and the computing device may include more or fewer components than those shown, and may include combinations or different arrangements of components. For example, the computing device may further include components such as a display screen, imaging components, microphone, speaker, radio frequency circuit, input unit, sensors (e.g., accelerometer, angular velocity sensor, light sensor, etc.), audio circuit, WiFi module, power supply, Bluetooth module, etc., but these are not to be elaborated here.

[0060] Embodiments of the present invention further provide a computer-readable storage medium storing at least one instruction, the at least one instruction to be executed by a processor to realize the method for removing wafer surface defects described in each of the above embodiments.

[0061] Embodiments of the present application further provide a computer program product which includes computer instructions, which are stored in a computer-readable storage medium, and a processor of a computing device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, thereby enabling the computing device to perform and implement a method for removing wafer surface defects according to each of the selective implementation methods of the above aspects.

[0062] As will be apparent to those skilled in the art, in one or more of the above examples, the functions described in the embodiments of this application can be implemented by hardware, software, firmware, or any combination thereof. When implemented by software, these functions may be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. The computer-readable medium includes computer storage media and communication media. Of these, the communication medium includes any medium that facilitates the transmission of computer programs from one place to another. The storage medium may be any available medium accessible by a general-purpose or special-purpose computer.

[0063] Based on the method for removing wafer surface defects described above, refer to Figure 12, which shows a wafer manufacturing method according to an embodiment of the present application, and this method is Step S1210 involves determining a first removal measure and a second removal measure for removing linear defects according to the method for removing wafer surface defects described in any one of the embodiments described above, The wafer processing process may also include step S1220, which involves removing linear defects from the wafer surface using the first and second removal measures.

[0064] It should be explained that the technical embodiments described in the present invention can be combined in any way, as long as they do not contradict each other.

[0065] The above describes only specific embodiments of the present application, and the scope of protection is not limited thereto. A person skilled in the art can easily conceive of modifications and substitutions within the technical scope described in the present application, and all such modifications and substitutions should be considered within the scope of protection of the present application. Therefore, the scope of protection of the present application should be in accordance with the attached claims.

Claims

1. A method for removing wafer surface defects, wherein the method is To obtain related defect types that have a quantitative correlation with linear defects, The process involves determining the causative defect of the linear defect from among the aforementioned related defect types, wherein the causative defect is the primary cause of the formation of the linear defect. To obtain the second cause of the linear defect during the wafer processing process, A method for removing wafer surface defects, comprising generating a first removal measure to reduce the quantity of the causative defects and a second removal measure to instruct a change in processing parameters during the wafer processing process for the first and second causative causes, wherein the first and second removal measures can reduce the quantity of linear defects on the wafer surface.

2. The method according to claim 1, wherein the number of linear defects and the number of causative defects exhibit a positive correlation.

3. The method according to claim 1 or 2, wherein the causative defect is a residue defect.

4. Determining the causative defect of the linear type defect from among the aforementioned related defect types is: The method according to claim 3, wherein, in the wafer polishing process, the residual defects are identified as the causative defects of the linear defects, in accordance with the fact that the filler present in microcracks at localized locations on the wafer surface reacts chemically and physically with the microcracks due to the high temperature generated during polishing, thereby forming linear defects.

5. Obtaining the second cause of the aforementioned linear defect during the wafer processing process is: The method according to claim 3, wherein the wafer polishing process includes determining the coincidence between the direction of motion of polishing particles at the wafer edge and the direction of linear defects as the second cause of occurrence.

6. For the first and second causes of occurrence described above, generating a first removal measure to reduce the number of the causative defects and a second removal measure to instruct a change in the processing parameters during the wafer processing process are, Depending on the first cause of occurrence, it is determined that the first removal measure is to reduce the amount of residual organic matter on the wafer surface, thereby reducing the residual defect. The method according to claim 3, further comprising determining that the second removal measure is to change the motion trajectory of the polishing particles at the wafer edge, depending on the second cause of occurrence.

7. The second removal measure is, The method according to claim 6, wherein the wafer polishing process includes polishing the wafer surface using polishing particles having mismatched edge surface areas to change the trajectory of the polishing particles at the wafer edge.

8. An apparatus for removing wafer surface defects, the apparatus includes a first acquisition section, a confirmation section, a second acquisition section, and a countermeasure generation section, of which, The first acquisition unit is configured to acquire related defect types that have a quantitative correlation with linear defects, The determination portion is configured to determine the causative defect of the linear defect from among the related defect types, and of these, the causative defect becomes the first cause of the formation of the linear defect. The second acquisition unit is configured to acquire the second cause of the linear defect during the wafer processing process. The countermeasure generation unit is configured to generate, for the first cause and the second cause, a first removal countermeasure to reduce the number of the causative defects and a second removal countermeasure to instruct the wafer processing parameters to be changed, respectively, wherein the first removal countermeasure and the second removal countermeasure can reduce the number of linear defects on the wafer surface, and the apparatus removes wafer surface defects.

9. A computing device including a processor and memory, wherein the processor is for executing instructions stored in the memory so as to realize a method for removing wafer surface defects as described in any one of claims 1 to 7.

10. A computer storage medium storing at least one instruction, wherein the at least one instruction is to be executed by a processor so as to realize a method for removing wafer surface defects according to any one of claims 1 to 7.

11. A wafer manufacturing method, wherein the method is Determining a first removal measure and a second removal measure for removing linear defects according to the method for removing wafer surface defects described in any one of claims 1 to 7, A wafer manufacturing method comprising removing linear defects from the wafer surface using the first removal measure and the second removal measure during the wafer processing process.

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