Semiconductor device having interconnects formed by atomic layer deposition

Abstract

A semiconductor device assembly is provided, comprising a first semiconductor die and a second semiconductor die. The first semiconductor die has a first dielectric material layer and a first conductive pad disposed within a first opening in the first dielectric material layer. The second semiconductor die has a second dielectric material layer facing the first dielectric material layer and a second conductive pad disposed within a second opening in the second dielectric material layer and corresponding to the first conductive pad. A spacer extends between the first dielectric material layer and the second dielectric material layer. A conductive material is disposed between the first conductive pad and the second conductive pad (e.g., by atomic layer deposition (ALD)) to implement an interconnect that electrically couples the first semiconductor die and the second semiconductor die.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor device assemblies, and more particularly to laminated semiconductor devices having interconnects formed by atomic layer deposition (ALD).

Background Art

[0002] Microelectronic devices generally have a die (e.g., a chip) that includes integrated circuits in which very small elements are densely integrated. Usually, the die includes an array of bond pads electrically coupled to the integrated circuit. The bond pads are external electrical contacts through which power voltages, signals, etc. are transmitted and received between the integrated circuit. After the die is formed, these are “packaged” and the bond pads are connected to a larger array of electrical terminals that can be more easily connected by various power lines, signal lines, and ground lines. Conventional processes for packaging a die include electrically connecting the bond pads on the die to an array of leads, ball pads, or other types of electrical terminals, and encapsulating the die to protect it from environmental factors (e.g., moisture, particles, static electricity, and physical shock).

Brief Description of the Drawings

[0003] [Figure 1] A simplified schematic cross-sectional view of a semiconductor device assembly according to an embodiment of the present technology is shown. [Figure 2] A simplified schematic plan view and cross-sectional view of a series of processes for manufacturing a semiconductor device assembly according to an embodiment of the present technology are shown. [Figure 3A] A simplified schematic plan view and cross-sectional view of a series of processes for manufacturing a semiconductor device assembly according to an embodiment of the present technology are shown. [Figure 3B] A simplified schematic plan view and cross-sectional view of a series of processes for manufacturing a semiconductor device assembly according to an embodiment of the present technology are shown. [Figure 4]Simplified schematic plan and cross-sectional views of a series of steps for manufacturing a semiconductor device assembly according to one embodiment of this technology are shown. [Figure 5] Simplified schematic plan and cross-sectional views of a series of steps for manufacturing a semiconductor device assembly according to one embodiment of this technology are shown. [Figure 6] Simplified schematic plan and cross-sectional views of a series of steps for manufacturing a semiconductor device assembly according to one embodiment of this technology are shown. [Figure 7] A simplified schematic cross-sectional view of a semiconductor device assembly according to one embodiment of this technology is shown. [Figure 8] A schematic diagram of a system including a semiconductor device assembly according to one embodiment of this technology is shown. [Figure 9] This document shows a method for manufacturing a semiconductor device assembly according to one embodiment of this technology. [Modes for carrying out the invention]

[0004] Computing devices often include semiconductor devices to implement processors, memory, and other functional elements. Semiconductor devices can be stacked to increase the number of circuit elements implemented within the device without increasing the device's footprint. Many multilayer semiconductor devices utilize hybrid bonding to form vertical interconnects. Hybrid bonding utilizes the volume expansion of a conductive material (e.g., copper) to form vertical interconnects through openings in bonded dielectric material layers. For example, two semiconductor dies are aligned such that conductive pads placed in openings in the dielectric material layer on one semiconductor die align with conductive pads placed in openings in the dielectric material layer on the other semiconductor die. The dielectric material layers on each semiconductor die may be bonded and the conductive pads heated so that they expand toward each other.

[0005] Ideally, conductive pads expand and, through diffusion, form metal-metal interconnects within the bonded dielectric material layers. However, in other cases, under-expanded or over-expanded interconnects can occur, limiting the reliability of the semiconductor device, due to the spacing between conductive pads, which may result from the chemical mechanical polishing (CMP) process, which is difficult to control. For example, if the conductive pads are too far apart, voids may remain between the interconnects, which can cause short circuits in the semiconductor device. Alternatively, if the conductive pads are too close together, the interconnects may decouple the dielectric material layers, resulting in a decrease in the mechanical strength of the semiconductor device assembly.

[0006] To solve these and other problems, the present invention discloses a semiconductor device having an interconnect formed by atomic layer deposition (ALD). The semiconductor device includes a first semiconductor die and a second semiconductor die. The first semiconductor die has a first dielectric material layer and a first conductive pad disposed within a first opening in the first dielectric material layer. The second semiconductor die has a second dielectric material layer facing the first dielectric material layer and a second conductive pad disposed within a second opening in the second dielectric material layer and corresponding to the first conductive pad. A spacer extends between the first and second dielectric material layers. A conductive material is disposed between the first and second conductive pads (e.g., by ALD) to implement an interconnect that electrically couples the first and second semiconductor dies. In this way, a highly reliable semiconductor device can be assembled, an example of which is shown in Figure 1.

[0007] Figure 1 shows a simplified schematic cross-sectional view of a semiconductor device assembly 100, which includes semiconductor dies 102 and 104 electrically coupled to each other. Semiconductor die 102 may be mounted on a substrate 106, which may be a wafer-level substrate for mounting multiple semiconductor dies, or a die-level substrate for mounting individual semiconductor dies. Similarly, semiconductor die 104 may be mounted on a substrate 108, which may be a wafer-level or die-level substrate. Thus, the semiconductor device assembly 100 can be formed by wafer-to-wafer bonding, chip-to-wafer bonding, or chip-to-chip bonding. Semiconductor dies 102 and 104 may be bonded in a surface-to-surface, surface-to-backside, or backside-to-backside configuration. In this way, semiconductor die 102 or semiconductor die 104 may each include through-silicon vias (TSVs) (not shown) that extend through the substrate 106 or substrate 108 and provide electrical connections to surface-side circuits via TSVs exposed on the backside.

[0008] A dielectric material layer 110 (e.g., silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride) may be placed on the semiconductor die 102 to mount a passivation layer. The dielectric material layer 110 may have one or more openings through which contact pads 112 (e.g., copper pads) placed on the semiconductor die 102 are exposed. The contact pads 112 may be recessed from the dielectric material layer 110 (e.g., by only 5 nm to 10 nm) due to dishing by CMP, for example. The contact pads 112 may be connected to circuit elements (e.g., traces, lines, vias) so that additional circuit components can be electrically coupled to the semiconductor die 102 and provide functions to the semiconductor die 102 (e.g., power, ground, input / output (I / O) signal transmission). A dielectric material layer 114 may be placed on the semiconductor die 104 such that the dielectric material layer 114 faces the dielectric material layer 110. The dielectric material layer 114 may have an opening that exposes the contact pad 116, and the contact pad 116 corresponds to the contact pad 112 placed on the semiconductor die 102.

[0009] In contrast to other semiconductor devices, dielectric material layers 114 and 110 do not necessarily need to be in contact with each other. Instead, a spacer 118 may be placed between dielectric material layers 110 and 114 to maintain a predetermined distance between semiconductor die 102 and semiconductor die 104. This allows the semiconductor device assembly 100 to be configured to meet specifications. The spacer 118 may be placed on and extending from dielectric material layer 110 or dielectric material layer 114. In some cases, the spacer 118 does not need to cover the entire dielectric material layer 110 or dielectric material layer 114. Instead, the spacer 118 may be an independent structure that covers only a portion of the dielectric material layer 110 or dielectric material layer 114. In some embodiments, the spacer 118 may contain a dielectric material (e.g., the same dielectric material as dielectric material layer 110 or dielectric material layer 114 or a different dielectric material) or a polymer. The spacer 118 may have a thickness of 120 (for example, a thickness measured perpendicular to the surface on which the spacer 118 is placed), and this thickness 120 may be less than 100 nm, less than 200 nm, less than 500 nm, etc. In some cases, a bond may be formed between the dielectric material layer on the opposite side of the dielectric material layer on which the spacer 118 is placed. For example, if the spacer 118 is placed on the dielectric material layer 110, the distal end of the spacer 118 may be bonded to the dielectric material layer 114 (for example, by a fusion bond).

[0010] A conductive material 122 (e.g., a tin-free material, a lead-free material, or a non-solder material) may be placed between contact pads 112 and 116 to implement an interconnect that electrically bonds semiconductor die 102 and semiconductor die 104. The conductive material 122 may be deposited by ALD. In some embodiments, ALD is a process that can deposit material with fine particle size (e.g., sub-nanometer precision). However, due to such precision, ALD can take considerably longer to deposit than other material deposition techniques (e.g., deposition rates of 100 nm / hour to 300 nm / hour). Therefore, ALD can be used for deposition requiring high controllability in small spaces. In the illustrated example, ALD is used to deposit the conductive material 122 between contact pads 112 and 116. As a result, the conductive material 122 can implement interconnects of sizes such as less than 100 nm, less than 200 nm, and less than 500 nm. Any number of conductive materials can be used to implement the interconnect. For example, conductive material 122 may include copper, aluminum, silver, or gold. In some cases, conductive material 122 may also include cobalt because it has material properties that are advantageous with respect to ALD.

[0011] The interconnects formed by the techniques described here differ from those formed by other bonding techniques, such as hybrid bonding. For example, hybrid bonding utilizes the thermal expansion properties of conductive pads to form metal-metal interconnects from a single conductive material. In the hybrid bonding process, the connection between contact pad 112 and contact pad 116 is formed by a high-temperature annealing process, in which contact pads 112 and 116 expand toward each other. Once in contact, metal atoms from contact pads 112 and 116 diffuse toward each other, forming the connection. In such a situation, dishing of contact pads 112 and 116 (e.g., erosion of a portion of the contact pad compared to other portions of the contact pad or dielectric material) must be strictly controlled to prevent over-expansion or under-expansion.

[0012] In contrast to these implementations, the technology disclosed herein utilizes a separate deposition process to form an interconnect between contact pads 112 and 116. The ALD process is an additive process in which conductive material 122 is selectively added to contact pads 112 and 116 and deposited until the gap between them is filled. Thus, a larger dishing margin is permitted for contact pads 112 and 116, and this dishing may remain even after the conductive material 122 has been deposited. This reduces the risk of under-expanded or over-expanded interconnects, thereby improving the robustness of the semiconductor device assembly 100. Furthermore, due to its selective addition capability, the conductive material 122 can adapt to misalignments of contact pads 112 and 116.

[0013] In yet another embodiment, the conductive material 122 and the contact pad 112 or contact pad 116 may contain different conductive materials. For example, the contact pad 112 or contact pad 116 may contain copper, and the conductive material 122 may contain cobalt, gold, silver, or any other conductive material. In some embodiments, the conductive material 122 may be continuous (e.g., seamless) and may not have metal-metal bonding as formed by hybrid bonding, as diffusion does not occur between the contact pad 112 and the contact pad 116 to form an interconnect. Furthermore, as ALD can slowly deposit the conductive material 122, the conductive material 122 is deposited not only vertically but also radially on already deposited conductive material 122, thereby causing the conductive material 122 to expand into the gap between the dielectric material layer 110 and the dielectric material layer 114. In this way, the conductive material 122 may be wider than the contact pad 112 or contact pad 116 in some parts.

[0014] As described above, the spacer 118 does not need to cover the entire surface of the dielectric material layer 110 or the dielectric material layer 114. As a result, a gap may exist between the dielectric material layer 110, the dielectric material layer 114, the spacer 118, and the conductive material 122. In some cases, a gap fill 124 can be used to fill this gap. In this way, the semiconductor device assembly 100 can be further supported. The gap fill 124 may contain a dielectric material or a polymer. If the gap fill 124 contains a dielectric material, the dielectric material may be the same as or different from the dielectric material used in the spacer 118. Similarly, if the gap fill 124 contains a polymer, the polymer may be the same as or different from the polymer used in the spacer 118. In some cases, the gap fill 124 may contain a dielectric material arranged by ALD.

[0015] This disclosure goes on to describe a series of steps in the manufacturing process of a semiconductor device assembly according to one embodiment of the Art. Specifically, Figures 2 to 6 are simplified schematic plan and cross-sectional views illustrating a series of steps for manufacturing a semiconductor device assembly according to one embodiment of the Art. For ease of explanation, these steps are illustrated in relation to a particular embodiment. However, the steps described with reference to Figures 2 to 6 may be performed to manufacture a semiconductor device assembly according to other embodiments.

[0016] Figure 2 shows a simplified schematic cross-sectional view of a semiconductor device assembly 200 including a substrate 202 (e.g., a wafer-level substrate, a die-level substrate). In some embodiments, the semiconductor device assembly 200 may include a wafer of semiconductor dies, or a sliced ​​semiconductor die. A dielectric material layer 204 is located on one side of the substrate 202 (e.g., the front side or the back side). A contact pad 206 is located on the same side of the substrate 202 so that additional circuit components (e.g., semiconductor dies) can be bonded there. The dielectric material layer 204 includes an opening into which the contact pad 206 is exposed. The contact pad 206 may be recessed from the dielectric material layer 204 (e.g., by only 5 nm to 10 nm) due to dishing by CMP, for example. In some embodiments, the dielectric material layer 204 does not need to be planar, as the dielectric material layer 204 does not come into contact with the dielectric material layer on the additional die and therefore does not require a flat surface to improve adhesion.

[0017] Figure 3A shows a simplified schematic cross-sectional view of the semiconductor device assembly 300a after at least one spacer 302 has been placed on the dielectric material layer 204. Figure 3B shows a simplified schematic plan view of the top surface of the semiconductor device assembly 300b. This at least one spacer 302 may be placed on the top surface of the dielectric material layer 204. The at least one spacer 302 may include multiple independent islands spaced apart from each other. As shown in Figure 3B, the at least one spacer 302 does not cover the entire top surface of the dielectric material layer 204. Thus, the cross-sectional area of ​​the at least one spacer 302 in the same plane as its top surface (the plane shown in Figure 3B) may be smaller than the area of ​​the top surface of the dielectric material layer 204. This at least one spacer 302 may extend a certain amount (e.g., less than 100 nm, less than 200 nm, less than 500 nm) above the top surface of the dielectric material layer 204.

[0018] The at least one spacer 302 described above may be positioned by any suitable technique. For example, the at least one spacer 302 may be deposited using photolithography. The at least one spacer 302 may contain a dielectric material or polymer. In some cases, the upper surface of the at least one spacer 302 may be planarized using CMP. In this way, the upper surface of the at least one spacer 302 can provide a flat contact surface to which an additional semiconductor die can be bonded.

[0019] Figure 4 shows a simplified schematic cross-sectional view of a semiconductor device assembly 400. The semiconductor device assembly 400 includes a substrate 402 on which semiconductor dies are mounted. In some mounting configurations, the substrate 402 is a wafer-level substrate for mounting multiple semiconductor dies, or a die-level substrate for mounting a single, fragmented semiconductor die. Thus, the semiconductor device assembly 400 can be formed by wafer-to-wafer bonding, chip-to-wafer bonding, or chip-to-chip bonding. A dielectric material layer 404 is located on one side of the substrate 402. The dielectric material layer 404 has openings through which contact pads 406 are exposed. The contact pads 406 correspond to contact pads 206. The dielectric material layer 404 faces the dielectric material layer 204. The dielectric material layer 404 is in contact with the bonding surface of the spacer 302. In this way, the spacer 302 can maintain the gap between the semiconductor dies. In some cases, the dielectric material layer 404 may be directly bonded to the spacer 302. For example, the spacer 302 may contain a dielectric material, and the spacer 302 and the dielectric material layer 404 may form a fusion bond. Alternatively, the spacer 302 may contain a polymer, and the spacer 302 may be bonded to the dielectric material layer 404 by heating or adhesive.

[0020] FIG. 5 shows a simplified schematic cross-sectional view of a semiconductor device assembly 500 after a conductive material 502 is disposed between contact pad 206 and contact pad 406. In some embodiments, the conductive material 502 is disposed by ALD. In some cases, ALD enables selective deposition at specific locations. Thus, the conductive material 502 can be selectively deposited within the narrow gap between contact pad 206 and contact pad 406 and also outside the lateral positions of contact pad 206 and contact pad 406. For example, the conductive material 502 can be deposited within a gap less than 100 nm, less than 200 nm, less than 500 nm, etc. The conductive material 502 can include any number of conductive materials. For example, the conductive material 502 can be a material different from the material used to implement contact pad 206 or contact pad 406. As a specific example, the conductive material 502 can include cobalt.

[0021] FIG. 6 shows a simplified schematic cross-sectional view of a semiconductor device assembly 600 after a gap fill 602 is disposed. Since spacer 302 does not necessarily cover the entire surface of dielectric material layer 204 and the conductive material 502 is selectively deposited between contact pad 206 and contact pad 406, a gap can exist between dielectric material layer 204, dielectric material layer 404, spacer 302, and the conductive material 502. The gap fill 602 can be disposed within this gap. For example, the gap fill 602 can be deposited using ALD. In some cases, the gap fill 602 can include a dielectric material or a polymer. By disposing the gap fill 602, the mechanical strength of the semiconductor device assembly 600 can be improved and electrical contact with the conductive material 502 can be prevented.

[0022] Figure 7 shows a simplified schematic cross-sectional view of a semiconductor device assembly 700, which includes a stack of semiconductor dies 702 packaged as a semiconductor device (e.g., individual pieces derived from two bonded semiconductor wafers). The semiconductor dies 702 may be bonded in a front-to-front, front-to-back, or back-to-back configuration. One or more of the semiconductor dies 702 may include a TSV 704 for bonding back-side contact pads to a front-side metallization layer (e.g., traces, lines, vias, or other connection structures). In some embodiments, interconnects 706 for electrically bonding the semiconductor dies 702 together may be formed by the techniques disclosed herein (e.g., ALD deposition with spacers).

[0023] The semiconductor die 702 may be coupled to a package-level substrate 708 (e.g., a printed circuit board (PCB), an interposer, or other semiconductor die). A connecting structure 710 (e.g., solder balls, solder bumps, conductive pillars) may be positioned between the bottom contact pads of the semiconductor die on the underside of the bottom layer of the semiconductor die 702 and the top contact pads (not shown) of the package-level substrate 708, and may implement an interconnect that electrically couples the semiconductor die 702 and the package-level substrate 708. An underfill material 712 (e.g., capillary underfill) may be provided between the bottom die of the semiconductor die 702 and the package-level substrate 708 to provide electrical insulation to the connecting structure 710 and to mechanically support the semiconductor device assembly 700. The package-level substrate 708 may include internal wiring circuits (e.g., traces, lines, vias, or other connection structures) that connect the top contact pads to the bottom contact pads. The connection structure 714 may be located on the lower contact pad and may provide external connections to other devices (e.g., devices on the motherboard). The semiconductor device assembly 700 may further include a sealing material 716 (e.g., a molding resin composition) that at least partially seals the stack of semiconductor dies 702 and the package-level substrate 708 to prevent electrical contact with them, or that imparts mechanical strength to the semiconductor device assembly 700.

[0024] In the above exemplary embodiments, the semiconductor device assembly has been illustrated and described as including semiconductor dies of a specific configuration. However, in other embodiments, assemblies having different configurations of semiconductor dies may be provided. For example, the semiconductor device assembly illustrated in any of the above examples may be implemented using, for example, a vertical stack of semiconductor dies or a plurality of semiconductor dies, with appropriate modifications made as necessary.

[0025] In one aspect of the present disclosure, the semiconductor device illustrated in the assemblies of FIGS. 1 to 7 may include memory dies such as dynamic random access memory (DRAM) dies, NOT-AND (NAND) memory dies, NOT-OR (NOR) memory dies, magnetic random access memory (MRAM) dies, phase change memory (PCM) dies, ferroelectric random access memory (FeRAM) dies, static random access memory (SRAM) dies, and the like. In embodiments where a plurality of dies are provided within a single assembly, the semiconductor device may include the same type of memory dies (e.g., both NAND, both DRAM), or may include different types of memory dies (e.g., one DRAM and the other NAND). In another aspect of the present disclosure, the semiconductor die of the above-described assembly may be a logic die (e.g., a controller die, a processor die), or may be a combination of a logic die and a memory die (e.g., a memory controller die and a memory die controlled by the memory controller die).

[0026] Any of the semiconductor devices and semiconductor device assemblies described above with reference to Figures 1 to 7 can be incorporated into countless larger or more complex systems, a representative example being system 800 schematically shown in Figure 8. System 800 may include a semiconductor device assembly 802 (e.g., a discrete semiconductor device), a power supply 804, a driver 806, a processor 808, and other subsystems or components 810. The semiconductor device assembly 802 may include features generally similar to those of the semiconductor device assembly described above with reference to Figures 1 to 7. The resulting system 800 can perform a variety of functions, such as memory storage, data processing, and other appropriate functions. Thus, typical systems 800 may include, without limitation, portable devices (e.g., mobile phones, tablets, e-readers, digital audio players), computers, vehicles, consumer electronics, and other products. The components of system 800 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communication network). The components of system 800 may also include remote devices and various computer-readable media.

[0027] Figure 9 shows an example of a method 900 for manufacturing a semiconductor device assembly according to one embodiment of the present technology. Although illustrated in a specific configuration, one or more steps of method 900 may be omitted, repeated, or reconfigured. Furthermore, method 900 may include additional steps not shown in Figure 9, such as steps described in detail in one or more other methods described herein.

[0028] In 902, a first semiconductor die is provided. The first semiconductor die includes a first dielectric material layer and a first conductive pad disposed within a first opening in the first dielectric material layer. In 904, a second semiconductor die is provided. The second semiconductor die includes a second dielectric material layer and a second conductive pad disposed within a second opening in the second dielectric material layer. In 906, a spacer is placed on the first dielectric material layer. The spacer extends from the first dielectric material layer. In 908, the first semiconductor die and the second semiconductor die are aligned such that the first dielectric material layer faces the second dielectric material layer, the second dielectric material layer is in contact with the spacer, and the first conductive pad corresponds to the second conductive pad. In 910, a conductive material (for example, using ALD) is deposited between the first conductive pad and the second conductive pad, and an interconnect that electrically couples the first semiconductor die and the second semiconductor die is implemented. In this way, a highly reliable semiconductor device can be assembled.

[0029] The above describes specific details of several embodiments of semiconductor devices and related systems and methods. Depending on the context in which it is used, the term "substrate" may refer to a wafer-level substrate or a die-level substrate. Furthermore, unless otherwise indicated in the context, the structures disclosed herein can be formed using conventional semiconductor manufacturing techniques. Materials can be deposited using, for example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, ALD, or other suitable techniques. Similarly, materials can be removed using, for example, plasma etching, wet etching, CMP, or other suitable techniques.

[0030] The technologies disclosed herein relate to semiconductor devices, systems comprising semiconductor devices, and related methods for manufacturing semiconductor devices. The term “semiconductor device” may refer to a solid-state device comprising one or more semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, diodes, and the like. Furthermore, the term “semiconductor device” may refer to a finished device, or to an assembly or other structure at various processing stages before becoming a finished product. Depending on the context in which it is used, the term “substrate” may refer to a structure that supports electronic components (e.g., dies), such as a PCB or wafer-level substrate, a die-level substrate, or other dies for die stacking or three-dimensional interface (3DI) applications.

[0031] The devices discussed herein (including memory devices) may be formed on semiconductor substrates or semiconductor dies such as silicon, germanium, silicon-germanium alloys, gallium arsenide, or gallium nitride. In some cases, the substrate may be a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or the conductivity of subregions of the substrate can be controlled by doping with various chemical species, not limited to phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping means.

[0032] The functions described herein may be implemented by hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are also included within the scope of this disclosure and the accompanying claims. The features implementing the functions may be physically located in various locations, and some of the functions may be distributed so as to be implemented in different physical locations.

[0033] In this specification, when “or” is used in a list of items (for example, a list of items preceded by phrases such as “at least one of” or “one or more of”), including in the claims, it shall be interpreted as an inclusive list. For example, the list of items “at least one of A, B, or C” means at least one of A, B, and C, i.e., A, B, C, AB, AC, BC, or ABC (i.e., A, B, and C). Furthermore, in this specification, the phrase “based on” shall not be interpreted as referring only to a closed set of conditions. For example, an exemplary step described as “based on condition A” may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, in this specification, the phrase “based on” shall be interpreted in the same manner as the phrase “based at least in part on”.

[0034] In this specification, terms such as “vertical”, “lateral”, “upper”, “lower”, “above”, and “below” may refer to the relative orientation or position of a feature in a semiconductor device, assuming the orientation shown in the drawings. For example, “upper” or “uppermost” may refer to a feature located closer to the top of the page than other features. However, these terms should be interpreted broadly to include cases where the semiconductor device is in an inverted or tilted orientation in which other orientations, such as “top / bottom”, “over / under”, “above / below”, “up / down”, and “left / right”, can be reversed depending on the orientation.

[0035] As can be understood from the foregoing description, specific embodiments of the present invention have been described for illustrative purposes, but various modifications can be made without departing from the scope of the invention. In this description, numerous specific details have been discussed in order to provide a sufficient and practical description of embodiments of the present art. However, those skilled in the art will recognize that the disclosure can be implemented without one or more of these specific details. In other cases, well-known structures or operations often associated with memory systems and memory devices have not been illustrated or described in detail so as not to obscure other aspects of the present art. In general, it should be understood that, in addition to the specific embodiments disclosed herein, various other devices, systems, and methods may also be included within the scope of the present art.

Claims

1. A method for manufacturing a semiconductor device assembly, A first dielectric material layer, The first dielectric material layer includes a first conductive pad disposed within a first opening in the first dielectric material layer, To provide a first semiconductor die, A second dielectric material layer, Includes a second conductive pad disposed within a second opening in the second dielectric material layer. To provide a second semiconductor die, Placing a spacer on the first dielectric material layer and extending the spacer from the first dielectric material layer, Aligning the first semiconductor die and the second semiconductor die such that the first dielectric material layer faces the second dielectric material layer, the second dielectric material layer contacts the spacer, and the first conductive pad corresponds to the second conductive pad, A conductive material is deposited between the first conductive pad and the second conductive pad using atomic layer deposition. A method for manufacturing a semiconductor device assembly, including [a specific component].

2. A method according to claim 1, further comprising depositing a polymer or dielectric material between the first dielectric material layer, the second dielectric material layer, the conductive material and the spacer using atomic layer deposition.

3. A method according to claim 1, wherein the spacer is positioned only on a portion of the exposed surface of the first dielectric material layer.

4. A method according to claim 1, further comprising forming a direct bond between the spacer and the second dielectric material layer.

5. A method according to claim 1, wherein the spacer comprises a dielectric material or a polymer.

6. A method according to claim 1, wherein the first conductive pad comprises copper and the conductive material comprises cobalt.

7. A method according to claim 1, further comprising thinning the spacer using chemical mechanical polishing.

8. A semiconductor device assembly, A first dielectric material layer, The first dielectric material layer includes a first conductive pad disposed within a first opening in the first dielectric material layer, The first semiconductor die, A second dielectric material layer facing the first dielectric material layer, The second conductive pad is disposed within a second opening in the second dielectric material layer and corresponds to the first conductive pad, The second semiconductor die, A spacer disposed on the first dielectric material layer and extending from the first dielectric material layer to the second dielectric material layer, A conductive material is disposed between the first conductive pad and the second conductive pad, and implements an interconnect that electrically couples the first semiconductor die and the second semiconductor die, and at least a portion of the conductive material extends within the gap between the first dielectric material layer and the second dielectric material layer. A semiconductor device assembly comprising the above features.

9. A semiconductor device assembly according to claim 8, wherein the first conductive pad is recessed from the first dielectric material layer.

10. A semiconductor device assembly according to claim 9, wherein the first conductive pad is recessed from the first dielectric material layer by an amount exceeding 5 nm.

11. A semiconductor device assembly according to claim 8, wherein the first conductive pad and the conductive material are conductive materials different from each other.

12. A semiconductor device assembly according to claim 11, wherein the first conductive pad comprises copper and the conductive material comprises cobalt.

13. A semiconductor device assembly according to claim 8, wherein the spacer is disposed only on a portion of the surface of the first dielectric material layer facing the second dielectric material layer.

14. A semiconductor device assembly according to claim 8, further comprising a polymer or dielectric material disposed between the first dielectric material layer, the second dielectric material layer, the conductive material and the spacer.

15. A semiconductor device assembly according to claim 8, wherein the spacer comprises a polymer or a dielectric material.

16. A semiconductor device assembly according to claim 8, wherein the thickness of the spacer is less than 0.5 μm.

17. A semiconductor device assembly according to claim 8, wherein the conductive material is formed using an atomic layer deposition process.

18. A semiconductor device assembly according to claim 8, wherein the interconnect is continuous between the first conductive pad and the second conductive pad, and does not have a metal-to-metal bond.

19. A semiconductor device assembly according to claim 8, wherein the conductive material is a tin-free and lead-free material.

20. A method for manufacturing a semiconductor device assembly, A first dielectric material layer, The first dielectric material layer includes a first conductive pad disposed within a first opening in the first dielectric material layer, To provide a first semiconductor die, A second dielectric material layer, The second dielectric material layer includes a second conductive pad disposed within a second opening in the second dielectric material layer, To provide a second semiconductor die, Placing a spacer on the first dielectric material layer and extending the spacer from the first dielectric material layer, The spacer is bonded to the second dielectric material layer such that the first dielectric material layer faces the second dielectric material layer and the first conductive pad corresponds to the second conductive pad, A conductive material is deposited between the first conductive pad and the second conductive pad using atomic layer deposition. A polymer or dielectric material is deposited using atomic layer deposition such that at least a portion of it is disposed between the first dielectric material layer and the second dielectric material layer. A method for manufacturing a semiconductor device assembly, including [a specific component].

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