Memory structure comprising a 3D NOR-type memory string of channel-all-around ferroelectric memory transistors and method for manufacturing the same

Abstract

This disclosure provides a memory structure comprising randomly accessible channel-all-around ferroelectric memory transistors configured as a horizontal NOR-type memory string. The NOR-type memory string is formed on a semiconductor substrate within a plurality of scalable memory stacks of channel-all-around ferroelectric memory transistors. The three-dimensional memory stack is manufactured by a process comprising the steps of forming a multilayer stack with holes for forming local word line structures, and forming slit trenches for dividing the multilayer stack into memory stacks containing the local word line structures. The memory structure comprising channel-all-around memory transistors of this disclosure enables a scalable configuration for realizing high-density and high-capacity memory devices.

Description

Technical Field

[0001] The present invention relates to a high-density memory structure and a method for manufacturing the same. In particular, the present invention relates to a memory structure having a three-dimensional NOR-type memory string of a channel all-around ferroelectric memory transistor. Further, the present invention relates to a vertical channel all-around ferroelectric field effect transistor formed on a semiconductor substrate.

Background Art

[0002] A NOR-type memory string comprises multiple storage transistors that share a common source region and a common drain region, and each storage transistor can be individually addressed and accessed. U.S. Patent No. 10,121,553 (Patent Document 1), issued on November 6, 2018, entitled "Capacitively Coupled Non-Volatile Thin-Film Transistor NOR-Type String in a Three-Dimensional Array," discloses a storage transistor (or memory transistor) configured as a three-dimensional array of NOR-type memory strings formed on the upper side of a semiconductor substrate plane. The entire disclosure of Patent Document 1 is incorporated herein by reference for any purpose. The NOR-type memory string disclosed in Patent Document 1 comprises a number of thin-film storage transistors that share a common bit line and a common source line. Specifically, Patent Document 1 discloses a NOR-type memory string including (i) a common source region and a common drain region extending longitudinally along the horizontal direction, and (ii) gate electrodes of each storage transistor extending vertically. In this specification, the term “vertical” refers to a direction perpendicular to the plane of the semiconductor substrate, and the term “horizontal” refers to a direction parallel to the plane of the semiconductor substrate. In a three-dimensional array, NOR memory strings are provided on multiple planes (e.g., eight or sixteen planes) on the semiconductor substrate, and the NOR memory strings on each plane are arranged in columns along two mutually orthogonal horizontal directions. In the case of charge-trapped storage transistors, data is stored in each storage transistor using a charge storage film as the gate dielectric material. For example, the charge storage film includes a tunnel dielectric layer, a charge trapping layer, and a blocking layer, which can be realized as a multilayer in which silicon oxide (or oxynitride), silicon nitride (silicon-rich nitride), and silicon oxide are stacked in that order, and is called an ONO layer. An electric field applied to the charge storage film changes the threshold voltage of the storage transistor by adding charge to or removing charge from the charge trapping layer of the charge storage film, thereby encoding a given logic state in the storage transistor.

[0003] Advances in electrically polarizable materials ("ferroelectric materials"), particularly those used in semiconductor manufacturing processes, suggest new potential applications in ferroelectric memory circuits. For example, the paper "Ferroelectricity in Hafnium Oxide: CMOS compatible Ferroelectric Field Effect Transistors," by TS Boscke et al., published in 2011 International Electron Devices Meeting (IEDM), pp. 24.5.1-24.5.4, discloses a ferroelectric field-effect transistor ("FeFET") using hafnium oxide as the gate dielectric material. By controlling the polarization direction of the ferroelectric gate dielectric layer, the FeFET can be written to / erased to have one of two threshold voltages. Each threshold voltage of the FeFET constitutes a state representing a specified logical value, such as a "written" or "erased" state. Such FeFETs are being applied to high-density memory circuits. In another embodiment, U.S. Patent No. 9,281,044 (Patent Document 2), issued on March 8, 2016, by DVNirmal Ramaswamy et al., entitled "Apparatus having a ferroelectric field-effect transistor memory array and related method," discloses a three-dimensional array of FeFETs. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] U.S. Patent No. 10,121,553 [Patent Document 2] U.S. Patent No. 9,281,044 [Overview of the Initiative] [Means for solving the problem]

[0005] This disclosure provides a memory structure comprising a three-dimensional NOR-type memory string of channel-all-around ferroelectric memory transistors and a method for manufacturing the same. This disclosure is substantially described with reference to, for example, at least one figure and is more fully described in the claims.

[0006] In some embodiments, the present disclosure provides a three-dimensional memory structure formed on the plane of a semiconductor substrate, comprising a plurality of memory stacks arranged along a first direction substantially parallel to the plane of the semiconductor substrate, each memory stack separated from adjacent memory stacks along the first direction by trenches, each memory stack and each trench extending in a second direction perpendicular to the first direction and substantially parallel to the plane of the semiconductor substrate, each memory stack comprising a plurality of active layers arranged along a third direction substantially perpendicular to the plane of the semiconductor substrate, each active layer comprising a first conductive layer and a second conductive layer stacked with respect to each other in the third direction and separated from each other by a first insulating layer. A three-dimensional memory structure is provided, comprising: a plurality of memory stacks, each active layer being separated from adjacent active layers along a third direction by a second insulating layer; and a plurality of local word line structures provided within each memory stack as columnar bodies extending in a third direction, each local word line structure being surrounded by a first conductive layer and a second conductive layer, each local word line structure comprising concentric layers of an oxide semiconductor layer, a ferroelectric dielectric layer, and a gate conductor layer, the oxide semiconductor layer being provided in a region overlapping with the first and second conductive layers, surrounding the local word line structure and in contact with the first and second conductive layers. Each active layer in the memory stack forms a plurality of thin-film ferroelectric memory transistors configured as a NOR-type memory string, and each thin-film ferroelectric memory transistor is formed at a position where the active layer and the local word line structure intersect.

[0007] In another embodiment, the present disclosure provides a method suitable for use in manufacturing a memory structure comprising memory transistors of a NOR type memory string on a plane of a semiconductor substrate, comprising the step of forming a multilayer stack by alternately stacking multilayers and interlayer sacrificial layers on the plane of a semiconductor substrate, wherein each multilayer comprises a first sacrificial layer, a second sacrificial layer, and a first insulating layer interposed between the first and second sacrificial layers, and the multilayer stack extends in first and second directions that are orthogonal to each other and substantially parallel to the plane of the semiconductor substrate, and the multilayers and interlayer sacrificial layers The steps include: stacking sacrificial layers in a third direction substantially perpendicular to the plane of a semiconductor substrate; forming a plurality of holes in a multilayer stack that extend in the third direction through the multilayer and interlayer sacrificial layers, the plurality of holes including a first plurality of holes formed in the memory array region; forming a local word line structure in each of the first plurality of holes, the step including forming concentric layers of a dielectric liner layer, an oxide semiconductor layer, a ferroelectric dielectric layer, and a gate conductor layer in each of the first plurality of holes; and multilayer film A method is provided comprising the steps of: dividing a multilayer stack into multiple memory stacks by forming a plurality of trenches in a stack, each memory stack comprising a subset of local word line structures formed within the stack, each memory stack being separated from adjacent memory stacks along a first direction by one of the plurality of trenches, each memory stack and each trench extending in a second direction, and each memory stack comprising a multilayer and interlayer sacrificial layer arranged in a third direction; replacing a first sacrificial layer and a second sacrificial layer with a first conductive layer and a second conductive layer using access through the plurality of trenches, the first conductive layer and the second conductive layer being in contact with the oxide semiconductor layer of each local word line structure in each memory stack; removing the interlayer sacrificial layer using access through the plurality of trenches to expose a portion of the oxide semiconductor layer formed on the outer periphery of the local word line structures formed in the first plurality of holes; and removing at least a portion of the exposed portion of the oxide semiconductor layer using access through the plurality of trenches.

[0008] In another embodiment, the present disclosure provides an integrated circuit comprising a vertical ferroelectric field-effect transistor formed on a plane of a semiconductor substrate, wherein the ferroelectric field-effect transistor includes a columnar gate conductor layer provided as a columnar body extending in a first direction substantially orthogonal to the plane of the semiconductor substrate, an annular ferroelectric dielectric layer formed to surround the columnar gate conductor layer, an annular oxide semiconductor layer formed to surround the annular ferroelectric dielectric layer, and a first conductive layer and a second conductive layer provided as planes parallel to the plane of the semiconductor substrate, which are stacked along the first direction, separated from each other by a first insulating layer, surround the outer periphery of the annular oxide semiconductor layer, and are in contact with the annular oxide semiconductor layer. In a ferroelectric field-effect transistor, a first conductive layer, a second conductive layer, and an annular oxide semiconductor layer are formed at the intersection of these layers. The first conductive layer forms the drain region, the second conductive layer forms the source region, the annular oxide semiconductor layer forms the junction-less channel region, the annular ferroelectric dielectric layer forms the gate dielectric layer, and the columnar gate conductor layer forms the gate electrode of the ferroelectric field-effect transistor.

[0009] In another embodiment, the present disclosure provides an array of memory strings, each memory string comprising a plurality of vertical ferroelectric field-effect transistors formed on a plane of a semiconductor substrate, each ferroelectric field-effect transistor comprising: a columnar gate conductor layer formed as a columnar body extending in a first direction substantially orthogonal to the plane of the semiconductor substrate; an annular ferroelectric dielectric layer formed to surround the columnar gate conductor layer; an annular oxide semiconductor layer formed to surround the annular ferroelectric dielectric layer; and a first conductive layer and a second conductive layer formed as planes parallel to the plane of the semiconductor substrate, stacked along the first direction, separated from each other by a first insulating layer, surrounding the outer periphery of the annular oxide semiconductor layer and in contact with the annular oxide semiconductor layer. In a ferroelectric field-effect transistor, a first conductive layer, a second conductive layer, and an annular oxide semiconductor layer are formed at the intersection of these layers. The first conductive layer forms the drain region, the second conductive layer forms the source region, the annular oxide semiconductor layer forms the junction-less channel region, the annular ferroelectric dielectric layer forms the gate dielectric layer, and the columnar gate conductor layer forms the gate electrode of the ferroelectric field-effect transistor.

[0010] The above and other advantages, aspects and novel features of the present invention, as well as details of the exemplary embodiments thereof, will be better understood by referring to the following description and accompanying drawings. [Brief explanation of the drawing]

[0011] Various embodiments of the present invention are disclosed in the following detailed description and accompanying drawings. While the drawings depict various embodiments of the present invention, the present invention is not limited to the embodiments depicted. It should be understood that in the drawings, similar reference numerals indicate similar structural elements. Furthermore, it should be understood that the depictions in the drawings are not necessarily drawn to a fixed scale.

[0012] [Figure 1A]Figure 1A is a perspective view of a memory structure comprising a three-dimensional array of NOR-type memory strings of channel-all-around ferroelectric memory transistors according to an embodiment of the present disclosure. [Figure 1B] Figure 1B is a perspective view of a memory structure comprising a three-dimensional array of NOR-type memory strings of channel-all-around ferroelectric memory transistors according to an embodiment of the present disclosure. [Figure 1C] Figure 1C is a perspective view of a memory structure comprising a three-dimensional array of NOR-type memory strings of channel-all-around ferroelectric memory transistors according to an embodiment of the present disclosure. [Figure 1D] Figure 1D is a cross-sectional view showing each component of the memory structure shown in Figure 1A, and illustrates ferroelectric memory transistors in several embodiments. [Figure 1E] Figure 1E is a cross-sectional view showing each component of the memory structure shown in Figure 1C, and illustrates ferroelectric memory transistors in several embodiments. [Figure 2] Figure 2 is a transistor-level schematic diagram of a memory device including a three-dimensional array of NOR-type memory strings in an embodiment of the present disclosure. [Figure 3A] Figure 3A includes cross-sectional views of the memory structure of Figure 1A in two different planes, according to an embodiment of the present disclosure. [Figure 3B] Figure 3B includes cross-sectional views of the memory structure of Figure 1C in two different planes, according to an embodiment of the present disclosure. [Figure 4A] Figure 4A is an enlarged perspective view of the memory structure shown in Figures 1A to 1C in an embodiment of the present disclosure. [Figure 4B] Figure 4B is an enlarged perspective view of the memory structure shown in Figures 1A to 1C in an embodiment of the present disclosure. [Figure 5] Figure 5 is a top view of a memory structure including a precharge transistor and a stepped structure according to an embodiment of the present disclosure. [Figure 6]FIG. 6 is a cross-sectional view of the memory structure of FIG. 5 including a precharge transistor and a stepped structure in an embodiment of the present disclosure. [Figure 7] FIG. 7 is an enlarged cross-sectional view of a memory stack including a local word line structure in an embodiment of the present disclosure. [Figure 8] FIG. 8 is an enlarged cross-sectional view of a memory stack including a local word line structure in another embodiment of the present disclosure. [Figure 9A] FIG. 9A is an enlarged cross-sectional view of a memory stack including a local word line structure in another embodiment of the present disclosure. [Figure 9B] FIG. 9B is an enlarged cross-sectional view of a memory stack including a local word line structure in another embodiment of the present disclosure. [Figure 10] FIG. 10 is a top view of a memory structure including a stepped structure connected to a common bit line and a common source line in an embodiment of the present disclosure. [Figure 11] FIG. 11 is a cross-sectional view of the memory structure of FIG. 10 including a stepped structure connected to a common bit line and a common source line in an embodiment of the present disclosure. [Figure 12] FIG. 12 is a flowchart showing a manufacturing process for manufacturing a memory structure including a channel all-around type ferroelectric memory transistor in an embodiment of the present disclosure. [Figure 13A] FIG. 13A shows a memory structure in an intermediate process of the manufacturing method of FIG. 12 in some embodiments. [Figure 13B] FIG. 13B shows a memory structure in an intermediate process of the manufacturing method of FIG. 12 in some embodiments. [Figure 13C] FIG. 13C shows a memory structure in an intermediate process of the manufacturing method of FIG. 12 in some embodiments. [Figure 13D] FIG. 13D shows a memory structure in an intermediate process of the manufacturing method of FIG. 12 in some embodiments. [Figure 13E]Figure 13E shows memory structures in intermediate processes of the manufacturing method shown in Figure 12 in several embodiments. [Figure 13F] Figure 13F shows memory structures in intermediate processes of the manufacturing method shown in Figure 12 in several embodiments. [Figure 13G] Figure 13G shows memory structures in intermediate processes of the manufacturing method shown in Figure 12 in several embodiments. [Figure 13H] Figure 13H shows a memory structure in an intermediate process of the manufacturing method shown in Figure 12, in several embodiments. [Figure 13I] Figure 13I shows memory structures in intermediate processes of the manufacturing method shown in Figure 12 in several embodiments. [Figure 13J] Figure 13J shows memory structures in intermediate processes of the manufacturing method shown in Figure 12 in several embodiments. [Figure 13J1] Figure 13J1 shows memory structures in intermediate processes of the manufacturing method shown in Figure 12 in several embodiments. [Figure 13K] Figure 13K shows memory structures in intermediate processes of the manufacturing method shown in Figure 12 in several embodiments. [Figure 13L] Figure 13L shows a memory structure in an intermediate process of the manufacturing method shown in Figure 12, in several embodiments. [Figure 13M] Figure 13M shows a memory structure in an intermediate process of the manufacturing method shown in Figure 12, in several embodiments. [Figure 13N] Figure 13N shows a memory structure in an intermediate process of the manufacturing method shown in Figure 12, in several embodiments. [Figure 14] Figure 14 is a cross-sectional view of a memory structure of a channel-all-around ferroelectric memory transistor in another embodiment of the present disclosure. [Figure 15] Figure 15 is a top view of a memory structure in another embodiment of the present disclosure, which includes a stepped structure connected to a common bit line and a common source line. [Figure 16]Figure 16 is a cross-sectional view of the memory structure of Figure 15, which includes a stepped structure connected to a common bit line and a common source line, according to an embodiment of the present disclosure. [Figure 17A] Figure 17A is a top view of a memory structure including a single layer of global word lines in several embodiments. [Figure 17B] Figure 17B is a cross-sectional view of a memory structure including a single layer of global word lines in several embodiments. [Figure 18A] Figure 18A is a top view of a memory structure including two layers of global word lines in several embodiments. [Figure 18B] Figure 18B is a cross-sectional view of a memory structure including two layers of global word lines in several embodiments. [Figure 19A] Figure 19A is a top view of a memory structure in which an upper conductive layer (upper global word line) and a bottom conductive layer (bottom global word line) of the global word line are included in several embodiments. [Figure 19B] Figure 19B is a cross-sectional view of a memory structure in several embodiments, including an upper conductive layer (upper global word line) and a bottom conductive layer (bottom global word line) for the global word line. [Figure 19C] Figure 19C is an enlarged cross-sectional view of a memory structure in which the upper conductive layer (upper global word line) and the bottom conductive layer (bottom global word line) of the global word line are included in several embodiments. [Figure 19D] Figure 19D is a cross-sectional view of the memory structure shown in Figures 19A to 19C, illustrating the manufacturing process for forming the upper and lower conductive layers of the global word line in several embodiments. [Figure 19E] Figure 19E is a cross-sectional view of the memory structure shown in Figures 19A to 19C, illustrating the manufacturing process for forming the upper and lower conductive layers of the global word line in several embodiments. [Figure 19F]Figure 19F is a cross-sectional view of the memory structure shown in Figures 19A to 19C, illustrating the manufacturing process for forming the upper and lower conductive layers of the global word line in several embodiments. [Figure 19G] Figure 19G is a cross-sectional view of the memory structure shown in Figures 19A to 19C, illustrating the manufacturing process for forming the upper and lower conductive layers of the global word line in several embodiments. [Figure 19H] Figure 19H is a cross-sectional view of the memory structure shown in Figures 19A to 19C, illustrating the manufacturing process for forming the upper and lower conductive layers of the global word line in several embodiments. [Figure 19I] Figure 19I is a cross-sectional view of the memory structure shown in Figures 19A to 19C, illustrating the manufacturing process for forming the upper and lower conductive layers of the global word line in several embodiments. [Figure 19J] Figure 19J is a cross-sectional view of the memory structure shown in Figures 19A to 19C, illustrating the manufacturing process for forming the upper and lower conductive layers of the global word line in several embodiments. [Figure 19K] Figure 19K is a cross-sectional view of the memory structure shown in Figures 19A to 19C, illustrating the manufacturing process for forming the upper and lower conductive layers of the global word line in several embodiments. [Figure 20] Figures 20(a) and 20(b) illustrate a method for patterning hole openings in a hard masking layer using single-mask, single-exposure photolithography in several embodiments. [Figure 21] Figures 21(a) and 21(b) illustrate a method for patterning hole openings in a hard masking layer using two-mask two-exposure photolithography in several embodiments. [Figure 22]Figure 22 shows the application of the memory device of this disclosure as an embedded memory device in several embodiments. [Figure 23] Figure 23 shows a detailed structure of a memory transistor formed within a memory structure in another embodiment of the present disclosure. [Modes for carrying out the invention]

[0013] In embodiments of the present invention, the memory structure comprises randomly accessible channel-all-around ferroelectric memory transistors configured as a horizontal NOR-type three-dimensional array. The NOR-type memory strings are formed on a semiconductor substrate within a plurality of scalable memory stacks of thin-film memory transistors. This three-dimensional memory stack is manufactured by a manufacturing method comprising the steps of forming a plurality of holes in a multilayer stack for fabricating local word line structures, and forming slit trenches in the multilayer stack for dividing the multilayer stack into a plurality of memory stacks containing local word line structures. The memory structure with channel-all-around ferroelectric memory transistors enables a scalable configuration for realizing high-density and high-capacity memory devices.

[0014] In some embodiments, the ferroelectric memory transistor is a thin-film ferroelectric field-effect transistor (FeFET) having a ferroelectric polarization layer as the gate dielectric layer. The ferroelectric polarization layer, also called the “ferroelectric gate dielectric layer” or “ferroelectric dielectric layer,” is formed adjacent to the oxide semiconductor layer as the channel region. The ferroelectric memory transistor includes a source region and a drain region. Both the source and drain regions are formed from a metallic conductive material and are in electrical contact with the oxide semiconductor channel region. Each ferroelectric memory transistor thus formed is a junction-less transistor that does not have a p / n junction in the channel, and the threshold voltage is modulated by the polarization of mobile carriers in the ferroelectric polarization layer. In the memory structure of the present invention, the ferroelectric memory transistors in each NOR-type memory string are controlled by individual controlled gate electrodes to enable individual addressing and access of each memory transistor. In some embodiments, the ferroelectric polarization layer is formed from a doped hafnium oxide material, and the oxide semiconductor channel region is formed from an amorphous metallic oxide semiconductor material.

[0015] In this specification, the term “storage transistor” is used interchangeably with the term “memory transistor” to refer to a memory device formed within the memory structure described herein. In some embodiments, the memory structure of this disclosure, comprising a NOR memory string of randomly accessible memory transistors (or storage transistors), can have applications in a computer system as main memory where data storage locations are directly accessible by the computer system's processor, in the role previously played by conventional random access memories (RAM), such as dynamic RAM (DRAMS) and static RAM (SRAM). For example, the memory structure of this disclosure can be applied to a computer system to function as random access memory to support the operation of microprocessors, graphical processors, and artificial intelligence processors. In other examples, the memory structure of this disclosure can also be applied to form a storage system, such as a solid-state drive, or to replace a hard drive, to provide long-term data storage to a computer system.

[0016] As used herein, the term “oxide semiconductor layer” (also referred to as “semiconductor oxide layer” or “metal oxide semiconductor layer”) refers to a thin-film semiconductor material made from a conductive metal oxide such as zinc oxide or indium oxide, or any suitable conductive metal oxide having a charge carrier with electron mobility that can be modified or regulated by appropriate preparation or inclusion of appropriate impurities.

[0017] In this description, for the sake of facilitating reference to the drawings, a Cartesian coordinate system is used, as shown in the figures, in which the Z direction is perpendicular to the plane of the semiconductor surface and the X and Y directions are perpendicular to the Z direction. Furthermore, the drawings provided herein are idealized depictions for illustrating embodiments of the disclosure and are not intended to be actual depictions of any particular component, structure, or apparatus. The drawings are not drawn to a constant scale, and some layer thicknesses and dimensions may be exaggerated for clarity. Deformations from the illustrated shapes are also expected. For example, areas shown as box shapes may generally have rough and / or nonlinear features. Illustrated acute angles may be rounded. Similar reference numerals refer to similar components throughout.

[0018] Figures 1A, 1B, and 1C are perspective views of a memory structure 10 comprising a three-dimensional array of NOR-type memory strings of channel-all-around ferroelectric memory transistors in embodiments of the present disclosure. Figures 1D and 1E are cross-sectional views showing the components of the memory structure 10 in Figures 1A and 1C, illustrating ferroelectric memory transistors in several embodiments. In the memory structure 10 of Figure 1B, the dielectric layers (channel spacer dielectric layer and interlayer insulating layer) are omitted from the illustration to simplify the explanation of the components of the ferroelectric memory transistor in the three-dimensional structure.

[0019] Referring to Figures 1A and 1B, the memory structure 10 of the present disclosure includes a memory stack 17 formed on a semiconductor layer 12 (also referred to as a semiconductor substrate), and each memory stack 17 includes a plurality of NOR-type memory strings stacked vertically on top of each other. An insulating layer 14 may be provided between the semiconductor substrate 12 and the memory stack 17. Each memory stack 17 is isolated from adjacent memory stacks in the X direction by trenches 19, also referred to herein as "slit trenches." The slit trenches 19 are narrow trenches whose width in the X direction is much smaller than the width of the memory stack 17. In some embodiments, the NOR-type memory strings of the memory stack 17 are formed by a group of thin films sequentially deposited on the plane of the semiconductor substrate 12, each group of thin films referred to herein as an active layer 16. The active layers 16 of the NOR-type memory strings of each memory stack 17 are stacked on top of each other, and each active layer 16 is isolated from adjacent active layers by an interlayer insulating layer 15. The interlayer insulating layer 15 is implemented as a dielectric layer or air gap insulating layer. In some embodiments, the interlayer insulating layer 15 is an oxygen-containing dielectric layer. Each active layer 16 includes a common drain line 22 (or bit line) and a common source line 24 (or source line) that are spaced apart from each other vertically (Z direction) by a channel isolation layer 23. The common drain line 22 and common source line 24 within each active layer 16 extend horizontally (Y direction) to form a NOR-type memory string of memory transistors. The memory transistors within each NOR-type memory string share the bit line 22 (common drain line) and the source line 24 (common source line).

[0020] In embodiments of this disclosure, a columnar local word line structure 13 is formed within each memory stack 17. The columnar local word line structure 13 extends through the memory stack 17 in the Z direction. Each local word line structure 13 configured in this way is surrounded by bit lines 22 and source lines 24. Each columnar local word line structure 13 includes concentric layers of a channel layer 26, a ferroelectric gate dielectric layer 27, and a gate conductor layer 28, formed sequentially from its outer periphery toward the center. In some embodiments, an interface layer 25 is optionally formed as a concentric layer between the channel layer 26 and the ferroelectric gate dielectric layer 27. In this embodiment, the channel layer 26 is an oxide semiconductor layer.

[0021] In embodiments of this disclosure, the annular channel layer 26 of the columnar local word line structure 13 is separated from each other between adjacent active layers 16. That is, the channel layer 26 is provided in each active layer 16 in a region that overlaps with the bit line 22 and source line 24 of each active layer 16, and in contact with the bit line 22 and source line 24. The channel layer 26 is not present in the region of the interlayer insulating layer 15, or at least partially removed, thereby separating the channel layer 26 from each other between adjacent active layers 16. If an interface layer 25 is provided as shown in Figures 1A and 1B, the exposed layer of the local word line structure 13 in the region of the interlayer insulating layer 15 can be the interface layer 25. Alternatively, if the local word line structure 13 does not have an interface layer 25, or if the interface layer 25 is completely or partially removed during the channel layer removal process, the exposed layer of the local word line structure 13 in the region of the interlayer insulating layer 15 becomes the ferroelectric gate dielectric layer 27. The presence or absence of the interface layer 25 in the region of the interlayer insulating layer 15 is not important for the implementation of the present invention. In another embodiment, the ferroelectric gate dielectric layer 27 is also removed at least partially between adjacent active layers 16. By removing the ferroelectric gate dielectric layer 27 at least partially in the region of the interlayer insulating layer 15, it is possible to restrict the lateral movement of polarization regions between memory transistors on adjacent planes within the memory stack 17, or to restrict the movement of oxygen atoms between adjacent active layers 16.

[0022] The channel layer 26 of the memory transistor configured in this way is an annular layer formed on the outer periphery of the columnar local word line structure 13, thereby realizing a channel-all-around type transistor structure. The bit line 22 (common drain line) and source line 24 (common source line) are provided to surround the annular channel layer 26 and to be in contact with the annular channel layer 26. The annular channel layer 26 is formed adjacent to the ferroelectric gate dielectric layer 27, which is formed as an annular layer. The inner central part of the columnar local word line structure 13 is the gate conductor layer 28. If an interface layer 25 is provided, the interface layer 25 is provided as an annular layer between the annular channel layer 26 and the annular ferroelectric gate dielectric layer 27. In this way, a ferroelectric memory transistor is formed at the intersection of the active layer 16 and the local word line structure 13. Therefore, in each memory stack 17, the memory transistor is formed perpendicular to a plurality of mutually parallel planes of the memory stack. In each active layer 16 of the memory stack 17, memory transistors 20 are formed at each intersection of the common source line 24 and common drain line 22 with the local word line structure 13, thereby forming a memory string. As described above, the term "perpendicular" refers to a direction perpendicular to the surface of the semiconductor substrate, and the term "horizontal" refers to any direction parallel to the surface of the semiconductor substrate.

[0023] Figure 1D shows a detailed structure of a memory transistor 20 formed on the memory structure 10 shown in Figures 1A and 1B in several embodiments. Specifically, Figure 1D shows a pair of memory transistors 20-1 and 20-2 on two adjacent faces of the memory stack 17. Referring to Figure 1D, the memory transistor 20 includes a first conductive layer 22 forming a bit line (or common drain line) and a second conductive layer 24 forming a source line (or common source line), the first conductive layer 22 and the second conductive layer 24 being separated from each other by a channel spacer dielectric layer 23. The memory transistor 20 further includes an annular channel layer 26 formed perpendicularly along the sidewall of the columnar local word line structure 13 and in contact with both the first conductive layer 22 and the second conductive layer 24. An annular ferroelectric gate dielectric layer 27 and a gate conductor layer 28 are formed adjacent to the annular channel layer 26. Specifically, a portion of the annular channel layer 26 is provided between the bit line 22 and the annular ferroelectric gate dielectric layer 27 in the XY plane. Another portion of the annular channel layer 26 is provided between the source line 24 and the annular ferroelectric gate dielectric layer 27 in the XY plane. In this embodiment, an annular interface layer 25 is provided between the channel layer 26 and the ferroelectric gate dielectric layer 27. The memory transistor 20 is insulated from adjacent memory transistors in the memory stack by an interlayer insulating layer 15. The memory transistors configured in this way, sharing a common source line and a common bit line, form a NOR-type memory string (also referred to herein as a "horizontal NOR-type memory string" or "HNOR-type memory string") along each active strip (in the Y direction).

[0024] In the embodiments shown in Figures 1A, 1B, and 1D, the interlayer insulating layer 15 is implemented as air gap insulation. For example, air gap insulation is achieved by forming an air gap liner layer 15b on the exposed surface of the interlayer insulating region (the region of the interlayer insulating layer 15) between the active layers 16, and forming air gap insulation without filling the remaining cavity 15a of the interlayer insulating region. The air gap liner layer 15b may be a silicon oxide layer, a silicon nitride layer, or another suitable dielectric layer. Furthermore, in the embodiment shown in Figure 1A, air gap insulation is also formed within the slit trenches 19 between adjacent memory stacks 17. In the embodiment shown in Figure 1A, the air gap insulation between adjacent memory stacks 17 includes a dielectric liner layer 36 that lines the sidewalls of the slit trenches 19 and caps the openings of the air gap insulating layer 15. The air gap insulation is then formed by non-conformally depositing the dielectric layer 38 to form a cap at the upper end of the slit trenches 19 and sealing the cavity of the slit trenches 19. In some embodiments, the dielectric layer 38 is a non-conformally deposited silicon dioxide (SiO2) layer.

[0025] In another embodiment, the memory structure of the present disclosure may be constructed using a dielectric-filled isolation layer instead of air gap insulation. Figure 1C shows a memory structure 10a constructed in a similar manner to the memory structure 10 of Figure 1A, but using a dielectric-filled isolation layer instead of air gap insulation. Referring to Figure 1C, the interlayer insulating layer 15 of the memory structure 10a is formed as a dielectric layer. In some embodiments, the interlayer insulating layer 15 is an oxygen-containing dielectric layer. In one example, the interlayer insulating layer 15 is a silicon dioxide layer. Figure 1E shows a detailed structure of a memory transistor 20 formed on the memory structure 10a of Figure 1C in some embodiments. The memory transistor 20 of Figure 1E is constructed similarly to the memory transistor 20 of Figure 1D, except that the interlayer insulating layer 15 is formed as a dielectric layer or a dielectric-filled layer.

[0026] Furthermore, in the embodiment shown in Figure 1C, the memory structure 10a has a slit trench 19 filled with a dielectric layer 39 to provide isolation between adjacent memory stacks 17. In another embodiment, the memory structure 10a can be formed using a dielectric packing layer 15 for the interlayer insulating layer and air gap insulation for the slit trench 19. More specifically, the memory structure of the present disclosure is realized by selectively using insulating elements or insulating materials between active layers and active stacks, thereby achieving desired insulation between memory transistors.

[0027] In the embodiments shown in Figures 1D and 1E, the interlayer insulating layer 15 extends to the ferroelectric gate dielectric layer 27. As described above, the exposed layer of the local word line structure 13 in the region of the interlayer insulating layer 15 can be the interface layer 25. In other embodiments, the exposed layer of the local word line structure 13 in the region of the interlayer insulating layer 15 can be the ferroelectric gate dielectric layer 27. If the interface layer 25 is provided, the interface layer 25 is completely or partially removed in the region of the interlayer insulating layer 15.

[0028] In this embodiment, the memory transistor in the NOR-type memory string is a ferroelectric field-effect transistor that includes a ferroelectric thin film as the gate dielectric layer (also referred to as the ferroelectric polarization layer, ferroelectric gate dielectric layer, or ferroelectric dielectric layer). In a ferroelectric field-effect transistor (FeFET), the polarization direction of the ferroelectric gate dielectric layer is controlled by an electric field applied between the transistor's drain terminal (bit line 22) and the transistor's gate electrode (gate conductor layer 28), and the threshold voltage of the FeFET can be changed by changing the polarization direction. In some embodiments, the electric field is applied to both the transistor's drain and source terminals relative to the transistor's gate electrode. For example, the FeFET can be written / erased to have one of two threshold voltages, and each threshold voltage of the FeFET can be used to encode a given logic state. For example, the two threshold voltages of the FeFET can be used to encode a "written" state and an "erased" state, each representing a specified logic value. In one example, the written state is associated with a lower threshold voltage, and the erased state is associated with a higher threshold voltage. In some embodiments, three or more threshold voltages may be used to represent three or more memory states in each FeFET.

[0029] Referring again to Figures 1A and 1B, in embodiments of this disclosure, each memory stack 17 includes local word line structures 13 arranged as a two-dimensional array in the XY plane. Specifically, the local word line structures 13 are arranged in two rows in the X direction and alternately in the Y direction. Memory transistors 20 are formed at each intersection of the bit lines 22 and source lines 24 and the local word line structures 13. With this configuration, in each active layer 16 of the memory stack 17, the bit lines 22 and source lines 24 intersect with a plurality of local word line structures 13 in the memory stack 17, thereby forming a NOR-type memory string of ferroelectric memory transistors 20. The local word line structures 13 intersect with the active layer 16 in a plurality of planes of the memory structure 10, thereby forming a NOR-type memory string in a plurality of planes of the memory structure 10. With this configuration, a three-dimensional array of NOR-type memory strings is formed, thereby realizing a high-density and high-capacity memory structure. Each local word line structure 13 within each memory stack 17 is connected to each global word line 30 extending in the X direction. Thus, each memory transistor 20 within a NOR-type memory string is connected to a different global word line 30. During operation, one local word line structure 13 within the memory string can be selected by activating one global word line 30, and one memory transistor can be accessed from multiple active layers 16 within the memory stack 17 by selecting one bit line 22.

[0030] In the examples shown in Figures 1A and 1B, the memory structure 10 includes two memory stacks, memory stack 0 and memory stack 1, separated from each other by a slit trench 19. In the example shown in Figure 1B, the memory stack includes two active layers: active layer 0 having bit line BL0 and source line SL0, and active layer 1 having bit line BL1 and source line SL1. Active layer 0 and active layer 1 are separated from each other by an interlayer insulating layer 15. In the example shown in Figure 1B, each memory stack is provided with four local word line structures. Memory stack 0 is provided with four local word line structures LWL0-0, LWL1-0, LWL2-0, and LWL3-0. Memory stack 1 is provided with four local word line structures LWL0-1, LWL1-1, LWL2-1, and LWL3-1. In each memory stack, each local word line structure is connected to its corresponding global word line. In other words, the local word line structures LWL0-x, LWL1-x, LWL2-x, and LWL3-x are connected to different global word lines, and by activating one global word line, only one local word line structure corresponding to that global word line can be selected. In this embodiment, four global word lines GWL0, GWL1, GWL2, and GWL3 are provided, extending in the X direction. Global word line GWL0 is connected to local word line structures LWL0-0 and LWL0-1. Global word line GWL1 is connected to local word line structures LWL1-0 and LWL1-1. Global word line GWL2 is connected to local word line structures LWL2-0 and LWL2-1. Global word line GWL3 is connected to local word line structures LWL3-0 and LWL3-1. With this configuration, an activated global word line can select only one local word line structure within each memory stack.In this embodiment, in order to facilitate the connection between each local word line structure and each global word line, the array of columnar local word line structures in each memory stack is arranged alternately (staggered) in the Y direction, so that each global word line is connected to only one local word line structure in each memory stack.

[0031] In Figure 1B, via 29 is shown to connect a local word line structure to its corresponding global word line, with the darkly painted cap portion indicating the connection point between the local word line structure and the global word line. Note that via 29 is merely an example and is not intended to represent an actual component of the memory structure 10. In some embodiments, the global word line 30 is formed using a damascene process, and the global word line material is in contact with the gate conductor layer exposed on top of the local word line structure.

[0032] In embodiments of this disclosure, the memory transistors 20 within the memory structure 10 are junction-less ferroelectric memory transistors. Therefore, each memory transistor 20 includes only conductive layers as source and drain regions, and does not include semiconductor layers. The bit-line conductive layer (first conductive layer) and the source-line conductive layer (second conductive layer) are formed using a low-resistivity metallic conductive material. In some embodiments, the bit-line conductive layer and the source-line conductive layer are metallic layers such as a tungsten (W) layer lined with titanium nitride (TiN), a tungsten (W) layer lined with tungsten nitride (WN), a molybdenum (Mo) layer lined with molybdenum nitride (MoN), a linerless tungsten layer, a linerless molybdenum layer, a linerless cobalt layer, or other metallic layers. The channel spacer insulating layer 23 (also referred to as the channel spacer dielectric layer) between the first conductive layer and the second conductive layer may be a dielectric layer such as silicon oxide (SiO2). The channel layer 26 is an oxide semiconductor layer. In some embodiments, the channel layer 26 is formed using amorphous oxide semiconductor materials such as indium gallium zinc oxide (InGaZnO or IGZO), indium zinc oxide (IZO), indium tungsten oxide (IWO), or indium tin oxide (ITO), or other suitable oxide semiconductor materials. Oxide semiconductor channel regions (channel layers formed using oxide semiconductor materials) have the advantage of high electron mobility, and therefore offer high switching performance and are free from concerns about electron and hole tunneling. For example, indium gallium zinc oxide (IGZO) films have a thickness of 10.0 to 100.0 cm, depending on the relative composition of indium, gallium, zinc, and oxygen. 2 It has an electron mobility of / V.

[0033] To form a ferroelectric memory transistor, the memory transistor 20 includes a ferroelectric polarization layer 27 in contact with the channel layer 26. The ferroelectric polarization layer 27 (also referred to as the ferroelectric dielectric layer) functions as the storage layer of the memory transistor. In some embodiments, an interface layer 25 is provided between the channel layer 26, which is an oxide semiconductor layer, and the ferroelectric polarization layer 27. The interface layer 25 is a thin layer, and may have a thickness of 0.5 nm to 2 nm. In some embodiments, the interface layer 25 is formed using a high dielectric constant material (also referred to as a "high-K" material) having a high dielectric constant (K). In some embodiments, the interface layer 25 may be a silicon nitride (Si3N4) layer, a silicon oxynitride layer, or an aluminum oxide (Al2O3) layer. In one example, if the interface layer 25 is provided and the ferroelectric polarization layer 27 has a thickness of 4 to 5 nm, the interface layer 25 may have a thickness of 1.5 nm. The inclusion of the interface layer 25 in Figures 1A to 1E is illustrative and not intended to limit the scope. The interface layer 25 is optional and may be omitted in other embodiments of this disclosure. In other embodiments, if the interface layer 25 is provided, it may be formed as a multilayer of multiple different dielectric materials. In this specification, a high dielectric constant material or high K material refers to a material having a dielectric constant higher than that of silicon dioxide or a dielectric constant of 3.9.

[0034] In some embodiments, the ferroelectric polarization layer 27 is formed from a doped hafnium oxide material such as zirconium-doped hafnium oxide (HfZrO or "HZO"). In other embodiments, the hafnium oxide may be doped with silicon (Si), iridium (Ir), or lanthanum (La). In some embodiments, the ferroelectric polarization layer 27 is a material selected from zirconium-doped hafnium oxide (HZO), silicon-doped hafnium oxide (HSO), aluminum zirconium-doped hafnium oxide (HfZrAlO), aluminum-doped hafnium oxide (HfO2:Al), lanthanum-doped hafnium oxide (HfO2:La), hafnium-zirconium oxynitride (HfZrON), hafnium-zirconium aluminum oxide (HfZrAlO), and any hafnium oxide containing zirconium impurities.

[0035] The ferroelectric polarization layer 27 is an annular layer, with its outer circumference in contact with the channel layer 26 and its inner circumference in contact with the gate conductor layer 28. In some embodiments, the gate conductor layer 28 includes a conductive liner layer 28a and a low-resistance conductor layer 28b. The conductive liner layer 28a is provided as an adhesive layer to the gate conductor layer 28. In some embodiments, the conductive liner layer 28a is a titanium nitride (TiN) layer, a tungsten nitride (WN) layer, or a molybdenum nitride (MoN) layer, and the low-resistance conductor layer 28b is formed using tungsten, molybdenum, or other metals. In some embodiments, the conductive liner layer 28a is unnecessary, and the gate conductor layer 28 includes only a linerless low-resistance conductor layer 28b, such as a tungsten or molybdenum layer. In other embodiments, the low-resistance conductor layer 28b is a highly doped n-type or p-type polysilicon and can be used with or without a conductive liner. The gate conductor layer 28 forms the control gate electrode of the memory transistor and functions as the local word line in the memory structure 10. In some embodiments, the gate conductor layer 28 is a highly doped N+ polysilicon layer or a highly doped P+ polysilicon layer, where the highly doped polysilicon layer affects the work function of the global word line and therefore also shifts the threshold voltage of the ferroelectric memory transistor.

[0036] In this configuration, the oxide semiconductor channel layer 26 (a channel layer formed using an oxide semiconductor material) forms an N-type unipolar channel region in which the bit line conductive layer 22 and the source line conductive layer 24, which form the drain terminal and source terminal, are in direct contact with the channel region. The ferroelectric memory transistor formed in this way is normally in an ON state (i.e., a conducting state) and is a depletion-mode device that can be turned OFF (i.e., a non-conducting state) by depleting the N-type carriers in the channel region. The threshold voltage of the ferroelectric memory transistor is a function of the thickness of the annular oxide semiconductor channel layer 26 in the XY plane. That is, the threshold voltage of the ferroelectric memory transistor is the voltage required to deplete the carriers within the thickness of the oxide semiconductor channel region and shut off the ferroelectric memory transistor. In embodiments of this disclosure, the ferroelectric memory transistor has a channel length in the Z direction defined by the channel spacer insulating layer 23 between the bit line 22 and the source line 24. Furthermore, in embodiments of this disclosure, the ferroelectric memory transistor has a channel width defined by the outer circumference length of the annular channel layer 26.

[0037] In embodiments of the present disclosure, a three-dimensional array of NOR-type memory strings of the ferroelectric memory transistors of the present disclosure can be applied to realize a non-volatile memory device or a quasi-volatile memory device. For example, a quasi-volatile memory may have an average retention time of more than 100 ms, such as about 10 minutes or several hours, while a non-volatile memory device may have a minimum data retention time of several days or several years. In the case of quasi-volatile memory, the ferroelectric memory transistors 20 need to be refreshed from time to time to restore a predetermined written or erased polarization state. For example, the ferroelectric memory transistors 20 in the memory structure 10 are refreshed every few minutes or several hours. Specifically, the ferroelectric memory transistors of the present disclosure can realize a quasi-non-volatile memory device with a refresh interval of approximately several hours to several days. This refresh interval of the ferroelectric memory transistors of the present disclosure is significantly longer than the refresh interval of DRAM, which requires very frequent refreshes of tens of milliseconds or so.

[0038] A notable feature of the ferroelectric memory transistor 20 of this disclosure is that the memory transistor has a very short channel length, which increases voltage isolation between different threshold voltages and enables a large memory window. This also makes it possible to fabricate the memory structure 10 without requiring expensive lithography techniques to achieve the short channel length. Specifically, the channel length of the ferroelectric memory transistor 20 is determined by the thickness L1 of the channel spacer dielectric layer 23 (Figures 1B, 1D, and 1E). The thickness L1 can be precisely controlled during the deposition of sublayers 22, 23, and 24 that form the initial memory stack. Because the thickness L1 can be controlled by the deposition process and the channel leakage of the oxide semiconductor channel layer is very low, it is possible to fabricate a ferroelectric memory transistor 20 with a very short channel length, such as a 5 nm channel length, without using expensive lithography techniques such as extreme ultraviolet scanners (EUV) used to pattern short channels in planar transistors. In some embodiments, the thickness L1, i.e., the channel length of the memory transistor, may be in the range of 5 nm to 20 nm, or 5 nm to 7 nm.

[0039] Another advantage of the very short channel achieved in the memory transistors of this disclosure is that, during memory write or erase operations, the fringing electric fields at the source-channel intersection and the drain-channel intersection overlap, thereby enabling high-speed write or erase along the entire channel, corresponding to the polarized or depolarized ferroelectric dielectric layer, and resulting in a wide memory operating window. More specifically, the short channel length causes the ferroelectric memory transistor to operate such that the applied voltage and fringing field result in polarization of the ferroelectric gate dielectric layer throughout the entire channel. Alternatively, a wide memory operating window can be utilized to reduce stress on the oxide semiconductor layer of the ferroelectric memory transistor, or by performing write and erase operations with only partial depolarization. In this specification, partial polarization refers to biasing the ferroelectric memory transistor to a polarization level in the ferroelectric dielectric layer between the positive and negative polarization states associated with the erase and write states of the ferroelectric memory transistor. In this specification, the term “polarization state” is used to refer to the polarization direction of an electric dipole in a ferroelectric dielectric layer, which refers to a positive or negative polarization state associated with the erase or write state of a ferroelectric memory transistor. Furthermore, in this specification, the term “polarization level” refers to different polarization levels associated with different threshold voltage values ​​induced by polarization, which are achieved in the ferroelectric dielectric layer. In embodiments of this disclosure, a ferroelectric memory transistor can be operated with a bias voltage that induces only partial polarization in order to obtain a threshold voltage value that is within the full memory window capability range of the ferroelectric memory transistor. In other embodiments, a wide memory window of the memory transistor allows for the use of low-voltage operation for write and erase operations, thereby reducing stress on the ferroelectric memory transistor and increasing its durability.

[0040] Another notable feature of the ferroelectric memory transistor 20 is that the memory transistor has a large channel width, which allows for an increase in the transistor's "on" current without increasing the die size of the memory structure. The channel layer of the memory transistor is formed as an annular layer on the outer periphery of the columnar local word line structure. This annular channel layer provides a channel width approximately four times larger than that of a sidewall channel layer of the same dimensions in a memory transistor with similar planar dimensions. The ability to increase the memory transistor's "on" current is beneficial in compensating for the increase in bit line capacitance that may result from an increase in channel width.

[0041] In embodiments of the present disclosure, the memory structure includes a memory array portion constructed as described above to form a three-dimensional array of NOR-type memory strings. To complete the memory device, the memory structure includes stepped portions provided at the ends (ends in the Y direction) of the memory strings. Thin-film memory transistors of the NOR-type memory strings are formed within the memory array portion, and the stepped portions on both sides of the array portion include stepped structures that provide connections via conductive vias to the common bit line and optionally a common source line of the NOR-type memory strings. In some embodiments, the common source line is pre-charged to function as a virtual voltage reference source during write, read, and erase operations, thereby eliminating the need for continuous electrical connections to support circuits during such operations. Herein, the common source line is described as electrically floating, meaning there is no continuous electrical connection to the common source line. In embodiments of the present disclosure, various processing steps can be used to form the stepped structure within the memory structure. The processing steps for forming the stepped structure can be performed before, after, or between the processing steps for forming the memory array portion.

[0042] Figures 1A to 1C show the memory structure 10 (memory structure 10a) configuration of a memory array including a three-dimensional array of NOR-type memory strings. In Figures 1A and 1C, the memory structure 10 (memory structure 10a) is shown to include two memory stacks, eight active layers, and five local word line structures. In Figure 1B, for the sake of simplicity, the memory structure 10 is shown to include two memory stacks, two active layers, and four local word line structures. Figures 1A to 1C are illustrative and not intended to be limiting. In actual implementations, the memory structure may include eight, sixteen, twenty, or more active layers, 1,000 to 2,000 memory stacks, and 2,000 to 4,000 local word line structures. For example, the memory structure 10 (memory structure 10a) may include a number of active layers, memory stacks, and local word line structures suitable for forming a modular memory unit with 64 million memory transistors (equivalent to a data capacity of 64 Mb). The memory structure 10 can be used as a building block for fabricating high-capacity and high-density memory devices. In embodiments of this disclosure, the memory structure 10 represents modular memory units called “tiles,” and the memory device is formed using an array of modular memory units. In exemplary embodiments, the memory device is configured as a two-dimensional array of tiles arranged along the X and Y directions, and each tile includes a three-dimensional array of ferroelectric memory transistors having support circuits formed beneath each tile. More specifically, the memory device includes multiple memory arrays of thin-film ferroelectric memory transistors configured as a two-dimensional array of “tiles” formed on a planar semiconductor substrate (i.e., the tiles are arranged in a matrix). Each tile may be configured to be addressed individually and independently, or it may form a larger memory segment (e.g., a row of tiles or a two-dimensional block of tiles) and be configured to be addressed on a per-memory segment basis. In some embodiments, each row of tiles ("row of tiles") is configured to form an operating unit called a “bank.”A group of banks then forms a "bank group." This configuration allows banks within a bank group to share a data input / output bus in a multiplexed manner. Alternatively, a memory device can include a large array of tiles accessed individually to maximize tile access frequency and minimize tile access contention, thereby increasing memory access bandwidth. Tiles configured in this way form modular units, allowing for flexibility in configuring memory modules to meet application requirements.

[0043] Figure 2 is a transistor-level schematic diagram of a memory device including a three-dimensional array of NOR-type memory strings in an embodiment of the present disclosure. In some embodiments, the memory device of Figure 2 is constructed using one of the memory structures of Figures 1A to 1E. That is, the memory device of Figure 2 is constructed using channel-all-around ferroelectric memory transistors described in Figures 1A to 1E. Referring to Figure 2, the memory device 200 of the present disclosure includes a plurality of NOR-type memory strings 212 configured as a three-dimensional array to form a high-density memory structure. The three-dimensional array of NOR-type memory strings is configured as a memory stack 215 of NOR-type memory strings 212, within each memory stack 215, the NOR-type memory strings 212 are stacked in a first direction (e.g., the Z direction). Figure 2 shows three memory stacks 215: memory stack 0, memory stack 1, and memory stack 2. A three-dimensional array of NOR-type memory strings is also configured as a series of NOR-type memory strings 212 arranged in a second direction (e.g., the X direction) that forms a plane, with each series of NOR-type memory strings 212 arranged in one or more planes parallel to each other along a first direction (the Z direction). Each memory string 212 includes a series of memory transistors 202 in a NOR configuration connected in parallel to each other between a common bit line 204 and a common source line 206. The memory transistors form a horizontal NOR-type memory string (also referred to as an "HNOR-type memory string") extending in a third direction (e.g., the Y direction). In this embodiment, the memory transistors 202 are thin-film ferroelectric field-effect transistors (also referred to as "ferroelectric memory transistors"). Furthermore, in some embodiments, the memory transistors 202 are junction-less ferroelectric memory transistors formed using oxide semiconductor channels.

[0044] Each ferroelectric memory transistor 202 in each memory string 212 has a drain terminal connected to a common bit line BLx (e.g., BL0, BL1, BL2, ...) corresponding to the transistor, and a source terminal connected to a common source line SLx (e.g., SL0, SL1, SL2, ...) corresponding to the transistor. Thus, each ferroelectric memory transistor 202 in each memory string 212 is connected in parallel with its corresponding common bit line 204 and common source line 206 to form a NOR-type memory string. Each ferroelectric memory transistor 202 in each memory string 212 further has a gate terminal connected to its corresponding word line WLx (e.g., WL0, WL1, WL2, ...). Each ferroelectric memory transistor 202 vertically aligned across multiple memory strings 212 in the memory stack 215 is connected to its corresponding common word line 208 (also referred to as "local word line 208"). Each local word line 208 corresponding to each memory transistor arranged horizontally in the second direction (X direction) is connected to a common global word line GWLx (e.g., GWL0, GWL1, GWL2, ...).

[0045] In some embodiments, the common source line 206 is electrically floating (i.e., no continuous electrical connection is provided), and the source voltage is applied from the common bit line 204 using a precharge transistor (not shown). For example, one or more precharge transistors are provided between the common bit line and the common source line. The common source line can be charged to the voltage of the common bit line by applying a voltage to the common bit line and turning on the precharge transistor to electrically short-circuit the common bit line to the common source line. The precharge transistor is then turned off, and the voltage of the common source line is maintained by the charge of an associated capacitor ("virtual ground") such as the parasitic capacitance of the common source line. In other embodiments, both the common bit line 204 and the common source line 206 are electrically biased or driven by a control circuit connected to the memory device 200 via hardwire connections. Using an electrically floating source line has the advantage of reducing the density of connector wires required in the stepped structure (not shown) of the three-dimensional array, as hardwire connections are not required.

[0046] The ferroelectric memory transistors of this disclosure offer high durability, long data retention periods, and relatively low-voltage operation in both erase (e.g., gate-source voltages below 3.0 volts) and write (e.g., gate-source voltages below -3.0 volts) operations. By combining ferroelectric or polarization properties with three-dimensional structures (e.g., thin-film NOR memory strings), memory devices comprising the ferroelectric memory transistors of this disclosure offer the further advantage of realizing high-density and low-cost memory arrays while maintaining the advantages of high-speed random-access memory circuits (low read latency).

[0047] In embodiments of this disclosure, a three-dimensional array of NOR memory strings of the memory device 200 is formed on a semiconductor substrate. To complete the memory circuit, various types of circuits to support the operation of the NOR memory strings formed on the semiconductor substrate are formed inside or on the surface of the semiconductor substrate. Such circuits are referred to as “under-array circuits” (“CuA”) and may include digital and analog circuits such as decoders, drivers, sense amplifiers, sequencers, state machines, logic gates, memory caches, multiplexers, voltage level shifters, voltage sources, latches, registers, and connectors. These circuits perform iterative local operations on the memory array formed on the semiconductor substrate, such as processing random addresses and executing commands for activation, erase, write, read, or refresh. In some embodiments, the transistors in the CuA are constructed using processes optimized for control circuits (e.g., advanced manufacturing processes optimized for forming low-voltage and high-speed logic circuits). In some embodiments, the CuA are constructed using fin-type field-effect transistors (FinFETs) or gate-all-around field-effect transistors (GAAFETs) to achieve a compact circuit layer and improved transistor performance.

[0048] In some embodiments, the memory device 200 is formed on a semiconductor substrate without integrated circuits, and the memory device 200 is bonded to another semiconductor substrate containing the memory control circuit using hybrid bonding or the like. In one embodiment, hybrid bonding is formed on the upper surface of the memory array opposite to the semiconductor layer on which the memory array is constructed, and connected to a corresponding hybrid bonding formed on another semiconductor layer containing the control circuit that operates the memory array. The semiconductor layer or semiconductor substrate on which the memory device 200 is formed can be configured in various ways depending on the degree of integration with the memory control circuit.

[0049] In some embodiments, CuA provides data paths to and from the memory array, and further, to and from a memory controller located on the same semiconductor substrate as CuA. Alternatively, the memory controller may be located on a separate semiconductor substrate, in which case CuA and its associated data paths are electrically connected to the memory controller using various integration techniques, such as hybrid bonding, through-silicon vias (TSVs), exposed contacts, and other suitable interconnection techniques. In one example, the memory controller may be connected to CuA using an electrophotonic-based interconnection system.

[0050] In some examples, the memory controller includes control circuits for performing other memory control functions such as data routing and error correction to access and operate the memory transistors in the memory array connected to it, and for providing interface functions with the system that interacts with the memory array. In one example, the memory controller provides commands such as erase, write, and read commands to the circuit underarray (CuA), usually along with information such as memory cell addresses and write data for write operations. The memory array uses the underarray circuitry to autonomously perform memory operations in response to the received commands.

[0051] In the memory device 200, each memory transistor 202 in the NOR-type memory string 212 can perform read, write, or erase operations by appropriately biasing its corresponding common word line 208 (WLx) and a common bit line 204 (BLy) shared with other memory transistors 202 in the NOR-type memory string 212. The common word line corresponding to each memory transistor 202 is shared with memory transistors in other NOR-type memory strings in a plane that align with that memory transistor along a first direction (Z-direction or "vertical direction"). In some embodiments, the common source line is typically electrically floating, i.e., not hardwired to any potential. During read, write, or erase operations, the common source line of the NOR-type memory string is typically subjected to a relatively constant voltage maintained by a voltage source or the charge of an associated capacitor ("virtual ground"), such as the parasitic capacitance of the common source line. For example, the common source line of a NOR-type memory string is biased to a given voltage by a precharge operation that provides a desired voltage to the common bit line and transfers the voltage on the common bit line to the common source line via one or more precharge transistors. For example, to perform a write or erase operation on a selected memory transistor, a sufficient voltage difference (e.g., 1.5V to 3V for a ferroelectric memory transistor) is applied between the word line and at least the common bit line. To avoid interference with unselected memory transistors, unintended erase or write operations on unselected memory transistors can be prevented by applying a predetermined voltage difference between the common word line and the common bit line corresponding to the unselected memory transistor, which is significantly lower than the voltage required for writing or erasing. To perform a read operation on a selected memory transistor, a read voltage (e.g., 1V for a ferroelectric memory transistor) is applied to the word line, and the bit line is biased to a positive voltage (e.g., approximately 0.05V to approximately 0.9V) to allow current to flow between the drain and source terminals of the selected memory transistor.The current in the bit line is detected by a sense amplifier via a bit line selector, which allows the logic state or stored data of the selected memory transistor to be determined.

[0052] In some embodiments, to perform an erase operation on a selected memory transistor, the selected word line is biased to 2-3V, the selected bit line is biased to 0V, and the source line is set to 0V (e.g., by a pre-charge operation). A forbidden voltage of 1.1-1.5V is applied to the unselected word line, bit line, and source line. In some embodiments, to perform a write operation on a selected memory transistor, the selected word line is biased to 0V, the selected bit line is biased to 1.8-2V, and the source line is set to 0.5-0.8V (e.g., by a pre-charge operation). A forbidden voltage of 0.5-0.8V is applied to the unselected word line, bit line, and source line. In some embodiments, to perform a read operation on a selected memory transistor, the selected word line is biased to 0.7-1V, the selected bit line is biased to 0.5V, and the source line is set to 0V (e.g., by a pre-charge operation). A forbidden voltage of 0V is applied to the unselected word line, bit line, and source line.

[0053] In some embodiments, a channel-all-around ferroelectric memory transistor having a toroidal channel layer allows for the use of different voltage magnitudes for write and erase operations. Specifically, the write voltage applied between the word line and the common bit line to write the memory transistor to a first logic set has a first voltage magnitude. On the other hand, the erase voltage applied between the word line and the common bit line to erase the memory transistor to a second logic set has a second voltage magnitude with the opposite voltage polarity to the write voltage. The toroidal channel layer allows for the use of different voltage magnitudes for the write and erase voltages.

[0054] Figures 3A and 3B include cross-sectional views of the memory structure of Figures 1A and 1C in two different planes, according to embodiments of the present disclosure. Each of Figures 3A and 3B includes two figures, Figure (i) and Figure (ii), where Figure (i) is a horizontal cross-sectional view (i.e., an XY plane view) along line AA' in Figure (ii), and Figure (ii) is a vertical cross-sectional view (i.e., an XZ plane view) along line AA' in Figure (i). Furthermore, Figures 3A and 3B show enlarged views of parts of the memory structure to illustrate the detailed configuration of the memory structure. Specifically, Figure 3A shows a cross-sectional view of two memory stacks in the memory structure 10 of Figure 1A, and Figure 3B shows a cross-sectional view of two memory stacks in the memory structure 10a of Figure 1C.

[0055] Referring to Figure 3A, the memory structure 10 includes a pair of adjacent memory stacks 17, referred to herein as memory stack 0 and memory stack 1, separated from each other by slit trenches 19. Figure (i) of Figure 3A shows a cross-sectional view in the XY plane at the bit line layer BL1. In this embodiment, each memory stack 17 includes local word line structures 13 arranged in two columns extending in the Y direction. In each memory stack 17, the two columns of local word line structures 13 are arranged alternately in the Y direction such that the local word line structures 13 in each column do not align with the local word line structures in the adjacent column in the X direction. By arranging the local word line structures 13 in each column alternately in the Y direction in this way, it is possible to connect global word lines to only one local word line structure within each memory stack across multiple memory stacks.

[0056] In embodiments of this disclosure, each local word line structure 13 is formed within a hole formed in the memory stack 17 during the manufacturing process. In this embodiment, the hole has a circular shape in cross-section, but in other embodiments it may have a different shape. The concentric layers of the channel layer, ferroelectric layer, and gate conductor layer are deposited within the hole, for example, using a damascene process or atomic layer deposition (ALD). For example, each local word line structure 13 includes a channel layer 26 formed as an annular layer on the periphery side of the hole, a ferroelectric layer 27 formed as an annular layer inside the channel layer 26, and a gate conductor layer 28 formed inside the ferroelectric layer 27 and filling the remaining cavity (space) of the hole. In some embodiments, an interface layer 25 is provided between the channel layer 26 and the ferroelectric layer 27. As shown in Figure 3A(i), each local word line structure 13 is surrounded by conductive layers forming a bit line 22 (common drain line) and a source line 24 (common source line). Referring to Figure 3A(ii), in each memory stack 17, the bit line conductive layer 22 and source line conductive layer 24 within each active layer 16 are arranged to surround and contact the annular channel layer 26 of each local word line structure 13 within the memory stack 17. Specifically, a portion of the annular channel layer 26 is provided between the bit line 22 and the annular ferroelectric gate dielectric layer 27 in the XY plane, or overlaps with them. Also, a portion of the annular channel layer 26 is provided between the source line 24 and the annular ferroelectric gate dielectric layer 27 in the XY plane, or overlaps with them.

[0057] Figure 3A(ii) shows a cross-sectional view in the X-Z plane of a local word line structure 13 spanning two memory stacks 17. This figure shows two active layers 16 of the memory structure 10, which are separated or isolated from each other by an interlayer insulating layer 15, which in this example is air gap insulation. Each active layer 16 includes a first conductive layer 22 as a common drain line or bit line 22 and a second conductive layer 24 as a common source line or source line 24. The first conductive layer 22 and the second conductive layer 24 within the active layer 16 are separated by a channel spacer dielectric layer 23. The channel spacer dielectric layer 23 defines the channel length of the memory transistor 20. With this configuration, the first conductive layer 22 (BL) and the second conductive layer 24 (SL) are formed to contact and surround the channel layer 26, thereby forming a channel-all-around ferroelectric memory transistor 20.

[0058] The cross-sectional view in Figure 3A (ii) is a cross-section of the local word line structure LWL0-0 of memory stack 0 and LWL0-1 of memory stack 1. The local word line structures LWL1-0 and LWL1-1 are positioned offset in the Y direction and can be seen through the air gap insulating layer 15. In this figure, the channel spacer insulating layer 23 is shown as transparent to make visible the local word line structures LWL1-0 and LWL1-1, which are positioned behind or offset in the Y direction. In fact, if the channel spacer dielectric layer 23 is a silicon dioxide (SiO2) layer, the channel spacer dielectric layer 23 is transparent to visible light.

[0059] Each memory transistor 20 of the memory structure 10 is insulated from adjacent memory transistors along the memory stack (in the Z direction) by an interlayer insulating layer 15. In the embodiment shown in Figure 3A, the interlayer insulating layer 15 is an air gap insulation formed by an air gap cavity layer 15a and an optional air gap liner layer 15b. The air gap liner layer 15b is a dielectric layer used to cover or passivate the exposed surface of the air gap cavity 15a. In some embodiments, the air gap liner layer 15b is a silicon nitride layer or an aluminum oxide (Al2O3) layer. The thickness of the air gap liner 15b can be 1 nm to 3 nm. In Figure 3A, the sizes of the components may be exaggerated for illustrative purposes. Please understand that the depictions in this figure and other figures are not necessarily to scale. The air gap cavity 15a forming the interlayer insulating layer 15 provides effective insulation between adjacent memory transistors 20 along the memory stack 17. In embodiments of this disclosure, the interlayer insulating layer 15 is also used to provide physical isolation between the channel layer 26 of a memory transistor in the same memory stack and the channel layer of a memory transistor above or below it, thereby providing insulation for each memory transistor in the memory stack. Specifically, the channel layer 26 is removed in the interlayer insulating region between two adjacent active layers. The channel layer 26 is provided in the active layer 16 in a region that overlaps with the first conductive layer forming the bit line 22 and the second conductive layer forming the source line 24, and is in contact with the first conductive layer and the second conductive layer.

[0060] In another embodiment, as shown in Figure 3B, the interlayer insulating layer 15 is formed as a dielectric layer. In some examples, after separating the channel layer 26 in the interlayer insulating region between two adjacent active layers, a dielectric layer, such as a silicon dioxide (SiO2) layer, is deposited, for example by atomic layer deposition (ALD), to fill the cavity in the interlayer insulating region. This deposition process also deposits a dielectric layer on the sidewalls of the slit trench 19, as shown by the sidewall portion 34. The remaining cavity of the slit trench 19 may be left unfilled for use as air gap insulation, as shown in Figure 3B, or it may be filled with a dielectric layer, as shown in Figure 1C.

[0061] In the intermediate processing step, a dielectric liner layer 32 is formed on the sidewall of the hole to provide a smooth surface for depositing the channel layer 16 and the ferroelectric dielectric layer 27. The portions of the dielectric liner layer 32 adjacent to the bit line conductive layer 22 and the source line conductive layer 24 are removed during the metal substitution process to allow the bit line conductive layer 22 and the source line conductive layer 24 to contact the channel layer 26. Furthermore, the portions of the dielectric liner layer 32 adjacent to the interlayer insulating layer 15 are removed to facilitate the separation of the channel layer 26 between two adjacent active layers 16. Thus, as shown in Figures 3A and 3B, only a portion of the dielectric liner layer 32 remains in the completed memory structure 10 (memory structure 10a). Specifically, only the portion of the dielectric liner layer 32 adjacent to the channel spacer isolation layer 23 remains on the sidewall of the local word line structure 13. In some embodiments, the dielectric liner layer 32 is a silicon dioxide layer (SiO2) and may have a thickness of about 2-3 nm in the X direction.

[0062] In embodiments of this disclosure, the memory structure 10 (memory structure 10a) is composed of a multilayer stack including a sacrificial material and a dielectric layer. After the formation of the local word line structure 13, slit trenches 19 are formed in the multilayer stack, thereby dividing the multilayer stack into a plurality of memory stacks 17. Subsequently, a metal substitution process is performed using the slit trenches 19 to replace specific sacrificial layers with a first conductive layer and a second conductive layer to form bit lines 22 and source lines 24. The slit trenches 19 are also used in a channel isolation process to remove channel layers 26 in interlayer insulating regions between active layers 16. After the completion of the memory structure 10, the slit trenches 19 can be used as air gap insulators by filling them with a dielectric layer such as silicon dioxide or leaving them unfilled. The manufacturing process of the memory structure 10 (memory structure 10a) is described in detail below.

[0063] In some embodiments, the active layer of the memory structure 10 is formed as a thin film having a thickness of 15 nm to 25 nm in the Z direction. In one embodiment, the first conductive layer 22 and the second conductive layer 24 have a thickness of 20 nm in the Z direction, and the channel spacer dielectric layer 23 has a thickness of 25 nm in the Z direction. In one embodiment, each local word line structure 13 has a diameter of 55 nm and is spaced 55 nm apart in the Y direction from adjacent local word line structures 13. In other embodiments, the local word line structures 13 have a diameter of 40 to 70 nm. The memory stack 17 and slit trenches 19 have a pitch of 224 nm in the X direction, and the slit trenches 19 have a width of 50 to 75 nm in the X direction. The thickness of the annular channel layer 26 made of oxide semiconductor is in the range of 5 to 10 nm in the X or Y direction. The thickness of the annular ferroelectric dielectric layer 27 is in the range of 3 to 7 nm in the X or Y direction. In one example, the thickness of the annular channel layer 26 made of an oxide semiconductor is 7 nm, and the thickness of the annular ferroelectric dielectric layer 27 is 5 nm. The gate conductor layer 28 fills the remaining space in the center of the local word line structure 13. In some embodiments, the gate conductor layer 28 includes a conductive liner layer 28a made of titanium nitride (TiN) or the like. The conductive liner layer 28a has a thickness of 2 to 3 nm.

[0064] Figures 4A and 4B are enlarged perspective views of the memory structure shown in Figures 1A and 1C in embodiments of the present disclosure. Specifically, Figure 4A shows an enlarged view of a channel-all-around ferroelectric memory transistor 20 formed on a columnar local word line structure 13. The columnar local word line structure 13 is connected to the corresponding global word line 30. Figure 4B is a cross-sectional view of the local word line structure 13 in Figure 4A. In the perspective views of Figures 4A and 4B, the dielectric layers (channel spacer dielectric layer and interlayer insulating layer) are omitted from the illustration in order to more clearly show the structure of the memory transistor 20. Referring to Figures 4A and 4B, the bit line conductive layer 22 and the source line conductive layer 24 surround the columnar local word line structure 13. The oxide semiconductor channel layer 26 is formed in an annular shape so as to surround the ferroelectric gate dielectric layer 27 and the gate conductor layer 28. The oxide semiconductor channel layer 26 is provided in a region that overlaps with the bit line conductive layer 22 and the source line conductive layer 24 in the vertical direction, and is in contact with the bit line conductive layer 22 and the source line conductive layer 24. The channel layer 26 is removed or separated from the interlayer region between two adjacent active layers, i.e., between the source line 24 and the bit line 22. In this embodiment, the local word line structure 13 includes an interface layer 25, which is exposed in the interlayer region. Alternatively, the interface layer 25 may be completely or partially removed. As described in Figures 3A and 3B, the cavities in the interlayer region and the cavities of the slit trench may be filled with a dielectric layer such as silicon dioxide (SiO2). Alternatively, an air gap dielectric liner layer may be formed to passivate the exposed surface of the interlayer region, with the remaining cavities left unfilled to form air gap insulation.

[0065] Figure 5 is a top view of a memory structure including a precharge transistor and a stepped structure according to an embodiment of the present disclosure. Figure 6 is a cross-sectional view of the memory structure of Figure 5 including the precharge transistor and the stepped structure according to an embodiment of the present disclosure. Referring to Figures 5 and 6, the memory structure 40 includes a three-dimensional array of NOR-type memory strings of channel-all-around ferroelectric memory transistors formed within a multilayer memory stack. The memory structure 40 includes a plurality of memory stacks 44 arranged in the X direction and separated from each other by slit trenches 45. Each memory stack 44 includes a plurality of active layers 50 separated from each other in the Z direction by interlayer insulating layers 51. In this embodiment, the memory stack 44 includes eight active layers L0 to L7. Each active layer 50 includes a first conductive layer as a common drain line or bit line, a second conductive layer as a common source line or source line, and a channel spacer dielectric layer interposed between the first conductive layer and the second conductive layer.

[0066] Each memory stack 44 includes a memory array portion 42 having columnar local word line structures 56 for forming channel-all-around ferroelectric memory transistors at each intersection with the active layer 50. Each memory stack 44 further includes a precharge array portion 43 having columnar precharge local word line structures 58 for forming channel-all-around non-memory transistors at each intersection with the active layer 50. As described above with reference to Figure 2, non-memory transistors (precharge transistors) are used to set the common source line voltage when the common source line is electrically floating within the memory structure. In some embodiments, the precharge transistors are formed using the same channel layer and gate conductor layer as the memory transistors. The precharge transistors are formed using a non-polarizable gate dielectric layer to form the non-memory transistors.

[0067] Each memory stack 44 further includes stepped structures 46a and 46b provided at both ends of the memory stack 44 in the Y direction. More specifically, each memory stack 44 includes a first stepped structure 46a corresponding to an odd-numbered active layer 50 and a second stepped structure 46b corresponding to an even-numbered active layer 50. Each stepped structure has a first conductive via 47 for connecting to a common drain line (bit line) of the active layer 50 and a second conductive via 48 for connecting to a circuit formed on the semiconductor substrate 52. Each stepped structure further has a metal wire 49 connecting the first conductive via 47 to the second conductive via 48 at each step, thereby connecting the common drain line of each active layer 50 to a circuit formed on the semiconductor substrate 52. In this embodiment, the second conductive via 48 is formed aligned with the first conductive via 47 in the Y direction and penetrates the multilayer memory stack 44. The second conductive via 48 is surrounded by a dielectric spacer layer 53, which prevents the second conductive via 48 from being electrically short-circuited with the conductive layer in the active layer 50.

[0068] The memory structure 40 configured in this way includes a first stepped structure 46a connected to the bit lines of the odd-numbered active layers (e.g., active layers L1, L3, L5, and L7) and a second stepped structure 46b connected to the bit lines of the even-numbered active layers (e.g., active layers L0, L2, L4, and L6). By using the first stepped structure 46a and the second stepped structure 46b connected to every other active layer, the manufacturing process for forming the stepped structure can be greatly simplified.

[0069] Figure 7 is an enlarged cross-sectional view of a memory stack including local word line structures in an embodiment of the present disclosure. Referring to Figure 7, a portion of the memory stack 60 having local word line structures 64 in the XY plane is shown. The cross-sectional view in Figure 7 is a cross-section across the bit line layer 62 in the memory stack 60. The memory stack 60 is bounded by slit trenches 66. Both the memory stack 60 and the slit trenches 66 extend in the Y direction. Global word lines 65 connected to each local word line structure 64 extend in the X direction.

[0070] In the embodiment shown in Figure 7, the memory stack 60 includes a series of local word line structures 64 arranged in two columns aligned in the X direction and extending in the Y direction. That is, the local word line structures 64 are arranged as a two-dimensional array on the XY plane. The local word line structures 64 in each column are arranged alternately in the Y direction such that each global word line 65 extending in the X direction is connected to only one local word line structure 64 in each memory stack 60. In Figure 7, the dotted circles 68 indicate that the gate conductor layer of the local word line structure 64 is connected to the corresponding global word line 65.

[0071] In the example shown in Figure 7, each columnar local word line structure 64 has a diameter of 55 nm and is spaced 55 nm apart from adjacent local word line structures in the Y direction. The width of the slit trench 66 in the X direction is 55 nm, and the pitch of the slit trench 66 and the memory stack 60 is 224 nm. The local word line structure 64 has a margin of approximately 20 nm in the X direction from the edge of the memory stack. In this configuration, the pitch of the global word line 65 is 55 nm, and the width of the global word line 65 in the Y direction is 27.5 nm. In one embodiment, the global word line 65 is formed using double patterning lithography or self-aligned double patterning lithography. In other embodiments, the global word line 65 can be formed using single patterning lithography.

[0072] Figure 8 is an enlarged cross-sectional view of a memory stack including local word line structures in another embodiment of the present disclosure. Referring to Figure 8, a portion of the memory stack 70 having local word line structures 74 in the XY plane is shown. The cross-sectional view in Figure 8 is a cross-section across the bit line layer 72 in the memory stack 70. The memory stack 70 is bounded by slit trenches 76. Both the memory stack 70 and the slit trenches 76 extend in the Y direction. Global word lines 75 connected to each local word line structure 74 extend in the X direction.

[0073] In the embodiment shown in Figure 8, the memory stack 70 includes a series of local word line structures 74 arranged in a single column extending in the Y direction. Each global word line 75 extending in the X direction is connected to one local word line structure 74 in each memory stack 70. In Figure 8, the dotted circles 78 indicate that the gate conductor layer of a local word line structure 74 is connected to the corresponding global word line 75. Arranging the local word line structures 74 in a single column allows for a relaxation of the pitch of the global word lines 75. Furthermore, narrowing the memory stack 70 in the X direction can reduce the parasitic capacitance of the active layer. The length of the memory stack 70 in the Y direction can be extended to accommodate the number of local word line structures 74 required to form a desired number of memory transistors.

[0074] Figures 9A and 9B are enlarged cross-sectional views of a memory stack including a local word line structure in another embodiment of the present disclosure. In the embodiments described above, the columnar local word line structure is formed in a hole having a circular shape in the XY plane. In the embodiments shown in Figures 9A and 9B, the columnar local word line structure is formed in a hole having an elliptical or oblong shape in the XY plane.

[0075] First, referring to Figure 9A, a portion of the memory stack 80 having local word line structures 84 in the XY plane is shown. The cross-sectional view in Figure 9A is a cross-section across the bit line layer 82 within the memory stack 80. The memory stack 80 is bounded by slit trenches 86. Both the memory stack 80 and the slit trenches 86 extend in the Y direction. The global word lines 85 connected to each local word line structure 84 extend in the X direction.

[0076] In the embodiment shown in Figure 9A, the memory stack 80 includes a series of local word line structures 84 arranged in two columns aligned in the X direction and extending in the Y direction. The XY cross-section of each local word line structure 84 has an elliptical (oval) shape with a major axis parallel to the Y direction and a minor axis parallel to the X direction. The local word line structures 84 in each column are arranged alternately in the Y direction such that each global word line 85 extending in the X direction is connected to only one local word line structure 84 in each memory stack 80. In Figure 9A, the dotted circle 88 indicates that the gate conductor layer of the local word line structure 84 is connected to the corresponding global word line 85.

[0077] Next, referring to Figure 9B, a portion of the memory stack 90 having local word line structures 94 in the XY plane is shown. The cross-sectional view in Figure 9B is a cross-section across the bit line layer 92 within the memory stack 90. ​​The memory stack 90 is bounded by slit trenches 96. Both the memory stack 90 and the slit trenches 96 extend in the Y direction. The global word lines 95 connected to each local word line structure 94 extend in the X direction.

[0078] In the embodiment shown in Figure 9B, the memory stack 90 includes a series of local word line structures 94 arranged in two columns aligned in the X direction and extending in the Y direction. Each local word line structure 94 has an elliptical (oval) shape with a major axis parallel to the X direction and a minor axis parallel to the Y direction. The local word line structures 94 in each column are arranged alternately in the Y direction such that each global word line 95 extending in the X direction connects to only one local word line structure 94 in each memory stack 90. ​​In Figure 9B, the dotted circle 98 indicates that the gate conductor layer of a local word line structure 84 is connected to the corresponding global word line 85.

[0079] In embodiments of the present disclosure, the columnar local word line structure can be formed such that its XY cross-section has a circular, elliptical, or oblong shape. The channel layer and ferroelectric dielectric layer of the columnar local word line structure are formed as annular concentric layers, regardless of the shape of the XY cross-section of the columnar local word line structure. The shape of the XY cross-section of the columnar local word line structure can be selected to optimize the arrangement or density of the columnar local word line structures formed on the memory stack, taking into account the dimensions of the global word lines formed on the memory stack to connect to the columnar local word line structure.

[0080] In the embodiments described in Figures 5 and 6, the memory structure of the Disclosure is formed solely by hardwire connections to the bit lines, while the source lines are left electrically floating (i.e., without hardwire or continuous electrical connections). A precharge transistor is then used to set the source lines to a desired voltage for each predetermined memory operation. In another embodiment, the memory structure of the Disclosure may be configured to have physical or hardwire connections to both the bit lines (common drain lines) and source lines (common source lines) via a stepped structure.

[0081] Figure 10 is a top view of a memory structure in an embodiment of the present disclosure, including a stepped structure connected to a common bit line and a common source line. Figure 11 is a cross-sectional view of the memory structure of Figure 10, including a stepped structure connected to a common bit line and a common source line, in an embodiment of the present disclosure. Referring to Figures 10 and 11, the memory structure 40a includes a three-dimensional array of NOR-type memory strings of channel-all-around ferroelectric memory transistors formed within a multilayer memory stack. The memory structure 40a includes a plurality of memory stacks 44 arranged in the X direction and separated from each other by slit trenches 45. Each memory stack 44 includes a plurality of active layers 50 separated in the Z direction by interlayer insulating layers 51. In this embodiment, the memory stack 44 includes eight active layers L0 to L7. Each active layer 50 includes a first conductive layer as a common drain line or bit line, a second conductive layer as a common source line or source line, and a channel spacer dielectric layer interposed between the first conductive layer and the second conductive layer. In the cross-sectional view of Figure 11, the common source line within the active layer 50 is shown with a cross-hatch pattern to distinguish it from the bit line of the active layer 50. The use of different patterns in the cross-sectional view of Figure 11 does not necessarily suggest that the common source line and the common drain line are formed from different conductive materials. In many cases, the common source line and the common drain line are formed from the same conductive material. Similarly, in Figures 6 and 11 (and Figure 16 later described later), the channel spacer dielectric layer and the interlayer insulating layer 51 within the active layer 50 are shown with different patterns to distinguish these two layers. The use of different patterns in the cross-sectional views of Figures 6, 11, and 16 does not necessarily suggest that the channel spacer dielectric layer and the interlayer insulating layer 51 are formed from different materials. In some embodiments, the channel spacer dielectric layer and the interlayer insulating layer 51 are formed from the same dielectric material, such as a silicon dioxide layer. In other embodiments, the channel spacer dielectric layer may be a silicon dioxide layer and the interlayer insulating layer 51 may be implemented as air gap insulation.

[0082] Each memory stack 44 includes a memory array portion 42 having columnar local word line structures 56 for forming channel all-around ferroelectric memory transistors at each intersection with the active layer 50. In the memory structure 40a, since the source lines are hardwired, non-memory transistors (precharge transistors) are not required. Each memory stack 44 includes stepped structures 46, 54 formed at both ends of the memory stack 44 in the Y direction. In this embodiment, each memory stack 44 includes a stepped structure 46 for bit lines and a stepped structure 54 for source lines. The stepped structure 46 for bit lines has a first conductive via 47 for connecting to the common drain line (bit line) of each active layer 50 and a second conductive via 48 for connecting to a circuit formed on the semiconductor substrate 52. The stepped structure 46 for bit lines further has a metal wire 49 connecting the first conductive via 47 to the second conductive via 48 at each step, so that the common drain line of each active layer is connected to a circuit formed on the semiconductor substrate 52. The stepped source wire structure 54 has a first conductive via 47 for contacting the common source wire (source wire) of each active layer 50 and a second conductive via 48 for connecting to a circuit formed on the semiconductor substrate 52. The stepped source wire structure 54 further has a metal wire 49 connecting the first conductive via 47 to the second conductive via 48 at each step, thereby connecting the common source wire of each active layer to a circuit formed on the semiconductor substrate 52.

[0083] In this embodiment, the second conductive vias 48 of each stepped structure 46, 54 are aligned with the first conductive via 47 in the Y direction and are formed to penetrate the multilayer memory stack. The second conductive vias 48 are surrounded by a dielectric spacer layer 53, which prevents the second conductive vias 48 from being electrically short-circuited with the conductive layers in the active layer 50.

[0084] The memory structure 40a configured in this way includes a stepped bit line structure 46 connected to the bit lines of all active layers (i.e., active layers L0 to L7) and a stepped source line structure 54 connected to the source lines of all active layers (i.e., active layers L0 to L7). By using the stepped bit line structure 46 and the stepped source line structure 54, both the bit lines and source lines of the memory transistors in the memory structure 40a can be hardwired to circuits formed on the semiconductor substrate 52. Therefore, a bias voltage can be directly applied to the source lines to perform memory operation.

[0085] Figure 12 is a flowchart showing a manufacturing process for producing a memory structure including a channel-all-around ferroelectric memory transistor in an embodiment of the present disclosure. Figures 13A to 13N (including Figure 13J1) show memory structures in intermediate processes of the manufacturing method of Figure 12 in several embodiments. The following description will be made with reference to Figures 12 and 13A to 13N. Each of Figures 13A to 13N includes two figures, Figure (i) and Figure (ii), where Figure (i) is a horizontal cross-sectional view along line AA' in Figure (ii) (i.e., an XY plan view), and Figure (ii) is a vertical cross-sectional view along line AA' in Figure (i) (i.e., an XZ plan view).

[0086] Referring to Figure 12, the manufacturing process 300 for producing a channel-all-around ferroelectric memory transistor within a memory structure begins with step 302 of forming a multilayer stack on a semiconductor substrate. As shown in Figure 13A, first, a semiconductor substrate 102 is prepared, and any circuit to be formed within the semiconductor substrate 102, such as CuA or an interconnect conductor, is formed inside or on the surface of the semiconductor substrate 102. Subsequently, an insulating layer 104 is formed on the semiconductor substrate 102 to cover and protect the circuit formed inside or on the surface of the semiconductor substrate 102. In some embodiments, the insulating layer 104 is a dielectric layer and also functions as an etching stop layer in subsequent processing steps. In some embodiments, the insulating layer 104 is a silicon oxycarbide (SiOC) layer or an aluminum oxide (Al2O3) layer. The insulating layer 104 can be formed using any material having selectivity suitable for the subsequent etching process.

[0087] Next, a multilayer stack is formed by continuously depositing (i) a multilayer film 101 and (ii) an interlayer sacrificial layer 120 on the plane of the semiconductor substrate 102, specifically on an insulating layer 104 formed on the semiconductor substrate 102. In this embodiment, the interlayer sacrificial layer 120 is deposited on the insulating layer 104 before depositing the first multilayer film 101. The multilayer film 101 includes three sublayers in the Z direction in this order: (a) a first sacrificial layer 122, (b) a channel spacer dielectric layer 113, and (c) a second sacrificial layer 127. Figure 13A shows the memory structure 100 after the deposition of the initial layers of the thin film. The multilayer film 101 is also referred to as the "active layer" in this specification. Figure (i) of Figure 13A is a horizontal cross-section along line AA' in the first sacrificial layer 122 of Figure (ii). Figure 13A(ii) is a vertical cross-section of the memory structure 100 along line AA' shown in Figure (i). The first sacrificial layer 122 and the second sacrificial layer 124 are replaced by their respective conductive layers in subsequent processing steps. The interlayer sacrificial layer 120 (also referred to herein as the third sacrificial layer) is replaced by an insulating material in subsequent processing steps to form an interlayer insulating layer that provides isolation between active layers, as will be described in detail below. In one embodiment, each sublayer and interlayer sacrificial layer 120 in the multilayer film 101 generally has a thickness of 30 nm or less. In another embodiment, each sublayer and interlayer sacrificial layer 120 in the multilayer film 101 does not have the same thickness as one another. Dimensions herein are for illustrative purposes only and are not intended to be limiting. Any suitable thickness or dimension may be used in actual implementation.

[0088] In some embodiments, the memory structure 100 may include bottom and top sublayers designated as dummy layers that do not necessarily form active layers or parts of memory transistors. Furthermore, in this embodiment, the memory structure 100 includes an uppermost interlayer sacrificial layer 120 and an etching stop layer 126 formed on the uppermost interlayer sacrificial layer 120. The uppermost interlayer sacrificial layer 120 is replaced by an interlayer insulating layer in a subsequent processing step. The etching stop layer 126 is used as a stop layer in a subsequent chemical mechanical polishing (CMP) process. In some embodiments, the etching stop layer 126 is a silicon oxycarbide (SiOC) layer or a silicon nitride (Si3N4) layer. In the example shown in Figure 13A, the multilayer stack includes four active layers. In other examples, the multilayer stack can be formed using any appropriate number of one or more active layers.

[0089] In some embodiments, the first sacrificial layer 122 and the second sacrificial layer 124 are silicon nitride (Si3N4) layers, respectively. The channel spacer dielectric layer 113 is an insulating dielectric material such as silicon dioxide (SiO2). The interlayer sacrificial layer 120 (or third sacrificial layer) is a sacrificial material selected from carbon, silicon oxide (aSi), and silicon germanium (SiGe). In one embodiment, the interlayer sacrificial layer 120 is a silicon oxide (a-Si) layer.

[0090] After a multilayer stack having a desired number of active layers 101 is formed, the manufacturing process 300 proceeds to the step of forming stepped structures on both sides of the memory structure (Figure 12, step 303). Various methods for forming stepped structures are known in the art and can be applied to form stepped structures that contact at least the common drain line in the memory structure being manufactured. For example, the stepped structure can be formed by sequentially masking and etching each multilayer in the multilayer stack. Detailed processes for forming the stepped structure are not described herein, and the stepped structure is not shown in Figure 13A. After the stepped structure is formed, the memory structure is filled with dielectric layers to form stepped contact openings to circuits formed in the semiconductor substrate 102, with one contact opening for each step of the stepped structure. In embodiments of this disclosure, the manufacturing process 300 can form the contact openings in the stepped structure by a dry etching process or the like. The contact openings are formed to penetrate the multilayer stack and reach the semiconductor substrate, enabling connection to circuits formed in the semiconductor substrate. Dielectric spacer layers are formed within the contact openings. For example, the dielectric spacer layer may be a silicon dioxide layer (SiO2). The bottom of the dielectric spacer layer is punched out, and a conductive layer is deposited to fill the contact opening. In this way, a contact with the circuit formed on the semiconductor substrate is formed. In some embodiments, the conductive layer is a tungsten layer lined with titanium nitride (TiN / W). After the deposition step, excess material can be removed from the top of the memory structure 100, for example, by chemical mechanical polishing (CMP). The CMP process is stopped on the etching stop layer 126. In this description, the stepped contact to the circuit in the semiconductor substrate is also referred to as a "CC contact".

[0091] If the memory structure uses a precharge transistor to set the common source line voltage, the manufacturing process 300 proceeds to the step of forming a precharge transistor in the precharge transistor (PCH) portion of the memory structure (Figure 12, step 304). The precharge transistor is optional and may be omitted in other embodiments of the present disclosure. For example, the memory structure may have a hardwired connection to a common source line, in which case a precharge transistor for setting the source line voltage is not required. In one embodiment, a hole opening is formed in the precharge transistor (PCH) portion of a multilayer stack to form the precharge transistor. Subsequently, a device layer for the precharge transistor is deposited in the hole opening using a process such as atomic layer deposition (ALD). In some embodiments, the device layer for the precharge transistor includes a dielectric liner layer, a channel layer, a non-memory gate dielectric layer, and a gate conductor layer. In one embodiment, the dielectric liner layer is a 2 nm thick silicon dioxide layer, the channel layer is a 5 nm thick oxide semiconductor layer (e.g., IGZO), the non-memory gate dielectric layer is a 5 nm thick aluminum oxide (Al2O3) layer, and the remaining space is filled with a tungsten layer lined with titanium nitride.

[0092] In embodiments of this disclosure, the processing steps for forming the stepped structure and / or precharge transistors (if any) may be performed before, after, or alternately with the processing steps for forming the memory transistors. The order of the steps of the manufacturing processes described herein is illustrative and not intended to limit.

[0093] The manufacturing process 300 proceeds to the formation of memory transistors in the memory array portion of the memory structure. Referring to Figure 13A, a masking layer 128 is formed on the memory structure (on the etching stop layer 126) and hole openings 129 are patterned. In some embodiments, the masking layer 128 is an amorphous hard mask, such as an amorphous carbon hard mask. The masking layer 128 is patterned, for example, using a photolithography patterning step (using a mask and a patterning layer) followed by a mask-opening process to form hole openings 129 for forming holes in the multilayer stack. Note that in Figure 13A, the masking layer 128 is not drawn to scale. Also understand that in the high aspect ratio etching process of the multilayer stack of the memory structure 100, an amorphous hard mask of sufficient thickness is used. Furthermore, as will be understood by those skilled in the art, the photolithography process and the mask-opening process may include the use of an additional masking layer (not shown) to form the hole opening pattern on the masking layer 128.

[0094] Using the hole opening pattern thus defined on the masking layer 128, the manufacturing process 300 proceeds to the step of forming holes in the multilayer stack using a high aspect ratio etching process (Figure 12, step 306). For example, a selective anisotropic dry etching process is used to form hole openings in the multilayer stack using the masking layer 128. After performing the etching process to form the hole openings, the remaining portion of the masking layer 128 is removed. The resulting structure is shown in Figure 13B. In the example shown in Figure 13B, two sets of hole openings 129 are formed to form memory transistors in two memory stacks. Each set of hole openings 129 is arranged in two rows in the X direction and alternately in the Y direction. In some embodiments, the diameter of the hole openings 129 is 55-70 nm. In one embodiment, the hole openings 129 have the dimensions, spacing, and pitch described above with reference to Figure 7. As will be described in more detail later, the formed slit trench divides the memory structure into separate mesas, each mesa containing a pair of hole openings and memory transistors formed within the hole openings. In this description, the hole opening 129 is also referred to as an LWL hole.

[0095] In some embodiments, the manufacturing process of the present disclosure forms LWL holes using a mask having a mask pattern of hole openings having a first diameter. After printing the hole openings onto a patterning layer (e.g., a photoresist layer) and transferring the mask pattern onto a masking layer, the size of the hole openings within the masking layer 128 is further adjusted or enlarged by additional etching or the like. In this way, larger hole sizes can be achieved with smaller pitches that exceed the limits of photolithography. The multilayer stack is then etched using a high aspect ratio etching process with the enlarged masking layer.

[0096] Next, the manufacturing process 300 proceeds to the step of forming a device layer for the memory transistor within the LWL hole 129 (Figure 12, step 308). The device layer for the memory transistor is deposited within the LWL hole 129 using a process such as atomic layer deposition (ALD). In some embodiments, the device layer for the memory transistor includes a dielectric liner layer, a channel layer, a ferroelectric gate dielectric layer, and a gate conductor layer. In some embodiments, an interface layer may be included between the channel layer and the ferroelectric gate dielectric layer. First, referring to Figure 13C, a dielectric liner layer 131 is deposited on the sidewall of the LWL hole 129. For example, the dielectric liner layer 131 is deposited conformally on the sidewall of the LWL hole 129. In one embodiment, the dielectric liner layer 131 is deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), or a combination thereof. In this embodiment, the dielectric liner layer 131 is a silicon dioxide layer (SiO2). In other embodiments, the dielectric liner layer 131 can be the material used for the first sacrificial layer 122 and the second sacrificial layer 124, and another dielectric material having etching selectivity for the channel layer to be formed. In one example, the dielectric liner layer 131 has a thickness of 1 to 5 nm in the X direction. For example, in one embodiment, the dielectric liner layer 131 may have a thickness of 2 nm in the X direction. The dielectric liner layer 131 has the advantage of providing a uniform and flat surface for depositing the device layer for the memory transistor in subsequent processing steps.

[0097] Next, the manufacturing process 300 proceeds to the step of forming a local word line (LWL) structure lined with a dielectric liner layer within an LWL hole. One or more deposition steps are performed to deposit the device layers of the ferroelectric memory transistor. In some embodiments, the deposition of the device layers of the memory transistor includes depositing an oxide semiconductor channel layer 116 within the LWL hole, and then conformally depositing a ferroelectric gate dielectric layer 117 on the oxide semiconductor channel layer 116 as an annular concentric layer. For example, the channel layer 116 and the gate dielectric layer 117 can be deposited using an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a combination thereof. Then, the remaining cavity (space) of the LWL hole is filled with a gate conductor layer 118 using ALD technology or the like. In some embodiments, an interface layer 125 is deposited between the channel layer 116 and the ferroelectric gate dielectric layer 117 using atomic layer deposition (ALD) technology or the like. After the deposition step, excess material can be removed from the top of the memory structure, for example, using chemical mechanical polishing (CMP). Figure 13D shows the resulting memory structure.

[0098] In one embodiment, the oxide semiconductor channel layer 116 is an indium gallium zinc oxide (IGZO) layer, and the ferroelectric gate dielectric layer 117 is a zirconium-doped hafnium oxide (HZO) layer. In some embodiments, the oxide semiconductor channel layer 116 and the ferroelectric gate dielectric layer 117 are deposited in the same process chamber without breaking the vacuum between the deposition processes of the two layers. In some embodiments, the gate conductor layer 118 is a metallic layer and includes a thin conductive liner layer 118a and a conductive filler layer 118b. The thin conductive liner layer 118a may be a titanium nitride (TiN) liner or a tungsten nitride (WN) liner. The conductive filler layer 118b may be a tungsten (W) layer, a metal such as molybdenum (Mo), or a highly doped n-type or p-type polysilicon. In one embodiment, the gate conductor layer 118 is a tungsten layer (TiN / W) lined with titanium nitride. The interface layer 125, if present, is an aluminum oxide (Al2O3) layer. In one embodiment, the oxide semiconductor channel layer 116 has a thickness of 5 to 10 nm in the X direction, and in one example, it may have a thickness of 7 nm in the X direction. In one embodiment, the ferroelectric gate dielectric layer 117 has a thickness of 3 to 6 nm in the X direction, and in one example, it may have a thickness of 5 nm in the X direction. The gate conductor layer 118 fills the remaining space of the LWL hole.

[0099] In some embodiments, the optional interface layer 125 has a thickness of 1.5 to 3 nm in the X direction, and in one example, it may have a thickness of 2 nm in the X direction. In one embodiment, the interface layer 125 is an aluminum oxide (Al2O3) layer, which is annealed to obtain an amorphous film having the desired properties. In some embodiments, the aluminum oxide (Al2O3) layer can be annealed in oxygen (O2), ozone (O3), nitrous oxide (N2O), a forming gas (H2N2), or argon (Ar). The interface layer 125 is optional and may be omitted in other embodiments of this disclosure. In some embodiments, the interface layer 125 is deposited in the same process chamber as the ferroelectric gate dielectric layer, without breaking the vacuum between the deposition processes of the two layers.

[0100] In this embodiment, the memory structure 100 is used to form a ferroelectric memory transistor. The gate dielectric layer 117 is a ferroelectric material that forms the ferroelectric gate dielectric layer. For example, the ferroelectric gate dielectric layer is deposited using atomic layer deposition (ALD) technology. The deposited ferroelectric material is crystallized into a ferroelectric phase by thermal annealing. In some embodiments, the ferroelectric gate dielectric layer is a doped hafnium oxide material such as zirconium-doped hafnium oxide (HfZrO or "HZO"). The ferroelectric phase of HZO is the orthorhombic phase of the material. In some embodiments, the deposited ferroelectric gate dielectric layer (HZO film) is thermal annealed in the presence of a conductive capping layer to crystallize into a desired orthorhombic phase. In embodiments of this disclosure, the manufacturing process 300 deposits a conductive capping layer on the ferroelectric gate dielectric layer and then thermal anneals the ferroelectric gate dielectric layer. In one embodiment, the conductive capping layer is a titanium nitride layer. In one embodiment, the conductive capping layer forms a conductive liner layer of the gate conductor layer. After thermal annealing, the conductive filler of the gate conductor layer is deposited on the conductive liner layer. In another embodiment, the conductive capping layer is a sacrificial capping layer, which is removed after thermal annealing using a selective etching process on the ferroelectric gate dielectric layer 117 or the like. Next, a gate conductor layer containing a thin conductive liner (e.g., TiN) and a conductive filler (e.g., W) is deposited on the thermal annealed ferroelectric gate dielectric layer.

[0101] In one embodiment, the manufacturing process 300 forms an LWL structure within an LWL hole by depositing an oxide semiconductor channel layer 116 on a dielectric liner layer 131 and a ferroelectric gate dielectric layer 117 on the oxide semiconductor channel layer 116. An optional interface layer 125 may be deposited on the oxide semiconductor channel layer 116 before the deposition of the ferroelectric gate dielectric layer 117, for example, within the same process chamber without breaking the vacuum. Subsequently, a conductive capping layer, such as a titanium nitride (TiN) layer, is deposited on the ferroelectric gate dielectric layer 117. In some embodiments, the oxide semiconductor channel layer 116, the ferroelectric gate dielectric layer 117, and the conductive capping layer are deposited within the same process chamber without breaking the vacuum between deposition processes. In some embodiments, the conductive capping layer also functions as a thin conductive liner layer 118a of the gate conductor layer. In other embodiments, the conductive capping layer is a sacrificial capping layer that is removed after annealing. After depositing the ferroelectric gate dielectric layer 117 and the conductive capping layer, the manufacturing process 300 performs an annealing treatment to crystallize the ferroelectric gate dielectric layer 117. In one embodiment, a rapid thermal annealing (RTA) process is used, in which the annealing treatment is performed in a nitrogen (N2) atmosphere at an annealing temperature of 400-500°C for 30 seconds to 15 minutes. In another embodiment, an RTA process is used in which a 4 nm HZO layer and a 3 nm TiN conductive capping layer are used as the ferroelectric gate dielectric layer, and the annealing treatment is performed at an annealing temperature of 475°C for 8 to 10 minutes. In one embodiment, after the annealing treatment, the manufacturing process 300 deposits the conductive filler material layer 118b (e.g., W) of the gate conductor layer 118 onto the conductive liner layer 118a (e.g., TiN). In yet another embodiment, after the annealing treatment, the manufacturing process 300 removes the sacrificial capping layer using a selective etching process or the like for the ferroelectric gate dielectric layer 117. Next, the manufacturing process 300 deposits a gate conductor layer 118 on the annealed ferroelectric gate dielectric layer 117.As described above, the gate conductor layer 118 may include a thin conductive liner layer 118a (e.g., TiN) and a conductive filler material layer 118b (e.g., W).

[0102] After the formation of the LWL structure, the manufacturing process 300 proceeds to the step of forming slit trenches in the multilayer stack (Figure 12, step 310). Referring to Figure 13E, a cap oxide film 142 is formed on the memory structure 10. Subsequently, the memory structure 10 is patterned using a masking layer (not shown) to define the memory stack and define the region in which the slit trenches will be formed. A selective anisotropic dry etching process is performed to etch through the multilayer stack (including the cap oxide layer 142) to form the slit trenches 119. This divides the memory structure 10 into mesas corresponding to the memory stack for forming NOR strings of memory transistors. Note that the etching process for forming the slit trenches 119 is performed only through the multilayer stack and does not interact with conductive or metallic layers. For example, the etching process for forming the slit trenches 119 is performed between the stepped contacts of a stepped structure (if present), but does not intersect with the stepped contacts themselves. In one embodiment, the etching process for forming the slit trench 119 is a high aspect ratio dry etching process.

[0103] After the formation of the slit trench 119 that isolates the memory stack, the manufacturing process 300 proceeds to the step of performing metal replacement through the slit trench to form a common drain line (bit line) and a common source line (source line) (Figure 12, step 312). First, referring to Figure 13F, the metal replacement process is initiated by removing the first sacrificial layer and the second sacrificial layer within each active layer. The first sacrificial layer 122 and the second sacrificial layer 124 can be removed, for example, using a selective dry etching or selective wet etching process, thereby forming a cavity 133 between the channel spacer dielectric layer 113 and the interlayer sacrificial layer 120. The first dielectric liner layer 131 acts as an etching stop layer for removing the first sacrificial layer 122 and the second sacrificial layer 124. In this way, the removal of the first sacrificial layer 122 and the second sacrificial layer 124 is stopped on the first dielectric liner layer 131, and the channel layer 116 is protected during the etching process. Subsequently, the first dielectric liner layer 131 is removed through the cavity 133, thereby exposing the back surface of the channel layer 116. In one example, the first sacrificial layer 122 and the second sacrificial layer 124 are silicon nitride layers and are removed using a selective wet etching process with high-temperature phosphoric acid. In another example, the first dielectric liner layer 131 is a silicon dioxide layer and is removed using a wet etching process such as hydrofluoric acid (HF). Note that if the etching stop layer 126 is a silicon nitride layer, care must be taken not to etch and remove the silicon nitride etching stop layer 126. For example, after the etching process to form the slit trench 119, a processing step can be incorporated to form a cap layer on the sidewall of the etching stop layer 126, which is a silicon nitride layer. For example, the cap layer can be a silicon dioxide layer. In this way, even if the first sacrificial layer 122 and the second sacrificial layer 124, which are silicon nitride layers, are removed, the silicon nitride etching stop layer 126 will not be removed.

[0104] The remaining channel spacer dielectric layer 113 and interlayer sacrificial layer 120 are generally less than 30 nm thick and between 30 nm and 60 nm long. The channel spacer dielectric layer 113 and interlayer sacrificial layer 120 are held in place by bonding to the first dielectric liner layer 131, channel layer 116, ferroelectric layer 117, and conductive liner 168. The channel spacer dielectric layer 113 and interlayer sacrificial layer 120 are supported by rigid metallic vertical local word structures. The vertical local word structures are repeated at a predetermined pitch along the entire length of each metal stack in the Y direction (as shown in Figure (i) of Figure 13F). The feature of having strong mechanical support by metallic local word line structures throughout the entire depth of a very tall and narrow memory stack provides physical stability to the memory stack, thereby enabling scaling up the height of the memory stack, even for memory structures with very high aspect ratios.

[0105] Next, as shown in Figure 13G, a conductive layer 134 is deposited in the cavity 133 to replace the removed first and second sacrificial layers. For example, the conductive layer 134 can be deposited using atomic layer deposition or chemical vapor deposition. Prior to the conductive layer deposition process, surface oxidation of the exposed back surface of the channel layer 116 can be removed without damaging the channel layer. In the conductive layer deposition process, excess conductive material is formed on the side walls 135 of the slit trench and on the upper part 136 of the memory structure 100. The excess conductive material is removed by a dry etching process or CMP, etc. In one example, the excess material is removed by a selective dry etching process, and optionally, any remaining metal residue or stringer is then removed by a selective wet etching process. Figure 13H shows the resulting memory structure. More specifically, the metal replacement process forms conductive layers 112 and 114 in the cavity 133. In one embodiment, conductive layers 112 and 114 are each a titanium nitride-lined tungsten (TiN / W) layer. As a result of the metal substitution process, the first conductive layer 112 and the second conductive layer 114 are formed in each active layer that contacts the oxide semiconductor channel layer 116 and are separated from each other by a channel spacer dielectric layer 113. In each active layer 101, the first conductive layer 112 functions as the common drain layer (bit line) of the formed NOR-type memory string, and the second conductive layer 114 functions as the common source line (source line). In some embodiments, the first conductive layer 112 and the second conductive layer 114 are each a metal layer, and may be a titanium nitride (TiN)-lined tungsten (W) layer, a tungsten (W)-lined tungsten nitride (WN) layer, a molybdenum layer, a cobalt layer, or any of the other conductive materials described above.

[0106] After the metal substitution process, the manufacturing process 300 proceeds to the step of performing vertical channel separation through a slit trench (Figure 12, step 314). Referring to Figure 13I, the interlayer sacrificial layer 120 is removed to form a cavity 137. Depending on the material used for the interlayer sacrificial layer 120, various removal processes can be used. For example, if the interlayer sacrificial layer 120 is a carbon layer, the carbon layer can be removed by ashing in an oxygen atmosphere. If the interlayer sacrificial layer 120 is silicon oxide or silicon germanium, selective wet or dry etching processes can be used. The dielectric liner layer 131 is then also removed through the cavity 137, for example by a wet etching process. As a result, a portion of the oxide semiconductor channel layer 116 is exposed in the interlayer region. The exposed portion of the oxide semiconductor channel layer 116 is removed by a dry etching process or a wet etching process, etc. In one example, the exposed portion of the oxide semiconductor channel layer 116 is removed using an atomic layer etching (ALE) process. Figure 13J shows the resulting structure. The dotted circle 138 indicates the region where the channel layer 116 has been removed. By removing the channel layer 116 from the interlayer region, the channel layer 116 is separated into each memory transistor formed in each active layer. That is, the channel layer 116 is separated in the Z direction relative to each active layer 101.

[0107] In some embodiments, the channel layer 116 is an oxide semiconductor material such as IGZO, and in the manufacturing process 300, the exposed portion of the channel layer 166 is selectively etched by a wet etching process using, for example, sulfuric acid, citric acid, acetic acid, hydrochloric acid, or ammonium hydroxide (NH4OH). In some embodiments, the memory structure 100 includes an interface layer 125, and since etching of the back surface of the channel layer 116 is selective to the interface layer 125, the interface layer 125 acts as an etching stop layer in the etching process of the back surface of the channel layer 116. That is, the exposed portion of the channel layer 116 is etched through the slit trench 119 and cavity 137, and this etching process stops when it reaches the interface layer 125. In one embodiment, the interface layer 125 is an aluminum oxide (Al2O3) layer. In another embodiment, the back surface etching process can be carried out as a multi-step etching process including an atomic layer etching step used to remove the last 1 nm to 2 nm of the channel layer. This atomic layer etching step stops at either the interface layer 125 or the ferroelectric gate dielectric layer 117. In some embodiments, the interface layer 125 may be partially or completely removed during the etching process. The presence or absence of the interface layer 125 in the interlayer insulating region does not affect the performance of the memory transistor.

[0108] In another embodiment, the exposed portion of the channel layer 116 between two adjacent active layers 101 (in the Z direction) in the memory stack can be partially removed, leaving a thin portion that does not effectively function as a parasitic channel conductor.

[0109] In the embodiment shown in Figure 13J, the channel isolation process stops when the exposed portion of the channel layer 166 is removed, the channel region is physically (completely or partially) isolated, and each active layer 101 in each memory stack is insulated from one another. In another embodiment, the channel isolation process can be continued to remove the exposed portion of the ferroelectric gate dielectric layer 117 by changing the chemical composition or process of the etching solution. Figure 13J1 shows the memory structure after the exposed portion of the ferroelectric gate dielectric layer 117 has been removed through the cavity 137. Isolation of the ferroelectric gate dielectric layer 117 is optional and may be omitted in other embodiments of this disclosure. The dotted circle 139 indicates the region where the ferroelectric gate dielectric layer 117 and the interface layer 125 (if present) have been removed. Removal of the ferroelectric gate dielectric layer 117 in the interlayer region has the advantage of preventing lateral movement of polarization regions or lateral movement of oxygen atoms between memory transistors in planes adjacent to each other in the vertical direction.

[0110] The manufacturing process 300 proceeds to a step of passivating or insulating the memory structure thus formed (Figure 12, step 316). Referring to Figure 13K, in this embodiment, a dielectric layer is filled into the cavity 137 of the interlayer region to form an interlayer insulating layer 115 between adjacent active layers 101 in the Z direction. In some embodiments, the interlayer insulating layer 115 is an oxygen-containing dielectric layer. In one embodiment, the interlayer insulating layer 115 is a silicon dioxide layer. In some embodiments, the interlayer insulating layer 115 is deposited using atomic layer deposition techniques. By depositing the interlayer insulating layer 115 in the interlayer cavity, dielectric material 154 is also deposited on the sidewalls of the slit trench 119. After the deposition of the interlayer insulating layer 115, excess material can be removed from the top of the memory structure using, for example, chemical mechanical polishing (CMP). In some examples, the CMP process removes the cap oxide layer 142. The CMP process is stopped at an etching stop layer 126, which serves as a CMP stop layer. Therefore, the memory stack is passivated or insulated by the deposition of the interlayer insulating layer 115.

[0111] Subsequently, as shown in Figure 13L, the manufacturing process 300 proceeds to the step of filling the slit trench with a dielectric layer 151. In this case, the memory structure 100 is completely filled with a dielectric layer such as a silicon dioxide layer. After depositing the dielectric layer 151 in the slit trench and performing a CMP process to remove excess material from the top of the memory structure, a cap oxide layer 152 is deposited on the memory structure to complete the insulation of the memory structure 100.

[0112] In other embodiments, the manufacturing process 300 may form air gap insulation within the slit trenches 119. Referring to Figure 13M, dielectric material 154 is deposited on the sidewalls of the slit trenches 119, and an interlayer insulating layer 115 is deposited in the interlayer cavity. Then, a non-formal deposition process is performed to form a dielectric layer 155, such as a silicon dioxide layer, which seals the top of the memory structure. This non-formal deposition process forms a dielectric layer 155 that seals the top of each slit trench 119, and the cavities of the slit trenches 119 are left unfilled to be used as air gap insulation 153. Subsequently, a CMP process removes excess material deposited in the non-formal deposition process from the top of the memory structure, and then a cap oxide layer 152 is deposited on the memory structure 100b. In embodiments of this disclosure, the memory structure can be formed using dielectric-filled trenches 151 (Figure 3L) or air gap insulation 152 (Figure 3M) for insulation between memory stacks. The following explanation describes the remaining process steps using memory structure 100b, which includes air gap isolation between memory stacks.

[0113] Following the vertical channel separation process, the manufacturing process 300 proceeds to the step of forming contacts from the stepped structure to the common drain layer (bit wire) (Figure 12, step 317). In this description, the stepped contacts to the common drain layer are referred to as "CB contacts". Specifically, the manufacturing process 300 can form contact openings in the stepped structure by a dry etching process or the like. The contact openings are formed through the sealing oxide layer to each step of the stepped structure so as to connect to the first conductive layer 112 of each active layer 101. Next, the contact openings are filled with a conductive layer. In some embodiments, the conductive layer is a tungsten layer lined with titanium nitride (TiN / W). The stepped contact structures, CB contacts and CC contacts, are shown in Figure 6.

[0114] Next, the manufacturing process 300 proceeds to the step of forming a global word line (GWL) that connects to the local word line structures within the memory structure (Figure 12, step 318). Various methods can be used to form the global word line. In this embodiment, the global word line is formed on top of the memory structure 100b. In the embodiment shown in Figure 13N, vias 156 for connecting to the gate conductor layer of each LWL structure are formed in the cap oxide layer 152. Next, a conductive layer 158 is formed on the cap oxide layer, in contact with the vias 156 to form the global word line. The global word line 158 extends in the X direction and is electrically connected to one local word line structure in each memory stack. In one embodiment, the vias 156 are formed of tungsten and the global word line 158 is formed of copper. In other embodiments, as will be described in detail later, the global word line can be formed using a damascene process, a single patterning process, or a double patterning process. In some embodiments, as will be described in detail later, a memory structure can be formed that includes a global word line formed at the bottom of the memory structure (for example, within a semiconductor substrate) and a global word line formed at the top of the memory structure.

[0115] In this embodiment, the manufacturing process 300 can form the stepped contact connection portion simultaneously with the global word line. That is, the masking process for forming the global word line can define the region for forming the connector for connecting the CC contact and the CB contact. Alternatively, the conductive layer for the global word line can be deposited simultaneously to connect the CC contact of each contact opening to the CB contact. The stepped contact structure of the CB contact and CC contact is shown in Figure 6.

[0116] Using the manufacturing process described above, a memory structure comprising a three-dimensional array of NOR-type memory strings of channel-all-around ferroelectric memory transistors is manufactured. The above description describes a manufacturing process flow for forming a stepped structure connected only to the common drain layer. However, it should be understood that the manufacturing process can be adapted to form a stepped structure connected to both the common drain layer and the common source layer, as shown in Figures 10 and 11.

[0117] In embodiments of this disclosure, the memory structure comprises a ferroelectric memory transistor formed using an oxide semiconductor layer as a channel layer. In the embodiments described above, the oxide semiconductor channel layer is formed using a single oxide semiconductor material deposited in hole openings forming a columnar local word line structure. In some embodiments, the oxide semiconductor channel layer is formed as a two-layer channel including a first oxide semiconductor layer formed on the sidewall of the columnar local word line structure, and a second oxide semiconductor layer formed between the first oxide semiconductor layer and a conductive layer forming the drain / source line. The second oxide semiconductor layer is in electrical contact with the first oxide semiconductor layer and functions as a two-layer channel region of the ferroelectric memory transistor. The second oxide semiconductor layer is also in electrical contact with the conductive layer forming the drain and source line and functions as a low-contact-resistance contact layer between the drain / source conductive layer and the first oxide semiconductor layer. On the other hand, the first oxide semiconductor layer functions as a main channel layer that provides the channel region of the ferroelectric memory transistor with desired high mobility and high on-current.

[0118] In some embodiments, the second oxide semiconductor is a metal oxide semiconductor material that provides a lower contact resistance to the bit-line / source-line (or source / drain) conductive layer than that provided by the first oxide semiconductor layer. In one embodiment, the first oxide semiconductor layer is an indium gallium zinc oxide (IGZO) layer with a thickness of approximately 6 nm, and the second oxide semiconductor layer is an indium aluminum zinc oxide (InAlZnO or IAZO) layer, an indium aluminum oxide (IAO) layer, an indium oxide (InO) layer, or an indium tin oxide (ITO) layer with a thickness of less than 3 nm. In some embodiments, the thickness of the second oxide semiconductor layer is approximately 1 nm to 2 nm. In other embodiments, other oxide semiconductor materials that provide a desirable low contact resistance to the bit-line / source-line conductive layer can be used as the second oxide semiconductor layer. In some embodiments, it is desirable to use a metal oxide semiconductor material as the second oxide semiconductor layer that has high resistance to deoxygenation of the channel layer by the source / drain conductive layer and suppresses oxidation of the source / drain conductive layer during heat treatment.

[0119] Figure 14 is a cross-sectional view of a memory structure of a channel-all-around ferroelectric memory transistor in another embodiment of the present disclosure. The memory structure of Figure 14 is substantially similar to the memory structure of Figure 3B, except that it includes a second oxide semiconductor layer as a contact layer for the source conductive layer / drain conductive layer. Similar components in Figures 3B and 14 are given the same reference numerals, and detailed descriptions are omitted. Referring to Figure 14, the memory structure 400 includes a channel-all-around ferroelectric memory transistor 20 formed at the intersection of a bit-line conductive layer 22, a source-line conductive layer 24, and a columnar local word-line structure 13. In this embodiment, a second oxide semiconductor layer 35 is formed between the oxide semiconductor channel layer 26 and the bit-line conductive layer 22 and the source-line conductive layer 24. Specifically, one side of the second oxide semiconductor layer 35 is in contact with the oxide semiconductor channel layer 26, and the other side is in contact with the bit-line conductive layer 22 or the source-line conductive layer 24. The second oxide semiconductor layer 35 configured in this way functions as a contact layer between the oxide semiconductor layer 26 and the bit line conductive layer 22 or the source line conductive layer 24. The second oxide semiconductor layer 35 is formed from an oxide semiconductor material that provides lower contact resistance to the bit line conductive layer 22 and the source line conductive layer 24 than the oxide semiconductor channel layer 26.

[0120] In embodiments of this disclosure, the second oxide semiconductor layer 35 can be formed during a metal substitution process, such as step 312 of the manufacturing process 300 (Figure 12). More specifically, after removing the first and second sacrificial layers and the dielectric liner layer, the second oxide semiconductor layer 35 is deposited on the exposed surfaces in the cavity exposed by the removal of the first and second sacrificial layers. Specifically, the second oxide semiconductor layer 35 is deposited conformally on all exposed surfaces of the memory structure 400. Prior to the deposition process, surface oxidation of the exposed back surface of the channel layer 26 can be removed without damaging the channel layer 26. In some embodiments, the second oxide semiconductor layer 35 is deposited using an atomic layer deposition (ALD) process. In some embodiments, the second oxide semiconductor layer 35 is formed of a different material than the material forming the first oxide semiconductor layer 26. In some embodiments, the second oxide semiconductor layer 35 is formed using an amorphous oxide semiconductor material such as indium aluminum zinc oxide (InAlZnO or IAZO), indium aluminum oxide (IAO), indium oxide (InO), indium zinc oxide (IZO), or indium tin oxide (ITO), or other suitable oxide semiconductor material. In other embodiments, both the first oxide semiconductor layer 26 and the second oxide semiconductor layer 35 are indium gallium zinc oxide (IGZO) layers, but with different elemental ratios. That is, the first oxide semiconductor layer 26 is an indium gallium zinc oxide (IGZO) layer having a first elemental ratio of indium, gallium, and zinc, and the second oxide semiconductor layer 35 is an indium gallium zinc oxide (IGZO) layer having a second elemental ratio of indium, gallium, and zinc, where the first and second elemental ratios are different from each other. In some embodiments, the thickness of the second oxide semiconductor layer 35 is less than 3 nm, for example, about 1 nm to 2 nm.

[0121] After depositing the second oxide semiconductor layer 35, a conductive layer is deposited on the memory structure 400 to form the bit line conductive layer 22 and the source line conductive layer 24. In some embodiments, the conductive layer is deposited using chemical vapor deposition or atomic layer deposition. After the deposition of the conductive layer, excess material formed on the sidewalls of the slit trench 19 and on the upper surface of the memory structure 400 is removed by a selective dry etching process, and optionally subsequently by a selective wet etching process to remove any remaining metal residue or stringer. Meanwhile, excess material of the second oxide semiconductor layer 35 formed on the sidewalls of the slit trench 19 is also removed by the same process as the conductive material removal or by a different process. Subsequent channel separation, passivation, and global word line formation can be carried out using the methods described above with reference to the manufacturing process 300 in Figure 12. The resulting structure is shown in Figure 14. The bit line / source line conductive layer and the second oxide semiconductor layer thus formed are separated / insulated from each other into separate layers. Specifically, in this embodiment, each bit line / source line conductive layer is partially surrounded by each isolation portion (insulating portion) of the second oxide semiconductor layer by forming it using the ALD process.

[0122] In the memory structure 400, the bit line conductive layer 22 and the source line conductive layer 24 are separated from each other by the channel spacer dielectric layer 23. Each isolated portion (insulating portion) of the second oxide semiconductor layer 35 is in electrical contact with its corresponding bit line conductive layer 22 or source line conductive layer 24, but is insulated from other isolated portions of the second oxide semiconductor layer 35. Each isolated portion of the second oxide semiconductor layer 35 is in physical and electrical contact with its corresponding portion of the first oxide semiconductor layer 26, thereby forming a two-layer channel of the ferroelectric memory transistor. In each active layer 16, the bit line conductive layer 22 forms the common drain line of the NOR-type memory string, and the source line conductive layer 24 forms the common source line of the NOR-type memory string. In some embodiments, the bit wire conductive layer 22 and the source wire conductive layer 24 are metal layers, and may be a tungsten (W) layer lined with titanium nitride (TiN), a tungsten (W) layer lined with tungsten nitride (WN), a molybdenum layer, a cobalt layer, or any of the other conductive materials mentioned above.

[0123] In the embodiments described above with reference to Figures 5 and 6, each memory stack of the memory structure is formed to extend over the entire distance between the first stepped structure 46a and the second stepped structure 46b. In another embodiment, each memory stack can be divided in half to form shorter common drain and common source lines. Figure 15 is a top view of a memory structure in another embodiment of the present disclosure, including stepped structures connected to a common bit line and a common source line. Figure 16 is a cross-sectional view of the memory structure of Figure 15, including stepped structures connected to a common bit line and a common source line, in an embodiment of the present disclosure. With reference to Figures 15 and 16, the memory structure 40b includes a three-dimensional array of NOR-type memory strings of channel-all-around ferroelectric memory transistors formed within a multilayer memory stack. The memory structure 40b includes a plurality of memory stacks arranged in the X direction and separated from each other by slit trenches 45. Each memory stack includes a plurality of active layers 50 separated from each other in the Z direction by interlayer insulating layers 51. Each active layer 50 includes a first conductive layer as a common drain line or bit line, a second conductive layer as a common source line or source line, and a channel spacer dielectric layer interposed between the first and second conductive layers. In this embodiment, the memory stack is divided into a first memory stack portion 44a and a second memory stack portion 44b. The first memory stack portion 44a and the second memory stack portion 44b are separated by a slit trench 59. Thus, the common drain line of the first memory stack portion 44a is isolated / insulated from the common drain line of the second memory stack portion 44b. With this configuration, the first memory stack portion 44a and the second memory stack portion 44b include a first memory array portion 42a or a second memory array portion 42b having columnar local word line structures 56 for forming channel all-around ferroelectric memory transistors at each intersection with the active layer 50.Furthermore, the first memory stack portion 44a and the second memory stack portion 44b further include a precharge array portion 43a or a precharge array portion 43b, which includes a columnar precharge local word line structure 58 for forming channel-all-around type non-memory transistors at each intersection with the active layer 50.

[0124] By separating the memory stack into a first memory stack portion 44a and a second memory stack portion 44b, the common drain and common source lines for the memory strings within each active layer 50 can be shortened, which has the advantage of reducing the resistance and capacitance of the common drain line (bit line of the memory transistor). As a result, the RC delay of the bit line is reduced, and the access time of the memory transistor is improved. In the memory structure 40b, the memory strings of the first memory array portion 42a are accessed by the first stepped structure 46a, and the memory strings of the second memory array portion 42b are accessed by the second stepped structure 46b. The first stepped structure 46a and the second stepped structure 46b provide access to the common drain line of each active layer 50.

[0125] In embodiments of the present disclosure, columnar local word line structures within a memory array are connected to global word lines to receive bias voltages from circuits within CuA in order to perform memory operations. Various techniques can be used to form global word lines in the memory structures of the present disclosure.

[0126] In the embodiments described above, the global word line is formed on top of the memory structure after the manufacturing process that forms the active layer and local word line structures of the memory stack. In the first embodiment, the global word line is formed as a single layer on top of the memory structure. In one embodiment, if the pitch of the local word line structures is small or approaches the limits of photolithography, e.g., about 55 nm, the single layer global word line can be formed using a self-aligned double patterning technique. Figures 17A and 17B are a top view and a cross-sectional view, respectively, of a memory structure including a single layer global word line in several embodiments. Referring first to Figure 17A, a memory structure is shown having memory stacks 140a and 140b separated from each other by a slit trench 119. Memory stacks 140a and 140b include a NOR string in which local word line structures 103 are arranged in two rows, and the local word line structures 103 in each row are arranged alternately with respect to the local word line structures 103 in the adjacent row. Each global word line 158 is positioned across memory stacks 140a and 140b so as to contact one local word line structure 103 within each memory stack. When the global word lines 158 are formed in a single layer in this way, they have a pitch P1 that is the same as the pitch of the local word line structures. If the pitch P1 is small or if there are limitations to photolithography, the global word lines 158 can be formed using double patterning techniques.

[0127] Figure 17B shows a cross-sectional view of the memory stack along the BB' line. Referring to Figure 17B, after the formation of the active layer 101, a double patterning layer is deposited and patterned to form a mandrel. Then, using the formed mandrel, an oxide layer 152 having openings to receive the conductive layer is patterned using a damascene process. For example, in some embodiments, the conductive layer is a copper layer. In this way, a single-layer global word line 158 is formed that connects to each local word line structure 103 in the memory stack.

[0128] In a second embodiment, the global word line is formed as two conductive layers on top of the memory structure. Figures 18A and 18B are a top view and a cross-sectional view of a memory structure including two layers of global word lines in several embodiments, respectively. Referring first to Figure 18A, a memory structure is shown having memory stacks 140a and 140b separated from each other by a slit trench 119. Memory stacks 140a and 140b include NOR strings in which local word line structures 103 are arranged in two rows, and the local word line structures 103 in each row are arranged alternately with respect to the local word line structures 103 in the adjacent row. Each lower global word line 163 is positioned across memory stacks 140a and 140b so as to be in contact with one of the first group of local word line structures 103 in each memory stack. Each upper-layer global word line 167 is positioned across memory stacks 140a and 140b so as to contact one of the second group of local word line structures 103 within each memory stack. By forming the global word lines in two layers in this way, the pitch P2 of the global word lines can be made larger than the pitch P1 of a single-layer global word line.

[0129] Figure 18B shows a cross-sectional view of the memory stack along the BB' line. Referring to Figure 18B, after the formation of the active layer 101, a dielectric layer 152 is formed on top of the memory structure. Then, shallow vias 161 are formed within the dielectric layer 152 for connecting to the first group of local word line structures 103. Subsequently, an additional patterning layer is formed on top of the memory structure to form the lower global word lines 163. In one embodiment, the lower global word lines 163 are formed by a damascene process. In another embodiment, the lower global word lines 163 are formed using dielectric spacers (not shown) before forming the filling dielectric layer 162. Next, an interlayer insulating layer 164 is formed on the lower global word lines 163. Then, deep vias 165 are formed in the interlayer insulating layer 164 for connecting to the second group of local word line structures 103. Finally, an additional patterning layer is formed on top of the memory structure to form the upper global word lines 167. In one embodiment, the upper global word lines 167 are formed by a damascene process. In some embodiments, both the shallow via 161 and the deep via 165 are tungsten-filled vias. The lower global word line 163 and the upper global word line 167 are conductive layers such as copper. With this configuration, the lower global word line 163 is connected to a first group of local word line structures 103, and the upper global word line 167 is connected to a second group of local word line structures 103. By increasing the pitch of the lower global word line 163 and the upper global word line 167, the manufacturing process can be simplified and the electrical characteristics of the electrical connections can be improved.

[0130] In a third embodiment, the global word line is formed as an upper conductive layer provided at the top of the memory array and a bottom conductive layer provided at the bottom of the memory array. Figures 19A, 19B, and 19C are a top view, a cross-sectional view, and an enlarged cross-sectional view of a memory structure including the upper conductive layer (upper global word line) and bottom conductive layer (bottom global word line) of the global word line in several embodiments, respectively. Figures 19D to 19K are cross-sectional views of the memory structure of Figures 19A to 19C and show the manufacturing process for forming the upper conductive layer and bottom conductive layer of the global word line in several embodiments. First, referring to Figure 19A, a memory structure is shown having memory stacks 140a and 140b separated from each other by a slit trench 119. Memory stacks 140a and 140b contain NOR-type strings in which local word line structures 103 are arranged in two columns, and each column of local word line structures 103 is arranged alternately with respect to the local word line structures 103 of the adjacent column. Referring to the top view of Figure 19A, each upper global word line 176 is positioned across memory stacks 140a and 140b so as to contact one of the first group of local word line structures 103 in each memory stack. Each bottom global word line 170 is positioned across memory stacks 140a and 140b so as to contact one of the second group of local word line structures 103 in each memory stack. With this configuration, the pitch P2 of the global word lines can be made larger than the pitch P1 of the single-layer global word lines.

[0131] Figure 19B shows a cross-sectional view of a memory stack along line BB'. Figure 19C shows a detailed view of the bottom global word line in several embodiments. Referring to Figures 19B and 19C, first, the bottom global word line 170 is formed on the semiconductor substrate 102. That is, when fabricating a CuA circuit within the semiconductor substrate 102, the bottom global word line 170 is formed along a desired global word line connection path. Subsequently, for example, at the start of fabricating a memory array on the semiconductor substrate 102, one or more dielectric layers are formed on the semiconductor substrate 102 and on the bottom global word line 170. Next, bottom vias 172 are formed to connect to the bottom global word line 170. Then, conductive landing pads 174 are formed, aligned with the positions where local word line structures are formed and aligned with the bottom vias 172. In this embodiment, conductive landing pads 174 are provided for all local word line structures, even if only a subset of the local word line structures are connected to the bottom global word line. Therefore, a subset of the conductive landing pads described above is positioned in alignment with the vias 172 to connect to the bottom global word lines 170. Conductive landing pads 174 that are not connected to any of the bottom global word lines are dummy landing pads. The landing pads 174 can also function as etching stop layers for the etching process of the holes used to form the local word line structure.

[0132] Subsequently, the memory array is manufactured using the method described above. First, as shown in Figure 19D, holes are formed in the multilayer stack during the manufacturing process of the local word line structure, up to a landing pad 174 which functions as an etching stop layer. Next, the memory transistor device layer is deposited. In some embodiments, a dielectric liner layer (not shown in this figure) is first deposited in the hole openings. Then, as shown in Figure 19E, the channel layer 116 and the ferroelectric gate dielectric layer 117 are deposited in the holes. In some embodiments, after the deposition of the channel layer 116 and the ferroelectric gate dielectric layer 117 (with or without an optional interface layer 125), a conductive capping layer is deposited on the ferroelectric gate dielectric layer 117 (see Figure 19E). Subsequently, the ferroelectric gate dielectric layer 117 is annealed. In some embodiments, the annealing is a rapid thermal annealing process performed in a nitrogen (N2) atmosphere at an annealing temperature of 400-500°C for 30 seconds to 15 minutes. After annealing, a punch-through etching process is performed to etch the conductive capping layer at the bottom of the LWL hole, as shown by the dotted line in Figure 19F. Then, as shown in Figure 19G, the local word line device layers, including the ferroelectric dielectric layer, interface layer (if present), oxide semiconductor channel layer, and dielectric liner layer, are removed from the bottom of the LWL hole, for example, by an isotropic etching process. In some embodiments, the conductive capping layer remains on the annealed ferroelectric gate dielectric layer 117 and acts as a protective layer for the ferroelectric dielectric layer during the etching process. All local word line structures are treated in the same manner to form openings to the conductive landing pad 174. After the openings to the conductive landing pad 174 are formed, the conductive capping layer is removed, for example, by a selective etching process on the ferroelectric gate dielectric layer 117. Next, as shown in Figure 19H, a gate conductor layer 118, including a gate conductor liner layer 118a and a gate conductor filling layer 118b, is deposited in the central portion of the local word line structure (i.e., inside the ferroelectric gate dielectric layer 117). The gate conductor layer 118 extends to the conductive landing pad 174.In other embodiments, as shown in Figure 19I, the conductive capping layer can be left in place to function as a gate conductor liner layer, in which case the gate conductor layer 118 includes only the conductive filler material layer 118b. For example, the conductive capping layer may be a titanium nitride (TiN) layer with a thickness of 2-3 nm, and the gate conductor layer 118 may include a tungsten layer to fill the remaining space of the LWL hole. If the conductive landing pad 174 is connected to the bottom via 172, the local word line structure is connected to the bottom global word line 170. Otherwise, the local word line structure is connected to a dummy conductive landing pad.

[0133] The manufacturing process of the memory structure continues through the slit opening, metal replacement, and channel replacement processes described above. The resulting structure is shown in Figure 19J. After the formation of the active layer of the memory structure, an upper global word line 176 is formed on top of the memory structure, connected to a subset of local word line structures that are not connected to the bottom global word line, as shown in Figure 19K. For example, an oxide layer 152 having openings to accept a conductive layer is patterned using a damascene process. For example, in some embodiments, the conductive layer is a copper layer. In this way, the upper global word line 176 is formed, connected to the above subset of local word line structures 103 in the memory stack. In this way, the first group of local word line structures are connected to the upper global word line 176, and the second group of local word line structures are connected to the bottom global word line 170. By increasing the pitch of the upper global word line and the bottom global word line, the manufacturing process can be simplified, and the electrical characteristics of the electrical connections can be improved.

[0134] In embodiments of this disclosure, the memory device is manufactured by forming closely arranged columnar local word line structures within a multilayer stack, as described above with reference to Figure 13A. For example, a masking layer, such as an amorphous hard masking layer, is patterned using photolithography techniques or a mask-opening process to define hole openings in the hard masking layer. These hole openings correspond to LWL holes formed within the memory structure. In some embodiments, hole openings can be defined in the masking layer using single-exposure photolithography techniques. Figures 20(a) and 20(b) show methods for patterning hole openings in a hard masking layer using single-mask, single-exposure photolithography in some embodiments. Specifically, Figure 20(a) shows a mask having a mask pattern that can be used to define hole openings in a masking layer using single-mask, single-exposure photolithography in some embodiments. Figure 20(b) shows hole openings formed on a masking layer using the mask of Figure 20(a) in several embodiments. First, referring to Figure 20(a), the mask 502 has a hole opening pattern 506 defined for patterning hole openings on a patterning layer such as a photoresist layer. The hole opening pattern 506 is arranged in two rows and alternately (staggered) in the Y direction. The dimensions of the hole opening pattern 506 are 55 nm, and the spacing in the Y direction is 55 nm. The hole opening pattern 506 is formed in a region 504 corresponding to the region in the memory structure where the memory stack is formed.

[0135] Figure 20(b) shows a masking layer 512, such as an amorphous hard masking layer, formed on the memory structure 510 in the intermediate processing step. The masking layer 512 is patterned using a mask 502 to form hole openings corresponding to the hole opening pattern 506. Referring to both Figures 20(a) and 20(b), in the manufacturing process, after the formation of the multilayer stack of the memory structure 510 (e.g., the multilayer stack shown in Figure 13A), the masking layer 512, such as an amorphous hard masking layer, is formed on the multilayer stack. Additional masking layers, such as an anti-reflective coating (e.g., SiON), an additional carbon-containing masking layer (e.g., SOC or spin-on carbon), and / or an additional silicon-containing masking layer (e.g., SOG or spin-on glass), may be formed on the masking layer 512. Finally, a patterning layer, such as a photoresist layer, is formed on the masking layer 512. The mask 502 is used in the photolithography process to print a mask pattern 506 onto a photoresist layer. For example, the photoresist layer is exposed using the mask 502, and then developed after exposure. In one example, immersion lithography can be used. Next, the developed or patterned photoresist layer is used to transfer the mask pattern 506 to one or more masking layers until the mask pattern 506 is transferred to a masking layer 512 (hard masking layer). This process is also called the mask opening process.

[0136] As a result of the mask opening process, hole openings 516 are formed in the masking layer 512. Note that the hole opening pattern 506 drawn on the mask 502 is square, but the pattern printed on the patterning layer using the photolithography process is circular. Therefore, the mask pattern transferred to the masking layer 512 will be circular hole openings 516 corresponding to the square hole opening pattern 506 of the mask 502. The circular hole openings 516 are patterned on the masking layer 512 using the photolithography process and the mask opening process. Then, as in the method described with reference to Figure 13B, the patterned masking layer 512 is used in a high aspect ratio etching process to form LWL holes in the multilayer stack.

[0137] In the example shown in Figure 20(a), the dimensions of the hole openings are 55 nm, and the spacing in the Y direction is 55 nm. The pitch in the X direction of the formed memory stack and slit trenches is 224 nm. The spacing "d1" between adjacent hole opening patterns arranged in a staggered pattern is small, at 17 nm, making hole opening positioning a challenge in the photolithography process. This small spacing makes it difficult to accurately print the hole opening patterns using general photolithography techniques.

[0138] In other embodiments of this disclosure, multi-patterning photolithography techniques are used to form hole openings in a memory structure. Multi-patterning photolithography techniques reduce process complexity and enable the formation of higher density patterns (e.g., pitches of 35 nm or less). Figures 21(a) and 21(b) show methods for patterning hole openings in a hard masking layer using two-mask two-exposure photolithography in several embodiments. Specifically, Figure 21(a) shows two masks having mask patterns that can be used to define hole openings within a masking layer using two-mask two-exposure photolithography in several embodiments. Figure 21(b) shows hole openings formed on the masking layer using the masks of Figure 21(a) in several embodiments. In one embodiment, a multi-patterning photolithography technique called litho-freeze litho-etching (LFLE) is used. First, referring to Figure 21(a), the first mask 522 has a first line space pattern 526 defined on it, and the second mask 523 has a second line space pattern 528 defined on it. In Figure 21(a), the two masks are shown superimposed. The first line space pattern 526 of the first mask 522 and the second line space pattern 528 of the second mask 523 are oriented at an angle of 45 degrees with respect to the central axis along the Y direction (Y axis). More specifically, the first mask 522 has a first line space pattern 526 oriented at an angle of 45 degrees counterclockwise with respect to the Y axis. The second mask 523 has a second line space pattern 528 oriented at an angle of 45° clockwise with respect to the Y axis (or an angle of 135° counterclockwise with respect to the Y axis). Then, the hole opening pattern 530 is defined at a position where the first line space pattern 526 of the first mask 522 and the second line space pattern 528 of the second mask 523 are oriented at a 90-degree angle to each other (i.e., at a position that is orthogonal to each other).

[0139] By using multi-patterning photolithography techniques, narrow spacing between hole aperture patterns can be avoided. In the example shown in Figure 21(a), the linespace pattern has a line width of 45 nm and a spacing of 33 nm. 45 nm dimension hole aperture patterns can be formed without concern for narrow spacing between hole aperture patterns. In some embodiments, multi-patterning photolithography techniques can be applied to pattern conductive landing pads in the semiconductor layer below the memory array to form bottom global word lines. The following description describes multi-patterning photolithography techniques as an example of forming hole apertures in a multilayer stack to form LWL holes.

[0140] Figure 21(b) shows a masking layer 542, such as an amorphous hard masking layer, formed on the memory structure 540 in an intermediate processing step. The masking layer 542 is patterned using a first mask 522 and a second mask 523 to form hole openings corresponding to the first line space pattern 526 and the second line space pattern 528. Referring to both Figures 21(a) and 21(b), in the manufacturing process, after the formation of the multilayer stack of the memory structure 540 (e.g., the multilayer stack shown in Figure 13A), the masking layer 542, such as an amorphous hard masking layer, is formed on the multilayer stack. Additional masking layers, such as an anti-reflective coating (e.g., SiON), an additional carbon-containing masking layer (e.g., SOC or spin-on carbon), and / or an additional silicon-containing masking layer (e.g., SOG or spin-on glass), may be formed on the masking layer 542.

[0141] In some examples, the mask patterns of the first mask 522 and the second mask 523 can be printed on the masking layer as follows: First, a first patterning layer (e.g., a photoresist layer) is formed on the masking layer. The first mask 522 is used in a photolithography process to print a first line-space mask pattern 526 on the first patterning layer, for example, by exposing the photoresist layer using the first mask 522 and developing the photoresist layer after exposure. In one example, immersion lithography technique can be used. Next, a second patterning layer (e.g., a photoresist layer) is formed on the developed first photoresist layer. The second mask 523 is used in a photolithography process to print a second line-space mask pattern 528 on the second patterning layer, for example, by exposing the photoresist layer using the second mask 523 and developing the photoresist layer after exposure. As a result of the photolithography process using the first mask 522 and the second mask 523, a hole opening pattern 530 is formed in the region where the first line space mask pattern 526 and the second line space mask pattern 528 overlap. That is, the pattern formed in the region where the two developed photoresist layers overlap becomes the hole opening pattern 530. Next, the developed photoresist layers are used to transfer the hole opening pattern 530 to one or more masking layers until the hole opening pattern 530 is transferred to the masking layer 542 (hard masking layer) (mask opening process).

[0142] As a result of the mask opening process, hole openings 546 are formed in the masking layer 542. As described above, the hole opening pattern 530 formed in the overlapping region of the first line space mask pattern 526 and the second line space mask pattern 528 is square, but the pattern printed on the pattern layer using the photolithography process is circular. Therefore, circular hole openings 546 corresponding to the square hole opening pattern 530 are formed in the masking layer 542. Subsequently, the patterned masking layer 542 is used in a high aspect ratio etching process to form LWL holes in the multilayer stack, similar to the method described with reference to Figure 13B.

[0143] In embodiments of the present disclosure, the memory structures of the present disclosure can be incorporated into a logic integrated circuit as embedded memory. For example, an embedded memory circuit can be formed using a memory structure having one, two, four, or eight active layers. Furthermore, the memory structures of the present disclosure can be adapted as embedded memory circuits by using a smaller tile size with fewer memory transistors in the memory strings and fewer memory strings per tile. Specifically, the ferroelectric memory transistors in embodiments of the present disclosure can be operated at low bias voltages, such as voltage levels below 2V, and therefore the memory structures of the present disclosure are suitable for use as embedded memory circuits.

[0144] Figure 22 shows the application of the memory device of this disclosure as an embedded memory device in several embodiments. Referring to Figure 22, the memory device 600 is configured as described above with reference to Figures 1A to 1C. The memory device 600 includes a two-dimensional array of tiles 602, each tile 602 including a memory array which is a three-dimensional array of junctionless ferroelectric memory transistors. The memory array within each tile 602 is formed on a semiconductor substrate 606. An insulating layer 604 is provided between the semiconductor substrate 606 and the memory array (tile 602) formed thereon. The semiconductor substrate 606 is provided with support circuits (CuA) for operating the memory transistors in the memory array. In some embodiments, the support circuits for the ferroelectric memory transistors in each tile 602 are provided for modularization in the portion of the semiconductor substrate 606 below each tile 602.

[0145] In some embodiments, the memory device interacts with a memory controller to perform memory operations. As described above, the memory controller includes a control circuit for accessing and operating the memory transistors in the memory device, performing memory control functions, and controlling interface functions for host access. In some embodiments, the memory module is formed from a memory device formed on one semiconductor die and a memory controller formed on another semiconductor die. The memory die and memory controller die can be integrated using various integration techniques such as TSVs, hybrid bonds, exposed contacts, interposers, printed circuit boards, and other suitable interconnection techniques, particularly techniques for high-density interconnection.

[0146] In this embodiment, the memory controller is integrated into the semiconductor substrate of the logic integrated circuit 620. Specifically, digital or analog logic circuits 622, such as a core processor, can be formed on the logic integrated circuit 620. The memory controller circuit 624 is integrated into the logic integrated circuit 620 and formed on a portion of the semiconductor substrate of the logic integrated circuit 620. The memory device 600 is coupled to the memory controller circuit 624 and electrically connected using various bonding techniques. In this figure, the memory device 600 includes an array of connectors 608 that are coupled to corresponding mating connectors 610 formed on the logic integrated circuit 620. In some embodiments, the connectors 608 and mating connectors 610 are hybrid integrated couplings, such as copper-to-copper couplings, and may have a pitch of less than 2 μm or less than 1 μm.

[0147] The memory device 600 configured in this way operates as an embedded memory circuit within the logic integrated circuit 620 via an embedded memory controller circuit 624. The memory controller circuit 624 can directly connect to digital or analog circuits 622 on the logic integrated circuit 620 via interconnection lines 626 formed within the logic integrated circuit, without the need for an interface circuit. Therefore, the ferroelectric memory transistors in the memory device 600 can utilize the circuits of the logic integrated circuit 620 with minimal delay. That is, the memory transistors can be accessed with low latency via the interconnection lines 626 between the memory controller circuit 624 and the logic circuits 622. Such a configuration is also referred to as "in-memory computing." In-memory computing is particularly desirable in artificial intelligence and machine learning applications that are data-intensive and require large amounts of memory in close proximity to CPU and GPU core processors, which can be formed as logic circuits 622 within the logic integrated circuit 620. In embodiments of this disclosure, low latency and large capacity can be achieved in memory computing systems for data-intensive applications by forming an embedded memory circuit using a memory device 600 that includes an array of three-dimensional NOR-type memory strings of ferroelectric memory transistors. It should be noted that because ferroelectric memory transistors operate at high temperatures, the memory device 600 equipped with ferroelectric memory transistors can be embedded in the logic integrated circuit 620 by positioning it above the logic integrated circuit 620 rather than to the side of the logic integrated circuit 620. The embedded memory circuit of this disclosure achieves improved latency by eliminating RC delay caused by signal routing through an interposer.

[0148] In some embodiments, the memory device 600 may be built directly on a logic integrated circuit 620 on the same semiconductor substrate. For example, the memory device 600 may be built on an insulating layer formed on the logic integrated circuit to protect already fabricated circuits. For example, the insulating layer may be a protective layer such as a silicon oxide or polyimide layer. The electrical connection between the memory device 600 and the memory control circuit, or the direct electrical connection between the memory device 600 and other application-specific logic circuits, is provided via vias formed in the insulating layer. In this case, bonding of the memory device using connectors 608 and mating connectors 610 is not required.

[0149] In the embodiments described above with reference to Figures 1D and 1E, the ferroelectric memory transistor 20 formed within the memory structure 10 may have an interface layer 25 between the oxide semiconductor channel layer 26 and the ferroelectric polarization layer 27. This optional interface layer 25 is a thin dielectric layer and may be provided to function as a barrier layer or adhesive layer. In some embodiments, the memory structure of the present disclosure includes a ferroelectric memory transistor in which an interface dielectric layer is provided between the ferroelectric dielectric layer and the gate conductor layer. Figure 23 shows a detailed structure of a memory transistor formed within a memory structure in another embodiment of the present disclosure. Specifically, Figure 23 shows a memory structure 700 including a pair of memory transistors 720-1 and 720-2 on two adjacent faces of a memory stack. The memory structure 700 is configured similarly to the memory structures described above, except that an interface dielectric layer is provided.

[0150] Referring to Figure 23, the memory transistor 720 includes a first conductive layer 22 that forms a drain region (common drain line or common bit line) and a second conductive layer 24 that forms a source region (common source line), the first conductive layer 22 and the second conductive layer 24 being separated from each other by a channel spacer dielectric layer 23. The memory transistor 720 further includes an annular channel layer 26 formed perpendicularly along the sidewall of the columnar local word line structure and in contact with both the first conductive layer 22 and the second conductive layer 24. An annular ferroelectric gate dielectric layer 27 and a gate conductor layer 28 are formed adjacent to the annular channel layer 26. Specifically, a portion of the annular channel layer 26 is provided between the bit line 22 and the gate conductor layer 28 in the XY plane, or overlaps with them. Also, a portion of the annular channel layer 26 is provided between the source line 24 and the gate conductor layer 28 in the XY plane. In this embodiment, the channel layer 26 is an oxide semiconductor layer such as an IGZO layer. In some embodiments, the gate conductor layer 28 includes a conductive liner layer 28a (e.g., TiN) as an adhesive layer and a low-resistance conductor layer 28b (e.g., W). The memory transistor 720 is isolated from adjacent memory transistors in the memory stack by an interlayer insulating layer 15. Memory transistors configured in this way, sharing a common source line and a common bit line, form a NOR-type memory string (also referred to herein as a “horizontal NOR-type memory string” or “HNOR-type memory string”) in each memory stack.

[0151] To form a ferroelectric memory transistor, the memory transistor 720 includes a ferroelectric dielectric layer or ferroelectric polarization layer as the gate dielectric layer 27 (also referred to as the ferroelectric gate dielectric layer). For example, the ferroelectric gate dielectric layer 27 is formed from a doped hafnium oxide material such as a zirconium-doped hafnium oxide (HfZrO or "HZO") layer. The ferroelectric polarization layer 27 functions as a storage layer of the memory transistor. In this embodiment, the memory transistor 720 further includes an interface dielectric layer 755 formed between the ferroelectric gate dielectric layer 27 and the gate conductor layer 28. For example, the interface dielectric layer 755 is formed during a local word line structure fabrication process in which concentric layers of the channel layer, ferroelectric layer, interface dielectric layer, and gate conductor layer are deposited in a hole using a damascene process or atomic layer deposition (ALD). More specifically, after the deposition of the ferroelectric polarization layer 27, an interface dielectric layer 755 is conformally deposited on the annular ferroelectric polarization layer 27, and then the gate conductor layer 28 is deposited on the interface dielectric layer 755.

[0152] In some embodiments, the interface dielectric layer 755 is a thin layer and may have a thickness of 0.5 nm to 3 nm. In some embodiments, the interface dielectric layer 755 is formed using a material having a high dielectric constant (K), i.e., a high dielectric constant material (high-K material) having a dielectric constant higher than that of silicon dioxide (SiO2). In some embodiments, the interface dielectric layer 755 may be a silicon nitride (Si3N4) layer, a silicon oxynitride (Si3N4) layer, an aluminum oxide (Al2O3) layer, or a zirconium oxide (ZrO2) layer. For example, if the ferroelectric dielectric layer 27 has a thickness of 4 to 5 nm, the interface dielectric layer 755 may have a thickness of 2 nm. The interface dielectric layer 755 functions as a barrier layer for the gate conductor layer 28 of the ferroelectric memory transistor 720. The interface dielectric layer 755 is optional and may be omitted in other embodiments of this disclosure. In other embodiments, if the interface dielectric layer 755 is provided, it may be formed as a multilayer of multiple different dielectric materials.

[0153] In another aspect of the present disclosure, a perpendicular ferroelectric field-effect transistor is formed using the structure and process described above. In embodiments of the present disclosure, an integrated circuit includes a perpendicular ferroelectric field-effect transistor formed on a plane of a semiconductor substrate. For example, the perpendicular ferroelectric field-effect transistor is formed in the same way as the ferroelectric memory transistor described with reference to any of the figures described above. In one embodiment, with reference to Figures 1A to 1E as an example, the perpendicular ferroelectric field-effect transistor 20 includes a gate conductor layer 28 provided as a columnar body extending in a first direction (e.g., the Z direction), an annular ferroelectric dielectric layer 27 formed to surround the outer periphery of the gate conductor layer 28, and an annular oxide semiconductor layer 26 formed to surround the outer periphery of the annular ferroelectric dielectric layer 27. The perpendicular ferroelectric field-effect transistor 20 further includes a first conductive layer 22 and a second conductive layer 24 provided as planes parallel to the plane of the semiconductor substrate. The first conductive layer 22 and the second conductive layer 24 are provided to surround the outer periphery of the annular oxide semiconductor layer and to be in contact with the annular oxide semiconductor layer 26.

[0154] In some embodiments, the first conductive layer 22 and the second conductive layer 24 are laminated along a first direction (e.g., the Z direction) and are separated from each other by the first insulating layer 23.

[0155] Each vertical ferroelectric field-effect transistor is formed at the intersection of the first conductive layer 22 and the second conductive layer 24 and the annular oxide semiconductor layer 26. The first conductive layer 22 forms the drain region of the vertical ferroelectric field-effect transistor, and the second conductive layer 24 forms the source region of the vertical ferroelectric field-effect transistor. The oxide semiconductor layer 26 forms a junction-less channel region, and the annular ferroelectric dielectric layer 27 forms the gate dielectric layer of the vertical ferroelectric field-effect transistor. The gate conductor layer 28 forms the gate electrode of the vertical ferroelectric field-effect transistor. For example, each vertical ferroelectric field-effect transistor is formed within a memory structure as shown in Figures 1A to 1C, and in more detail in Figures 1D and 1E.

[0156] In another embodiment, an array of memory strings is formed, each including a plurality of vertical ferroelectric field-effect transistors formed on a plane of a semiconductor substrate. For example, each vertical ferroelectric field-effect transistor is formed similarly to the ferroelectric memory transistor described with reference to any of the figures above. In one embodiment, with reference to Figures 1A to 1E as an example, each ferroelectric field-effect transistor 20 includes a gate conductor layer 28 provided as a columnar body extending in a first direction (e.g., the Z direction) substantially perpendicular to the plane of the semiconductor substrate, an annular ferroelectric dielectric layer 27 formed to surround the outer periphery of the gate conductor layer 28, and an annular oxide semiconductor layer 26 surrounding the outer periphery of the annular ferroelectric dielectric layer 27. Each ferroelectric field-effect transistor 20 further includes a first conductive layer 22 and a second conductive layer 24 provided as planes parallel to the plane of the semiconductor substrate. The first conductive layer 22 and the second conductive layer 24 are arranged to overlap each other along the first direction (Z direction) and are separated from each other by a first insulating layer 23. The first conductive layer 22 and the second conductive layer 24 are provided so as to surround the outer periphery of the cyclic oxide semiconductor layer and to be in contact with the cyclic oxide semiconductor layer 26.

[0157] Each vertical ferroelectric field-effect transistor is formed at the intersection of the first conductive layer 22, the second conductive layer 24, and the annular oxide semiconductor layer 27. The first conductive layer 22 forms the drain region of the vertical ferroelectric field-effect transistor, and the second conductive layer 24 forms the source region of the vertical ferroelectric field-effect transistor. The oxide semiconductor layer 26 forms the junction-less channel region, and the annular ferroelectric dielectric layer forms the gate dielectric layer of the vertical ferroelectric field-effect transistor. The gate conductor layer 28 forms the gate electrode of the vertical ferroelectric field-effect transistor.

[0158] In some embodiments, the array of memory strings relates to a stack of memory strings stacked on top of each other in a first direction (e.g., the Z direction), and each memory string in the stack relates to a plurality of ferroelectric field-effect transistors extending in a second direction (e.g., the Y direction). The array of memory strings also further includes a plurality of columnar gate conductor layers arranged in the second direction and corresponding to each ferroelectric field-effect transistor along each memory string. With such a configuration, vertical ferroelectric field-effect transistors throughout the stack of memory strings are formed along each gate conductor layer and aligned vertically. The vertically aligned ferroelectric field-effect transistors are electrically isolated from one or more adjacent ferroelectric field-effect transistors by a second isolation layer 15.

[0159] In this specification, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” are used to facilitate the description of the relationship between one component and another as shown in the drawings. It should be understood that such spatially relative terms are intended to encompass various orientations or settings of the device in use or operation, in addition to the directions or settings shown in the drawings. For example, if the device in the drawing is turned upside down, a component described as being located “below” or “directly below” another component would be located “above” the other component. Therefore, the exemplary term “below” can encompass both the “above” and “below” directions or settings. Furthermore, the device may be oriented in other settings (e.g., rotated 90 degrees, or any other orientation), and the spatially relative terms used herein shall be interpreted accordingly.

[0160] When it is stated that one component or layer is “placed on,” “connected to,” or “joined” another component or layer, it should be understood that it may be “directly” “placed on,” “connected to,” or “joined” the other component or layer, or there may be an intermediary component or layer between the two components or layers. In contrast, when it is stated that one component or layer is “directly placed on,” “directly connected to,” or “directly joined” another component or layer, there is no intermediary component or layer between the two components or layers.

[0161] In this detailed description, process steps described in one embodiment may be used in another embodiment even if they are not explicitly described in another embodiment. Where this specification refers to a method including two or more defined steps, the defined steps may be performed in any order or simultaneously, unless the context indicates or specific instructions are otherwise provided herein. Furthermore, unless the context indicates or specific instructions are otherwise provided, the method may also include one or more other steps performed before any defined step, between two defined steps, or after all defined steps.

[0162] In this detailed description, various embodiments or examples of the present invention can be carried out in various forms, such as processes, apparatus, systems, and compositions of materials. A detailed description of one or more embodiments of the present invention is provided above, along with accompanying drawings illustrating the principles of the present invention. Although the present invention has been described in relation to such embodiments, the present invention is not limited to any embodiment. Various modifications and variations are possible within the scope of the present invention. The scope of the present invention is limited only by the appended claims, and the present invention encompasses various alternative forms, modifications, and equivalents. In order to provide a complete understanding of the present invention, numerous specific details are described herein. These details are provided for illustrative purposes only, and the present invention can be carried out in accordance with the claims without some or all of these specific details. For clarity, technical matters known in the art relating to the present invention are not described in detail so as not to unnecessarily obscure the present invention. The present invention is defined by the appended claims.

Claims

1. A three-dimensional memory structure formed on a semiconductor substrate, A plurality of memory stacks arranged along a first direction substantially parallel to the plane of the semiconductor substrate, wherein each memory stack is separated from adjacent memory stacks along the first direction by trenches, each memory stack and each trench extends in a second direction perpendicular to the first direction and substantially parallel to the plane of the semiconductor substrate, each memory stack includes a plurality of active layers arranged along a third direction substantially perpendicular to the plane of the semiconductor substrate, each active layer includes a first conductive layer and a second conductive layer stacked together in the third direction and separated from each other by a first insulating layer, and each active layer is separated from adjacent active layers along the third direction by a second insulating layer, the plurality of memory stacks, Each of the memory stacks is provided as a columnar body extending in the third direction, wherein each local word line structure is surrounded by a first conductive layer and a second conductive layer, and each local word line structure includes concentric layers of an oxide semiconductor layer, a ferroelectric dielectric layer, and a gate conductor layer, and the oxide semiconductor layer is provided in a region overlapping with the first conductive layer and the second conductive layer, surrounding the local word line structure and in contact with the first conductive layer and the second conductive layer, and the local word line structure is provided in such a region, Each active layer in the memory stack forms a plurality of thin-film ferroelectric memory transistors configured as a NOR-type memory string. Each of the thin-film ferroelectric memory transistors is formed at a position where the active layer and the local word line structure intersect, forming a three-dimensional memory structure.

2. A three-dimensional memory structure according to claim 1, Each thin-film ferroelectric memory transistor in each NOR-type memory string shares a first conductive layer that functions as a common drain line and a second conductive layer that functions as a common source line. A three-dimensional memory structure in which the oxide semiconductor layer provided in a region overlapping with the first conductive layer and the second conductive layer, in contact with the first conductive layer and the second conductive layer, functions as a junction-less channel region of each thin-film ferroelectric memory transistor within each NOR-type memory string.

3. A three-dimensional memory structure according to claim 1, Each of the memory stacks includes a series of local word line structures arranged in a single column extending in the second direction, A three-dimensional memory structure in which each active layer within each memory stack forms a NOR-type memory string of thin-film ferroelectric memory transistors.

4. A three-dimensional memory structure according to claim 1, Each of the memory stacks includes a series of local word line structures arranged in two or more columns that are aligned in the first direction and extend in the second direction. The local word line structure within each of the aforementioned columns and the local word line structure in adjacent columns are offset in the second direction. A three-dimensional memory structure in which each active layer within each memory stack forms a NOR-type memory string of thin-film ferroelectric memory transistors.

5. A three-dimensional memory structure according to claim 4, Each of the local word line structures arranged in two or more columns within each memory stack is connected to each global word line extending in the first direction. A three-dimensional memory structure in which each of the two or more local word line structures arranged in the memory stack is connected to a different global word line.

6. A three-dimensional memory structure according to claim 5, The global word line is a three-dimensional memory structure formed in a single layer on the upper surface of the three-dimensional memory structure.

7. A three-dimensional memory structure according to claim 5, The global word line includes a lower global word line and an upper global word line formed in two layers on the upper surface of the three-dimensional memory structure. The lower global word line and the upper global word line are connected to the alternating local word line structures arranged in two or more columns within the memory stack, forming a three-dimensional memory structure.

8. A three-dimensional memory structure according to claim 5, The global word line includes a bottom global word line formed on the semiconductor substrate and an upper global word line formed on the upper surface of the three-dimensional memory structure. The bottom global word line and the upper global word line are connected to alternating local word line structures arranged in two or more columns within the memory stack. The bottom global word line is connected to the gate conductor layer of each local word line structure within or on the surface of the semiconductor substrate, forming a three-dimensional memory structure.

9. A three-dimensional memory structure according to claim 1, A three-dimensional memory structure in which, within the memory stack, the oxide semiconductor layer of the local word line structure does not exist in the region between two adjacent active layers in the third direction.

10. A three-dimensional memory structure according to claim 1, A three-dimensional memory structure in which, within the memory stack, the oxide semiconductor layer of the local word line structure is partially removed in the region between two adjacent active layers in the third direction.

11. A three-dimensional memory structure according to claim 9, A three-dimensional memory structure in which, within the memory stack, the ferroelectric dielectric layer of the local word line structure does not exist in the region between two adjacent active layers in the third direction.

12. A three-dimensional memory structure according to claim 1, The oxide semiconductor layer comprises one of the following: an indium gallium zinc oxide (IGZO) layer, an indium zinc oxide (IZO) layer, an indium tungsten oxide (IWO) layer, or an indium tin oxide (ITO) layer, in a three-dimensional memory structure.

13. A three-dimensional memory structure according to claim 1, The ferroelectric dielectric layer comprises a three-dimensional memory structure containing a doped hafnium oxide layer.

14. A three-dimensional memory structure according to claim 1, Each of the local word line structures further includes an interface layer formed as a concentric layer between the oxide semiconductor layer and the ferroelectric dielectric layer, comprising a three-dimensional memory structure.

15. A three-dimensional memory structure according to claim 14, The aforementioned interface layer is made of silicon nitride (Si ３ N ４ ) layer or aluminum oxide (Al ２ O ３ A three-dimensional memory structure that includes any of the ) layers.

16. A three-dimensional memory structure according to claim 1, The first insulating layer is silicon dioxide (SiO ２ A three-dimensional memory structure including layers.

17. A three-dimensional memory structure according to claim 1, The above-mentioned second insulating layer is a three-dimensional memory structure comprising an oxygen-containing dielectric layer or an air gap cavity lined with a dielectric liner.

18. A three-dimensional memory structure according to claim 1, A three-dimensional memory structure in which each of the first conductive layer and the second conductive layer includes a metal layer.

19. A three-dimensional memory structure according to claim 1, The gate conductor layer comprises a conductive layer selected from titanium nitride or tungsten nitride, in a three-dimensional memory structure.

20. A three-dimensional memory structure according to claim 1, The gate conductor layer is a three-dimensional memory structure comprising a first metal layer formed on the ferroelectric dielectric layer and a second metal layer formed on the first metal layer.

21. A three-dimensional memory structure according to claim 20, The first metal layer comprises a metal layer selected from titanium nitride or tungsten nitride. The three-dimensional memory structure comprises a second metal layer selected from tungsten or molybdenum.

22. A three-dimensional memory structure according to claim 1, The gate conductor layer comprises a highly doped N-type polysilicon layer or a highly doped P-type polysilicon layer, in a three-dimensional memory structure.

23. A three-dimensional memory structure according to claim 1, A three-dimensional memory structure in which the channel length of each thin-film ferroelectric memory transistor is a function of the thickness of the first insulating layer in the third direction.

24. A three-dimensional memory structure according to claim 23, The thickness of the first insulating layer in the third direction is in the range of 10 to 30 nm. A three-dimensional memory structure.

25. A three-dimensional memory structure according to claim 1, A three-dimensional memory structure in which the channel width of each thin-film ferroelectric memory transistor is a function of the outer periphery length of the oxide semiconductor layer of the local word line structure.

26. A three-dimensional memory structure according to claim 2, The aforementioned common source line is an electrically floating, three-dimensional memory structure.

27. A three-dimensional memory structure according to claim 26, The NOR-type memory string further comprises a plurality of non-memory transistors formed within each of the aforementioned NOR-type memory strings, The aforementioned non-memory transistor is designated as a pre-charge transistor, The precharge transistor is activated during precharge operation to electrically connect the first conductive layer and the second conductive layer in each NOR-type memory string to each other, and the voltage on the second conductive layer is made equal to the voltage on the first conductive layer, in a three-dimensional memory structure.

28. A three-dimensional memory structure according to claim 27, A plurality of precharged local word line structures are provided within each memory stack as columnar bodies extending in the third direction, each precharged local word line structure is surrounded by a first conductive layer and a second conductive layer, each precharged local word line structure includes concentric layers of an oxide semiconductor layer, a nonpolar gate dielectric layer, and a gate conductor layer, and the oxide semiconductor layer is provided in a region overlapping with the first conductive layer and the second conductive layer, surrounding the local word line structure and in contact with the first conductive layer and the second conductive layer, further comprising the precharged local word line structure. The precharge transistor is formed at the position where the active layer and the precharge local word line structure intersect in a three-dimensional memory structure.

29. A three-dimensional memory structure according to claim 1, The three-dimensional memory structure further comprises a first stepped structure provided at the first end in the second direction of the three-dimensional memory structure, and a second stepped structure provided at the second end in the second direction of the three-dimensional memory structure, The first stepped structure connects the first conductive layer in every other active layer within the plurality of memory stacks to a circuit formed in the semiconductor substrate. The second stepped structure is a three-dimensional memory structure that connects the first conductive layer in other active layers within the plurality of memory stacks to a circuit formed in the semiconductor substrate.

30. A three-dimensional memory structure according to claim 1, The three-dimensional memory structure further comprises a first stepped structure provided at the first end in the second direction of the three-dimensional memory structure, and a second stepped structure provided at the second end in the second direction of the three-dimensional memory structure, The first stepped structure connects the first conductive layer in each of the active layers in the plurality of memory stacks to a circuit formed in the semiconductor substrate. The second stepped structure is a three-dimensional memory structure that connects the second conductive layer in each of the active layers in the plurality of memory stacks to a circuit formed in the semiconductor substrate.

31. A three-dimensional memory structure according to claim 1, The plurality of memory stacks are divided into a first memory stack portion and a second memory stack portion by a second trench extending in the first direction. The three-dimensional memory structure further comprises a first stepped structure provided at the first end of the three-dimensional memory structure in the second direction, and a second stepped structure provided at the second end of the three-dimensional memory structure in the second direction. The first stepped structure connects the first conductive layer in each active layer of the first memory stack portion to a circuit formed in the semiconductor substrate. The second stepped structure is a three-dimensional memory structure that connects the first conductive layer in each active layer of the second memory stack portion to a circuit formed on the semiconductor substrate.

32. A three-dimensional memory structure according to claim 1, A three-dimensional memory structure in which a circuit for supporting the memory operation of the thin-film ferroelectric memory transistors is formed on the plane of the semiconductor substrate approximately directly below the plurality of memory stacks.

33. A three-dimensional memory structure according to claim 2, The gate conductor layer is biased to a first voltage value with respect to the common drain line in order to perform a write operation on the thin-film ferroelectric memory transistor and bring it to a first logic state. The gate conductor layer is biased to a second voltage value with respect to the common drain line in order to perform an erase operation on the thin-film ferroelectric memory transistor and bring it to a second logic state. A three-dimensional memory structure in which the first voltage value and the second voltage value have opposite voltage polarities and different voltage magnitudes.

34. A three-dimensional memory structure according to claim 2, A three-dimensional memory structure in which, in each of the thin-film ferroelectric memory transistors within the NOR-type memory string, the common drain line and the common source line are biased to substantially the same voltage in order to perform a write operation or erase operation on the thin-film ferroelectric memory transistor.

35. A three-dimensional memory structure according to claim 2, The gate conductor layer is biased to a third voltage value with respect to the common drain line in order to partially polarize the thin-film ferroelectric memory transistor and bring it to a first logic state. A three-dimensional memory structure in which the gate conductor layer is biased to a fourth voltage value with respect to the common drain line in order to partially polarize the thin-film ferroelectric memory transistor and bring it into a second logic state.

36. A three-dimensional memory structure according to claim 1, The plurality of memory stacks and the local word line structures formed within the memory stacks are three-dimensional memory structures having dimensions that are scalable in the first and second directions.

37. A three-dimensional memory structure according to claim 1, The local word line structure, provided as a columnar body, is arranged as a two-dimensional array in a plane defined by the first direction and the second direction. A three-dimensional memory structure in which each local word line structure in each column along the second direction of the two-dimensional array is offset in the second direction with respect to the adjacent local word line structures in other columns.

38. A three-dimensional memory structure according to claim 1, A three-dimensional memory structure characterized in that the local word line structure provided as a columnar body has a circular shape in a plane defined by the first direction and the second direction.

39. A three-dimensional memory structure according to claim 1, The local word line structure, provided as a columnar body, has an elliptical shape in the plane defined by the first direction and the second direction. The ellipse is a three-dimensional memory structure having a minor axis and a major axis in the plane defined by the first direction and the second direction.

40. A three-dimensional memory structure according to claim 39, A three-dimensional memory structure in which the major axis of the ellipse extends parallel to the first direction or the second direction.

41. A three-dimensional memory structure according to claim 1, The oxide semiconductor layer formed as a concentric layer within the local word line structure includes a first oxide semiconductor layer. Each active layer in the plurality of memory stacks includes a second oxide semiconductor layer having a first isolation portion and a second isolation portion. (i) The first isolation portion of the second oxide semiconductor layer partially surrounds the first conductive layer and is in contact with the first conductive layer, and the second isolation portion of the second oxide semiconductor layer partially surrounds the second conductive layer and is in contact with the second conductive layer, and the first conductive layer and the second conductive layer are separated from each other by the first insulating layer. (ii) A three-dimensional memory structure wherein the first and second isolation portions of the second oxide semiconductor layer are in contact with the first oxide semiconductor layer of the local word line structure, and the second oxide semiconductor layer is made of a material different from the material forming the first oxide semiconductor layer.

42. A three-dimensional memory structure according to claim 41, The first oxide semiconductor layer comprises indium gallium zinc oxide (IGZO), The second oxide semiconductor layer comprises an oxide semiconductor material selected from indium aluminum oxide (IAO), indium oxide (InO), indium zinc oxide (IZO), and indium tin oxide (ITO), in a three-dimensional memory structure.

43. A three-dimensional memory structure according to claim 41, The first oxide semiconductor layer has a first thickness, The second oxide semiconductor layer has a second thickness that is thinner than the first thickness, in a three-dimensional memory structure.

44. A three-dimensional memory structure according to claim 1, The local word line structure further includes an interface layer formed as a concentric layer between the ferroelectric dielectric layer and the gate conductor layer, comprising a three-dimensional memory structure.

45. A three-dimensional memory structure according to claim 44, The interface layer is a silicon nitride (Si ３ N ４ ), aluminum oxide (Al ２ O ３ ), or zirconium oxide (ZrO ２ ) layer, and includes any one of them, a three-dimensional memory structure.

46. A method suitable for use in manufacturing a memory structure comprising memory transistors of a NOR type memory string on a semiconductor substrate, A step of forming a multilayer film stack by alternately stacking multilayers and interlayer sacrificial layers on the plane of the semiconductor substrate, wherein each multilayer includes a first sacrificial layer, a second sacrificial layer, and a first insulating layer interposed between the first and second sacrificial layers, the multilayer film stack extends in a first and second direction which are orthogonal to each other and substantially parallel to the plane of the semiconductor substrate, and the multilayers and interlayer sacrificial layers are stacked in a third direction which is substantially orthogonal to the plane of the semiconductor substrate, A step of forming a plurality of holes in the multilayer stack that penetrate the multilayer and the interlayer sacrificial layer and extend in the third direction, wherein the plurality of holes include a first plurality of holes formed in the memory array region, A step of forming a local word line structure in each of the first plurality of holes, comprising the step of forming concentric layers of a dielectric liner layer, an oxide semiconductor layer, a ferroelectric dielectric layer, and a gate conductor layer in each of the first plurality of holes, A step of dividing the multilayer film stack into a plurality of memory stacks by forming a plurality of trenches in the multilayer film stack, wherein each memory stack includes a subset of the local word line structure formed within the stack, each memory stack is separated from adjacent memory stacks along a first direction by one of the plurality of trenches, each memory stack and each trench extends in a second direction, and each memory stack includes the multilayer and the interlayer sacrificial layer arranged in a third direction, A step of replacing the first sacrificial layer and the second sacrificial layer with a first conductive layer and a second conductive layer using access through the plurality of trenches, wherein the first conductive layer and the second conductive layer are in contact with the oxide semiconductor layer of each local word line structure in each memory stack, The steps include removing the interlayer sacrificial layer using access through the plurality of trenches to expose a portion of the oxide semiconductor layer formed on the outer periphery of the local word line structure formed in the first plurality of holes, A method comprising the step of removing at least a portion of the exposed portion of the oxide semiconductor layer using access through the plurality of trenches.

47. The method according to claim 46, A method wherein each local word line structure within each memory stack is surrounded by the first conductive layer and the second conductive layer.

48. The method according to claim 46, The step of replacing the first sacrificial layer and the second sacrificial layer with the first conductive layer and the second conductive layer using access through the plurality of trenches is, The steps include removing the first sacrificial layer and the second sacrificial layer using access through multiple trenches to expose a portion of the dielectric liner layer, The steps include removing the exposed portion of the dielectric liner layer and exposing a portion of the oxide semiconductor layer by using access through the plurality of trenches and the cavity formed by the removal of the interlayer sacrificial layer, A method comprising the step of forming a first conductive layer and a second conductive layer in a cavity formed by removing the first sacrificial layer, the second sacrificial layer and the dielectric liner layer using access through the plurality of trenches, wherein the first conductive layer and the second conductive layer are in contact with the oxide semiconductor layer of each local word line structure in each memory stack.

49. The method according to claim 48, The step of removing the interlayer sacrificial layer to expose a portion of the oxide semiconductor layer is, The steps include removing the interlayer sacrificial layer using access through the plurality of trenches to expose a portion of the dielectric liner layer, The steps include removing the exposed portion of the dielectric liner layer and exposing a portion of the oxide semiconductor layer by using the access through the plurality of trenches and the cavity formed by the removal of the interlayer sacrificial layer, A method comprising the step of removing at least a portion of the exposed portion of the oxide semiconductor layer using access through the plurality of trenches and the cavity formed by the removal of the interlayer sacrificial layer.

50. The method according to claim 46, A step of forming a dielectric layer on the memory structure, wherein the dielectric layer includes cavities exposed by the removal of the interlayer sacrificial layer and cavities exposed by the plurality of trenches, A step of forming a masking layer on the upper surface of the memory structure, wherein the upper surface of the memory structure is the surface opposite to the semiconductor substrate, and the masking layer exposes the gate conductor layer of the local word line structure in the plurality of memory stacks. A method further comprising the step of forming a global word line on the upper surface of the memory structure using the masking layer, wherein the global word line extends in the first direction and contacts the gate conductor layer of the local word line structure across the plurality of memory stacks, and each global word line contacts the gate conductor layer of one of the local word line structures in each of the memory stacks.

51. The method according to claim 46, The steps include forming a dielectric layer in the cavity exposed by removing the interlayer sacrificial layer and on the side walls of the plurality of trenches, A step of forming an insulating cap layer covering the plurality of trenches on the upper part of the plurality of trenches, wherein the upper part of the plurality of trenches is the part opposite to the semiconductor substrate, and A method further comprising the step of forming air gap insulation by the remaining cavities of the plurality of trenches and the cavities formed by the removal of the interlayer sacrificial layer.

52. The method according to claim 51, A step of forming a masking layer on the upper surface of the memory structure, wherein the upper surface of the memory structure is the surface opposite to the semiconductor substrate, and the masking layer exposes the gate conductor layer of the local word line structure in the plurality of memory stacks. A method further comprising the step of forming a global word line on the upper surface of the memory structure using the masking layer, wherein the global word line extends in the first direction and contacts the gate conductor layer of the local word line structure across the plurality of memory stacks, and each global word line contacts the gate conductor layer of one of the local word line structures in each of the memory stacks.

53. The method according to claim 46, A method further comprising a step of forming an interface layer as a concentric layer between the oxide semiconductor layer and the ferroelectric dielectric layer.

54. The method according to claim 53, The step of removing at least a portion of the exposed portion of the oxide semiconductor layer using access through the plurality of trenches is: A method comprising the step of removing the exposed portion of the oxide semiconductor layer by using the interface layer as an etching stop layer with access through the plurality of trenches.

55. The method according to claim 53, The aforementioned interface layer is made of silicon nitride (Si ３ N ４ ) layer or aluminum oxide (Al ２ O ３ A method that includes any of the layers.

56. The method according to claim 46, The step of forming the local word line structure in each of the first plurality of holes is: The steps include: depositing the dielectric liner layer on the side walls of the first plurality of holes using atomic layer deposition; The steps include depositing the oxide semiconductor layer on the dielectric liner layer in the first plurality of holes using atomic layer deposition, The steps include: depositing the ferroelectric dielectric layer on the oxide semiconductor layer in the first plurality of holes using atomic layer deposition; A method comprising the step of depositing the gate conductor layer on the ferroelectric dielectric layer in the first plurality of holes using atomic layer deposition.

57. The method according to claim 56, A method for depositing the oxide semiconductor layer and the ferroelectric dielectric layer without breaking the vacuum between the deposition steps.

58. The method according to claim 46, The plurality of holes include a second plurality of holes formed in a precharge array region provided adjacent to the memory array region along the second direction, This method is A step of forming a precharged local word line structure in each of the second plurality of holes, further comprising the step of forming concentric layers of an oxide semiconductor layer, a nonpolar gate dielectric layer, and a gate conductor layer in each of the second plurality of holes, A method wherein each memory stack includes one or more local word line structures and one or more precharged local word line structures.

59. The method according to claim 46, The method wherein each memory stack includes a series of local word line structures arranged in a single column extending in the second direction.

60. The method according to claim 46, Each of the memory stacks includes a series of local word line structures arranged in two or more columns that are aligned in the first direction and extend in the second direction. A method wherein the local word line structure within each of the columns is offset in the second direction with respect to the local word line structure in an adjacent column.

61. The method according to claim 46, The method wherein the oxide semiconductor layer comprises one of the following: an indium gallium zinc oxide (IGZO) layer, an indium zinc oxide (IZO) layer, an indium tungsten oxide (IWO) layer, or an indium tin oxide (ITO) layer.

62. The method according to claim 46, The method wherein the ferroelectric dielectric layer comprises a doped hafnium oxide layer.

63. The method according to claim 46, The first insulating layer is silicon dioxide (SiO ２ A method including a layer.

64. The method according to claim 46, A method wherein each of the first conductive layer and the second conductive layer includes a metal layer.

65. The method according to claim 46, The method wherein the gate conductor layer includes a first metal layer formed on the ferroelectric dielectric layer and a second metal layer formed on the first metal layer.

66. The method according to claim 65, The first metal layer comprises a metal layer selected from titanium nitride or tungsten nitride. The method wherein the second metal layer comprises a metal layer selected from tungsten or molybdenum.

67. The method according to claim 46, The steps include: performing a thermal annealing treatment on the ferroelectric dielectric layer after depositing the ferroelectric dielectric layer and the conductive capping layer; A method further comprising the step of depositing a conductive filler material after performing the thermal annealing treatment to form the gate conductor layer.

68. The method according to claim 46, The steps include: performing a thermal annealing treatment on the ferroelectric dielectric layer after depositing the ferroelectric dielectric layer and the conductive capping layer; After performing the thermal annealing treatment, the step of removing the conductive capping layer, A method further comprising the step of depositing the gate conductor layer on the ferroelectric dielectric layer that has been heat-annealed.

69. The method according to claim 46, The process further includes the steps of forming a first stepped structure at the first end of the multilayer stack in the second direction, and forming a second stepped structure at the second end of the memory structure in the second direction, The first stepped structure connects the first conductive layer in every other multilayer to a circuit formed on the semiconductor substrate. The second stepped structure is a method for connecting the first conductive layer in the other multilayer to a circuit formed on the semiconductor substrate.

70. The method according to claim 46, The process further includes the steps of forming a first stepped structure at the first end of the multilayer stack in the second direction, and forming a second stepped structure at the second end of the memory structure in the second direction, The first stepped structure connects the first conductive layer within each of the multilayers to a circuit formed on the semiconductor substrate. The second stepped structure is a method for connecting the second conductive layer within each of the multilayers to a circuit formed on the semiconductor substrate.

71. The method according to claim 46, A method wherein the multilayer film stack and the local word line structure formed in the plurality of holes have dimensions that are scalable in the first direction and the second direction.

72. The method according to claim 46, The step of forming the plurality of holes in the multilayer film stack is, The step includes forming the plurality of holes so as to be arranged as a two-dimensional array in a plane defined by the first direction and the second direction, A method wherein each hole in each column of the two-dimensional array along the second direction is offset in the second direction with respect to each hole in an adjacent column.

73. The method according to claim 46, The step of forming the plurality of holes in the multilayer film stack is, A method comprising the step of forming a plurality of holes having a circular shape in a plane defined by the first direction and the second direction.

74. The method according to claim 46, The step of forming the plurality of holes in the multilayer film stack is, The process includes the step of forming a plurality of holes having an elliptical shape in a plane defined by the first and second directions, A method wherein the ellipse has a major axis and a minor axis in the plane defined by the first direction and the second direction.

75. The method according to claim 74, The step of forming the plurality of holes having an elliptical shape is, A method comprising the step of forming the ellipse such that its major axis is parallel to the first direction or the second direction.

76. The method according to claim 46, The concentric layers of the oxide semiconductor layer formed in the local word line structure include a first oxide semiconductor layer. The step of replacing the first sacrificial layer and the second sacrificial layer with the first conductive layer and the second conductive layer is, The steps include removing the first sacrificial layer and the second sacrificial layer using access through the plurality of trenches to expose a portion of the first oxide semiconductor layer, A method comprising the step of forming a second oxide semiconductor layer adjacent to the first oxide semiconductor layer of the local word line structure using access through the plurality of trenches and the cavity formed by the removal of the interlayer sacrificial layer, and forming a conductive layer in the remaining cavity formed by the removal of the first and second sacrificial layers, wherein the conductive layer is in contact with the second oxide semiconductor layer, the second oxide semiconductor layer is in contact with the first oxide semiconductor layer, and the first and second oxide semiconductor layers are formed from different oxide semiconductor materials.

77. The method according to claim 76, The first oxide semiconductor layer comprises indium gallium zinc oxide (IGZO), The method wherein the second oxide semiconductor layer comprises an oxide semiconductor material selected from indium aluminum oxide (IAO), indium oxide (InO), indium zinc oxide (IZO), and indium tin oxide (ITO).

78. The method according to claim 46, The step of forming the plurality of holes in the multilayer film stack is, A method comprising the step of forming a plurality of holes using a multi-patterning photolithography method using a first mask and a second mask, wherein the first mask and the second mask define a line space pattern offset from each other in a second direction with respect to a central axis, and the overlapping region of the first mask and the second mask defines hole openings corresponding to the plurality of holes.

79. The method according to claim 46, A method further comprising the step of forming an interface layer as a concentric layer between the ferroelectric dielectric layer and the gate conductor layer.

80. The method according to claim 79, The aforementioned interface layer is made of silicon nitride (Si ３ N ４ ) layer, aluminum oxide (Al ２ O ３ ) layer, or zirconium oxide (ZrO ２ A method that includes any of the layers.

81. An integrated circuit comprising a vertical ferroelectric field-effect transistor formed on the plane of a semiconductor substrate, The ferroelectric field-effect transistor is A columnar gate conductor layer is provided as a columnar body extending in a first direction substantially perpendicular to the plane of the semiconductor substrate, An annular ferroelectric dielectric layer formed so as to surround the columnar gate conductor layer and A ring-shaped oxide semiconductor layer formed so as to surround the aforementioned ring-shaped ferroelectric dielectric layer, A first conductive layer and a second conductive layer provided on the semiconductor substrate as planes parallel to the plane, wherein the first conductive layer and the second conductive layer are stacked along the first direction, separated from each other by a first insulating layer, surround the outer periphery of the annular oxide semiconductor layer, and are in contact with the annular oxide semiconductor layer, The ferroelectric field-effect transistor is formed at a position where the first conductive layer, the second conductive layer, and the annular oxide semiconductor layer intersect. The first conductive layer forms a drain region, The second conductive layer forms a source region, The aforementioned cyclic oxide semiconductor layer forms a junction-less channel region. The aforementioned annular ferroelectric dielectric layer forms a gate dielectric layer. The columnar gate conductor layer forms the gate electrode of the ferroelectric field-effect transistor in the integrated circuit.

82. The integrated circuit according to claim 81, The aforementioned cyclic oxide semiconductor layer is provided in the region between the first conductive layer and the second conductive layer and the cyclic ferroelectric dielectric layer. The aforementioned cyclic oxide semiconductor layer includes a first portion and a second portion. The first portion of the annular oxide semiconductor layer is provided between the first conductive layer and the annular ferroelectric dielectric layer in a second direction parallel to the plane of the semiconductor substrate, The second portion of the annular oxide semiconductor layer is provided between the second conductive layer and the annular ferroelectric dielectric layer in the second direction, in an integrated circuit.

83. The integrated circuit according to claim 81, The ferroelectric field-effect transistor includes a first ferroelectric field-effect transistor among the plurality of ferroelectric field-effect transistors formed along the columnar gate conductor layer, The plurality of ferroelectric field-effect transistors are stacked on top of each other in the first direction, An integrated circuit in which each of the ferroelectric field-effect transistors is electrically insulated from one or more adjacent ferroelectric field-effect transistors by a second insulating layer.

84. The integrated circuit according to claim 83, The plurality of ferroelectric field-effect transistors formed along the columnar gate conductor layer share the columnar gate conductor layer as a common gate electrode in an integrated circuit.

85. The integrated circuit according to claim 83, The annular oxide semiconductor layer of each ferroelectric field-effect transistor is provided in a region that overlaps with the first conductive layer and the second conductive layer of the ferroelectric field-effect transistor in a second direction parallel to the plane of the semiconductor substrate. The aforementioned cyclic oxide semiconductor layer is absent in the region between adjacent ferroelectric field-effect transistors in the integrated circuit.

86. The integrated circuit according to claim 83, An integrated circuit in which the second insulating layer between adjacent ferroelectric field-effect transistors surrounds and is in contact with the annular ferroelectric dielectric layer.

87. The integrated circuit according to claim 83, The annular oxide semiconductor layer of each ferroelectric field-effect transistor is provided in a region that overlaps with the first conductive layer and the second conductive layer of the ferroelectric field-effect transistor in a second direction parallel to the plane of the semiconductor substrate. An integrated circuit in which the aforementioned cyclic oxide semiconductor layer is removed in the region between adjacent ferroelectric field-effect transistors.

88. The integrated circuit according to claim 83, An integrated circuit in which the annular ferroelectric dielectric layer extends in the first direction across the plurality of ferroelectric field-effect transistors.

89. The integrated circuit according to claim 86, The annular oxide semiconductor layer of each ferroelectric field-effect transistor is provided in a region that overlaps with the first conductive layer and the second conductive layer of the ferroelectric field-effect transistor in a second direction parallel to the plane of the semiconductor substrate. The annular ferroelectric dielectric layer is absent in the region between adjacent ferroelectric field-effect transistors in the integrated circuit.

90. The integrated circuit according to claim 83, The ferroelectric field-effect transistor is formed on the outer periphery of the annular ferroelectric dielectric layer, An integrated circuit further comprising a cyclic interfacial dielectric layer interposed between the cyclic ferroelectric dielectric layer and the cyclic oxide semiconductor layer.

91. The integrated circuit according to claim 90, An integrated circuit in which the second insulating layer between adjacent ferroelectric field-effect transistors surrounds and contacts the annular interface dielectric layer.

92. The integrated circuit according to claim 81, The columnar gate conductor layer includes a first columnar gate conductor layer among the plurality of columnar gate conductor layers formed on the semiconductor substrate. The columnar gate conductor layers are arranged to extend in a third direction that is parallel to the plane of the semiconductor substrate and perpendicular to the second direction parallel to the plane of the semiconductor substrate. Each of the columnar gate conductor layers is related to the annular ferroelectric dielectric layer and the annular oxide semiconductor layer, A plurality of ferroelectric field-effect transistors are formed on each of the columnar gate conductor layers in a plurality of planes in the first direction. The first conductive layer and the second conductive layer in each of the aforementioned planes surround the outer periphery of the annular oxide semiconductor layer associated with each of the columnar gate conductor layers and are in contact with the annular oxide semiconductor layer. The ferroelectric field-effect transistors associated with each columnar gate conductor layer in each of the aforementioned planes form a NOR string of the ferroelectric field-effect transistors in an integrated circuit.

93. The integrated circuit according to claim 92, Each of the ferroelectric field-effect transistors in the NOR string shares a first conductive layer that functions as a common drain line and a second conductive layer that functions as a common source line. An integrated circuit in which the annular oxide semiconductor layer overlaps and contacts the first conductive layer and the second conductive layer, which function as junction-less channel regions of the ferroelectric field-effect transistors in each NOR-type memory string.

94. The integrated circuit according to claim 92, An integrated circuit in which the plurality of columnar gate conductor layers are arranged in a single row extending along the third direction.

95. The integrated circuit according to claim 92, Each of the columnar gate conductor layers is arranged in a second direction perpendicular to the first and third directions, and in two or more rows extending along the third direction. An integrated circuit in which each columnar gate conductor layer in each of the aforementioned rows is offset in the third direction relative to each columnar gate conductor layer in an adjacent row.

96. The integrated circuit according to claim 81, The columnar gate conductor layer comprises a first metal layer forming the inner portion of the gate conductor layer and a second metal layer which is an annular metal layer formed on the first metal layer, in an integrated circuit.

97. The integrated circuit according to claim 81, An integrated circuit in which the channel length of each ferroelectric field-effect transistor is a function of the thickness of the first insulating layer in the first direction.

98. The integrated circuit according to claim 81, An integrated circuit in which the channel width of each ferroelectric field-effect transistor is a function of the outer circumference length of the annular oxide semiconductor layer.

99. The integrated circuit according to claim 81, The gate conductor layer is biased to a first voltage value relative to the drain region in order to perform a write operation on the ferroelectric field-effect transistor to bring it to a first logic state. The gate conductor layer is biased to a second voltage value with respect to the drain region in order to perform an erase operation on the ferroelectric field-effect transistor and bring it to a second logic state. An integrated circuit in which the first voltage value and the second voltage value have opposite voltage polarities and different voltage magnitudes.

100. The integrated circuit according to claim 81, An integrated circuit in which the drain region and the source region are biased to substantially the same voltage in order to perform a write operation or erase operation on the ferroelectric field-effect transistor.

101. The integrated circuit according to claim 99, The gate conductor layer is biased with respect to the drain region to a third voltage value smaller than the first voltage value in order to partially polarize the ferroelectric field-effect transistor and bring it to the first logic state. The gate conductor layer is biased with respect to the drain region to a fourth voltage value smaller than the second voltage value in order to partially polarize the ferroelectric field-effect transistor and bring it to the second logic state, in an integrated circuit.

102. The integrated circuit according to claim 95, An integrated circuit in which each of the columnar gate conductor layers has a circular shape in a plane defined by the second and third directions.

103. The integrated circuit according to claim 95, Each of the columnar gate conductor layers has an elliptical shape in the plane defined by the second and third directions. An integrated circuit in which the ellipse has a minor axis and a major axis in the plane defined by the second direction and the third direction.

104. An array of memory strings, Each of the memory strings includes a plurality of vertical ferroelectric field-effect transistors formed on the plane of a semiconductor substrate. Each of the ferroelectric field-effect transistors is, A columnar gate conductor layer formed as a columnar body extending in a first direction substantially perpendicular to the plane of the semiconductor substrate, An annular ferroelectric dielectric layer formed so as to surround the columnar gate conductor layer, A ring-shaped oxide semiconductor layer formed so as to surround the aforementioned ring-shaped ferroelectric dielectric layer, A first conductive layer and a second conductive layer formed as planes parallel to the plane of the semiconductor substrate, wherein the first conductive layer and the second conductive layer are stacked along the first direction, separated from each other by a first insulating layer, surround the outer periphery of the annular oxide semiconductor layer, and are in contact with the annular oxide semiconductor layer, The ferroelectric field-effect transistor is formed at a position where the first conductive layer, the second conductive layer, and the annular oxide semiconductor layer intersect. The first conductive layer forms a drain region, The second conductive layer forms a source region, The aforementioned cyclic oxide semiconductor layer forms a junction-less channel region. The aforementioned annular ferroelectric dielectric layer forms a gate dielectric layer. The columnar gate conductor layer is an array of memory strings that forms the gate electrode of the ferroelectric field-effect transistor.

105. An array of memory strings according to claim 104, A stack of memory strings arranged in the first direction, wherein each memory string in the stack of memory strings is associated with a plurality of ferroelectric field-effect transistors extending in a second direction parallel to the plane of the semiconductor substrate, The present invention further includes a plurality of columnar gate conductor layers arranged in the second direction and associated with the plurality of ferroelectric field-effect transistors along each of the memory strings, The plurality of ferroelectric field-effect transistors are formed along each of the columnar gate conductor layers across the stack of the memory string and are aligned perpendicular to each other. An array of memory strings in which a plurality of vertically aligned ferroelectric field-effect transistors are electrically isolated from one or more adjacent ferroelectric field-effect transistors by a second insulating layer.

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