GOA drive circuit, display panel, and display device.

Abstract

GOA drive circuit (100), display panel (1), and display device, wherein the GOA drive circuit (100) includes a plurality of cascaded GOA units (110), each GOA unit (110) includes a trigger circuit (10), an inverter circuit (20), a pull-up circuit (30), and a pull-down circuit (40), the inverter circuit (20) includes a first thin-film transistor (T1) and a second thin-film transistor (T2), when the first clock signal (CKL) is high level, the trigger circuit (10) and the first thin-film transistor (T1) are turned on, when the trigger circuit (10) outputs a high level, the voltage across the second thin-film transistor (T2) is high level, and the through-current of the second thin-film transistor (T2) is small, when the first clock signal (CKL) is low level, the first thin-film transistor (T1) is turned off, and the second thin-film transistor (T2) similarly cannot form a through-current.

Description

Technical Field

[0001] [Cross - reference to Related Applications] This application claims the priority of a Chinese patent application with an application number of 202310863346.3 and an invention title of "GOA Driving Circuit, Display Panel and Display Device", which was filed with the China National Intellectual Property Administration on July 14, 2023, and all of its contents are incorporated herein by reference.

[0002] This application belongs to the technical field of display panels, and particularly relates to GOA driving circuits, display panels and display devices.

Background Art

[0003] GOA (Gate Driver on Array) technology integrates TFTs (Thin Film Transistors) in the GOA driving circuit on the array substrate, thereby omitting the gate driving integrated circuit part originally installed outside the array substrate, and reducing the product cost in terms of both material cost and process steps.

[0004] The GOA driving circuit usually includes a plurality of cascaded GOA units. A common GOA unit usually includes an inverting module, a reset module, a trigger module, and an output module as shown in FIG. 1. The inverting module is used to realize the inverting conversion from the pull - up control signal PU to the pull - down control signal PD. However, in the inverting module, when PU is asserted high, T6 is turned on to pull down the PD node. At this time, T5 is in the on state, and a through - current between Vgh and Vgl occurs, causing the GOA unit to malfunction and further causing the display of the display panel to malfunction.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The objective of this invention is to provide a GOA drive circuit that solves the problem of display abnormalities in the display panel caused by the through-current problem present in the reverse-phase module of conventional GOA units. [Means for solving the problem]

[0006] To solve the above technical problems, the technical solution used in the embodiments of this application is as follows. A first embodiment of the present invention provides a GOA drive circuit, It includes multiple cascaded GOA units, each GOA unit including a trigger circuit, a pull-up circuit, an inverter circuit, and a pull-down circuit. The input terminal of the trigger circuit is used to input a start signal or the output signal of the preceding GOA unit, the control terminal of the trigger circuit is used to input a first clock signal, the trigger circuit is turned on when triggered by a high-level signal of the first clock signal and outputs the start signal or the output signal, and is turned off when triggered by a low-level signal of the first clock signal. The input terminal of the pull-up circuit is used to input the second clock signal, the output terminal of the pull-up circuit constitutes the signal output terminal of the GOA unit, the control terminal of the pull-up circuit is connected to the output terminal of the trigger circuit, the pull-up circuit is triggered by the start signal or the output signal to turn on and output the second clock signal, The inverter circuit includes a first thin-film transistor and a second thin-film transistor, the first terminal of the first thin-film transistor being connected to the positive power supply terminal, the control terminal of the first thin-film transistor and the second terminal of the second thin-film transistor being used to input the first clock signal, the second terminal of the first thin-film transistor and the first terminal of the second thin-film transistor forming the output terminal of the inverter circuit, the control terminal of the second thin-film transistor being connected to the output terminal of the trigger circuit, the first thin-film transistor and the second thin-film transistor being triggered on by a high-level signal and triggered off by a low-level signal. The input terminal of the pull-down circuit is used to input a first row closing signal, the output terminal of the pull-down circuit is connected in common to the output terminal of the pull-up circuit, the control terminal of the pull-down circuit is connected to the output terminal of the inverter circuit, and the pull-down circuit is triggered to turn on by a high-level signal.

[0007] Preferably, each of the multiple GOA units is connected to the scan lines of the corresponding row on the array substrate, the scan lines of the multiple rows are connected to the pixel units of the multiple rows on the array substrate, and the multiple GOA units output row open signals and row closed signals to the pixel units of the multiple rows for each row.

[0008] Preferably, the first thin-film transistor and the second thin-film transistor are N-channel thin-film transistors.

[0009] Preferably, the trigger circuit includes a third thin-film transistor and a fourth thin-film transistor. The first terminal of the third thin-film transistor constitutes the input terminal of the trigger circuit, the second terminal of the third thin-film transistor is connected to the first terminal of the fourth thin-film transistor, the second terminal of the fourth thin-film transistor constitutes the output terminal of the trigger circuit, and the control terminals of the third thin-film transistor and the fourth thin-film transistor are commonly connected to constitute the control terminal of the trigger circuit.

[0010] Preferably, the GOA drive circuit further includes a reset circuit, The reset circuit is connected to the output terminal of the trigger circuit and is triggered by the reset control signal to reset each circuit of the GOA unit. The reset circuit includes a fifth thin-film transistor and a sixth thin-film transistor, The first terminal of the fifth thin-film transistor is used to input a second row closing signal, the second terminal of the fifth thin-film transistor is commonly connected to the first terminal of the sixth thin-film transistor, the second terminal of the sixth thin-film transistor constitutes the output terminal of the reset circuit, and the control terminal of the fifth thin-film transistor is commonly connected to the control terminal of the sixth thin-film transistor to input a reset control signal.

[0011] Preferably, the first row closing signal and the second row closing signal are low-level signals.

[0012] Preferably, the GOA drive circuit further includes a cascaded conduction circuit and a bootstrap capacitor, The input terminal of the cascade conduction circuit is used to input a third clock signal that is out of phase with the first clock signal, the output terminal of the cascade conduction circuit is connected to the input terminal of the trigger circuit of the next stage GOA unit, the cascade conduction circuit is triggered on by the start signal or the output signal and outputs the third clock signal, The bootstrap capacitor is connected in parallel between the output terminal and the control terminal of the cascade conduction circuit.

[0013] Preferably, the cascade conduction circuit includes a seventh thin-film transistor, an eighth thin-film transistor, and a ninth thin-film transistor. The first terminal of the seventh thin-film transistor and the first terminal of the ninth thin-film transistor are connected in common to form the input terminal of the cascade conduction circuit; the second terminal of the seventh thin-film transistor, the first terminal of the eighth thin-film transistor, the control terminal of the ninth thin-film transistor, and the first terminal of the bootstrap capacitor are connected in common to form the output terminal of the cascade conduction circuit; the control terminal of the seventh thin-film transistor, the second terminal of the bootstrap capacitor, and the output terminal of the trigger circuit are connected; the control terminal of the eighth thin-film transistor is connected to the output terminal of the inverter circuit; and the second terminal of the eighth thin-film transistor is used to input the first row closing signal.

[0014] Preferably, the pull-up circuit includes a tenth thin-film transistor, and the first terminal, second terminal and control terminal of the tenth thin-film transistor constitute the input terminal, output terminal and control terminal of the pull-up circuit, respectively. The pull-down circuit includes an 11th thin-film transistor, and the first terminal, second terminal, and control terminal of the 11th thin-film transistor constitute the input terminal, output terminal, and control terminal of the pull-down circuit, respectively.

[0015] Preferably, the pull-down circuit further includes a 12th thin-film transistor, a 13th thin-film transistor, and a coupling capacitor. The first terminal of the coupling capacitor is used to input the third clock signal, the second terminal of the coupling capacitor, the control terminal of the 12th thin-film transistor, and the first terminal of the 13th thin-film transistor are connected in common, the first and second terminals of the 12th thin-film transistor are connected in parallel to the first and second terminals of the 11th thin-film transistor, the control terminal of the 13th thin-film transistor is connected to the output terminal of the cascade conduction circuit, and the second terminal of the 13th thin-film transistor is used to input the second row closing signal.

[0016] Preferably, the cascade conduction circuit further includes a 14th thin-film transistor and a 15th thin-film transistor, The control terminal of the 14th thin-film transistor is connected to the second terminal of the coupling capacitor, the first and second terminals of the 14th thin-film transistor are connected in parallel to the first and second terminals of the 8th thin-film transistor, the first terminal of the 15th thin-film transistor is connected to the output terminal of the inverter circuit, the second terminal of the 15th thin-film transistor is used to input the second row closing signal, and the control terminal of the 15th thin-film transistor is used to input the third clock signal.

[0017] Preferably, within the time that the cascade conduction circuit and the pull-down circuit continue to output a low-level signal, the eighth thin-film transistor and the fourteenth thin-film transistor are alternately turned on and off, and the eleventh thin-film transistor and the twelfth thin-film transistor are alternately turned on and off. A second aspect of the embodiment of the present application provides a display panel including an array substrate and the GOA driving circuit provided on one or both sides of the array substrate. A third aspect of the embodiment of the present application provides a display device including a backlight module, a driving circuit board, and the display panel, wherein the backlight module and the display panel are provided opposite to each other, and the driving circuit board is electrically connected to the display panel.

[0018] Preferably, the backlight module is used to provide a backlight, the driving circuit board is connected to the display panel via a chip-on-film, an external control signal is input to a driving chip in the chip-on-film, and the driving chip converts the external control signal into a data signal and a control signal required for driving the GOA driving circuit correspondingly.

Effects of the Invention

[0019] A first aspect of the embodiment of the present application provides a GOA driving circuit including a plurality of cascaded GOA units, each GOA unit including a trigger circuit, an inverter circuit, a pull-up circuit, and a pull-down circuit, the inverter circuit including a first thin-film transistor and a second thin-film transistor. When the first clock signal is at a high level, the trigger circuit and the first thin-film transistor are turned on. When the trigger circuit outputs a high level, the voltages at both ends of the second thin-film transistor are both at a high level, and the through-current of the second thin-film transistor is small. When the first clock signal is at a low level, the first thin-film transistor is turned off, and the second thin-film transistor cannot form a through-current either, improving the operation reliability of the GOA unit and further improving the display reliability of the display panel.

[0020] For a better understanding, please refer to the relevant descriptions of the first aspect for the beneficial effects of the second and third aspects, and thus the explanations here are omitted.

Brief Description of the Drawings

[0021] To more clearly describe the technical solutions in the embodiments of the present application, the drawings necessary for use in the following descriptions of the embodiments or the prior art are briefly described below. Obviously, the drawings in the following descriptions are only some embodiments of the present application, and those skilled in the art can also obtain other drawings based on these drawings without creative labor. [Figure 1] It is a circuit schematic diagram of a conventional GOA unit. [Figure 2] It is a structural schematic diagram of a GOA driving circuit according to Embodiment 1 of the present application. [Figure 3] It is a first type of structural schematic diagram of a GOA unit according to Embodiment 1 of the present application. [Figure 4] It is a second type of structural schematic diagram of a GOA unit according to Embodiment 1 of the present application. [Figure 5] It is a circuit schematic diagram of a GOA unit according to Embodiment 2 of the present application. [Figure 6] It is a structural schematic diagram of a GOA unit according to Embodiment 3 of the present application. [Figure 7] It is a circuit schematic diagram of a GOA unit according to Embodiment 3 of the present application. [Figure 8] It is a signal timing schematic diagram of a GOA unit according to Embodiment 3 of the present application. [Figure 9] It is a waveform schematic diagram of a GPD node according to Embodiment 4 of the present application. [Figure 10] It is a change schematic diagram of the current and voltage of a thin film transistor according to Embodiment 4 of the present application. [Figure 11] It is a circuit schematic diagram of a GOA unit according to Embodiment 4 of the present application. [Figure 12] It is a signal timing schematic diagram of a GOA unit according to Embodiment 4 of the present application. [Figure 13] It is a first type of structural schematic diagram of a thin film transistor according to Embodiment 4 of the present application. [Figure 14] This is a schematic diagram of the second type of thin-film transistor according to Embodiment 4 of the present application. [Figure 15] This is a schematic diagram of the third type of thin-film transistor according to Embodiment 4 of the present application. [Figure 16] This is a schematic diagram of the structure of the display panel according to Embodiment 5 of the present application. [Figure 17] This is a schematic diagram of the structure of the display device according to Embodiment 6 of the present application. [Explanation of symbols]

[0022] 1: Display panel, 2: Drive circuit board, 3: Backlight module, 100: GOA drive circuit, 200: Array substrate, 110: GOA unit, 10: Trigger circuit, 20: Inverter circuit, 30: Pull-up circuit, 40: Pull-down circuit, 50: Reset circuit, 60: Cascade conduction circuit, 11: Substrate, 12: Buffer layer, 13: Active layer, 14: Gate insulating layer, 15: Top gate layer, 16: Interlayer insulating layer, 171: Source electrode, 172: Drain electrode, 18: Bottom gate layer, T1: 1st thin-film transistor, T2: 2nd thin-film transistor, T3: 3rd thin-film transistor, T4: 4th thin-film transistor, T5: 5th thin-film transistor, T6: 6th thin-film transistor, T7: 7th thin-film transistor, T8: 8th thin-film transistor, T9: 9th thin-film transistor, T10: 10th thin-film transistor, T11: 11th thin-film transistor, T12: 12th thin-film transistor, T13: 13th thin-film transistor, T14: 14th thin-film transistor, T15: 15th thin-film transistor, C1: bootstrap capacitor, C2: coupling capacitor, STV: Start signal, Cn1: First cascade conduction signal, Cn2: Second cascade conduction signal, Cn3: Third cascade conduction signal, Gn1: First scan signal, Gn2: Second scan signal, Gn3: Third scan signal, Cn-1: Cascade conduction signal of the preceding GOA unit, CKL: First clock signal, CKBL: Third clock signal, CK: Second clock signal, CKB: Fourth clock signal, ECK1: Fifth clock signal, ECK2: Sixth clock signal, VDD: Positive power supply signal, RST: Reset control signal, Cn: Cascade conduction signal of the current GOA unit, Gn: Scan signal of the current GOA unit, VGL1: First row closed signal, VGL2: Second row closed signal, GPU: Output signal of the flip-flop circuit, GPD: Output signal of the inverter circuit, GPDB: Coupling signal. [Modes for carrying out the invention]

[0023] To further clarify the technical problem, technical solution, and beneficial effects that this application aims to solve, the application will be described in more detail below with reference to the drawings and embodiments. Please understand that the specific embodiments described herein are merely illustrative and not limiting to the application.

[0024] Furthermore, the terms “first” and “second” are merely descriptive and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features described. Thus, features limited to “first” and “second” may explicitly or implicitly include one or more such features. In the description of this application, “multiple” means two or more unless otherwise specified.

[0025] Example 1 A first embodiment of the present invention provides a GOA drive circuit 100 which includes a plurality of cascaded GOA units 110, each of which is connected to the scan lines of a corresponding row on an array substrate 200, and the scan lines of the plurality of rows are connected to a plurality of pixel units on the array substrate 200, and the plurality of GOA units 110 output row open signals and row closed signals for each row to the plurality of pixel units, thereby realizing row scanning drive, and in combination with data signals input from a source drive circuit and a backlight, drives the pixel units to display the corresponding image information.

[0026] Here, each GOA unit 110 receives the corresponding start signal STV, clock signal, row closing signal, and cascade conduction signals output from the previous GOA unit 110, triggers the next GOA unit 110 to output the necessary cascade conduction signal Cn, for example, sequentially outputting the first cascade conduction signal Cn1, the second cascade conduction signal Cn2, and the third cascade conduction signal Cn3. Simultaneously, it triggers and outputs the scan signals necessary for its own pixel units, for example, the first scan signal Gn1 output to the first row of pixel units, the second scan signal Gn2 output to the second row of pixel units, and the third scan signal Gn3 output to the third row of pixel units.

[0027] The clock signal may include a first clock signal CKL, a second clock signal CK, a third clock signal CKBL, and a fourth clock signal CKB, where the scan signal Gn and the cascaded conducted signal Cn may be the same signal or different signals, and the specific type is not limited. Adjacent cascaded conducted signals have the same waveform and differ by a predetermined phase, and adjacent scan signals have the same waveform and differ by a predetermined phase, where the time length of the predetermined phase corresponds to the unit time length of one clock signal. For example, as shown in Figure 8, the first cascaded conducted signal Cn1 and the second cascaded conducted signal Cn2 differ by the unit time length of one clock signal, and the first scan signal Gn1 and the second scan signal Gn2 differ by the unit time length of one clock signal.

[0028] Here, as shown in Figure 2, the GOA drive circuit 100 may further include an EOA circuit that includes a plurality of EOA units, where the GOA unit 110 outputs a high level at the data input stage and a low level at other stages by driving the fifth clock signal ECK1 and the sixth clock signal ECK2 and the scanning signal corresponding to the GOA unit 110, and the EOA unit outputs a low level at the data input stage and a high level at other stages, that is, at the data input stage the EOA unit is in the off state and does not output a signal, and the EOA unit may be configured using an nT1C structure such as 4T1C or 8T1C.

[0029] In this embodiment, to solve the problem of through-current in the reverse-phase circuit, each GOA unit 110 includes a trigger circuit 10, a pull-up circuit 30, a pull-down circuit 40, and an inverter circuit 20.

[0030] The input terminal of the trigger circuit 10 is used to input the start signal STV or the output signal of the preceding GOA unit 110, and the control terminal of the trigger circuit 10 is used to input the first clock signal CKL, and the trigger circuit 10 is triggered to turn on by a high level signal of the first clock signal CKL and outputs the start signal STV or the output signal, and is triggered to turn off by a low level signal of the first clock signal CKL, The input terminal of the pull-up circuit 30 is used to input the second clock signal CK, the output terminal of the pull-up circuit 30 constitutes the signal output terminal of the GOA unit 110, and the control terminal of the pull-up circuit 30 is connected to the output terminal of the trigger circuit 10, and the pull-up circuit 30 is triggered to turn on by the start signal STV or the output signal and outputs the second clock signal CK, The inverter circuit 20 includes a first thin-film transistor T1 and a second thin-film transistor T2. The first terminal of the first thin-film transistor T1 is connected to the positive power supply terminal. The control terminal of the first thin-film transistor T1 and the second terminal of the second thin-film transistor T2 are used to input a first clock signal CKL. The second terminal of the first thin-film transistor T1 and the first terminal of the second thin-film transistor T2 constitute the output terminal of the inverter circuit 20. The control terminal of the second thin-film transistor T2 is connected to the output terminal of the trigger circuit 10. The first thin-film transistor T1 and the second thin-film transistor T2 are triggered on by a high-level signal and turned off by a low-level signal. The input terminal of the pull-down circuit 40 is used to input the first row closing signal VGL1, the output terminal of the pull-down circuit 40 is commonly connected to the output terminal of the pull-up circuit 30, the control terminal of the pull-down circuit 40 is connected to the output terminal of the inverter circuit 20, and the pull-down circuit 40 is triggered to turn on by a high-level signal.

[0031] In this embodiment, the output terminal of the trigger circuit 10 is a GPU node, the output signal of the trigger circuit 10 is a GPU, the output terminal of the inverter circuit 20 is a GPD node, the output signal of the inverter circuit 20 is a GPD, the high / low levels of the GPU node are used to control the on / off state of the pull-up circuit 30, the high / low levels of the GPD node are used to control the on / off state of the pull-down circuit 40, the inverter circuit 20 is used to receive the signal from the GPU node and is configured to output the signal from the GPD node based on the first clock signal CKL, the positive power supply signal VDD at the positive power supply terminal, and the corresponding level states of the signal from the GPU node.

[0032] The first thin-film transistor T1 and the second thin-film transistor T2 are N-channel thin-film transistors that trigger to turn on when a high level is received and to turn off when a low level is received.

[0033] Here, when the start signal STV or the output signal of the preceding GOA unit 110 is written to the trigger waveform, the output signal of the preceding GOA unit 110 may be the cascaded conducted signal Cn-1 or the scanning signal Gn-1 output to the pixel unit. In this case, the first clock signal CKL is a high-level signal, the trigger circuit 10 and the first thin-film transistor T1 are turned on, the start signal STV or the output signal of the preceding GOA unit 110 is output via the trigger circuit 10, the GPU node signal is high-level, the high-level signal is output to the pull-up circuit 30, the pull-up circuit 30 is triggered to turn on, the second clock signal CK is output, and the second clock signal CK is output as the output signal of the current GOA unit 110 to the next GOA unit 110 and the pixel unit of the row corresponding to the current stage. In this case, the voltages across the second thin-film transistor T2 are all high-level, and the through-current of the second thin-film transistor T2 is small.

[0034] Subsequently, the first clock signal CKL is switched to a low level, the trigger circuit 10 and the first thin-film transistor T1 are turned off, and the pull-up circuit 30 is turned off. At this time, the first thin-film transistor T1 is turned off, and the second thin-film transistor T2 cannot form a through-current, thereby improving the operational reliability of the GOA unit 110 and further improving the display reliability of the display panel 1.

[0035] When the first clock signal CKL is switched back to high level, a low-level signal is written to the start signal STV or the output signal of the preceding GOA unit 110. At this time, the pull-up circuit 30 is turned off, the first thin-film transistor T1 is turned on, the second thin-film transistor T2 is turned off, the GPD node signal is switched to the high level of the positive power supply signal VDD, the pull-down circuit 40 is turned on, and the GOA unit 110 continues to output the first row closing signal VGL1, which is a low-level signal.

[0036] By adjusting the structure of the inverter circuit 20, the through-current of the inverter circuit is improved, and the operational reliability of the GOA unit 110 and the display reliability of the display panel 1 are further enhanced.

[0037] Furthermore, in order for the GOA unit 110 to return to its initial state before a different frame screen switches, preferably as shown in Figure 4, the GOA drive circuit 100 further includes a reset circuit 50, which is connected to the output terminal of the trigger circuit 10 and is triggered by a reset control signal RST to reset each circuit of the GOA unit 110. Before the frame screen switches, the reset control signal RST resets all stages of the GOA unit 110, and the reset circuit 50 outputs a low-level signal to the pull-up circuit 30 and the inverter circuit 20, which reset the pull-up circuit 30, the pull-down circuit 40 and the inverter circuit 20 to the off state and switch over. After the reset is complete, the start signal STV or the output signal of the previous stage GOA unit 110 is received.

[0038] Here, the trigger circuit 10, pull-up circuit 30, pull-down circuit 40, and reset circuit 50 can employ corresponding thin-film transistor structures, and their specific structures are not limited.

[0039] The beneficial effects of the embodiment of the present application compared to the prior art are that the GOA drive circuit 100 includes a plurality of cascaded GOA units 110, each GOA unit 110 includes a trigger circuit 10, an inverter circuit 20, a pull-up circuit 30, and a pull-down circuit 40, the inverter circuit 20 includes a first thin-film transistor T1 and a second thin-film transistor T2, when the first clock signal CKL is high level, the trigger circuit 10 and the first thin-film transistor T1 are turned on, when the trigger circuit 10 outputs a high level, the voltage across the second thin-film transistor T2 is high level, the through-current of the second thin-film transistor T2 is small, and when the first clock signal CKL is low level, the first thin-film transistor T1 is turned off, and the second thin-film transistor T2 similarly cannot form a through-current, thereby improving the operational reliability of the GOA unit 110 and further improving the display reliability of the display panel 1.

[0040] Example 2 As shown in Figure 1, if the reset circuit 50 and the trigger circuit 10 employ a single thin-film transistor structure, both thin-film transistors in the GPU node can potentially become leakage paths. That is, if the GPU node is at a high level and the other ends of the trigger circuit 10 and reset circuit 50 are at a low level, a voltage difference will occur, causing leakage current, which will lead to a voltage drop in the GPU node and affect the on / off output of the pull-up circuit 30.

[0041] To solve this problem, preferably, as shown in Figure 5, the trigger circuit 10 includes a third thin-film transistor T3 and a fourth thin-film transistor T4. The first terminal of the third thin-film transistor T3 constitutes the input terminal of the trigger circuit 10, the second terminal of the third thin-film transistor T3 is connected to the first terminal of the fourth thin-film transistor T4, the second terminal of the fourth thin-film transistor T4 constitutes the output terminal of the trigger circuit 10, and the control terminal of the third thin-film transistor T3 and the control terminal of the fourth thin-film transistor T4 are connected in common to constitute the control terminal of the trigger circuit 10.

[0042] The reset circuit 50 includes a fifth thin-film transistor T5 and a sixth thin-film transistor T6. The first terminal of the fifth thin-film transistor T5 is used to input the second row closing signal VGL2, the second terminal of the fifth thin-film transistor T5 is commonly connected to the first terminal of the sixth thin-film transistor T6, the second terminal of the sixth thin-film transistor T6 constitutes the output terminal of the reset circuit 50, and the control terminal of the fifth thin-film transistor T5 is commonly connected to the control terminal of the sixth thin-film transistor T6 to input the reset control signal RST.

[0043] The pull-up circuit 30 includes a 10th thin-film transistor T10, and the first terminal, second terminal, and control terminal of the 10th thin-film transistor T10 constitute the input terminal, output terminal, and control terminal of the pull-up circuit 30, respectively. The pull-down circuit 40 includes an 11th thin-film transistor T11, and the first terminal, second terminal, and control terminal of the 11th thin-film transistor T11 constitute the input terminal, output terminal, and control terminal of the pull-down circuit 40, respectively.

[0044] In this embodiment, both the trigger circuit 10 and the reset circuit 50 are configured with two thin-film transistors connected in series. Before the frame screen switches, the reset control signal RST is switched to a high level, the fifth thin-film transistor T5 and the sixth thin-film transistor T6 of the reset circuit 50 are turned on, and the second row closing signal VGL2 is output to the GPU node. The second row closing signal VGL2 is a low-level signal, and the low-level signal is output to the pull-up circuit 30 and the inverter circuit 20. The pull-up circuit 30, the pull-down circuit 40 and the inverter circuit 20 are reset and switched to the off state. After the reset is completed, the start signal STV or the output signal of the preceding GOA unit 110 is received.

[0045] Subsequently, when the start signal STV or the output signal of the preceding GOA unit 110 is written to the trigger waveform, the output signal of the preceding GOA unit 110 may be the cascaded conducted signal Cn-1 or the scanning signal Gn-1 output to the pixel unit. In this case, the first clock signal CKL is a high-level signal, the third thin-film transistor T3 and the fourth thin-film transistor T4 of the trigger circuit 10 and the first thin-film transistor T1 of the inverter circuit 20 are turned on, and the start signal STV or the output signal of the preceding GOA unit 110 is written to the trigger waveform. The signal is output via the circuit 10, and the GPU node is at a high level. The high-level signal is output to the 10th thin-film transistor T10 of the pull-up circuit 30, which is triggered and turned on, outputting the second clock signal CK. The second clock signal CK is output as the output signal of the current GOA unit 110 to the next GOA unit 110 and the pixel units of the corresponding row in this stage. In this case, the voltage across the second thin-film transistor T2 is at a high level, and the through-current of the second thin-film transistor T2 is small.

[0046] Subsequently, the first clock signal CKL is switched to a low level, the trigger circuit 10 and the first thin-film transistor T1 are turned off, and the tenth thin-film transistor T10 is also turned off. At this time, the first thin-film transistor T1 is turned off, and the second thin-film transistor T2 cannot form a through-current, thereby improving the operational reliability of the GOA unit 110 and further improving the display reliability of the display panel 1.

[0047] When the first clock signal CKL is switched back to high level, a low-level signal is written to the start signal STV or the output signal of the preceding GOA unit 110. At this time, the 10th thin-film transistor T10 is turned off, the first thin-film transistor T1 is turned on, the second thin-film transistor T2 is turned off, the GPD node signal is switched to high level of the positive power supply signal VDD, the 11th thin-film transistor T11 of the pull-down circuit 40 is turned on, and the GOA unit 110 continues to output the first row closed signal VGL1.

[0048] Here, the leakage current paths of the GPU nodes all employ a double thin-film transistor series connection structure; that is, both the trigger circuit 10 and the reset circuit 50 employ a double thin-film transistor structure, thereby reducing leakage current in the GPU nodes and further ensuring the operational reliability of the GOA unit 110 and the display reliability of the display panel 1.

[0049] Example 3 As shown in Figure 1, if the output signal of the pull-up circuit 30 is used as the trigger signal for the next-stage GOA unit 110, an abnormality in the pixel unit of the array board 200 may affect the normal operation of the GOA unit 110, causing the subsequent GOA unit 110 to operate abnormally and rendering the cascaded connection inoperable.

[0050] To solve this problem, as shown in Figure 6, the GOA drive circuit 100 further includes a cascade conduction circuit 60 and a bootstrap capacitor C1. The cascade conduction circuit 60 has an input terminal used to receive a third clock signal CKBL which is out of phase with the first clock signal CKL, and an output terminal connected to the input terminal of the trigger circuit 10 of the next stage GOA unit 110. The cascade conduction circuit 60 is triggered on by a start signal STV or an output signal and outputs the third clock signal CKBL. The bootstrap capacitor C1 is connected in parallel between the output terminal and the control terminal of the cascade conduction circuit 60.

[0051] In this embodiment, before the frame screen switches, the reset control signal RST is switched to a high level, the fifth thin-film transistor T5 and the sixth thin-film transistor T6 of the reset circuit 50 are turned on, the second row closing signal VGL2 is output to the GPU node, a low-level signal is output to the pull-up circuit 30 and the inverter circuit 20, the pull-up circuit 30, the pull-down circuit 40 and the inverter circuit 20 are reset and switched to the off state, and after the reset is completed, the start signal STV or the output signal of the preceding GOA unit 110 is received.

[0052] Subsequently, when the start signal STV or the output signal of the preceding GOA unit 110 is written to the trigger waveform, the output signal of the preceding GOA unit 110 may also be the preceding cascade conducted signal Cn-1. In this case, the first clock signal CKL is a high-level signal, the third thin-film transistor T3 and the fourth thin-film transistor T4 of the trigger circuit 10 and the first thin-film transistor T1 of the inverter circuit 20 are turned on, and the start signal STV or the output signal of the preceding GOA unit 110 is output via the trigger circuit 10, and the GPU node signal The signal is high level, and the high-level signal is output to the 10th thin-film transistor T10 and the cascade conduction circuit 60 of the pull-up circuit 30, triggering the 10th thin-film transistor T10 and the cascade conduction circuit 60 to turn ON, and the 10th thin-film transistor T10 outputs the second clock signal CK, which is output to the corresponding row pixel unit of the stage as the output signal of the stage's GOA unit 110. In this case, the voltage across the second thin-film transistor T2 is high level, and the through-current of the second thin-film transistor T2 is small.

[0053] Subsequently, when the first clock signal CKL is switched to a low level, the trigger circuit 10 and the first thin-film transistor T1 are turned off, and due to the presence of the bootstrap capacitor C1, the high level of the GPU node is stored in the bootstrap capacitor C1, and the GPU node maintains a high level. When the third clock signal CKBL is switched to a high level, the coupling of the cascade conduction circuit 60 pulls up the potential of the GPU node again. In this case, the cascade conduction circuit 60 and the pull-up circuit 30 are fully turned on, the cascade conduction circuit 60 outputs its own cascade conduction signal Cn to the trigger circuit 10 of the next stage GOA unit 110, and the pull-up circuit 30 outputs its own output signal Gn of the GOA unit 110 to the corresponding row of pixel units. Similarly, the first thin-film transistor T1 is turned off, and the second thin-film transistor T2 cannot form a through-current, thereby improving the operational reliability of the GOA unit 110 and further improving the display reliability of the display panel 1.

[0054] When the first clock signal CKL is switched back to high level, a low-level signal is written to the start signal STV or the cascaded conducted signal Cn-1 of the preceding GOA unit 110. At this time, the 10th thin-film transistor T10 is turned off, the first thin-film transistor T1 is turned on, the second thin-film transistor T2 is turned off, the GPD node signal is switched to high level of the positive power supply signal VDD, the 11th thin-film transistor T11 of the pull-down circuit 40 is turned on, and the GOA unit 110 continues to output the first row closing signal VGL1.

[0055] By using a cascade conduction circuit 60 and a pull-up circuit 30 to distinguish between the signal that the GOA unit 110 outputs to the next stage GOA unit 110 and the signal that it outputs to the pixel unit, the influence of the pixel unit on the signal output of the GOA unit 110 is reduced, and the operational reliability of the GOA unit 110 is improved.

[0056] Here, the cascade conduction circuit 60 can employ a corresponding thin-film transistor structure, and preferably, as shown in Figure 7, the cascade conduction circuit 60 includes a seventh thin-film transistor T7, an eighth thin-film transistor T8, and a ninth thin-film transistor T9. The first terminal of the 7th thin-film transistor T7 and the first terminal of the 9th thin-film transistor T9 are connected in common to form the input terminal of the cascade conduction circuit 60. The second terminal of the 7th thin-film transistor T7, the first terminal of the 8th thin-film transistor T8, the control terminal of the 9th thin-film transistor T9, and the first terminal of the bootstrap capacitor C1 are connected in common to form the output terminal of the cascade conduction circuit 60. The control terminal of the 7th thin-film transistor T7 and the second terminal of the bootstrap capacitor C1 are connected to the output terminal of the trigger circuit 10. The control terminal of the 8th thin-film transistor T8 is connected to the output terminal of the inverter circuit 20. The second terminal of the 8th thin-film transistor T8 is used to input the first row closing signal VGL1.

[0057] In this embodiment, as shown in Figure 8, when the start signal STV or the cascaded conduction signal Cn-1 of the preceding GOA unit 110 is written to the trigger waveform, the first clock signal CKL is a high-level signal, the third thin-film transistor T3 and the fourth thin-film transistor T4 of the trigger circuit 10 and the first thin-film transistor T1 of the inverter circuit 20 are turned on, the start signal STV or the cascaded conduction signal Cn-1 of the preceding GOA unit 110 is output via the trigger circuit 10, the GPU node signal is high-level, and the high-level signal is the pull-up signal of the pull-up circuit 30 The 10th thin-film transistor T10 and the 7th thin-film transistor T7 and 9th thin-film transistor T9 of the cascade conduction circuit 60 are output, triggering the 10th thin-film transistor T10, the 7th thin-film transistor T7 and the 9th thin-film transistor T9 to turn ON. The 10th thin-film transistor T10 outputs the second clock signal CK, which is output as the output signal Gn of its own GOA unit 110 to the corresponding row pixel unit of its own stage. At this time, the voltage across the second thin-film transistor T2 is at a high level, and the through-current of the second thin-film transistor T2 is small.

[0058] Subsequently, the first clock signal CKL is switched to a low level, turning off the trigger circuit 10 and the first thin-film transistor T1. Due to the presence of the bootstrap capacitor C1, the high level of the GPU node is stored in the bootstrap capacitor C1, and the GPU node maintains a high level. When the third clock signal CKBL is switched to a high level, the coupling of the seventh thin-film transistor T7 pulls up the potential of the GPU node again. At this time, the seventh thin-film transistor T7 and the tenth thin-film transistor T10 are fully turned on, the cascade conduction circuit 60 outputs its own cascade conduction signal Cn to the trigger circuit 10 of the next stage GOA unit 110, and the pull-up circuit 30 outputs its own GOA unit 110 output signal Gn to the corresponding row's pixel unit. At the same time, the 9th thin-film transistor receives a high-level signal, which is output to the connection node between the 3rd thin-film transistor T3 and the 4th thin-film transistor T4 via the 9th thin-film transistor T9, and also to the connection node between the 5th thin-film transistor T5 and the 6th thin-film transistor T6 via the 9th thin-film transistor T9. As a result, when the GPU node is in a high-level state, the connection node between the 3rd thin-film transistor T3 and the 4th thin-film transistor T4 is in a high-level state, and the connection node between the 5th thin-film transistor T5 and the 6th thin-film transistor T6 is in a high-level state, reducing the source-drain potential difference between the 4th thin-film transistor T4 and the 5th thin-film transistor T5, further reducing leakage current, and stabilizing the high-level state of the GPU node.

[0059] Similarly, since the first thin-film transistor T1 is turned off and the second thin-film transistor T2 cannot form a through-current, the operational reliability of the GOA unit 110 is improved, and the display reliability of the display panel 1 is further improved.

[0060] When the first clock signal CKL is switched back to a high level, a low-level signal is written to the start signal STV or the cascaded conduction signal Cn-1 of the preceding GOA unit 110. At this time, the 10th thin-film transistor T10 is turned off, the first thin-film transistor T1 is turned on, the second thin-film transistor T2 is turned off, the GPD node signal is switched to a high level of the positive power supply signal VDD, the 11th thin-film transistor T11 of the pull-down circuit 40 and the 8th thin-film transistor T8 of the cascaded conduction circuit 60 are turned on, the pull-down circuit 40 continues to output the first row closing signal VGL1 to its own row's pixel unit, and the cascaded conduction circuit 60 continues to output the first row closing signal VGL1 to the trigger circuit 10 of the next stage GOA unit 110.

[0061] Example 4 As shown in Figure 9, during operation, the time the GPD node is at a low level accounts for only 1 / number of pixel rows in the screen display time of one frame. As a result, the gates of the thin-film transistors in the pull-down circuit 40 and / or cascade conduction circuit 60 operate at high voltage for a long period of time. The eighth thin-film transistor T8 and the eleventh thin-film transistor T11 shown in Figure 7 are prone to changes in the characteristics of the thin-film transistors due to prolonged high-voltage driving. As shown in Figure 10, the threshold on-voltage Vth drifts, resulting in poor stability of the GOA unit 110.

[0062] To solve the problem of the characteristics of the thin-film transistors in the pull-down circuit 40 and / or cascade conduction circuit 60 changing due to being in a high-voltage state for a long period of time, preferably, as shown in Figure 11, the pull-down circuit 40 further includes a 12th thin-film transistor T12, a 13th thin-film transistor T13, and a coupling capacitor C2. The first terminal of coupling capacitor C2 is used to input the third clock signal CKBL, the second terminal of coupling capacitor C2, the control terminal of the 12th thin-film transistor T12, and the first terminal of the 13th thin-film transistor T13 are connected in common, the first and second terminals of the 12th thin-film transistor T12 are connected in parallel to the first and second terminals of the 11th thin-film transistor T11, the control terminal of the 13th thin-film transistor T13 is connected to the output terminal of the cascade conduction circuit 60, and the second terminal of the 13th thin-film transistor T13 is used to input the second row closing signal VGL2.

[0063] The cascade conduction circuit 60 further includes a 14th thin-film transistor T14 and a 15th thin-film transistor T15. The control terminal of the 14th thin-film transistor T14 is connected to the second terminal of the coupling capacitor C2, the first and second terminals of the 14th thin-film transistor T14 are connected in parallel to the first and second terminals of the 8th thin-film transistor T8, the first terminal of the 15th thin-film transistor T15 is connected to the output terminal of the inverter circuit 20, the second terminal of the 15th thin-film transistor T15 is used to input the second row closing signal VGL2, and the control terminal of the 15th thin-film transistor T15 is used to input the third clock signal CKBL.

[0064] As shown in Figures 11 and 12, GPDB is used as the coupling signal, and the coupling signal is a control signal output to the 14th thin-film transistor T14 and the 12th thin-film transistor T12. In the first time zone, RST controls the input of the second row closing signal VGL2 and resets the GOA units 110 of all stages.

[0065] During the second time zone, the start signal STV or the cascade conducted signal Cn-1 output from the preceding GOA unit 110 is written to the trigger waveform. At this time, the first clock signal CKL is at a high level, and the third thin-film transistor T3 and the fourth thin-film transistor T4 are turned on. The start signal STV or the cascade conducted signal Cn-1 output from the preceding GOA unit 110 is written to the GPU node. At this time, the GPU controls the second thin-film transistor T2 to write the first clock signal CKL to the GPD node, asserting the GPD node to a high level. As the third clock signal CKBL is asserted to a low level, the GPDB coupled by the coupling capacitor C2 is asserted to a low level, and the 12th thin-film transistor T12 and the 14th thin-film transistor T14 are turned off. At this time, since the third clock signal CKBL is a low-level signal, the 15th thin-film transistor T15 is turned off, and the 8th thin-film transistor T8 is turned on, outputting a low-level signal.

[0066] During the third time zone, the first clock signal CKL is switched to a low level, and the high level of the GPU node is stored in the bootstrap capacitor C1 and maintained until the third clock signal CKBL is switched to a high level. The coupling by the seventh thin-film transistor T7 pulls up the potential of the GPU node again, at which point the seventh thin-film transistor T7 and the tenth thin-film transistor T10 are fully turned on, and the outputs Cn and Gn of the GOA unit 110 are at the high levels of the third clock signal CKBL and the second clock signal CK, respectively.

[0067] At this time, the third clock signal CKBL controls the 15th thin-film transistor T15 to turn it on, the second row closing signal VGL2 is written to the GPD node, GPDB controls the 13th thin-film transistor T13 by Cn to turn it on, the first row closing signal VGL1 is written, and the pull-down circuit 40 is not output.

[0068] During the fourth time zone, when the first clock signal CKL is switched back to a high level, a low level is written to the GPU by the start signal STV or the cascaded conducted signal Cn-1 output from the preceding GOA unit 110, the seventh thin-film transistor T7 and the tenth thin-film transistor T10 are turned off, the second thin-film transistor T2 is turned off, the first thin-film transistor T1 is turned on, the positive power supply signal VDD is written to the GPD node, controlling and turning on the eighth thin-film transistor T8 and the eleventh thin-film transistor T11, and Cn and Gn output the first row closing signal VGL1.

[0069] At this time, the third clock signal CKBL is at a low level, and the coupling capacitor C2 asserts the GPDB voltage to a low level, turning off the 14th thin-film transistor T14 and the 12th thin-film transistor T12.

[0070] During the fifth time zone, when the first clock signal CKL is switched to a low level, the third clock signal CKBL controls the 15th thin-film transistor T15 to turn on, writing a low level of the second row closing signal VGL2 to the GPD node, turning off the 8th thin-film transistor T8 and the 11th thin-film transistor T11. The third clock signal CKBL then asserts the GPDB voltage to a high level through the coupling capacitor C2, turning on the 14th thin-film transistor T14 and the 12th thin-film transistor T12, and Cn and Gn output the first row closing signal VGL1.

[0071] Before the next frame's initialization reset, the 4th and 5th time zones are repeatedly cycled through.

[0072] Specifically, during the time that the cascade conduction circuit 60 and the pull-down circuit 40 continue to output a low-level signal, the 8th thin-film transistor T8 and the 14th thin-film transistor T14 are alternately switched on and off, and the 11th thin-film transistor T11 and the 12th thin-film transistor T12 are alternately switched on and off. The control terminal voltage is switched from a sustained high-level signal to a changing pulse signal, thereby improving the characteristic drift problem caused by long-term biasing of the thin-film transistors and enhancing the stability of the long-term operation of the GOA unit 110.

[0073] As shown in Figures 13 to 15, the thin-film transistor includes a stacked substrate 11, a bottom gate layer 18, a buffer layer 12, an active layer 13, a gate insulating layer 14, a top gate layer 15, an interlayer insulating layer 16, a source electrode 171, and a drain electrode 172. As shown in Figure 13, when the top gate layer 15 accesses a high level and the bottom gate layer 18 accesses a low level, the top channel of the channel region of the active layer 13 is turned on. As shown in Figure 14, when the bottom gate layer 18 accesses a high level and the top gate layer 15 accesses a low level, the bottom channel of the channel region of the active layer 13 is turned on. As shown in Figure 15, when the bottom gate layer 18 and the top gate layer 15 access low levels, there are no channels to turn off.

[0074] By switching between high and low levels to switch between top-gate-on and bottom-gate-on states, the thin-film transistor remains in the top-gate-on state for extended periods, avoiding the problem of carriers being trapped in interface defects of the active layer 13 or gate insulating layer 14 and internal defects of the gate insulating layer 14, which causes device drift.

[0075] Simultaneously, when the bottom gate is turned on, the negative pressure from the top gate excites carriers trapped in defects, thus resetting the threshold voltage.

[0076] Example 5 The present invention further provides a display panel 1, as shown in Figure 16, which includes an array substrate 200 and a GOA drive circuit 100, the specific structure of which refers to the above embodiment, and since this display panel 1 adopts all the technical proposals of all the above embodiments, it has at least all the beneficial effects of the technical proposals of the above embodiments, and a detailed explanation is omitted here. Here, the GOA drive circuit 100 is provided on one or both sides of the array substrate 200.

[0077] In this embodiment, the array substrate 200 includes a display area and a non-display area, and the non-display area is provided with a binding pin area and a GOA drive circuit 100. The GOA drive circuit 100 is provided on one or both sides of the non-display area of ​​the array substrate 200 and is used for sequential scanning of the display area, realizing row-by-row sequential scanning drive to the display area in accordance with the data signal.

[0078] Example 6 The present invention further provides a display device, as shown in Figure 17, which includes a backlight module 3, a drive circuit board 2, and a display panel 1. The specific structure of the display panel 1 refers to the above embodiment, and since this display device adopts all the technical proposals of all the above embodiments, it has at least all the beneficial effects of the technical proposals of the above embodiments, and a detailed explanation is omitted here. Here, the backlight module 3 is provided opposite the display panel 1, and the drive circuit board 2 is electrically connected to the display panel 1.

[0079] In this embodiment, the backlight module 3 is used to provide backlighting, and the drive circuit board 2 is connected to the display panel 1 via a chip-on-film. The external control signal is input to the drive chip on the chip-on-film, and the drive chip converts the external control signal into data signals and control signals necessary for driving the GOA drive circuit 100. The GOA drive circuit 100 converts and outputs a shift pulse signal using multiple sub-row scanning signals, thereby realizing row-sequential scanning drive of the display area in accordance with the data signals.

[0080] The above embodiments are merely for illustrative purposes and not limiting purposes. While the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they may still modify the inventions described in the above embodiments or make equivalent substitutions for some of their technical features. Such modifications or substitutions should not cause the essence of the corresponding invention to deviate from the spirit and scope of the inventions described in the embodiments of the present application, and should all be included within the scope of protection of the present application.

Claims

1. GOA drive circuit, It includes multiple cascaded GOA units, each GOA unit including a trigger circuit, a pull-up circuit, an inverter circuit, and a pull-down circuit. The input terminal of the trigger circuit is used to input a start signal or the output signal of the preceding GOA unit, the control terminal of the trigger circuit is used to input a first clock signal, the trigger circuit is turned on when triggered by a high-level signal of the first clock signal and outputs the start signal or the output signal, and is turned off when triggered by a low-level signal of the first clock signal. The input terminal of the pull-up circuit is used to input the second clock signal, the output terminal of the pull-up circuit constitutes the signal output terminal of the GOA unit, the control terminal of the pull-up circuit is connected to the output terminal of the trigger circuit, the pull-up circuit is triggered by the start signal or the output signal to turn on and output the second clock signal, The inverter circuit includes a first thin-film transistor and a second thin-film transistor, the first terminal of the first thin-film transistor being connected to the positive power supply terminal, the control terminal of the first thin-film transistor and the second terminal of the second thin-film transistor being used to input the first clock signal, the second terminal of the first thin-film transistor and the first terminal of the second thin-film transistor forming the output terminal of the inverter circuit, the control terminal of the second thin-film transistor being connected to the output terminal of the trigger circuit, the first thin-film transistor and the second thin-film transistor being triggered on by a high-level signal and triggered off by a low-level signal. The input terminal of the pull-down circuit is used to input a first row closing signal, the output terminal of the pull-down circuit is connected in common to the output terminal of the pull-up circuit, the control terminal of the pull-down circuit is connected to the output terminal of the inverter circuit, and the pull-down circuit is triggered to turn on by a high-level signal, in a GOA drive circuit.

2. The GOA driving circuit according to claim 1, wherein each of the multiple GOA units is connected to the scan lines of the corresponding row of the array substrate, the scan lines of the multiple rows are connected to the pixel units of the multiple rows on the array substrate, and the multiple GOA units output row open signals and row closed signals to the pixel units of the multiple rows for each row.

3. The GOA driving circuit according to claim 1, wherein the first thin-film transistor and the second thin-film transistor are N-channel thin-film transistors.

4. The trigger circuit includes a third thin-film transistor and a fourth thin-film transistor. The GOA drive circuit according to claim 1, wherein the first end of the third thin-film transistor constitutes the input terminal of the trigger circuit, the second end of the third thin-film transistor is connected to the first end of the fourth thin-film transistor, the second end of the fourth thin-film transistor constitutes the output terminal of the trigger circuit, and the control terminal of the third thin-film transistor and the control terminal of the fourth thin-film transistor are commonly connected to constitute the control terminal of the trigger circuit.

5. The GOA drive circuit further includes a reset circuit, The reset circuit is connected to the output terminal of the trigger circuit and is triggered by the reset control signal to reset each circuit of the GOA unit. The reset circuit includes a fifth thin-film transistor and a sixth thin-film transistor, The GOA drive circuit according to claim 4, wherein the first terminal of the fifth thin-film transistor is used to input a second row closing signal, the second terminal of the fifth thin-film transistor is commonly connected to the first terminal of the sixth thin-film transistor, the second terminal of the sixth thin-film transistor constitutes the output terminal of the reset circuit, and the control terminal of the fifth thin-film transistor is commonly connected to the control terminal of the sixth thin-film transistor to input a reset control signal.

6. The GOA drive circuit according to claim 5, wherein the first row closing signal and the second row closing signal are low-level signals.

7. The GOA drive circuit further includes a cascaded conduction circuit and a bootstrap capacitor, The input terminal of the cascade conduction circuit is used to input a third clock signal that is out of phase with the first clock signal, the output terminal of the cascade conduction circuit is connected to the input terminal of the trigger circuit of the next stage GOA unit, the control terminal of the cascade conduction circuit is connected to the output terminal of the trigger circuit, the cascade conduction circuit is triggered on by a high-level signal output from the trigger circuit and outputs the third clock signal. The GOA drive circuit according to claim 5, wherein the bootstrap capacitor is connected in parallel between the output terminal and the control terminal of the cascade conduction circuit.

8. The cascade conduction circuit includes a seventh thin-film transistor, an eighth thin-film transistor, and a ninth thin-film transistor. The GOA drive circuit according to claim 7, wherein the first end of the seventh thin-film transistor and the first end of the ninth thin-film transistor are connected in common to form the input terminal of the cascade conduction circuit, the second end of the seventh thin-film transistor, the first end of the eighth thin-film transistor, the control terminal of the ninth thin-film transistor, and the first end of the bootstrap capacitor are connected in common to form the output terminal of the cascade conduction circuit, the control terminal of the seventh thin-film transistor, the second end of the bootstrap capacitor, and the output terminal of the trigger circuit are connected, the control terminal of the eighth thin-film transistor is connected to the output terminal of the inverter circuit, the second end of the eighth thin-film transistor is used to input the first row closing signal, and the second end of the ninth thin-film transistor, the second end of the third thin-film transistor, and the first end of the fourth thin-film transistor are connected.

9. The pull-up circuit includes a tenth thin-film transistor, and the first terminal, second terminal, and control terminal of the tenth thin-film transistor constitute the input terminal, output terminal, and control terminal of the pull-up circuit, respectively. The GOA drive circuit according to claim 8, wherein the pull-down circuit includes an 11th thin-film transistor, and the first terminal, second terminal and control terminal of the 11th thin-film transistor constitute the input terminal, output terminal and control terminal of the pull-down circuit, respectively.

10. The pull-down circuit further includes a 12th thin-film transistor, a 13th thin-film transistor, and a coupling capacitor. The GOA drive circuit according to claim 9, wherein the first terminal of the coupling capacitor is used to input the third clock signal, the second terminal of the coupling capacitor, the control terminal of the 12th thin-film transistor and the first terminal of the 13th thin-film transistor are connected in common, the first and second terminals of the 12th thin-film transistor are connected in parallel to the first and second terminals of the 11th thin-film transistor, respectively, the control terminal of the 13th thin-film transistor is connected to the output terminal of the cascade conduction circuit, and the second terminal of the 13th thin-film transistor is used to input the second row closing signal.

11. The cascade conduction circuit further includes a 14th thin-film transistor and a 15th thin-film transistor, The GOA drive circuit according to claim 10, wherein the control terminal of the 14th thin-film transistor is connected to the second terminal of the coupling capacitor, the first and second terminals of the 14th thin-film transistor are connected in parallel to the first and second terminals of the 8th thin-film transistor, respectively, the first terminal of the 15th thin-film transistor is connected to the output terminal of the inverter circuit, the second terminal of the 15th thin-film transistor is used to input the second row closing signal, and the control terminal of the 15th thin-film transistor is used to input the third clock signal.

12. The GOA driving circuit according to claim 11, wherein the eighth thin-film transistor and the fourteenth thin-film transistor alternately turn on and off, and the eleventh thin-film transistor and the twelfth thin-film transistor alternately turn on and off, during the time that the cascade conduction circuit and the pull-down circuit continue to output a low-level signal.

13. It is a display panel, A display panel comprising an array substrate and a GOA driving circuit as described in claim 1, wherein the GOA driving circuit is provided on one or both sides of the array substrate.

14. A display device, A display device comprising a backlight module, a drive circuit board, and a display panel according to claim 13, wherein the backlight module and the display panel are arranged facing each other, and the drive circuit board and the display panel are electrically connected.

15. The display device according to claim 14, wherein the backlight module is used to provide backlight, the drive circuit board is connected to the display panel via a chip-on-film, an external control signal is input to a drive chip in the chip-on-film, and the drive chip converts the external control signal into a data signal and a control signal necessary for driving the GOA drive circuit.

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