Flexible circuit boards, COF modules, and electronic devices including the same

Abstract

The flexible circuit board according to the embodiment includes a first substrate and a second substrate, an adhesive layer disposed between the first substrate and the second substrate, a circuit pattern disposed on the first substrate and the second substrate, and a protective layer disposed on the circuit pattern, wherein the circuit pattern includes first to third circuit patterns disposed at different positions from each other, and a plurality of vias penetrating at least a portion of the first substrate and the second substrate, each of the first substrate and the second substrate including one face and the other face opposite to the one face, and at least one of the plurality of vias is formed penetrating the first substrate, the second substrate, and the adhesive layer and includes a plurality of first inclinations that reduce the horizontal width, and a second inclination provided between the plurality of first inclinations and different from the first inclinations.

Description

Technical Field

[0001] Examples relate to flexible circuit boards, COF modules, and electronic devices including the same.

Background Art

[0002] Recently, various electronic products have been made thinner, smaller, and lighter. Accordingly, various studies have been conducted to mount semiconductor chips at high density in a narrow area of electronic products.

[0003] Among them, the COF (Chip On Film) method can be applied to flexible displays because a flexible substrate is used. That is, the COF method has attracted attention in that it can be applied to various wearable electronic devices. In addition, since the COF method can achieve a fine pitch, it can be used to realize a high-resolution display with an increasing number of pixels.

[0004] COF (Chip On Film) is a method of mounting a semiconductor chip on a thin film-shaped flexible substrate. For example, the semiconductor chip can be an integrated circuit (IC) chip or a large scale integrated circuit (LSI) chip.

[0005] The chip can be connected to an external circuit board and a display panel via a circuit pattern. For example, pad portions are respectively arranged at one end and the other end of the circuit pattern. One of the pad portions is electrically connected to a terminal of the chip. Also, the other pad portion is connected to terminals of the printed circuit board and the display panel. Thereby, the chip, the circuit board, and the display panel are electrically connected via the COF. Also, a signal is transmitted to the display panel via the circuit pattern.

[0006] On the other hand, the size of the flexible circuit board is limited. If the size of the flexible circuit board increases, the bezel area of ​​the display panel may increase.

[0007] Circuit patterns are arranged on the flexible circuit board. These circuit patterns are spaced apart at predetermined intervals to prevent short circuits. Furthermore, the circuit patterns are formed with widths determined for optimal electrical characteristics and process efficiency. Therefore, the number of circuit patterns arranged on the flexible circuit board may be limited.

[0008] This presents a problem: when attempting to connect to a display panel with a large number of channels, the size of the flexible circuit board becomes larger.

[0009] Therefore, there is a need for a new flexible circuit board, COF module, and electronic device containing the same, which can solve the problems described above.

[0010] As a patent related to the aforementioned flexible circuit board, Korean registered patent KR10-0618898 (2006.09.01) has been disclosed. [Overview of the Initiative] [Problems that the invention aims to solve]

[0011] The embodiment provides a flexible circuit board with a large number of circuit patterns.

[0012] The embodiment provides a flexible circuit board with large circuit pattern widths and spacing.

[0013] The embodiment provides a small-sized flexible circuit board.

[0014] The embodiment provides a flexible circuit board with improved heat dissipation characteristics.

[0015] The embodiment provides a flexible circuit board with improved flatness. [Means for solving the problem]

[0016] The flexible circuit board according to the embodiment includes a first substrate and a second substrate, an adhesive layer disposed between the first substrate and the second substrate, a circuit pattern disposed on the first substrate and the second substrate, and a protective layer disposed on the circuit pattern, wherein the circuit pattern includes first to third circuit patterns disposed at different positions from each other, and a plurality of vias penetrating at least a portion of the first substrate and the second substrate, each of the first substrate and the second substrate including one face and the other face opposite to the one face, and at least one of the plurality of vias is formed penetrating the first substrate, the second substrate, and the adhesive layer and includes a plurality of first inclinations that reduce the horizontal width, and a second inclination provided between the plurality of first inclinations and different from the first inclinations.

[0017] A flexible circuit board according to one embodiment includes a first substrate and a second substrate, an adhesive layer between the first substrate and the second substrate, a circuit pattern on the first substrate and the second substrate, and a protective layer on the circuit pattern, wherein the first substrate includes one surface and the other surface opposite to the first surface, the second substrate includes one surface and the other surface opposite to the first surface, the other surface of the first substrate faces the second substrate, and one surface of the second substrate faces the first substrate, the circuit pattern includes a first to fourth circuit pattern, the first circuit pattern is connected to a printed circuit board, the second to fourth circuit patterns are connected to a display panel, and the fourth circuit pattern includes a fourtha pad portion disposed on one surface of the first substrate, a fourthb pad portion disposed on the other surface of the second substrate, and a fourth wiring portion disposed on one surface of the second substrate, the fourtha pad portion, the fourthb pad portion, and the fourth wiring portion are connected by vias. [Effects of the Invention]

[0018] The flexible circuit board according to the embodiment includes a first substrate and a second substrate.

[0019] A circuit pattern is arranged on at least one of the two surfaces of the first substrate. Similarly, a circuit pattern is arranged on at least one of the two surfaces of the second substrate. Furthermore, the first and second substrates are joined together by a bonding layer.

[0020] Therefore, the area on which the circuit patterns are arranged increases. This increases the number of circuit patterns that can be arranged on a single flexible circuit board, or increases the spacing between the circuit patterns. Consequently, the electrical characteristics and reliability of the flexible circuit board are improved.

[0021] Furthermore, the flexible circuit board includes a plurality of vias. At least one of the plurality of vias penetrates the adhesive layer. The width of the via formed in the adhesive layer may be greater than the width of the other vias.

[0022] The via is formed from one direction to the other. Therefore, the via is formed in a shape that narrows in width as it extends from one direction to the other. However, as the width of the via formed in the adhesive layer increases, the width of the central region of the via may increase.

[0023] Therefore, the contact area of ​​the vias increases, preventing the vias from coming off. Also, the increased area of ​​the vias improves heat dissipation characteristics. Consequently, the reliability of the flexible circuit board is improved.

[0024] The first substrate and the second substrate provided in the flexible circuit board according to the embodiment are bonded together by an adhesive layer.

[0025] As a result, the flexible circuit board according to the embodiment can further arrange the four circuit patterns. The fourth circuit pattern can be arranged on one surface of the first substrate, one surface of the second substrate, and the other surface of the second substrate.

[0026] Specifically, the fourth a pad portion and the fourth b pad portion are disposed on one surface of the first base material and the other surface of the second base material. Further, the fourth wiring portion is disposed on one surface of the second base material.

[0027] Thereby, the fourth wiring portion can be disposed regardless of the positions of the second wiring portion, the third wiring portion, and the fifth wiring portion. The second wiring portion, the third wiring portion, and the fifth wiring portion are disposed on one surface of the first base material and the other surface of the second base material. That is, the surface on which the fourth wiring portion is disposed is different from the surface on which the second wiring portion, the third wiring portion, and the fifth wiring portion are disposed.

[0028] Thereby, when the display panel has many channels, more circuit patterns can be formed on a base material of the same size. Alternatively, when the channels of the display panel are the same, the size of the base material can be reduced. Thereby, the size of the flexible circuit board can be reduced. Alternatively, when the channels of the display panel are the same, the width or area of the circuit pattern on the substrate can be increased. Thereby, the reliability and electrical characteristics of the flexible circuit board can be improved.

[0029] Also, warping (bowing) of the flexible circuit board according to the embodiment can be prevented. The flexible circuit board has the first base material and the second base material adhered by an adhesive layer. The first base material and the second base material are disposed with the same area. Therefore, the magnitudes of the upper and lower stresses can be similar with respect to the adhesive layer. Therefore, the stress difference between the upper surface and the lower surface of the flexible circuit board can be reduced. Thereby, it can be prevented that the flexible circuit board warps in one direction due to the stress difference.

Brief Description of the Drawings

[0030] [Figure 1] It is a top view of the first layer of the flexible circuit board according to the embodiment. [Figure 2] It is a bottom view of the first layer of the flexible circuit board according to the embodiment. [Figure 3]This is a top view of the second layer of a flexible circuit board according to an embodiment. [Figure 4] This is a bottom view of the second layer of a flexible circuit board according to an embodiment. [Figure 5] This is a cross-sectional view of the region A-A' in Figure 1. [Figure 6] This is a cross-sectional view of the B-B' region in Figure 2. [Figure 7] This is a cross-sectional view of the C-C' region in Figure 2. [Figure 8] This is a cross-sectional view of the D-D' region in Figure 1. [Figure 9] This is a cross-sectional view of the E-E' region in Figure 3. [Figure 10] This is a cross-sectional view of the F-F' region in Figure 1. [Figure 11] This is a cross-sectional view of the G-G' region in Figure 1. [Figure 12] This is a cross-sectional view of the H-H' region in Figure 1. [Figure 13] This is a cross-sectional view of the H-H' region in Figure 1. [Figure 14] This is a top view of the first layer of a flexible circuit board according to the first modified example. [Figure 15] This is a top view of the first layer of a flexible circuit board according to the second modified example. [Figure 16] This is a bottom view of the first layer of a flexible circuit board according to the third modified example. [Figure 17] This is a bottom view of the second layer of a flexible circuit board according to the fourth modified example. [Figure 18] This is a top view of the first layer of a flexible circuit board according to the second embodiment. [Figure 19] This is a top view of the second layer of a flexible circuit board according to the second embodiment. [Figure 20] This is a bottom view of the second layer of a flexible circuit board according to the second embodiment. [Figure 21] This is a cross-sectional view of the region A-A' in Figure 18. [Figure 22] This is a cross-sectional view of the B-B' region in Figure 18. [Figure 23]This is a cross-sectional view of the C-C' region in Figure 18. [Figure 24] This is a cross-sectional view of the D-D' region in Figure 18. [Figure 25] This is a cross-sectional view of the E-E' region in Figure 20. [Figure 26] This is a cross-sectional view of the F-F' region in Figure 20. [Figure 27] Figure 18 is a cross-sectional view of the G-G' region. [Figure 28] Figure 18 is a cross-sectional view of the G-G' region. [Figure 29] Figure 20 is a cross-sectional view of the H-H' region. [Figure 30] Figure 20 is a cross-sectional view of the H-H' region. [Figure 31] Figure 20 is a cross-sectional view of the H-H' region. [Figure 32] Figure 20 is a cross-sectional view of the H-H' region. [Figure 33] This diagram illustrates the connection between the COF module and other components in the embodiment. [Figure 34] This is a diagram relating to an electronic device including a flexible circuit board according to an embodiment. [Figure 35] This is a diagram relating to an electronic device including a flexible circuit board according to an embodiment. [Figure 36] This is a diagram relating to an electronic device including a flexible circuit board according to an embodiment. [Modes for carrying out the invention]

[0031] Desired embodiments of the present invention will be described in detail below with reference to the attached drawings. However, the technical concept of the present invention is not limited to the embodiments described, but can be realized in a variety of different forms, and within the scope of the technical concept of the present invention, one or more components can be selectively combined and substituted between embodiments.

[0032] Furthermore, unless otherwise clearly defined, terms used in the embodiments of the present invention (including technical and scientific terms) shall be interpreted as having meanings generally understood by those with ordinary skill in the art to which the present invention pertains, and commonly used terms, such as those defined in dictionaries, may be interpreted in consideration of their meaning in the context of the relevant art.

[0033] Furthermore, the terms used in the embodiments of the present invention are for illustrative purposes only and are not intended to limit the invention. In this specification, singular terms may also include plural terms unless otherwise specified in the text, and when it is written "A and / or at least one of B, C," it may include one or more of all possible combinations of A, B, and C.

[0034] Furthermore, when describing the components of the embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc., can be used. Such terms are merely used to distinguish a component from other components, and the terminology does not determine the essence, order, or procedure of that component.

[0035] Furthermore, when it is stated that one component is “connected,” “joined,” or “connected” to another component, this may include not only cases where the component is directly connected, joined, or connected to the other component, but also cases where it is “connected,” “joined,” or “connected” by another component that lies between it and the other component.

[0036] Furthermore, when it is stated that something is formed or positioned "above or below" each component, "above or below" includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or positioned between the two components.

[0037] Furthermore, when expressed as "up" or "down," it can include not only the upward direction but also the downward direction, based on a single component.

[0038] The following describes a flexible circuit board, a COF module, and an electronic device including the same according to the first embodiment, with reference to the drawings.

[0039] Referring to Figures 1 to 8, the flexible circuit board 1000 according to the embodiment includes a base material, a circuit pattern, an adhesive layer, and a protective layer.

[0040] The substrate may include a plurality of substrates. For example, the substrate may include a first substrate 110 and a second substrate 120.

[0041] The first substrate 110 may be placed on the second substrate 120. The circuit pattern and the protective layer may be placed on the first substrate 110 and the second substrate 120. The adhesive layer may be placed between the first substrate 110 and the second substrate 120. The first substrate 110 and the second substrate 120 are bonded together by the adhesive layer. The first substrate 110 and the second substrate 120 may have the same or similar area.

[0042] The first substrate 110 includes one surface 1-1S and another surface 1-2S opposite to the surface 1-1S. The other surface 1-2S is the surface facing the second substrate 120. The second substrate 120 includes one surface 2-1S and another surface 2-2S opposite to the surface 2-1S. The surface 2-1S is the surface facing the first substrate 110.

[0043] The first substrate 110 and the second substrate 120 may include cutting lines. The first substrate 110 may include a first cutting line CL1. The second substrate 120 may include a second cutting line CL2. The first cutting line CL1 and the second cutting line CL2 overlap in the thickness direction of the flexible circuit board 1000.

[0044] The flexible circuit board 1000 is cut along the cutting lines CL1 and CL2. Thus, the edges of the substrate are defined by the cutting lines CL1 and CL2. More specifically, the substrates 110 and 120 include the cutting lines CL1 and CL2, which are located inside the edges of the substrate before the flexible circuit board is cut. Furthermore, after the flexible circuit board is cut, the substrates 110 and 120 include the edges defined by the cutting lines CL1 and CL2.

[0045] For example, after the circuit pattern, protective layer, and chip are placed on the substrates 110 and 120, the substrates 110 and 120 can be cut along the cutting lines CL1 and CL2. This allows the flexible circuit board 1000 to be manufactured as a COF module 2000.

[0046] The substrates 110 and 120 include an effective region AA and an ineffective region UA. The effective region AA and the ineffective region UA ​​are separated by the cutting lines CL1 and CL2. Specifically, the effective region AA is defined as the area inside the cutting lines CL1 and CL2. The ineffective region UA ​​is defined as the area outside the cutting lines CL1 and CL2.

[0047] The circuit pattern, protective layer, and chip are arranged in the effective region AA. A dummy pattern and sprocket holes SH are arranged in the non-effective region UA. The dummy pattern can increase the strength of the base material 100. This prevents the flexible circuit board 1000 from warping. The flexible circuit board 1000 can also be wound and unwound in a roll-to-roll manner by means of the sprocket holes SH.

[0048] The first substrate 110 includes a chip mounting area CHA. The chip mounting area CHA is positioned on the surface 1-1S. The chip mounting area CHA is positioned on the effective area AA. A chip is positioned in the chip mounting area CHA. The pad portion of the circuit pattern extends into the interior of the chip mounting area CHA. The protective layer is not positioned on the chip mounting area CHA.

[0049] The substrates 110 and 120 may include ductile materials. For example, the substrates 110 and 120 may include polyimide (PI). However, the examples are not limited thereto. The substrates 110 and 120 may include polymeric materials including polyethylene terephthalate (PET) or polyethylene naphthalate (PEN). This allows the flexible circuit board to be used in a variety of electronic devices, including curved display devices. For example, the flexible circuit board can be used to mount semiconductor chips for wearable electronic devices.

[0050] The first substrate 110 and the second substrate 120 may contain the same material.

[0051] Alternatively, the first substrate 110 and the second substrate 120 may have the same or similar physical properties. For example, the first substrate 110 and the second substrate 120 may include materials having the same or similar coefficients of thermal expansion. This prevents the flexible circuit board from warping due to differences in the coefficients of thermal expansion.

[0052] Alternatively, the first substrate 110 and the second substrate 120 may include materials having the same or similar dielectric properties (Dk, Df). This reduces the difference in dielectric properties of the flexible circuit board, thereby reducing the signal loss of the flexible circuit board.

[0053] The substrates 110 and 120 may have a thickness within a set range. The thickness T1 of the substrates 110 and 120 may be 15 μm to 40 μm, 17 μm to 38 μm, or 20 μm to 35 μm. If the thickness of the substrates 110 and 120 exceeds 40 μm, the thickness of the flexible circuit board may increase. This may reduce the flexibility characteristics of the flexible circuit board. Also, if the thickness of the substrates 110 and 120 is less than 15 μm, the substrates 110 and 120 may be damaged. In particular, when placing chips or circuit patterns on the flexible circuit board, the substrates 110 and 120 may be damaged by the heat and pressure transmitted to them.

[0054] The first substrate 110 and the second substrate 120 may have the same or similar thickness. This allows substrates of the same area to be placed above and below the adhesive layer. Therefore, the stress difference between the upper and lower parts of the flexible circuit board can be reduced. This prevents the flexible circuit board from warping due to stress.

[0055] The adhesive layer 400 may be placed on the second substrate 120. More specifically, the adhesive layer 400 may be placed between the first substrate 110 and the second substrate 120. The first substrate 110 and the second substrate 120 may be bonded together by the adhesive layer 400.

[0056] The adhesive layer 400 may contain a resin substance. For example, the adhesive layer 400 may contain at least one resin selected from epoxy resin, acrylic resin, and silicone resin.

[0057] The thickness T2 of the adhesive layer and the thickness T1 of the substrate may be different. More specifically, the thickness T2 of the adhesive layer may be less than the thickness T1 of the substrate. Also, the thickness T2 of the adhesive layer and the thickness T3 of the circuit pattern may be different. More specifically, the thickness T2 of the adhesive layer may be greater than the thickness T3 of the circuit pattern.

[0058] The adhesive layer 400 may have a thickness within a set range. The thickness T2 of the adhesive layer may be 20 μm or less. More specifically, the thickness T2 of the adhesive layer may be 10 μm to 20 μm, 12 μm to 18 μm, or 14 μm to 16 μm. If the thickness T2 of the adhesive layer exceeds 20 μm, the thickness of the flexible circuit board may increase. This may reduce the flexibility characteristics of the flexible circuit board. Also, if the thickness of the adhesive layer 400 is less than 10 μm, the adhesive strength of the adhesive layer 400 may decrease. This may reduce the adhesive characteristics of the first substrate 110 and the second substrate 120.

[0059] The circuit pattern and the protective layer are arranged on the substrates 110 and 120. More specifically, the circuit pattern and the protective layer are arranged on the effective region AA and the non-effective region UA.

[0060] The circuit pattern may include a first circuit pattern, a second circuit pattern, a third circuit pattern, and a fourth circuit pattern. The protective layer may also include a first protective layer 310 and a second protective layer 320.

[0061] Referring to Figures 1 to 7, the first circuit pattern is arranged on the first substrate 110. The first circuit pattern includes a 1-1 circuit pattern and a 1-2 circuit pattern. The 1-1 circuit pattern is arranged on the one surface 1-1S. The 1-2 circuit pattern is arranged on the one surface 1-1S and the other surface 1-2S.

[0062] The 1-1 circuit pattern includes a 1-1 wiring portion 211a, a 1-1a pad portion 211b, and a 1-1b pad portion 211c. The 1-1 wiring portion 211a, the 1-1a pad portion 211b, and the 1-1b pad portion 211c may be made of the same material. Furthermore, the 1-1 wiring portion 211a, the 1-1a pad portion 211b, and the 1-1b pad portion 211c may be formed integrally.

[0063] The 1-1a pad portion 211b is positioned inside the chip mounting area CHA. This connects the 1-1a pad portion 211b to the terminals of the chip. This connects the 1-1 circuit pattern to the chip.

[0064] The 1-1b pad portion 211c is located outside the chip mounting area CHA. The 1-1b pad portion 211c is connected to terminals of an external circuit board. This connects the 1-1 circuit pattern to the circuit board.

[0065] The 1-1b pad section 211c may include a first test pad section TP1. That is, the 1-1b pad section 211c may be a first test pad section. In detail, the first circuit pattern may be tested before connecting the circuit board and the 1-1b pad section 211c. For example, the 1-1b pad section 211c can be used to check for open and short circuits in the first circuit pattern.

[0066] The 1-1 wiring section 211a is positioned between the 1-1a pad section 211b and the 1-1b pad section 211c. That is, the 1-1 wiring section 211a connects the 1-1a pad section 211b and the 1-1b pad section 211c. This connects the chip to the circuit board. Therefore, signals generated from the chip are transmitted to the circuit board.

[0067] The first protective layer 310 is placed on the circuit pattern 1-1. More specifically, the first protective layer 310 is placed on the area excluding the pad portion 211b of 1-1a and the pad portion 211c of 1-1b.

[0068] The first- and second circuit patterns include the first- and second wiring sections 212a, the first- and seconda pad sections 212b, and the first- and secondb pad sections 212c. The first- and second wiring sections 212a, the first- and seconda pad sections 212b, and the first- and secondb pad sections 212c may be made of the same material.

[0069] The 1-2a pad portion 212b is positioned on the surface 1-1S. The 1-2a pad portion 212b is positioned inside the chip mounting area CHA. As a result, the 1-2a pad portion 212b is connected to the terminals of the chip. As a result, the 1-2 circuit pattern and the chip are connected.

[0070] The 1-2b pad portion 212c is positioned on the surface 1-1S. The 1-2b pad portion 212c is positioned outside the chip mounting area CHA. The 1-2b pad portion 212c is connected to terminals of an external circuit board. This connects the 1-2 circuit pattern to the circuit board.

[0071] The 1-2b pad section 212c may include a first test pad section TP1. That is, the 1-2b pad section 212c may be a first test pad section. In detail, the first circuit pattern may be tested before connecting the circuit board to the 1-2b pad section 212c. For example, the 1-2b pad section 212c can be used to check for open and short circuits in the first circuit pattern.

[0072] The first- and second wiring sections 212a are arranged on the other surface 1-2S. The first- and second circuit patterns include a first via. The first via includes a firsta via V1a and a firstb via V1v. The firsta via V1a and the firstb via V1b are formed by penetrating the first substrate 110.

[0073] Referring to Figure 6, the 1-2 wiring section 212a is connected to the 1-2a pad section 212b by the 1a via V1a. Referring to Figure 7, the 1-2 wiring section 212a is connected to the 1-2b pad section 212c by the 1b via V1b. This connects the chip and the circuit board. Therefore, signals generated from the chip are transmitted to the circuit board.

[0074] Referring to Figures 1 to 4, Figure 8, and Figure 9, the second circuit pattern may be arranged on the first substrate 110 and the second substrate 120. The second circuit pattern includes a 2-1 circuit pattern and a 2-2 circuit pattern. The 2-1 circuit pattern is arranged on one surface 1-1S of the first substrate and the other surface 2-2S of the second substrate. The 2-2 circuit pattern is arranged on the other surface 1-2S of the first substrate and the other surface 2-2S of the second substrate.

[0075] The 2-1 circuit pattern includes a 2-1 wiring section 221a, a 2-1a pad section 221b, and a 2-1b pad section 221c. The 2-1 wiring section 221a, the 2-1a pad section 221b, and the 2-1b pad section 221c may be made of the same material.

[0076] The 2-1a pad portion 221b is positioned on the surface 1-1S. The 2-1a pad portion 221b is positioned inside the chip mounting area CHA. As a result, the 2-1a pad portion 221b is connected to the terminals of the chip. This connects the 2-1 circuit pattern and the chip.

[0077] The 2-1b pad portion 221c is positioned on the other surface 2-2S. The 2-1b pad portion 221c is connected to the terminals of an external display panel. This connects the second circuit pattern to the display panel.

[0078] The second-first wiring section 221a is arranged on the first substrate 110 and the second substrate 120. More specifically, the second-first wiring section 221a is arranged on the one surface 1-1S and the other surface 2-2S.

[0079] The 2-1 circuit pattern includes a 2a via V2a. The 2-1 wiring portion 221a of the first substrate 110 and the 2-1b pad portion 221c of the second substrate 120 are connected via the 2a via V2a.

[0080] Therefore, the 2-1a pad section 221b and the 2-1b pad section 221c are connected by the 2-1 wiring section 221a. This allows the chip and the display panel to be connected. Consequently, signals generated from the chip can be transmitted to the display panel.

[0081] The first protective layer 310 and the second protective layer 320 may be arranged on the 2-1 circuit pattern. More specifically, the first protective layer 310 is arranged on one surface 1-1S. More specifically, the first protective layer 310 is arranged on the 2-1 wiring portion 221a. The second protective layer 320 is arranged on the other surface 2-2S. More specifically, the second protective layer 320 is arranged on the 2-1 wiring portion 221a. The first protective layer 310 and the second protective layer 320 may be arranged in the area excluding the 2-1a pad portion 221b and the 2-1b pad portion 221c.

[0082] The 2-1 circuit pattern may include a second test pad portion TP2. The second test pad portion TP2 may be located on the other surface 2-2S. The second test pad portion TP2 may be located in the non-effective region UA. The second protective layer 320 is not located on the second test pad portion TP2. The second test pad portion TP2 may be connected to the 2-1 wiring portion 221a of the other surface 2-2S. In particular, the second test pad portion TP2 may be formed integrally with the 2-1 wiring portion 221a of the other surface 2-2S.

[0083] The second circuit pattern can be tested before connecting the display panel to the 2-1b pad section 221c. For example, the presence or absence of open and short circuits in the 2-1 circuit pattern can be checked via the second test pad section TP2.

[0084] The 2-2 circuit pattern includes a 2-2 wiring section 222a, a 2-2a pad section 222b, and a 2-2b pad section 222c. The 2-2 wiring section 222a, the 2-2a pad section 222b, and the 2-2b pad section 222c are made of the same material.

[0085] The 2-2a pad portion 222b is positioned on the surface 1-1S. The 2-2a pad portion 222b is positioned inside the chip mounting area CHA. As a result, the 2-2a pad portion 222b is connected to the terminals of the chip. As a result, the 2-2 circuit pattern and the chip are connected.

[0086] The second-2b pad portion 222c is positioned on the other surface 2-2S. The second-2b pad portion 222c is connected to the terminals of an external display panel. This connects the second circuit pattern to the display panel.

[0087] The second-second wiring section 222a is arranged on the first substrate 110. More specifically, the second-second wiring section 222a is arranged on the other surface 2-2S.

[0088] The 2-2 circuit pattern includes a 2b via V2b and a 2c via V2c. The 2-2 wiring section 222a is connected to the 2-2a pad section 222b by the 2b via V2b. The 2-2 wiring section 222a is connected to the 2-2b pad section 222c by the 2c via V2c. This allows the chip and the display panel to be connected. Therefore, signals generated from the chip can be transmitted to the display panel.

[0089] Referring to Figure 8, the 2a via V2a penetrates the first substrate 110, the adhesive layer 400, and the second substrate 120. Referring to Figure 9, the 2b via V2b penetrates the adhesive layer 400 and the second substrate 120.

[0090] The size of the second via V2a may vary from the first substrate 110 toward the second substrate 120. The second via V2a may be divided into a second via section V2a1, a second via section V2a2, and a second via section V2a3.

[0091] The 2a1 via portion V2a1 penetrates the adhesive layer 400. The 2a2 via portion V2a2 penetrates the first substrate 110. The 2a3 via portion V2a3 penetrates the second substrate 120.

[0092] The 2a1 via portion V2a1 has a first width W1. More specifically, the first width W1 is the maximum width of the 2a1 via portion V2a1. The width of the 2a1 via portion V2a1 may be greater in the central region than in the upper or lower region. More specifically, the width of the 2a1 via portion V2a1 may be greatest in the central region or in the region adjacent to the central region. Also, the width of the 2a1 via portion V2a1 may increase as it extends from the upper region to the central region. Also, the width of the 2a1 via portion V2a1 may decrease as it extends from the central region to the lower region.

[0093] The 2a2 via portion V2a2 has a second width W2 and a third width W3. The second width W2 is the maximum width of the 2a2 via portion V2a2, and the third width W3 is the minimum width of the 2a2 via portion V2a2. The width of the 2a2 via portion V2a2 decreases as it extends downwards. That is, the width of the 2a2 via portion V2a2 decreases as it extends in the direction of the adhesive layer 400. That is, the width of the 2a2 via portion V2a2 is largest in the upper region and smallest in the lower region.

[0094] The 2a3 via portion V2a3 has a fourth width W4 and a fifth width W5. The fourth width W4 is the maximum width of the 2a3 via portion V2a3, and the fifth width W5 is the minimum width of the 2a3 via portion V2a3. The width of the 2a3 via portion V2a3 decreases as it extends downwards. That is, the width of the 2a3 via portion V2a3 decreases as it extends in the direction of the second protective layer 320. That is, the width of the 2a3 via portion V2a3 is largest in the upper region and smallest in the lower region.

[0095] The first width W1 may be greater than at least one of the second width W2 and the third width W3. For example, the first width W1 may be greater than both the second width W2 and the third width W3. Alternatively, the first width W1 may be greater than the third width W3. That is, the first width W1 may be greater than the short width of the 2a2 via portion V2a2. Furthermore, the first width W1 may be the same as or different from the long width of the 2a2 via portion V2a2.

[0096] Furthermore, the first width W1 may be larger than the fourth width W4 and the fifth width W5. That is, the first width W1 may be larger than the short width and long width of the second a3 via portion V2a3.

[0097] Therefore, the width of the second via V2a may decrease, increase, and decrease sequentially as it extends from the first substrate 110 towards the second substrate 120. That is, it may decrease in the second via section V2a2, increase in the second via section V2a1, and decrease in the second via section V2a3.

[0098] This prevents the detachment of the 2a via V2a. The 2a1 via portion V2a1 is positioned in the central region of the 2a via V2a. Therefore, the contact area between the 2a via V2a and the adhesive layer 400 increases in the central portion. As a result, the 2a via V2a is fixed by the adhesive layer 400 in the central portion of the 2a via V2a, which can improve the adhesion strength of the 2a via V2a.

[0099] Furthermore, since the area of ​​the 2a via V2a increases, the heat dissipation characteristics of the flexible circuit board are improved. Therefore, the heat generated by the COF module during operation can be reduced.

[0100] Therefore, the 2a via V2a may be provided with a plurality of different inclinations having varying horizontal widths. Exemplarily, the 2a via V2a may include a plurality of first inclinations having a gradually decreasing horizontal width in the direction from the top surface to the bottom surface, and may include a second inclination different from the first inclinations between the plurality of first inclinations. In this case, the second inclination may be an inclination that decreases after an increase in horizontal width. The second inclination may be a curve having a specific curvature.

[0101] The size of the second via V2c may vary from the first substrate 110 toward the second substrate 120. The second via V2c may be divided into a second via section V2c1 and a second via section V2c2.

[0102] The second via portion V2c1 penetrates the adhesive layer 400. The second via portion V2c2 penetrates the second substrate 120.

[0103] The second via portion V2c1 has a first width W1'. More specifically, the first width W1' is the maximum width of the second via portion V2b1.

[0104] The second c2 via portion V2c2 has a second'width W2' and a third'width W3'. The second'width W2' is the maximum width of the second c2 via portion V2c2, and the third'width W3' is the minimum width of the second c2 via portion V2c2. The width of the second c2 via portion V2c2 increases as it extends downward. That is, the width of the second c2 via portion V2c2 increases as it extends in the direction of the second protective layer 320.

[0105] The first width W1' may be greater than at least one of the second width W2' and the third width W3'. For example, the first width W1' may be greater than both the second width W2' and the third width W3'. Alternatively, the first width W1' may be greater than the third width W3'. That is, the first width W1' may be greater than the short width of the second c2 via section V2c2. Furthermore, the first width W1' may be the same as or different from the long width of the second c2 via section V2c2.

[0106] Therefore, the width of the second via V2c may decrease and increase sequentially as it extends from the second substrate 120 toward the first substrate 110. That is, it may decrease in the second via section V2c2 and increase in the second via section V2c1.

[0107] This prevents the detachment of the second via V2c. The contact area of ​​the second via V2c with the adhesive layer 400 increases. As a result, the second via V2c is fixed by the adhesive layer 400, and the adhesion strength of the second via V2c may be improved.

[0108] Furthermore, the area of ​​the second via V2c increases, which improves the heat dissipation characteristics of the flexible circuit board. Therefore, the heat generated by the COF module during operation can be reduced.

[0109] Referring to Figure 8, the 2a via V2a can contact the circuit pattern in various ways. For example, the 2a via V2a can contact the side surface of the 2-1 wiring section 221a. Alternatively, referring to the enlarged view (a) of Figure 8, the 2a via V2a can contact the side and top surfaces of the 2-1 wiring section 221a. The top surface of the 2a via V2a may be concave. Alternatively, referring to the enlarged view (b) of Figure 8, the 2a via V2a can contact the side and top surfaces of the 2-1 wiring section 221a. The top surface of the 2a via V2a may be convex.

[0110] The second via V2c can also come into contact with the circuit pattern, similar to the second via V2a.

[0111] Referring to Figures 1 to 4, Figure 10, and Figure 11, the third circuit pattern may be arranged on the first substrate 110 and the second substrate 120. The third circuit pattern includes a third-first circuit pattern and a third-second circuit pattern. The third-first circuit pattern and the third-second circuit pattern are arranged on the first substrate 110 and the second substrate 120.

[0112] The 3-1 circuit pattern includes a 3-1 wiring section 231a, a 3-1a pad section 231b, and a 3-1b pad section 231c. The 3-1 wiring section 231a, the 3-1a pad section 231b, and the 3-1b pad section 231c may contain the same material.

[0113] The 3-1a pad portion 231b is positioned on the first substrate 110. The 3-1a pad portion 231b is positioned on the surface 1-1S. The 3-1a pad portion 231b is positioned inside the chip mounting area CHA. As a result, the 3-1a pad portion 231b is connected to the terminals of the chip. As a result, the 3-1 circuit pattern and the chip are connected.

[0114] The 3-1b pad portion 231c is positioned on the second substrate 120. The 3-1b pad portion 231c is positioned on the other surface 2-2S. The 3-1b pad portion 231c is connected to the terminals of an external display panel. This connects the 3-1 circuit pattern to the display panel.

[0115] The third-first wiring section 231a is arranged on the second substrate 120. More specifically, the third-first wiring section 231a is arranged on the surface 2-1S.

[0116] The 3-1 circuit pattern includes a 3a via V3a, a 3b via V3b, and a 3c via V3c. Referring to Figure 10, the 3-1 wiring section 231a is connected to the 3-1a pad section 231b via the 3a via V3a. The 3a via V3a penetrates the first substrate 110 and the adhesive layer 400. As a result, the shape of the 3a via V3a may be similar to the shape of the 2c via V2c.

[0117] Furthermore, the 3-1 wiring section 231a is connected to the 3-1b pad section 231c via the 3b via V3b. The 3b via V3b is formed by penetrating the second substrate 120. This allows the chip and the display panel to be connected. Therefore, signals generated from the chip can be transmitted to the display panel.

[0118] The third-first circuit pattern may include a third-first test pad section TP3-1. The third-first test pad section TP3-1 may be located on the other surface 2-2S. The third-first test pad section TP3-1 may be located in the non-effective region UA. Furthermore, the second protective layer 320 is not located on the third-first test pad section TP3-1. The third-first test pad section TP3-1 may be connected to the third-first wiring section 231a on the one surface 2-1S. In particular, the third-first test pad section TP3-1 may be connected to the third-first wiring section 231a via the third-c via V3c.

[0119] The third circuit pattern can be tested before connecting the display panel to the 3-1b pad section 231c. For example, the presence or absence of open and short circuits in the 3-1 circuit pattern can be checked via the 3-1 test pad section TP3-1.

[0120] The third-second circuit pattern includes a third-second wiring section 232a, a third-seconda pad section 233b, and a third-secondb pad section 232c. The third-second wiring section 232a, the third-seconda pad section 232b, and the third-secondb pad section 232c may contain the same material.

[0121] The 3-2a pad portion 232b is positioned on the first substrate 110. The 3-2a pad portion 232b is positioned on the surface 1-1S. The 3-2a pad portion 232b is positioned inside the chip mounting area CHA. As a result, the 3-2a pad portion 232b is connected to the terminals of the chip. As a result, the 3-2 circuit pattern and the chip are connected.

[0122] The 3-2b pad portion 232c is positioned on the second substrate 120. The 3-2b pad portion 232c is positioned on the other surface 2-2S. The 3-2b pad portion 232c is connected to the terminals of an external display panel. This connects the 3-2 circuit pattern to the display panel.

[0123] The third-second wiring section 232a is arranged on the second substrate 120. More specifically, the third-second wiring section 232a is arranged on the other surface 2-2S.

[0124] The 3-2 circuit pattern includes a 3d via V3d. Referring to Figure 11, the 3-2 wiring section 232a is connected to the 3-2a pad section 232b via the 3d via V3d. The 3-2 wiring section 232a and the 3-2b pad section 232c are connected on the other surface 2-2S. This allows the chip to be connected to the display panel. Therefore, signals generated from the chip can be transmitted to the display panel.

[0125] The size of the third via V3d may vary from the first substrate 110 toward the second substrate 120. The third via V3d may be divided into a third via portion V3d1, a third via portion V3d2, and a third via portion V3d3.

[0126] The third via portion V3d1 penetrates the adhesive layer 400. The third via portion V3d2 penetrates the first substrate 110. The third via portion V3d3 penetrates the second substrate 120.

[0127] The 3d1 via section V3d1 has a first "width W1". In detail, the first "width W1" is the maximum width of the 3d1 via section V3d1.

[0128] The third via portion V3d2 has a second "width W2" and a third "width W3". The second "width W2" is the maximum width of the third via portion V3d2, and the third "width W3" is the minimum width of the third via portion V3d2. The width of the third via portion V3d2 decreases as it extends downward. That is, the width of the third via portion V3d2 decreases as it extends in the direction of the adhesive layer 400.

[0129] The 3d3 via portion V3d3 has a fourth "width W4" and a fifth "width W5". The fourth "width W4" is the maximum width of the 3d3 via portion V3d3, and the fifth "width W5" is the minimum width of the 3d3 via portion V3d3. The width of the 3d3 via portion V3d3 decreases as it extends downward. That is, the width of the 3d3 via portion V3d3 decreases as it extends in the direction of the second protective layer 320.

[0130] The first "width W1" may be greater than at least one of the second "width W2" and the third "width W3". For example, the first "width W1" may be greater than both the second "width W2" and the third "width W3". Alternatively, the first "width W1" may be greater than the third "width W3". That is, the first "width W1" may be greater than the single width of the third via section V3d2. Furthermore, the first "width W1" may be the same as or different from the long width of the third via section V3d2.

[0131] Furthermore, the first "width W1" may be larger than the fourth "width W4" and the fifth "width W5". In other words, the first "width W1" may be larger than the short width and long width of the third via portion V3d3.

[0132] Therefore, the width of the third via V3d may decrease, increase, and decrease sequentially as it extends from the first substrate 110 towards the second substrate 120. That is, it may decrease in the third via portion V3d2, increase in the third via portion V3d1, and decrease in the third via portion V3d3.

[0133] This prevents the detachment of the 3d via V3d. The 3d1 via portion V3d1 is located in the central region of the 3d via V3d. Therefore, the contact area between the 3d via V3d and the adhesive layer 400 increases in the central portion. As a result, the 3d via V3d is fixed by the adhesive layer 400 in the central portion of the 3d via V3d, which can improve the adhesion of the 3d via V3d.

[0134] Furthermore, the area of ​​the third via V3d increases, which improves the heat dissipation characteristics of the flexible circuit board. Therefore, the heat generated by the COF module during operation can be reduced.

[0135] The second protective layer 320 may be placed on the circuit pattern 3-2. More specifically, the second protective layer 320 is placed on the other surface 2-2S. More specifically, the second protective layer 320 is placed on the wiring portion 3-2 232a. The second protective layer 320 may be placed in the area excluding the pad portion 3-2b 232c.

[0136] The third-second circuit pattern may include the third-second test pad portion TP3-2. The third-second test pad portion TP3-2 may be arranged on the other surface 2-2S. The third-second test pad portion TP3-2 may be arranged in the non-effective region UA. Furthermore, the second protective layer 320 is not arranged on the third-second test pad portion TP2. The third-second test pad portion TP2 may be connected to the third-second wiring portion 232a. In particular, the third-second test pad portion TP3-2 may be formed integrally with the third-second wiring portion 232a.

[0137] The 3-2 circuit pattern can be tested before connecting the display panel to the 3-2b pad section 232c. For example, the presence or absence of open and short circuits in the 3-2 circuit pattern can be checked via the 3-2 test pad section TP2.

[0138] Referring to Figures 1 to 4, the fourth circuit pattern 240 may be arranged on the first substrate 110 and the second substrate 120. The fourth circuit pattern may be arranged on one surface 1-1S and the other surface 2-2S. The fourth circuit pattern on one surface 1-1S and the other surface 2-2S is connected via a fourth via V4.

[0139] The fourth circuit pattern 240 is not connected to the chip. The fourth circuit pattern may be a power supply pattern. Therefore, the fourth circuit pattern 240 may be connected to the circuit board and the display panel.

[0140] Furthermore, the fourth circuit pattern 240 may be placed in the edge region of the flexible circuit board.

[0141] Figures 12 and 13 are diagrams illustrating the layer structure of the circuit pattern. Figures 12 and 13 are cross-sectional views of the H-H' region of the first substrate.

[0142] For the sake of explanation, we will use the first circuit pattern as an example. The following explanation applies equally to the second to fourth circuit patterns.

[0143] Referring to Figure 12, the first circuit pattern is formed in multiple layers. In detail, the 1-1 wiring section 211a, the 1-1a pad section 211b, and the 1-1b pad section 211c include a buffer layer 205, a metal layer 201, and a bonding layer 203.

[0144] The buffer layer 205 may include a multilayer structure. More specifically, the buffer layer 205 includes a first buffer layer 205a and a second buffer layer 205b. The first buffer layer 205a is disposed on the first substrate 110. The second buffer layer 205b is disposed on the first buffer layer 205a.

[0145] The first buffer layer 205a contains a material that has excellent adhesion to the first substrate 110. For example, the first buffer layer 205a may contain nickel (Ni). The second buffer layer 205b contains a material that has excellent adhesion to the first circuit pattern. For example, the second buffer layer 205b may contain chromium (Cr).

[0146] The buffer layer 205 can have a thin film thickness in the nanometer range. For example, the buffer layer 205 can have a thickness of 20 nm or less.

[0147] The buffer layer 205 improves the adhesion between the first substrate 110 and the first circuit pattern.

[0148] The metal layer 201 is disposed on the buffer layer 205. More specifically, the metal layer 201 is disposed on the second buffer layer 205b. The metal layer 201 contains a metallic substance. For example, the metal layer 201 may contain copper (Cu).

[0149] The metal layer 201 can be formed by electroplating using the buffer layer as a seed layer. In other words, the metal layer 201 can be a plated layer.

[0150] The thickness of the metal layer 201 may be 10 μm to 30 μm.

[0151] The bonding layer 203 is placed on the metal layer 201.

[0152] The bonding layer 203 is positioned on the side and top surfaces of the metal layer 201. For example, the bonding layer 203 may be positioned to enclose the metal layer 201.

[0153] The bonding layer 203 contains a metal. For example, the bonding layer 203 may contain tin (Sn).

[0154] The thickness of the bonding layer 203 may be 0.3 μm to 0.7 μm. The tin content may increase as the bonding layer 203 extends from the lower surface towards the upper surface.

[0155] In other words, the bonding layer 203 is in contact with the metal layer 201. Therefore, the tin content of the bonding layer 203 increases from the lower surface toward the upper surface. Also, the copper content of the bonding layer 203 decreases from the lower surface toward the upper surface.

[0156] As a result, pure tin can remain in a thickness range of 0.1 μm to 0.3 μm from the upper surface of the bonding layer 203.

[0157] The pad portion can be easily bonded to the terminals of the chip, the circuit board, and the display panel by the bonding layer 203. For example, when heat and pressure are applied to the pad portion, the upper surface of the bonding layer melts. Pure tin remains on the upper surface of the bonding layer. Therefore, the pad portion is easily bonded to the terminals of the chip, the circuit board, and the display panel.

[0158] Referring to Figure 13, the metal layer 201 may include a first metal layer 201a and a second metal layer 201b. The first metal layer 201a is placed on the buffer layer 205. The second metal layer 201b is placed on the first metal layer 201a.

[0159] The thickness of the first metal layer 201a may be less than the thickness of the second metal layer 201b.

[0160] For example, the thickness of the first metal layer 201a may be 0.7 μm to 2 μm, and the thickness of the second metal layer 201b may be 10 μm to 25 μm.

[0161] The first metal layer 201a and the second metal layer 201b may contain the same metallic substance. For example, the first metal layer 201a and the second metal layer 201b may contain copper (Cu).

[0162] The first metal layer 201a and the second metal layer 201b can be formed by a plating process. For example, the first metal layer 201a can be formed thinly on the buffer layer 205. Subsequently, the second metal layer 201b can be formed using the first metal layer 201a as a seed layer.

[0163] Furthermore, the bonding layer 203 may include a first bonding layer 203a and a second bonding layer 203b.

[0164] The first bonding layer 203a is disposed on the metal layer 201. More specifically, the first bonding layer 203a is disposed on the first wiring portion 211, the first pad portion 212a, and the second pad portion 212b.

[0165] The second bonding layer 203b is disposed on the first bonding layer 203a. More specifically, the second bonding layer 203b is disposed on the 1-1a pad portion 211b and the 1-1b pad portion 211c.

[0166] Therefore, the 1-1 wiring section 211a includes the buffer layer 205, the metal layer 201, and the first bonding layer 203a. The 1-1a pad section 211b and the 1-1b pad section 211c also include the buffer layer 205, the metal layer 201, the first bonding layer 203a, and the second bonding layer 203b.

[0167] Therefore, the layer structure of the 1-1 wiring section 211a is different from the layer structure of the 1-1a pad section 211b and the 1-1b pad section 211c.

[0168] The first bonding layer 203a and the second bonding layer 203b contain a metal. More specifically, the first bonding layer 203a and the second bonding layer 203b may contain tin (Sn).

[0169] The first bonding layer 203a and the second bonding layer 203b are arranged with different thicknesses. Specifically, the thickness of the second bonding layer 203b is greater than the thickness of the first bonding layer 203a.

[0170] For example, the first bonding layer 203a has a thickness of 0.02 μm to 0.06 μm. The second bonding layer 203b has a thickness of 0.2 μm to 0.6 μm.

[0171] Therefore, the thickness of the first-1 wiring portion 211a is reduced. Consequently, cracks in the first-1 wiring portion 211a can be prevented when bending the flexible circuit board.

[0172] The thickness of the first circuit pattern may be 2 μm to 25 μm. More specifically, the thickness of the first circuit pattern may be 5 μm to 20 μm. More specifically, the thickness of the first circuit pattern may be 7 μm to 15 μm.

[0173] If the thickness of the first circuit pattern is less than 2 μm, the resistance of the first circuit pattern may increase. If the thickness of the first circuit pattern exceeds 25 μm, it becomes difficult to realize a fine pattern.

[0174] The above description explained that circuit patterns are arranged on both sides of the first substrate and on all sides of the second substrate. However, the embodiments are not limited thereto.

[0175] Referring to Figure 14, in the flexible circuit board according to other embodiments, the circuit pattern is arranged only on one surface 1-1S of the first substrate. More specifically, no circuit pattern is arranged on the other surface 1-2S.

[0176] In other words, the flexible circuit board includes only the first-1 circuit pattern and does not include the first-2 circuit pattern.

[0177] Since the circuit patterns on the second substrate are identical, the following explanation is omitted.

[0178] Referring to Figures 15 to 17, in the flexible circuit board according to other embodiments, the circuit pattern is arranged only on the other surface 2-2S of the second substrate. More specifically, no circuit pattern is arranged on the one surface 2-1S.

[0179] In other words, the flexible circuit board includes only the 2-2 circuit pattern and does not include the 2-1 circuit pattern.

[0180] In the embodiment, the flexible circuit board can be formed by mounting a chip CH in the chip mounting area CHA and cutting along the cutting line CL. This forms a COF module.

[0181] The COF module 2000 is positioned between the display panel 4000 and the circuit board 3000 and can connect electrical signals.

[0182] The following describes a flexible circuit board according to the second embodiment.

[0183] Figure 18 is a top view of the first layer of the flexible circuit board according to the second embodiment, Figure 19 is a top view of the second layer of the flexible circuit board according to the second embodiment, Figure 20 is a bottom view of the second layer of the flexible circuit board according to the second embodiment, Figure 21 is a cross-sectional view obtained by cutting the A-A' region of Figure 18, Figure 22 is a cross-sectional view obtained by cutting the B-B' region of Figure 18, Figure 23 is a cross-sectional view obtained by cutting the C-C' region of Figure 18, Figure 24 is a cross-sectional view obtained by cutting the D-D' region of Figure 18, Figure 25 is a cross-sectional view obtained by cutting the E-E' region of Figure 20, Figure 26 is a cross-sectional view obtained by cutting the F-F' region of Figure 20, Figures 27 and 28 are cross-sectional views obtained by cutting the G-G' region of Figure 18, and Figures 29 and 30 are cross-sectional views obtained by cutting the H-H' region of Figure 20.

[0184] Referring to Figures 18 to 25, the flexible circuit board 1000A according to the second embodiment includes a base material, a circuit pattern, an adhesive layer, and a protective layer. In the following description, the same configuration as that of the flexible circuit board described with reference to Figures 1 to 17 will be omitted.

[0185] The flexible circuit board 1000A includes a first substrate 1110, a second substrate 1120, and an adhesive layer 1400.

[0186] The flexible circuit board 1000A includes a circuit pattern and a protective layer. The circuit pattern may include a first circuit pattern 1210, a second circuit pattern 1220, a third circuit pattern 1230, a fourth circuit pattern 1240, and a fifth circuit pattern 1250. The protective layer may include a first protective layer 1310 and a second protective layer 1320.

[0187] Referring to Figures 18 and 21, the first circuit pattern 1210 is arranged on the first substrate 1110. More specifically, the first circuit pattern 1210 is arranged on the surface 1-1S.

[0188] The first circuit pattern 1210 may include a first wiring portion 1211, a first a-pad portion 1212a, and a first b-pad portion 1212b. The first wiring portion 1211, the first a-pad portion 1212a, and the first b-pad portion 1212b may be made of the same material. Furthermore, the first wiring portion 1211, the first a-pad portion 1212a, and the first b-pad portion 1212b may be formed integrally.

[0189] The first pad portion 1212a is positioned inside the chip mounting area CHA. This connects the first pad portion 1212a to the terminals of the chip. This connects the first circuit pattern 1210 to the chip.

[0190] Furthermore, the first b pad portion 1212b is located outside the chip mounting area CHA. The first b pad portion 1212b is connected to terminals on an external circuit board. This connects the first circuit pattern 1210 to the circuit board.

[0191] On the other hand, the first b pad portion 1212b may be the first test pad portion TP1. In detail, the first circuit pattern 1210 can be tested before connecting the circuit board and the first b pad portion 1212b. For example, the first b pad portion 1212b can be used to check for open and short circuits in the first circuit pattern.

[0192] Furthermore, the first wiring section 1211 is positioned between the first a pad section 1212a and the first b pad section 1212b. That is, the first wiring section 1211 connects the first a pad section 1212a and the first b pad section 1212b. This connects the chip to the circuit board. Therefore, signals generated from the chip are transmitted to the circuit board.

[0193] The first protective layer 1310 is placed on the first circuit pattern 1210. More specifically, the first protective layer 1310 is placed on the area excluding the first a pad portion 1212a and the first b pad portion 1212b.

[0194] Referring to Figures 18, 20, and 22, the second circuit pattern 1220 may be arranged on the first substrate 1110 and the second substrate 1120. More specifically, the second circuit pattern 1220 is arranged on one surface 1-1S of the first substrate and the other surface 2-2S of the second substrate.

[0195] The second circuit pattern 1220 may include second wiring sections 1221a, 1221b, second a pad section 1222a, second b pad section 1222b, and first connection section V1. The second wiring sections 1221a, 1221b, second a pad section 1222a, and second b pad section 1222b may be made of the same material. Furthermore, the second wiring sections 1221a, 1221b, second a pad section 1222a, and second b pad section 1222b may be formed integrally.

[0196] The second circuit pattern 1220 includes multiple circuit patterns. Furthermore, one second circuit pattern 1220 includes one first via V1.

[0197] The second pad portion 1222a is positioned on the surface 1-1S. The second pad portion 1222a is positioned inside the chip mounting area CHA. As a result, the second pad portion 1222a is connected to the terminals of the chip. As a result, the second circuit pattern 1220 is connected to the chip.

[0198] Furthermore, the second b pad portion 1222b is positioned on the other surface 2-2S. The second b pad portion 1222b is connected to the terminals of an external display panel. This connects the second circuit pattern 1220 to the display panel.

[0199] The second wiring section includes a second a wiring section 1221a and a second b wiring section 1221b. The second a wiring section 1221a is arranged on the one surface 1-1S. The second b wiring section is arranged on the other surface 2-2S.

[0200] The second wiring section connects the second a pad section 1222a and the second b pad section 1222b. Specifically, the second a wiring section 1221a is connected to the second a pad section 1222a, and the second b wiring section 1221b is connected to the second b pad section 1222b.

[0201] This allows the chip and the display panel to be connected. Therefore, signals generated from the chip can be transmitted to the display panel.

[0202] The first protective layer 1310 and the second protective layer 1320 may be arranged on the second circuit pattern 1220. More specifically, the first protective layer 1310 is arranged on one surface 1-1S. More specifically, the first protective layer 1310 is arranged on the second circuit pattern 1220. The second protective layer 1320 is arranged on the other surface 2-2S. More specifically, the second protective layer 1320 is arranged on the second circuit pattern 1220. The first protective layer 1310 and the second protective layer 1320 may be arranged in the area excluding the 2a pad portion 1222a and the 2b pad portion 1222b.

[0203] The 2a wiring section 1221a and the 2b wiring section 1221b are electrically connected. More specifically, the 2a wiring section 1221a and the 2b wiring section 1221b are connected by the first via V1. The first via V1 is formed by penetrating the first substrate 1110, the adhesive layer 1400, and the second substrate 1120. As a result, the thickness of the first via V1 is greater than the thickness of the substrates 1110 and 1120. Furthermore, the thickness of the first via V1 is greater than the thickness of the adhesive layer 1400.

[0204] The second circuit pattern 1220 may include the second test pad portion TP2. The second test pad portion TP2 may be located on the other surface 2-2S. The second test pad portion TP2 may be located in the non-effective region UA. The second protective layer 1320 is not located on the second test pad portion TP2. The second test pad portion TP2 may be connected to the second b wiring portion 1221b. In particular, the second test pad portion TP2 may be formed integrally with the second b wiring portion 1221b.

[0205] The second circuit pattern 1220 can be tested before connecting the display panel and the second b pad section 1222b. For example, the presence or absence of open and short circuits in the second circuit pattern can be checked via the second test pad section TP2.

[0206] Referring to Figures 18, 20, and 23, the third circuit pattern 1230 is arranged on one surface 1-1S and the other surface 2-2S. The third circuit pattern 1230 includes a third wiring portion 1231, a third a pad portion 1232a, a third b pad portion 1232b, and a second via V2. The third wiring portion 1231, the third a pad portion 1232a, and the third b pad portion 1232b may be made of the same material. Furthermore, the third wiring portion 1231, the third a pad portion 1232a, and the third b pad portion 1232b may be formed integrally.

[0207] The third pad portion 1232a is positioned on the surface 1-1S. The third pad portion 1232a is positioned inside the chip mounting area CHA. As a result, the third pad portion 1232a is connected to the terminals of the chip. As a result, the third circuit pattern 1230 and the chip are connected.

[0208] Furthermore, the third b pad portion 1232b is positioned on the other surface 2-2S. The third b pad portion 1232b is connected to the terminals of an external display panel. This connects the third circuit pattern 1230 to the display panel.

[0209] Furthermore, the third wiring section 1231 is arranged on the other surface 2-2S. The third wiring section 1231 connects the thirda pad section 1232a and the thirdb pad section 1232b. This connects the chip and the display panel. As a result, signals generated by the chip are transmitted to the display panel.

[0210] The second protective layer 1320 may be placed on the third circuit pattern 1230. More specifically, the second protective layer 1320 is placed on the other surface 2-2S. More specifically, the second protective layer 1320 is placed on the third wiring portion 1231. The second protective layer 1320 may be placed in the area excluding the third b pad portion 1232b.

[0211] The third pad portion 1232a and the third wiring portion 1231 are electrically connected. More specifically, the third pad portion 1232a and the third wiring portion 1231 are connected by the second via V2. The second via V2 is formed by penetrating the first substrate 1110, the adhesive layer 1400, and the second substrate 1120. As a result, the thickness of the second via V2 is greater than the thickness of the substrates 1110 and 1120. Furthermore, the thickness of the second via V2 is greater than the thickness of the adhesive layer 1400.

[0212] The third circuit pattern 1230 may include a third test pad portion TP3. The third test pad portion TP3 may be located on the second-2 surface 2-2S. The third test pad portion TP3 may be located in the non-effective region UA. Furthermore, the second protective layer 1320 is not located on the third test pad portion TP3. The third test pad portion TP3 may be connected to the third wiring portion 1231. In particular, the third test pad portion TP3 may be formed integrally with the third wiring portion 1231.

[0213] The third circuit pattern 1230 can be tested before connecting the display panel to the third b pad section 1232b. For example, the third test pad section TP3 can be used to check for open and short circuits in the third circuit pattern.

[0214] Referring to Figures 18, 19, 20, 24, 25, and 26, the fourth circuit pattern 1240 is arranged on the first substrate 1110, the second substrate 1120, and the adhesive layer 1400.

[0215] The fourth circuit pattern 1240 includes a fourth wiring portion 1241, a fourth a pad portion 1242a, a fourth b pad portion 1242b, and a third via. The fourth wiring portion 1241, the fourth a pad portion 1242a, and the fourth b pad portion 1242b may contain the same material. Furthermore, the fourth wiring portion 1241, the fourth a pad portion 1242a, and the fourth b pad portion 1242b may be formed integrally.

[0216] The 4a pad portion 1242a is positioned on the first substrate 1110. The 4a pad portion 1242a is positioned on the surface 1-1S. The 4a pad portion 1242a is positioned inside the chip mounting area CHA. As a result, the 4a pad portion 1242a is connected to the terminals of the chip. As a result, the 4th circuit pattern 1240 and the chip are connected.

[0217] Furthermore, the 4b pad portion 1242b is positioned on the second substrate 1120. The 4b pad portion 1242b is positioned on the other surface 2-2S. The 4b pad portion 1242b is connected to the terminals of an external display panel. This connects the 4th circuit pattern 1240 to the display panel.

[0218] Furthermore, the fourth wiring section 1241 is arranged on the second substrate 1120. The fourth wiring section 1241 is arranged on the surface 2-1S. The fourth wiring section 1241 connects the 4a pad section 1242a and the 4b pad section 1242b. This connects the chip and the display panel. Therefore, signals generated by the chip are transmitted to the display panel.

[0219] Referring to Figure 19, the fourth wiring section 1241 extends upward and downward in the second direction on the surface 2-1S. The fourth wiring section 1241 extending upward in the second direction may be connected to the fourth b pad section 1242b. The fourth wiring section 1241 extending downward in the second direction may be connected to the fourth test pad section TP4.

[0220] The number of the fourth circuit patterns may differ from the number of the third circuit patterns. For example, the number of the fourth circuit patterns may be greater than the number of the third circuit patterns. No other circuit patterns are placed on one surface of the second substrate, and only the fourth wiring section is placed there. As a result, there is sufficient area for the fourth wiring section to be placed, and therefore, the number of fourth circuit patterns can be formed to be greater than the number of third circuit patterns.

[0221] Furthermore, the fourth wiring section may overlap the third wiring section with the second substrate in the thickness direction.

[0222] The fourth wiring section 1241, the fourth a pad section 1242a, and the fourth b pad section 1242b are electrically connected. The fourth wiring section 1241, the fourth a pad section 1242a, and the fourth b pad section 1242b are connected by a third via. The third via may include a third a via V3a, a third b via V3b, and a third c via V3c, depending on their position.

[0223] Referring to Figure 24, the 4a pad portion 1242a and the 4 wiring portion 1241 are connected by the 3a via V3a. The 3a via V3a penetrates the first substrate 1110. The 3a via V3a also partially penetrates the adhesive layer 1400. As a result, the thickness of the 3a via V3a is greater than the thickness of the substrates 1110 and 1120. Furthermore, the thickness of the 3a via V3a is greater than the thickness of the adhesive layer 1400. Also, the thickness of the 3a via V3a is less than the thickness of the first via V1. Furthermore, the thickness of the 3a via V3 is less than the thickness of the second via V2.

[0224] The thickness of the fourth circuit pattern may be less than the thickness T2 of the adhesive layer. More specifically, the thickness T3 of the fourth wiring portion 1241 may be less than the thickness T2 of the adhesive layer. This allows the adhesive layer 1400 to enclose the fourth wiring portion 1241. As a result, the fourth wiring portion 1241 can be protected by the adhesive layer 1400. The difference G between the thickness of the adhesive layer and the thickness of the fourth wiring portion 1241 and the thickness T3 of the fourth wiring portion 1241 may be different. For example, the thickness T3 of the fourth wiring portion 1241 may be greater than the thickness difference G.

[0225] The fourth wiring portion 1241 may have a thickness within a set range. The thickness T3 of the fourth wiring portion 1241 may be 8 μm or less. More specifically, the thickness T3 of the fourth wiring portion 1241 may be 1 μm to 8 μm, 2 μm to 7 μm, or 3 μm to 6 μm. If the thickness T3 of the fourth wiring portion 1241 exceeds 8 μm, the thickness of the adhesive layer also increases. This may increase the thickness of the flexible circuit board. This may reduce the flexibility characteristics of the flexible circuit board. Furthermore, if the thickness T3 of the fourth wiring portion 1241 is less than 1 μm, process efficiency may decrease.

[0226] Referring to Figure 25, the 4b pad portion 1242b and the 4th wiring portion 1241 are connected by the 3b via V3b. The 3b via V3b penetrates the first substrate 1110. As a result, the thickness of the 3b via V3b is the same as or similar to the thickness of the substrates 1110 and 1120. Also, the thickness of the 3b via V3b is greater than the thickness of the adhesive layer 1400. Also, the thickness of the 3b via V3b is less than the thickness of the first via V1. Also, the thickness of the 3b via V3b is less than the thickness of the second via V2. Also, the thickness of the 3b via V3b is less than the thickness of the 3a via V3a.

[0227] The fourth circuit pattern 1240 may include a fourth test pad portion TP4. The fourth test pad portion TP4 may be located on the second-2 surface 2-2S. The fourth test pad portion TP4 may be located on the non-effective region UA. Furthermore, the second protective layer 1320 is not located on the fourth test pad portion TP4.

[0228] The fourth circuit pattern 1240 can be tested before connecting the display panel to the 4b pad section 1242b. For example, the fourth test pad section TP4 can be used to check for open and short circuits in the fourth circuit pattern.

[0229] Referring to Figure 26, the fourth test pad portion TP4 and the fourth wiring portion 1241 are connected by the third via V3c. The third via V3c penetrates the first substrate 1110. As a result, the thickness of the third via V3c is the same as or similar to the thickness of the substrates 1110 and 1120. Also, the thickness of the third via V3c is greater than the thickness of the adhesive layer 1400. Also, the thickness of the third via V3c is less than the thickness of the first via V1. Also, the thickness of the third via V3c is less than the thickness of the second via V2. Also, the thickness of the third via V3c is less than the thickness of the third via V3a. Furthermore, the thickness of the third via V3b and the thickness of the third via V3c may be the same as or similar to that of the third via V3c.

[0230] Referring to Figures 18 and 20, the fifth circuit pattern 1250 may be arranged on the first substrate 1110 and the second substrate 1120. More specifically, the fifth circuit pattern 1250 may be arranged on one surface 1-1S and the other surface 2-2S.

[0231] The fifth circuit pattern 1250 includes a fifth a wiring section 1251a, a fifth b wiring section 1251b, a fifth a pad section 1252a, a fifth b pad section 1252b, and a fourth via V4. The fifth a wiring section 1251a, the fifth b wiring section 1251b, the fifth a pad section 1252a, and the fifth b pad section 1252b may contain the same material. Furthermore, the fifth a wiring section 1251a, the fifth b wiring section 1251b, the fifth a pad section 1252a, and the fifth b pad section 1252b may be formed integrally.

[0232] The 5a pad portion 1252a is arranged on the surface 1-1S. The 5a pad portion 1252a may be arranged adjacent to the 1a pad portion 1212a. The 5a pad portion 1252a is connected to terminals of an external circuit board. This allows the 5th circuit pattern 1250 and the circuit board to be connected.

[0233] Furthermore, the 5b pad portion 1252b is positioned on the other surface 2-2S. The 5b pad portion 1252b is connected to the terminals of an external display panel. This connects the 5th circuit pattern 1250 to the display panel.

[0234] The fifth wiring section may include the 5a wiring section 1251a and the 5b wiring section 1251b. The 5a wiring section 1251a and the 5b wiring section 1251b may be electrically connected by the fourth via V.

[0235] The fifth wiring section connects the fifth pad section 1252a and the fifth pad section 1252b. More specifically, the fifth wiring section 1251a is connected to the fifth pad section 1252a, and the fifth wiring section 1251b is connected to the fifth pad section 1252b.

[0236] The fifth circuit pattern 1250 may be a power supply pattern. Power can be supplied to the circuit board and the display panel by the fifth circuit pattern 1250.

[0237] The first protective layer 1310 and the second protective layer 1320 are arranged on the fifth circuit pattern 1250. More specifically, the first protective layer 1310 is arranged on the fifth circuit pattern 1250 on one surface 1-1S. The second protective layer 1320 is arranged on the fifth circuit pattern 1250 on the other surface 2-2S. The first protective layer 1310 and the second protective layer 1320 may be arranged in the area excluding the 5a pad portion 1252a and the 5b pad portion 1252b.

[0238] On the other hand, the previous explanation described a flexible circuit board comprising two substrates. However, the embodiments are not limited to this. The flexible circuit board may include three or more substrates.

[0239] At least one of the first circuit pattern 1210, the second circuit pattern 1220, the third circuit pattern 1230, the fourth circuit pattern 1240, and the fifth circuit pattern 1250 may include a metallic material with excellent electrical conductivity. More specifically, at least one of the first circuit pattern 1210, the second circuit pattern 1220, the third circuit pattern 1230, the fourth circuit pattern 1240, and the fifth circuit pattern 1250 may include copper (Cu). However, the embodiments are not limited thereto. At least one of the first circuit pattern 1210, the second circuit pattern 1220, the third circuit pattern 1230, and the fourth circuit pattern 1240 may include at least one metal from among copper (Cu), aluminum (Al), chromium (Cr), nickel (Ni), silver (Ag), molybdenum (Mo), gold (Au), titanium (Ti), and alloys thereof.

[0240] Furthermore, at least one of the first protective layer 1310 and the second protective layer 1320 may contain solder paste. For example, at least one of the first protective layer 1310 and the second protective layer 1320 may contain solder paste containing a thermosetting resin, a thermoplastic resin, a filler, a curing agent, or a curing accelerator.

[0241] The layer structure of the first to fifth circuit patterns will be described below with reference to Figures 27 and 28. For the sake of explanation, Figures 27 and 28 will be used to illustrate the first circuit pattern. However, the embodiments in Figures 27 and 28 can also be applied to the second to fifth circuit patterns.

[0242] Referring to Figure 27, the first circuit pattern may be formed in multiple layers. In detail, the first wiring portion 1211 and the first a pad portion 1212a may include a first metal layer 1201 and a second metal layer 1202. Although not shown in Figure 10, the first b pad portion 1212b may also include the first metal layer 1201 and the second metal layer 1202.

[0243] The first metal layer 1201 may be a seed layer for the circuit pattern. For example, the first metal layer 1201 may be a seed layer formed on the first substrate 1110 by electroless plating using a metallic substance such as copper (Cu).

[0244] Furthermore, the second metal layer 1202 may be a plated layer. For example, the second metal layer 1202 may be a plated layer formed by electroplating with the first metal layer 1201 as a seed layer.

[0245] The thickness of the first metal layer 1201 may be less than the thickness of the second metal layer 1202.

[0246] For example, the thickness of the first metal layer 1201 may be 0.7 μm to 2 μm. Also, the thickness of the second metal layer 1202 may be 10 μm to 25 μm.

[0247] The first metal layer 1201 and the second metal layer 1202 may contain the same metallic substance. For example, the first metal layer 1201 and the second metal layer 1202 may contain copper (Cu).

[0248] Furthermore, a bonding layer 1203 may be placed on the second metal layer 1202. More specifically, the bonding layer 1203 may be placed on the side surface of the first metal layer 1201, the side surface of the second metal layer 1202, and the top surface of the second metal layer 1202. That is, the bonding layer 1203 may be placed so as to enclose the metal layers.

[0249] The bonding layer 1203 may contain a metal. More specifically, the bonding layer 1203 may contain tin (Sn).

[0250] The bonding layer 1203 may be formed with a thickness of 0.3 μm to 0.7 μm. The tin content of the bonding layer 1203 may increase as it extends from the lower surface towards the upper surface.

[0251] In other words, the bonding layer 1203 is positioned in contact with the second metal layer 1202. As a result, the tin content may increase and the copper content may decrease as you move from the lower surface to the upper surface of the bonding layer 1203.

[0252] As a result, only pure tin can remain in the upper surface of the bonding layer 1203 in a thickness range of 0.1 μm to 0.3 μm.

[0253] The bonding layer 1203 allows the terminals of the chip, the terminals of the printed circuit board, and the terminals of the display panel to be easily bonded to the pad portion by heat and pressure. That is, when heat and pressure are applied to the pad portion, the upper surface of the bonding layer where pure tin remains melts. As a result, the terminals of the chip, the terminals of the printed circuit board, and the terminals of the display panel can be easily bonded to the pad portion.

[0254] The bonding layer 1203 can become part of the first pad portion 1212a and the second pad portion 1212b without being separated from them.

[0255] The first circuit pattern is subjected to a flash etching process during the manufacturing process to separate the circuit pattern. As a result, the first metal layer 1201 is etched. Therefore, the final thickness of the first circuit pattern may be less than the sum of the thicknesses of the first metal layer 1201, the second metal layer 1202, and the bonding layer 1203.

[0256] On the other hand, a buffer layer 1205 may be further arranged between the substrate 100 and the first circuit pattern. The adhesion between the first substrate 1100 and the circuit pattern can be improved by the buffer layer 1205.

[0257] The buffer layer 1205 may be formed in multiple layers. More specifically, the buffer layer 1205 may include a first buffer layer 1205a and a second buffer layer 1205b on the first buffer layer 1205a. In this configuration, the first buffer layer 1205a is in contact with the first substrate 1110, and the second buffer layer 1205b is in contact with the first circuit pattern 1210.

[0258] The first buffer layer 1205a may contain a material that has excellent adhesion to the first substrate 1110. For example, the first buffer layer 1205a may contain nickel (Ni). The second buffer layer 1205b may contain a material that has excellent adhesion to the second circuit pattern. For example, the second buffer layer 1205b may contain chromium (Cr).

[0259] The buffer layer 1205 can have a thin film thickness in the nanometer range. For example, the buffer layer 1205 can have a thickness of 20 nm or less.

[0260] The buffer layer 1205 improves the adhesion between the first substrate 1110 and the first circuit pattern.

[0261] Referring to Figure 28, the bonding layer 1203 can include multiple bonding layers. For example, the bonding layer 1203 can include a first bonding layer 1203a and a second bonding layer 1203b.

[0262] In detail, the first bonding layer 1203a may be placed on the first wiring portion 1211 and the first pad portion 1212a. Furthermore, the first bonding layer 1203a may also be placed on the second pad portion 1212b. That is, the first bonding layer 1203a may be placed on the first circuit pattern.

[0263] Furthermore, the second bonding layer 1203b may be placed only on the first a pad portion 1212a and the first b pad portion 1212b. That is, the first wiring portion 1211 and the pad portions 1212a and 212b can have different layer structures due to the second bonding layer 1203b.

[0264] The first bonding layer 1203a and the second bonding layer 1203b may contain metal. More specifically, the first bonding layer 1203a and the second bonding layer 1203b may contain tin (Sn).

[0265] The first bonding layer 1203a and the second bonding layer 1203b may be arranged with different thicknesses. In particular, the second bonding layer 1203b may be thicker than the first bonding layer 1203a.

[0266] For example, the first bonding layer 1203a may have a thin film thickness of 0.02 μm to 0.06 μm, and the second bonding layer 1203b may have a thickness of 0.2 μm to 0.6 μm.

[0267] If the first bonding layer is thickly positioned between the first protective layer 1310 and the first wiring portion 1211, cracks may occur in the first bonding layer when the flexible circuit board is bent. As a result, the first bonding layer 1203a is formed with a thin film thickness. This prevents cracks in the first bonding layer when the flexible circuit board is bent.

[0268] Furthermore, the tin content of the second bonding layer 1203b may increase as it extends from the lower surface towards the upper surface.

[0269] That is, the tin content of the second bonding layer 1203b may increase and the copper content may decrease in the direction from the lower surface to the upper surface.

[0270] As a result, only pure tin may remain in the thickness range of 0.1 μm to 0.3 μm on the upper surface of the second bonding layer 1203b.

[0271] With the second bonding layer 1203b, the terminals of the chip, the terminals of the printed circuit board, and the terminals of the display panel can be easily adhered to the pad portion by heat and pressure. That is, when heat and pressure are applied to the pad portion, the upper surface where pure tin remains in the bonding layer melts. As a result, the terminals of the chip, the terminals of the printed circuit board, and the terminals of the display panel can be easily adhered to the pad portion.

[0272] The flexible circuit board 1000A may define a separation region IA. The second protective layer 1320 includes an end portion in the second direction 2D. Specifically, the second protective layer 1320 overlapping the chip mounting region CHA includes a first end portion E1 adjacent to the 3b pad portion 1232b and a second end portion E2 facing the first end portion E1.

[0273] The separation region IA may be defined as a region between the first end portion E1 and the region corresponding to the chip mounting region CHA.

[0274] The flexible circuit board 1000A can be bent. Specifically, the flexible circuit board 1000A can be bent in all or part of the separation region IA. As a result, the flexible circuit board 1000A can include a bending region BA. The bending region BA may be disposed inside the separation region IA.

[0275] When the flexible circuit board 1000A is bent, stress is generated. Specifically, tensile stress is generated on the outer surface of the bend, and compressive stress is generated on the inner surface of the bend. The buffer layer, the bonding layer, and the metal layer may delaminate due to the stress. That is, cracks may be formed in the circuit pattern that overlaps with the bend region.

[0276] Referring to Figures 29 and 30, the flexible circuit board 1000A can bend over all or part of the separation region IA. The flexible circuit board 1000A can bend to face one surface 1-1S of the first substrate. As a result, tensile stress may be generated on the other surface 2-2S of the second substrate.

[0277] As a result, the other surface 2-2S has different bonding layers arranged in each region.

[0278] The first bonding layer 1203a is positioned on the separation region IA. The first bonding layer 1203a is also positioned on the region where the third b pad portion 1232b is positioned.

[0279] The second bonding layer 1203b is not placed on the separation region IA. The second bonding layer 1203b is placed on the region where the third b pad portion 1232b is placed.

[0280] The thickness of the first bonding layer 1203a is smaller than the thickness of the second bonding layer 1203b. Only the first bonding layer 1203a is placed in the separation region IA. As a result, the separation region IA can be easily bent.

[0281] Furthermore, the second bonding layer 1203b is positioned on the region where the pad portion is located. This allows the pad portion to be easily bonded to the pad portion of the chip.

[0282] One or more bonding layers may be arranged on the surface 1-1S corresponding to the other surface 2-2S.

[0283] Referring to Figure 29, only one bonding layer 1203 can be placed on the surface 1-1S. The thickness of the bonding layer 1203 may be greater than or equal to the thickness of the second bonding layer 1203b. Therefore, when placing a bonding layer on the surface 1-1S, multiple plating steps are not required. Thus, process efficiency can be improved.

[0284] Referring to Figure 30, multiple bonding layers can be arranged on the surface 1-1S. More specifically, the first bonding layer 1203a and the second bonding layer 1203b on the first bonding layer 1203a can be arranged on the surface 1-1S. This makes it possible to make the sizes of the bonding layers arranged above and below the bonding layer 1400 similar. This prevents the flexible circuit board from warping before folding. Furthermore, the plating process for the surface 1-1S and the other surface 2-2S can be performed simultaneously.

[0285] Referring to Figure 31, the flexible circuit board 1000A can bend over all or part of the separation region IA. The flexible circuit board 1000A can bend to face one surface 1-1S of the first substrate. As a result, tensile stress may be generated on the other surface 2-2S of the second substrate.

[0286] As a result, the other surface 2-2S has different bonding layers arranged in each region.

[0287] The first bonding layer 1203a is partially positioned on the separation region IA. As a result, the separation region IA may include an open region OA where the first bonding layer 1203a is not positioned.

[0288] The second bonding layer 1203b is not placed on the separation region IA. The second bonding layer 1203b is placed on the region where the third b pad portion 1232b is placed.

[0289] The first bonding layer 1203a is not disposed on the open region. Also, the second bonding layer 1203b is not disposed on the separation region and the open region. Therefore, the flexible circuit board can be easily bent. Also, when bending the flexible circuit board, it is possible to prevent cracks from being formed in the bonding layer on the separation region.

[0290] Referring to FIG. 32, the flexible circuit board 1000A can be curved in all or part of the separation region IA. The flexible circuit board 1000A can be curved so as to face one surface 1-1S of the first base material. Thereby, tensile stress can be generated on the other surface 2-2S of the second base material.

[0291] Thereby, different bonding layers are arranged for each region on the other surface 2-2S.

[0292] The first bonding layer 1203a is partially disposed on the separation region IA. Thereby, the separation region IA can include an open region OA where the first bonding layer 1203a is not disposed. Also, the first bonding layer 1203a is disposed on a region where the 3b pad portion 1232b is disposed.

[0293] The second bonding layer 1203b is not disposed on the separation region IA. The second bonding layer 1203b is disposed on a region where the 3b pad portion 1232b is disposed.

[0294] A plurality of protective layers can be disposed on the open region OA. Specifically, a second a protective layer 1320a and a second b protective layer 1320b on the second a protective layer 1320a can be disposed on the open region OA. The second a protective layer 1320a can be disposed only on the open region OA. \

[0295] Therefore, the flexible circuit board can be easily bent. Furthermore, when bending the flexible circuit board, it is possible to prevent cracks from forming in the bonding layer of the separation region. That is, no bonding layer is placed in the open region. In addition, multiple protective layers are placed in the open region. Therefore, when bending the flexible circuit board, it is possible to prevent cracks from forming in the bonding layer due to stress.

[0296] Referring to Figure 33, one end of the COF module 2000 in this embodiment may be connected to the display panel 4000, and the other end opposite to the first end may be connected to the circuit board 3000. For example, the display panel 4000 may be arranged on one side of the COF module 2000, and the circuit board 3000 may be arranged on the other side of the COF module 2000 opposite to the first side. However, the embodiment is not limited thereto, and the display panel 4000 and the circuit board 3000 may be arranged on the same side of the COF module 2000.

[0297] The COF module 2000 includes a flexible substrate. Therefore, it can have both a rigid and a bent configuration between the display panel 3000 and the circuit board 4000. That is, the COF module 2000 can include a bent region BA.

[0298] The COF module 2000 can be connected in a bent form between the display panel 4000 and the circuit board 3000, which are arranged facing each other. Therefore, the thickness of the electronic device can be reduced. Furthermore, the degree of design freedom can be improved. In addition, the wiring of the COF module 2000, including the flexible substrate, does not break even in a bent form. This improves the reliability of the electronic device including the COF module.

[0299] Because the COF module is flexible, it can be used in a variety of electronic devices.

[0300] For example, referring to Figure 34, the COF module can be applied to a curved, flexible touch window. Therefore, the touch device including the touch window can be flexible. Thus, the user can bend or curve it by hand.

[0301] Referring to Figure 35, the COF module can be applied to a variety of wearable touch devices, including curved displays. Therefore, electronic devices including the COF module can be made thinner or lighter.

[0302] Referring to Figure 36, the COF module can be used in a variety of electronic devices having a display portion, such as TVs, monitors, and notebooks.

[0303] The features, structures, and effects described in the above-described embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, and effects exemplified in each embodiment can be combined or modified and implemented in other embodiments by a person with ordinary skill in the art to which the embodiment belongs. Therefore, content related to such combinations and modifications should be interpreted as being within the scope of the present invention.

[0304] Furthermore, although the above description has focused on embodiments, these are merely illustrative examples and do not limit the present invention. Anyone with ordinary skill in the art to which the present invention belongs will understand that a variety of modifications and applications not exemplified above are possible, without departing from the essential characteristics of these embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. Any differences related to such modifications and applications should be interpreted as falling within the scope of the present invention as defined in the appended claims.

Claims

1. A first substrate and a second substrate, An adhesive layer is placed between the first and second substrates, Circuit patterns arranged on the first substrate and the second substrate, Includes a protective layer disposed on the circuit pattern, The circuit pattern includes first to third circuit patterns arranged at different positions from each other, and a plurality of vias penetrating at least a portion of the first substrate and the second substrate. Each of the first substrate and the second substrate includes one surface and the other surface opposite to the first surface, A flexible circuit board in which at least one of the plurality of vias is formed through the first substrate, the second substrate, and the adhesive layer and includes a plurality of first inclinations that decrease in horizontal width, and a second inclination provided between the plurality of first inclinations and different from the first inclinations.

2. The flexible circuit board according to claim 1, wherein the second inclination includes a first portion in which the horizontal width increases and a second portion in which the horizontal width decreases.

3. The flexible circuit board according to claim 2, wherein the second inclination is a curve having a specific curvature including the first and second parts.

4. The second circuit pattern includes the second-first circuit pattern and the second-second circuit pattern, The 2-1 circuit pattern includes a 2-1a pad portion on one surface of the first substrate, a 2-1b pad portion on the other surface of the second substrate, and a 2-1 wiring portion on one surface of the first substrate and the other surface of the second substrate. The wiring section 2-1 and the pad section 2-1b are connected via the via 2a. The flexible circuit board according to claim 1, wherein the second via is formed penetrating the first substrate, the adhesive layer, and the second substrate.

5. The second via includes a second via portion 2a1 penetrating the adhesive layer, a second via portion 2a2 penetrating the first substrate, and a second via portion 2a3 penetrating the second substrate. The width of the 2a2 via portion and the width of the 2a3 via portion decrease as they extend from the first substrate toward the second substrate. The 2a1 via portion has a first width, The 2a2 via portion has a long second width and a short third width, The 2a3 via portion has a fourth width which is long and a fifth width which is short, The flexible circuit board according to claim 4, wherein the first width is greater than at least one of the second width and the third width.

6. The first width is larger than the third width. The flexible circuit board according to claim 5, wherein the first width is greater than the fourth width and the fifth width.

7. The first width is larger than the second width and the third width. The flexible circuit board according to claim 5, wherein the first width is greater than the fourth width and the fifth width.

8. The 2-2 circuit pattern includes a 2-2a pad portion on one surface of the first substrate, a 2-2b pad portion on the other surface of the second substrate, and a 2-2 wiring portion on the other surface of the second substrate. The 2-2 wiring section is connected to the 2-2a pad section by the 2b via, The 2-2 wiring section is connected to the 2-2b pad section by the 2c via, The second via is formed by penetrating the first substrate, The flexible circuit board according to claim 4, wherein the second c via is formed penetrating the adhesive layer and the second substrate.

9. The second via includes a second via portion that penetrates the adhesive layer and a second via portion that penetrates the second substrate. The width of the second c2 via portion decreases as it extends from the first substrate toward the second substrate. The second c1 via portion has a first' width, The second c2 via portion has a long width 2' and a short width 3', The flexible circuit board according to claim 8, wherein the first' width is greater than at least one of the second' width and the third' width.

10. The third circuit pattern includes the third-first circuit pattern and the third-second circuit pattern, The 3-1 circuit pattern includes a 3-1a pad portion on one surface of the first substrate, a 3-1b pad portion on the other surface of the second substrate, and a 3-1 wiring portion on one surface of the second substrate. The 3-1 wiring section and the 3-1a pad section are connected via the 3a via. The wiring section 3-1 and the pad section 3-1b are connected via the via 3b. The third via is formed to penetrate the first substrate and the adhesive layer, The flexible circuit board according to claim 1, wherein the third via is formed through the second substrate.

Images