Host-device interface circuit testing

Abstract

Some embodiments provide systems, methods, and devices for self-testing integrated circuits. The integrated circuit includes an interface circuit configured to read test data and write test data to the memory of the integrated circuit. The integrated circuit includes a test circuit configured to test the interface circuit based on the test data written to the memory of the integrated circuit. Some embodiments provide an integrated circuit configured to store and read data. The integrated circuit includes a circuit configured to write a first portion of data to or read a first portion of data from the first memory via a BIST circuit of the first memory until a first BIST counter is saturated. The integrated circuit includes a circuit configured to write a second portion of data to or read a second portion of data from the second memory via a BIST circuit of the second memory until a second BIST counter is saturated.

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims priority to U.S. Patent Application No. 18 / 343,377, filed on June 28, 2023, entitled "HOST - TO - DEVICE INTERFACE CIRCUITRY TESTING", which is hereby incorporated by reference in its entirety.

Background Art

[0002] Modern integrated circuits (ICs) are very complex and are usually manufactured in large quantities with a low tolerance for defects. Therefore, to facilitate an acceptably low defect rate, modern ICs are designed to be automatically tested using automatic test equipment (ATE). The ATE typically inputs test data into the IC and compares the data output in response to the test data with the expected output data. If the data output in response to the test data does not match the expected output data, the IC may have a defect in some form.

[0003] A more detailed understanding can be obtained from the following description given as an example together with the accompanying drawings.

Brief Description of the Drawings

[0004] [Figure 1] It is a block diagram of an exemplary device that can implement one or more features of the present disclosure. [Figure 2] It is a block diagram of the device of FIG. 1 showing additional details. [Figure 3] It is a block diagram of an exemplary automatic test scenario based on ATE testing. [Figure 4] It is a block diagram of another exemplary automatic test scenario based on on - device testing. [Figure 5]This is a block diagram of another exemplary automated test scenario based on on-device testing. [Figure 6] This flowchart shows an exemplary method for automated testing of ICs using an onboard microcontroller. [Figure 7] This flowchart illustrates an exemplary method for automated testing of ICs using an onboard microcontroller. [Figure 8] An exemplary memory cube. [Figure 9] This is an example memory block with additional components for performing a built-in self-test (BIST). [Figure 10] This is a block diagram illustrating an example of a memory pool. [Figure 11] Figure 10 shows a block diagram illustrating the write operation in which the memory pool, as shown and described, is filled with write data. [Figure 12] Figure 10 is another block diagram illustrating a write operation in which the memory pool shown and described is filled with write data. [Figure 13] Figure 10 is another block diagram illustrating a write operation in which the memory pool shown and described is filled with write data. [Figure 14] Figure 10 is another block diagram illustrating a write operation in which the memory pool shown and described is filled with write data. [Figure 15] Figure 10 is a block diagram showing the read operation in which data is read from the memory pool as described. [Figure 16] Figure 10 is a block diagram showing the read operation in which data is read from the memory pool as described. [Figure 17] Figure 10 is a block diagram showing the read operation in which data is read from the memory pool as described. [Figure 18]Figure 10 is a block diagram showing the read operation in which data is read from the memory pool as described. [Figure 19] This flowchart shows an exemplary method for writing to a memory pool. [Figure 20] This flowchart shows an exemplary method for reading from a memory pool. [Modes for carrying out the invention]

[0005] An ATE typically inputs test data to the IC under test via a communication interface. This test data is sometimes called a stimulus, test pattern, or scan pattern. Some exemplary input interfaces include Peripheral Component Interconnect Express (PCIe) and Universal Serial Bus (USB), but any suitable interface can be used in different embodiments. The ATE includes circuitry that implements the interface on the IC and circuitry that implements the interface for communication. The circuitry on the IC (e.g., a scan chain) responds to the input test data and generates an output to the ATE. The ATE compares the output to an expected output to determine if the IC is defective. In conventional systems, it may be impossible to test the interface circuitry on the IC, for example, because the IC is actively receiving test patterns from the ATE and is unavailable for testing. Therefore, it may be desirable to provide a system, method, and / or device that addresses this.

[0006] Some embodiments provide an integrated circuit configured for self-testing. The integrated circuit includes an interface circuit configured to read test data and write test data to the integrated circuit's memory. The integrated circuit also includes a test circuit configured to test the interface circuit based on the test data written to the integrated circuit's memory.

[0007] In some embodiments, the interface circuit is configured to read test data from an external storage device. In some embodiments, the memory of the integrated circuit comprises multiple memories on the same die as the integrated circuit. In some embodiments, the memory of the integrated circuit comprises multiple memories in the same package as the integrated circuit. In some embodiments, the memory of the integrated circuit comprises a memory pool. In some embodiments, the memory of the integrated circuit comprises multiple memories configured to be accessed serially. In some embodiments, the memory of the integrated circuit comprises multiple memories configured to be written to and read from memory via a BIST circuit. In some embodiments, the interface circuit is configured to write a first portion of the test data to the first memory until the first portion of the test data has been completely written to the first memory on the integrated circuit, and after the first portion of the test data has been completely written, to the second portion of the test data until the second portion of the test data has been completely written to the second memory on the integrated circuit. In some embodiments, the test circuit is configured to read a first portion of the test data from a first memory until the first portion of the test data is completely read from a first memory on the integrated circuit, and after the first portion of the test data is completely read, to read a second portion of the test data from a second memory on the integrated circuit until the second portion of the test data is completely read from a second memory on the integrated circuit. In some embodiments, the test circuit is configured to read test data from the memory of the integrated circuit, input the test data to an interface circuit to generate test output data, and compare the test output data with expected output data.

[0008] Some embodiments provide a method for testing an integrated circuit. Test data is written to the memory of the integrated circuit via an interface circuit of the integrated circuit. The interface circuit is tested based on the test data written to the memory of the integrated circuit.

[0009] In some embodiments, test data is written from an external storage device to memory on the integrated circuit via an interface circuit of the integrated circuit. In some embodiments, the memory of the integrated circuit comprises multiple memories on the same die as the integrated circuit. In some embodiments, the memory of the integrated circuit comprises multiple memories in the same package as the integrated circuit. In some embodiments, the memory of the integrated circuit comprises a memory pool. In some embodiments, the memory of the integrated circuit comprises multiple memories configured to be accessed serially. In some embodiments, the memory of the integrated circuit comprises multiple memories configured to be written to and read from memory via a BIST circuit. In some embodiments, writing test data to memory on the integrated circuit via an interface circuit includes writing a first portion of the test data to a first memory until a first portion of the test data has been completely written to a first memory on the integrated circuit, and writing a second portion of the test data to a second memory until a second portion of the test data has been completely written to a second memory on the integrated circuit. In some embodiments, testing an interface circuit based on test data includes reading a first portion of the test data into a first memory until a first portion of the test data has been completely read from a first memory on the integrated circuit, and after the first portion of the test data has been completely read, reading a second portion of the test data from a second memory on the integrated circuit until a second portion of the test data has been completely read from a second memory on the integrated circuit. In some embodiments, testing an interface circuit based on test data written to the memory of an integrated circuit includes reading the test data from the memory of the integrated circuit, inputting the test data into the interface circuit to generate test output data, and comparing the test output data with expected output data.

[0010] Some embodiments provide an integrated circuit configured to store data. The integrated circuit includes a circuit configured to write a first portion of data to a first memory via a BIST circuit of a first memory until a first BIST counter saturates. The integrated circuit also includes a circuit configured to write a second portion of data to a second memory via a BIST circuit of a second memory until a second BIST counter saturates.

[0011] In some embodiments, the integrated circuit includes circuitry configured to trigger the writing of a second portion of data to a second memory based on the saturation of a first BIST counter. In some embodiments, the first and second memories are comprised of an integrated circuit, and the integrated circuit includes circuitry configured to read data from a memory device located outside the integrated circuit. In some embodiments, the first and second memories are comprised of an integrated circuit package, and the integrated circuit includes circuitry configured to read data from a memory device located outside the integrated circuit package. In some embodiments, the first and second memories are comprised of an integrated circuit die, and the integrated circuit includes circuitry configured to read data from a memory device located outside the integrated circuit die.

[0012] Some embodiments provide an integrated circuit configured to retrieve data. The integrated circuit includes a circuit configured to read a first portion of data from a first memory via a BIST circuit of the first memory until a first BIST counter is saturated. The integrated circuit also includes a circuit configured to read a second portion of data from a second memory via a BIST circuit of the second memory until a second BIST counter is saturated.

[0013] In some embodiments, the integrated circuit includes a circuit configured to trigger reading of a second portion of data from a second memory based on saturation of a first BIST counter. In some embodiments, the first memory and the second memory are comprised of an integrated circuit, and the data is read from a memory device external to the integrated circuit. In some embodiments, the first memory and the second memory are comprised of an integrated circuit package, and the data is read from a memory device external to the integrated circuit package. In some embodiments, the first memory and the second memory are comprised of an integrated circuit die, and the data is read from a memory device external to the integrated circuit die.

[0014] Some embodiments provide a method for storing data. A first portion of the data is written to a first memory via a BIST circuit of the first memory until a first BIST counter saturates. A second portion of the data is written to a second memory via a BIST circuit of the second memory until a second BIST counter saturates.

[0015] In some embodiments, saturation of the first BIST counter triggers writing of a second portion of the data to the second memory. In some embodiments, the first memory and the second memory are comprised of an integrated circuit, and the data is read from a memory device external to the integrated circuit. In some embodiments, the first memory and the second memory are comprised of an integrated circuit package, and the data is read from a memory device external to the integrated circuit package. In some embodiments, the first memory and the second memory are comprised of an integrated circuit die, and the data is read from a memory device external to the integrated circuit die.

[0016] Some embodiments provide a method for retrieving data. A first portion of the data is retrieved from a first memory via a BIST circuit of the first memory until a first BIST counter saturates. A second portion of the data is retrieved from a second memory via a BIST circuit of the second memory until a second BIST counter saturates.

[0017] In some embodiments, saturation of the first BIST counter triggers writing of the second portion of the data to the second memory. In some embodiments, the first memory and the second memory are comprised of an integrated circuit, and the data is retrieved from a memory device external to the integrated circuit. In some embodiments, the first memory and the second memory are comprised of an integrated circuit package, and the data is retrieved from a memory device external to the integrated circuit package. In some embodiments, the first memory and the second memory are comprised of an integrated circuit die, and the data is retrieved from a memory device external to the integrated circuit die.

[0018] FIG. 1 is a block diagram of an exemplary device 100 that may implement one or more features of the present disclosure. Device 100 may include, for example, a computer, a gaming device, a handheld device, a set-top box, a television, a cellular phone, a server, a tablet computer, or other types of computing devices. Device 100 includes a processor 102, a memory 104, a storage 106, one or more input devices 108, and one or more output devices 110. Additionally, device 100 may optionally include an input driver 112 and an output driver 114. It should be understood that device 100 may include additional components not shown in FIG. 1.

[0019] In various alternatives, the processor 102 includes a central processing unit (CPU), a graphics processing unit (GPU), a CPU and GPU located on the same die, or one or more processor cores, each of which may be a CPU or a GPU. In various alternatives, the memory 104 is located on the same die as the processor 102 or is located separately from the processor 102. The memory 104 includes volatile or non-volatile memory (e.g., random access memory (RAM), dynamic RAM, cache).

[0020] Storage 106 includes fixed or removable storage (e.g., hard disk drives, solid-state drives, optical discs, flash drives). Input devices 108 include, but are not limited to, keyboards, keypads, touchscreens, touchpads, detectors, microphones, accelerometers, gyroscopes, biometric scanners, or network connections (e.g., wireless local area network cards for transmitting and / or receiving wireless IEEE 802 signals). Output devices 110 include, but are not limited to, display devices 118, display connectors / interfaces (e.g., HDMI® or DisplayPort® connectors or interfaces for connecting to HDMI® or DisplayPort® compliant devices), speakers, printers, haptic feedback devices, one or more lights, antennas, or network connections (e.g., wireless local area network cards for transmitting and / or receiving wireless IEEE 802 signals).

[0021] The input driver 112 communicates with the processor 102 and the input device 108, enabling the processor 102 to receive input from the input device 108. The output driver 114 communicates with the processor 102 and the output device 110, enabling the processor 102 to send output to the output device 110. Note that the input driver 112 and the output driver 114 are optional components, and device 100 operates in the same manner if the input driver 112 and the output driver 114 are not present. The output driver 114 includes an accelerated processing device (APD) 116 coupled to the display device 118. The APD accepts computation and graphics rendering commands from the processor 102, processes those computation and graphics rendering commands, and provides pixel outputs to the display device 118 for display. As will be described in more detail below, the APD 116 includes one or more parallel processing units that perform computations according to the single-instruction-multiple-data (SIMD) paradigm. Thus, although various functions are described herein as being performed by or in conjunction with the APD116, in various alternative examples, functions described as being performed by the APD116 may, additionally or alternatively, be performed by other computing devices having similar capabilities that are not driven by the host processor (e.g., processor 102) and provide graphic output to the display device 118. For example, any processing system that performs processing tasks according to the SIMD paradigm is intended to be able to perform the functions described herein. Alternatively, a computing system that does not perform processing tasks according to the SIMD paradigm is intended to be able to perform the functions described herein.

[0022] Figure 2 is a block diagram of an embodiment of device 100 showing additional details regarding the execution of processing tasks on APD116. The processor 102 maintains one or more control logic modules for execution by the processor 102 in system memory 104. The control logic modules include an operating system 120, a kernel-mode driver 122, and an application 126. These control logic modules control various characteristics of the operation of the processor 102 and APD116. For example, the operating system 120 communicates directly with the hardware and provides an interface to the hardware for other software running on the processor 102. The kernel-mode driver 122 controls the operation of APD116 by providing an application programming interface (API) to software running on the processor 102 (e.g., application 126) to access various functions of APD116. The kernel-mode driver 122 also includes a just-in-time compiler that compiles programs for execution by the processing components of APD116 (such as the SIMD unit 138, which will be described in more detail below).

[0023] The APD116 executes commands and programs for selected functions, such as graphics operations and non-graphics operations, that are suitable for or may be suitable for parallel processing. Based on commands received from the processor 102, the APD116 can be used to perform graphics pipeline operations such as pixel calculations, geometric calculations, and rendering images to the display device 118. In addition, based on instructions received from the processor 102, the APD116 performs computational operations that are not directly related to graphics operations, such as operations related to video, physical simulations, computational fluid dynamics, and other tasks.

[0024] The APD116 includes a compute unit 132 which includes one or more SIMD units 138 that operate in parallel according to the SIMD paradigm at the request of the processor 102. The SIMD paradigm is one in which multiple processing elements share a single program control flow unit and program counter and thus execute the same program, but can execute that program with different data or using different data. For example, each SIMD unit 138 includes 16 lanes, and each lane executes the same instruction simultaneously with other lanes in the SIMD unit 138, but can execute that instruction with different data. Lanes can be switched off using predication if not all lanes need to execute a given instruction. Predication can also be used to execute programs with branch control flows. More specifically, for programs with conditional branch instructions or other instructions in which the control flow is based on calculations performed by individual lanes, predication of lanes corresponding to control flow paths that are not currently being executed, and serial execution of different control flow paths, enables arbitrary control flows.

[0025] The basic unit of execution in the compute unit 132 is a work-item. Each work-item represents a single instantiation of a program to be executed in parallel on a specific lane. Work-items can be executed concurrently as a "wavefront" on a single SIMD unit 138. One or more wavefronts constitute a "work group," which is a collection of work-items designated to run the same program. A work group can be executed by executing each of the wavefronts that make up the work group. Alternatively, wavefronts can be executed sequentially on a single SIMD unit 138, or partially or fully in parallel on different SIMD units 138. A wavefront can be thought of as the largest collection of work-items that can be executed concurrently on a single SIMD unit 138. Therefore, if a command received from processor 102 indicates that a particular program should be parallelized to such an extent that it cannot be run concurrently on a single SIMD unit 138, the program is divided into wavefronts that are parallelized on two or more SIMD units 138, or serialized on the same SIMD unit 138 (or both parallelized and serialized as needed). Scheduler 136 performs operations related to scheduling various wavefronts on different compute units 132 and SIMD units 138.

[0026] The parallel processing provided by the computing unit 132 is suitable for graphics-related operations such as pixel value calculation, vertex transformation, and other graphics and non-graphics operations (sometimes referred to as "computational" operations). Therefore, in some cases, the graphics processing pipeline 134, which accepts graphics processing commands from the processor 102, provides computational tasks to the computing unit 132 for parallel execution.

[0027] Additionally, the compute unit 132 is used to perform computational tasks that are not related to graphics or are not performed as part of the "normal" operation of the graphics processing pipeline 134 (for example, custom operations performed to supplement the operations performed on the graphics processing pipeline 134). An application 126 or other software running on the processor 102 sends a program that defines such computational tasks to the APD 116 for execution.

[0028] Figure 3 is a block diagram of an exemplary automated test scenario in which IC300 is automatically tested by ATE302 through communication interface 306. In this example, IC300 is a system-on-a-chip (SoC), but in other embodiments, any suitable IC or other circuit can be tested. For example, IC300 may be or include a processor such as processor 102 as shown and described with respect to Figures 1 and 2, or it may be or include an APD as shown and described with respect to Figures 1 and 2. Communication interface 306 includes any suitable communication interface such as PCIe or USB. In various embodiments, the test is a functional test to determine whether there is a manufacturing defect or other defect. For example, in some embodiments, the test is a structural test or a scan test.

[0029] The ATE302 inputs one or more test patterns 304 to the communication interface 306 of the IC300, and a test circuit of the IC300 (e.g., a microcontroller) tests the circuit 390 of the IC300 (e.g., multiple tiles) using one or more of the test patterns 304 to generate a response 308. In some embodiments, testing the circuit 390 includes stimulating the inputs of the circuit 390 based on one or more of the test patterns 304 to generate a response 308 as the output of the circuit 390.

[0030] IC300 returns a response 308 to ATE302 through the communication interface 306. The ATE302's comparator circuit 310 compares response 308 with an expected response 312 (stored, for example, in ATE302 or any other suitable location) to determine whether IC300 is defective. In this example, ATE302 outputs a pass / fail signal 314. In other embodiments, other outputs (e.g., an indicator of the cause of the failure) are possible.

[0031] Figure 4 is a block diagram of another exemplary automated test scenario in which IC400 performs automated testing using an onboard microcontroller 402 that reads a test pattern 404 and an expected response 412 from external storage 450 via a communication interface 406.

[0032] In this example, IC400 is a system-on-a-chip (SoC), but in other embodiments, any suitable IC or other circuitry can be tested. For example, IC400 may be or include a processor such as processor 102 as shown and described with respect to Figures 1 and 2, or it may be or include an APD as shown and described with respect to Figures 1 and 2. The communication interface 406 includes any suitable communication interface such as PCIe or USB. The external storage 450 includes any suitable memory, storage, expandable medium, cloud storage, or other device that can store data and communicate data to IC400.

[0033] The microcontroller 402 reads one or more test patterns 404 from the external storage 450 through the communication interface 406 of the IC 400, tests the circuit 490 for testing (e.g., multiple tiles) on the IC 400 using one or more of the test patterns 404, and generates a response 408.

[0034] Furthermore, the microcontroller 402 reads the expected response 412 through the communication interface 406 (stored, for example, in external storage 450 or any other suitable location), compares the expected response 412 with response 408, and determines whether IC 400 is defective. Note that the test pattern 404 and the expected response 412 are too large to be fully stored in the registers of the microcontroller 402; rather, parts of the test pattern 404 and the expected response 412 are read from external storage 450, for example, as needed during testing.

[0035] In this example, the microcontroller 402 sets a pass / fail register 414 to indicate whether IC 400 is defective. In other embodiments, other outputs are possible (e.g., an indicator of the cause of the failure), or other signals are possible (e.g., an output via the communication interface 406).

[0036] In both the scenario in Figure 3 and the scenario in Figure 4, the communication interface 306 or communication interface 406 is not tested and is not testable because, in some embodiments, these interfaces are in use during the test procedure (e.g., for the on-demand reading of test patterns 404 and expected responses 412 from external storage 450) and are isolated from the test procedure. In some embodiments, the isolation includes circuitry to prevent the output of the communication interface from interfering with other circuitry being tested (e.g., inputs to the circuitry being tested that are set to specific values ​​by the test). In the scenario in Figure 3, the ATE 302 directly supplies the test pattern 304 to the IC 300 for testing. In the scenario in Figure 4, the microcontroller 402 reads one or more test patterns 404 and expected responses 412 from external storage 450 through the communication interface 406 for testing. Typically, the IC being tested does not contain a single sufficiently large memory to store relatively large test data (e.g., on the order of gigabits of data) in some embodiments.

[0037] Figure 5 is a block diagram of another exemplary automated test scenario in which IC 500 performs automated testing using an onboard microcontroller 502 that reads a test pattern 504 and an expected response 512 from external storage 550 via a communication interface 506.

[0038] In this example, IC500 is a system-on-a-chip (SoC), but in other embodiments, any suitable IC may be used. For example, IC500 may be a processor such as processor 102 as shown and described with respect to Figures 1 and 2, or it may be an APD as shown and described with respect to Figures 1 and 2, or it may be an APD. The communication interface 506 includes any suitable communication interface such as PCIe or USB. The external storage 550 includes any suitable memory, storage, expandable medium, cloud storage, or other device that can store data and communicate data to IC500.

[0039] The microcontroller 502 reads one or more test patterns 504 from the external storage 550 through the communication interface 506 of the IC 500, tests the circuit 590 (e.g., multiple tiles) using one or more of the test patterns 504, and generates a response 508. The microcontroller 502 routes one or more test patterns 504 from the communication interface 506 to the circuit 590 via a multiplexing circuit 570 that selects the communication interface 506 as the source of the test patterns, and a routing circuit 580 (e.g., a scan input router) that communicates the test patterns to different parts of the circuit 590 for testing (e.g., different tiles).

[0040] Note that the communication interface 506 is isolated from the test and does not receive any of the test patterns 504, nor does it contribute to the response 508 at this point.

[0041] Furthermore, the microcontroller 502 reads the expected response 512 through the communication interface 506 (stored, for example, in external storage 550 or any other suitable location), compares the expected response 512 with response 508, and determines whether IC 500 is defective. The microcontroller 502 routes the expected response 512 from the communication interface 506 to circuit 590 via a multiplexing circuit 570 that selects the communication interface 506 as the source of the expected response, and a routing circuit 580.

[0042] In this example, the microcontroller 502 sets a pass / fail register 514 to indicate whether IC 500 is defective. In other embodiments, other outputs are possible (e.g., an indicator of the cause of the failure), or other signals are possible (e.g., an output via the communication interface 506).

[0043] After this is complete, the microcontroller 502 reads one or more test patterns 504 and expected responses 512 from the external storage 550 through the communication interface 506 of the IC 500 and writes the test patterns 504 to the memory pool 599. The memory pool 599 is described in more detail herein. In some embodiments, the memory pool refers to several memories used together to store data. For example, in some embodiments, the memory pool includes several memories that store data across the memory, for example, in series.

[0044] After the test patterns 504 have been written to the memory pool 599, the microcontroller 502 reads one or more test patterns 504 from the memory pool 599 and uses one or more of the test patterns 504 to test the circuit of the communication interface 506 under test and generate a response 508. Note that, from the perspective of the example shown, the communication interface 506 is part of the circuit 590 and is no longer isolated from the test at this point. In some embodiments, circuits that have already been tested are isolated from the test at this point.

[0045] The microcontroller 502 routes one or more test patterns 504 from the communication interface 506 to the circuits of the communication interface 506 via a multiplexing circuit 570 that selects memory 599 as the source of the test patterns, and a routing circuit 580 that communicates the test patterns to the circuits of the communication interface 506.

[0046] Furthermore, the microcontroller 502 reads the expected response 512 from the memory pool 599 and compares the expected response 512 with response 508 to determine whether IC 500 is defective. The microcontroller 502 routes the expected response 512 from the memory pool 599 to circuit 590 via a multiplexing circuit 570 that selects the memory pool 599 as the source of the expected response and a routing circuit 580.

[0047] In this example, the microcontroller 502 sets a pass / fail register 514 to indicate whether IC 500 is defective. In other embodiments, other outputs are possible (e.g., an indicator of the cause of the failure), or other signals are possible (e.g., an output via the communication interface 506).

[0048] Figure 6 is a flowchart illustrating an exemplary method 600 for automated testing of an IC using an onboard microcontroller that reads test patterns and expected responses from external storage via a communication interface. Method 600 can be used, for example, in conjunction with the exemplary test scenario shown and described with respect to Figure 4. While Method 600 is exemplary, other embodiments may include additional elements, omit elements, and / or perform elements in a different order.

[0049] In 602, the microcontroller is reset by a cold boot or another appropriate signal. In 604, the microcontroller initiates a communication interface (e.g., PCIe, another host-device interface, or another communication interface) and begins reading test patterns and expected response data from external storage (or other storage). The microcontroller isolates the communication interface circuitry and, in 606, stimulates the circuit under test using the test patterns. In 608, the microcontroller compares the output to the expected response data of the circuit under test (i.e., excluding the communication interface circuitry). In 610, the microcontroller completes the test and continues with other tasks (e.g., boot process, memory repair, resetting the circuitry, etc.).

[0050] Note that, according to Method 600, the communication interface circuit remains untested.

[0051] Figure 7 is a flowchart illustrating an exemplary method 700 for automated testing of an IC using an onboard microcontroller that reads test patterns and expected responses from external storage via a communication interface. Method 700 can be used, for example, in conjunction with the exemplary test scenario shown and described with respect to Figure 5. While Method 700 is exemplary, other embodiments may include additional elements, omit elements, and / or perform elements in a different order.

[0052] In step 702, the microcontroller is reset by a cold boot or another appropriate signal. In step 704, the microcontroller starts the communication interface (e.g., PCIe) and begins reading test patterns and expected response data for all circuits under test except the communication interface from external storage. In step 706, the microcontroller isolates the communication interface circuit and stimulates the circuit under test using the test patterns. In step 708, the microcontroller compares the output to the expected response data for the circuit under test (i.e., excluding the communication interface circuit).

[0053] In step 710, the microcontroller begins reading test patterns and expected response data for the communication interface from external storage and writes these test patterns to a memory pool (as further described herein). In step 712, the microcontroller isolates the communication interface circuit from external storage and from other circuits (e.g., other tiles) and stimulates the communication interface circuit with the stored test patterns. In step 714, the microcontroller compares the output with the expected response data of the communication interface circuit (i.e., excluding other circuits).

[0054] The microcontroller completes testing in 716, releases the isolation of the communication circuit, and then continues other tasks in 718 (e.g., boot process, memory repair, resetting the circuit, etc.).

[0055] Note that the communication interface circuit has been tested according to Method 700.

[0056] Figures 8 to 18 illustrate circuits and methods for pooling memory on an IC under test, in the manner shown and described, for example, with respect to Figures 5 and 7. In this way, in some embodiments, several smaller memories, buffers, and / or other storage devices mounted on the IC are combined or "pooled" to store test data for testing a communication interface (and / or any other circuitry on the IC that may be desired to be isolated, for example). It should be noted that the circuits and / or methods for pooling memory shown and described with respect to Figures 8 to 18 can be used for any other suitable purpose, e.g., for purposes other than testing the IC. Figures 8 to 18 can be implemented using any suitable circuitry, for example, as shown and described with respect to Figures 1 and 2.

[0057] Figure 8 is a block diagram of an exemplary memory 800. Memory 800 is an SRAM, a latch array, or any other suitable memory, buffer, or storage device. In this example, each word in memory 800 is N bits wide, and memory 800 is M words long (i.e., memory 800 is M × N bits in size).

[0058] To write data to memory 800, write address 802 is given to write decoder 804, and the write decoder is enabled by write enable signal 806. With write enable signal 806, write data 808 is written to memory 800 at write address 802.

[0059] To read data from memory 800, the read address 810 is given to the read decoder 812, and the read decoder is enabled by the read enable signal 813. Upon receiving the read enable signal 813, the read data 814 is read from memory 800 at the read address 810.

[0060] Figure 9 is a block diagram showing an exemplary memory 800 with additional components for performing a built-in self-test (BIST). In some embodiments, any suitable BIST component is used. In the example in Figure 9, the multiplexing circuit 900 selects the source of the write data 808 as either functional write data 903 (e.g., data from a circuit that writes data to memory 800 during typical operation) or BIST write data 902, and selects the source of the write address 802 and read address 810 as either the source of the functional write data 903 or the addresses provided by the BIST counter 904. The BIST circuit provides the functionality to input a test pattern into memory 800 for testing (e.g., as described above).

[0061] Figure 10 is a block diagram showing an exemplary memory pool 1000, showing memory 800 and its associated BIST circuit, memory 1002 and its associated BIST circuit, and memory 1004 and its associated BIST circuit. Memories 1002 and 1004 and their associated BIST circuits are substantially similar to memory 800, except that they may have different widths and / or sizes. In this example, memory 1002 has a word width of B and a word length of A (i.e., size B × A), and memory 1004 has a word width of E and a word length of D (i.e., size E × D).

[0062] The BIST circuits of memories 800, 1002, and 1004 communicate such that saturation of the counter in memory 800 triggers the counter in 1002, and saturation of the counter in memory 1002 triggers the counter in 1004, as will be further described herein. The combined BIST circuits facilitate pooling or combination of several memories for use when storing, for example, a large ATPG dataset (or other data in other embodiments).

[0063] Three memories and their associated BIST circuits are shown for the example, but note that in some embodiments, any suitable number of memories can be used together. In this example, each memory has a different width and a different total size, but note that in some embodiments, some or all of the memories may have the same width and / or the same size.

[0064] Figures 11 to 14 are block diagrams illustrating a write operation in which data (e.g., test data) is written to the memory pool 1000 (e.g., from external storage or a host). In some embodiments, data is written to the memory pool by receiving the data through the respective BIST circuits of memory 800, memory 1002, and memory 1004.

[0065] In some embodiments, each BIST circuit of memory 800, memory 1002, and memory 1004 is configured to store data, for example, as a memory pool. In some embodiments, the memory of memory pool 1000 is configured to be written sequentially, for example, as described with reference to Figures 11 to 14.

[0066] Figure 11 is a block diagram illustrating exemplary write operations of exemplary memory pool 1000 during a first N clock cycle. Writes to memory pool 1000 are initiated based on any appropriate trigger 1100, which starts a BIST counter for the first memory in memory pool 1000. In some embodiments, the counter indicates the row of memory currently being written.

[0067] In this example, the BIST counter 1102 is relative to memory 800, which is the first memory in the memory pool 1000. In each clock cycle, a column of data is written to the first row (row 0) of memory 800. Note that in some embodiments, other amounts of data are written each clock cycle (e.g., multiple columns, a portion of a column, one or more bytes, or a portion of bytes of data). In this example, row 0 of memory 800 is completely written after N clock cycles. After N clock cycles, the BIST counter 1102 increments (to a value of 1 in this example).

[0068] Figure 12 is a block diagram showing exemplary write operations of an exemplary memory pool 1000 during a second N clock cycle (i.e., clock cycle N+1 to clock cycle N*2). In each clock cycle, a column of data is written to the second row (row 1) of memory 800. Row 1 of memory 800 is completely written after N*2 clock cycles. After N*2 clock cycles, the BIST counter 1102 is incremented (to a value of 2 in this example). Each row of memory 800 is written in this manner until the counter 1102 is saturated (in this case, to a value of M).

[0069] Figure 13 is a block diagram showing exemplary write operation of exemplary memory pool 1000 during the first B clock cycle (i.e., clock cycle N*M+1 to clock cycle N*M+B) after memory 800 has been completely written. Saturation of counter 1102 results in trigger 1300 for starting the BIST counter for the next memory in memory pool 1000 (memory 1002 in this example).

[0070] In each clock cycle, a column of data is written to the first row (row 0) of memory 1002. Row 0 of memory 1002 is completely written after B clock cycles from the start of writing to memory 1002 (or N*M+B clock cycles from the start of writing to memory pool 1000), after which the BIST counter 1104 is incremented (to a value of 1 in this example). The operation continues, and so row 1 of memory 1002 is completely written after B*2 clock cycles from the start of writing to memory 1002, and so on, until each row of memory 1002 is written in this manner until the counter 1104 is saturated (in this case, to a value of A).

[0071] Figure 14 is a block diagram illustrating an exemplary write operation of memory pool 1000 after N+B+E clock cycles from the start of writing to memory pool 1000. Saturation of counter 1104 triggers the start of the BIST counter 1400 for the next memory in memory pool 1000 (in this example, memory 1004). The operation proceeds, thereby completely writing each row of memory 1004 after each subsequent E clock cycle from the start of writing to memory 1004 until counter 1106 saturates (in this case, at a value of E). At this point, memory pool 1000 is completely written.

[0072] Figures 15 to 18 are block diagrams illustrating the read operation in which test data is read from memory pool 1000. In some embodiments, the data is read from the memory pool by an on-chip microcontroller or other suitable circuitry. In some embodiments, each of the BIST circuits of memory 800, memory 1002, and memory 1004 is configured to be read, for example, as a memory pool. In some embodiments, the memory of memory pool 1000 is configured to be read sequentially, for example, as described with respect to Figures 15 to 18.

[0073] Figure 15 is a block diagram illustrating an exemplary read operation of an exemplary memory pool 1000 during a first N clock cycle. A read from memory pool 1000 is initiated based on any appropriate trigger 1500, which starts a BIST counter for the first memory in memory pool 1000. In some embodiments, the counter indicates the row of memory currently being read.

[0074] In this example, the BIST counter 1102 is relative to memory 800, which is the first memory in the memory pool 1000. In each clock cycle, a column of data is read from the first row (row 0) of memory 800. Note that in some embodiments, other amounts of data are read per clock cycle (e.g., multiple columns, a portion of a column, one or more bytes, or a portion of bytes of data). In this example, row 0 of memory 800 is completely read after N clock cycles. After N clock cycles, the BIST counter 1102 increments (to a value of 1 in this example).

[0075] Figure 16 is a block diagram showing an exemplary read operation of an exemplary memory pool 1000 during a second N clock cycle (i.e., clock cycle N+1 to clock cycle N*2). In each clock cycle, a column of data is read from the second row (row 1) of memory 800. Row 1 of memory 800 is completely written after N*2 clock cycles. After N*2 clock cycles, the BIST counter 1102 is incremented (to a value of 2 in this example). Each row of memory 800 is read in this manner until the counter 1102 is saturated (in this case, to a value of M).

[0076] Figure 17 is a block diagram showing an exemplary read operation of an exemplary memory pool 1000 during the first B clock cycle (i.e., clock cycle N*M+1 to clock cycle N*M+B) after memory 800 has been completely read. Saturation of counter 1102 results in trigger 1700 for the start of the BIST counter for the next memory in memory pool 1000 (memory 1002 in this example).

[0077] In each clock cycle, a column of data is read from the first row (row 0) of memory 1002. Row 0 of memory 1002 is completely written after B clock cycles from the start of reading from memory 1002 (or N*M+B clock cycles from the start of reading from memory pool 1000), after which the BIST counter 1104 is incremented (to a value of 1 in this example). The operation continues, and so row 1 of memory 1002 is completely read after B*2 clock cycles from the start of writing to memory 1002, and so on, until each row of memory 1002 is read in this manner until the counter 1104 is saturated (in this case, to a value of A).

[0078] Figure 18 is a block diagram illustrating an exemplary read operation of memory pool 1000 after N+B+E clock cycles from the start of writing to memory pool 1000. Saturation of counter 1104 triggers trigger 1800 for starting the BIST counter for the next memory in memory pool 1000 (in this example, memory 1004). The operation proceeds, thereby completely reading each row of memory 1004 after each subsequent E clock cycle from the start of reading from memory 1004 until counter 1106 saturates (in this case, at a value of E). At this point, memory pool 1000 is completely read.

[0079] Figure 19 is a flowchart illustrating exemplary method 1900 for writing to a memory pool, such as shown and described with respect to Figures 11 to 14. While method 1900 is exemplary, other embodiments include additional elements, omit elements, combine elements, separate elements, and / or execute elements in a different order. Method 1900 can be implemented using any suitable circuit, such as shown and described with respect to Figures 1 to 18.

[0080] In 1902, the memory counter i is initialized to i=0, and the BIST counter for each memory in the memory pool is initialized to 0. The memory counter i is used to track the current memory in the memory pool being written to, and the BIST counter is used to track which portion (e.g., line) of each memory is being written to. Note that these counters are illustrative, and in other embodiments, other methods may be available for tracking the current memory and / or a portion of the current memory.

[0081] At 1904, data is written to memory location i, and at 1906, the BIST counter of memory location i is incremented. If the BIST counter of memory location i is saturated (i.e., indicates the last portion of memory location i), then i is incremented at 1910; otherwise, method 1900 returns to 1904, and data is written to the next portion of memory location i, indicated by the value of the BIST counter of memory location i. After i is incremented at 1910, if i > number of memory locations in the memory pool (i.e., the last memory location is completely written), then method 1900 terminates; otherwise, method 1900 returns to 1904, and data is written to the next portion of memory location i.

[0082] Figure 20 is a flowchart illustrating exemplary method 2000 for reading from a memory pool, as shown and described with respect to Figures 15-18, for example. While method 2000 is exemplary, other embodiments may include additional elements, omit elements, combine elements, separate elements, and / or execute elements in a different order. Method 2000 can be implemented using any suitable hardware, such as those shown and described with respect to Figures 1-18, for example.

[0083] In 2002, the memory counter i is initialized to i=0, and the BIST counter for each memory in the memory pool is initialized to 0. The memory counter i is used to track the current memory in the memory pool being read, and the BIST counter is used to track which portion (e.g., line) of each memory is being read. Note that these counters are illustrative, and in other embodiments, other methods may be available to track the current memory and / or a portion of the current memory.

[0084] In 2004, data is read from memory location i, and in 2006, the BIST counter of memory location i is incremented. If the BIST counter of memory location i is saturated (i.e., indicates the last portion of memory location i), i is incremented in 2010; otherwise, method 2000 returns to 2004, and data is read from the next portion of memory location i, indicated by the value of the BIST counter of memory location i. After i is incremented in 2010, if the condition 2012 is i > number of memory locations in the memory pool (i.e., the last memory location has been completely read), method 2000 terminates; otherwise, method 2000 returns to 2004, and data is read from the next portion of memory location i.

[0085] It should be understood that many variations are possible based on the disclosures herein. Although features and elements are described above in specific combinations, each feature or element can be used alone without other features and elements, or in various combinations with or without other features and elements.

[0086] Various functional units illustrated in each figure and / or described herein (including, but not limited to, the processor 102, input driver 112, input device 108, output driver 114, output device 110, acceleration device 116, scheduler 136, graphics processing pipeline 134, compute unit 132, and SIMD unit 138) can be implemented as a general-purpose computer, processor, or processor core, or as a program, software, or firmware stored on a non-temporary computer-readable medium or another medium executable by a general-purpose computer, processor, or processor core. The methods provided may be implemented in a general-purpose computer, processor, or processor core. Suitable processors include, by example, general-purpose processors, dedicated processors, conventional processors, digital signal processors (DSPs), multiple microprocessors, one or more microprocessors associated with a DSP core, controllers, microcontrollers, application-specific integrated circuits (ASICs), field-programmable gate array (FPGA) circuits, any other type of integrated circuit (IC), and / or state machines. Such processors may be manufactured by configuring a manufacturing process using the results of processed hardware description language (HDL) instructions and other intermediate data, including netlists (such as instructions that can be stored in a computer-readable medium). The results of such processing may be maskwork, which is then used in a subsequent semiconductor manufacturing process to manufacture a processor that implements the features of the present disclosure.

[0087] The methods or flowcharts provided herein may be implemented in computer programs, software, or firmware incorporated into non-temporary computer-readable storage media for execution by a general-purpose computer or processor. Examples of non-temporary computer-readable storage media include read-only memory (ROM), random-access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs).

Claims

1. An integrated circuit configured for self-testing, An interface circuit configured to read test data and write the test data to the memory of the integrated circuit, The system comprises a test circuit configured to test the interface circuit based on the test data written to the memory of the integrated circuit, Integrated circuit.

2. The interface circuit is configured to read the test data from an external storage device. The integrated circuit according to claim 1.

3. The memory of the integrated circuit comprises a plurality of memories, the plurality of memories being located on the same die as the integrated circuit, in the same package as the integrated circuit, or both on the same die as the integrated circuit and in the same package as the integrated circuit. The integrated circuit according to claim 1.

4. The memory of the aforementioned integrated circuit includes a memory pool. The integrated circuit according to claim 1.

5. The memory of the integrated circuit comprises a plurality of memories, each of which is configured to be accessed serially, or configured to be written to and read from the memory via a built-in self-test (BIST) circuit, or configured to be accessed serially and also configured to be written to and read from the memory via a BIST circuit. The integrated circuit according to claim 1.

6. The memory comprises a first memory and a second memory, and the interface circuit is configured to write the first portion of the test data to the first memory on the integrated circuit until the first portion of the test data is completely written to the first memory, and then write the second portion of the test data to the second memory on the integrated circuit after the first portion of the test data has been completely written. The integrated circuit according to claim 1.

7. The memory comprises a first memory and a second memory, and the test circuit is configured to read the first portion of the test data from the first memory on the integrated circuit until the first portion of the test data has been completely read from the first memory, and after the first portion of the test data has been completely read, to read the second portion of the test data from the second memory on the integrated circuit. The integrated circuit according to claim 1.

8. The test circuit is configured to read the test data from the memory of the integrated circuit, input the test data to the interface circuit to generate test output data, and compare the test output data with expected output data. The integrated circuit according to claim 1.

9. A method for testing integrated circuits, The test data is written to the memory of the integrated circuit via the interface circuit of the integrated circuit, This includes testing the interface circuit based on the test data written to the memory of the integrated circuit, method.

10. The test data is written from an external storage device to the memory on the integrated circuit via the interface circuit of the integrated circuit. The method of claim 9.

11. The memory of the integrated circuit comprises a plurality of memories, the plurality of memories being located on the same die as the integrated circuit, in the same package as the integrated circuit, or both on the same die as the integrated circuit and in the same package as the integrated circuit. The method of claim 9.

12. The memory of the aforementioned integrated circuit includes a memory pool. The method of claim 9.

13. The memory of the integrated circuit comprises a plurality of memories, each of which is configured to be accessed serially, or configured to be written to and read from the memory via a built-in self-test (BIST) circuit, or configured to be accessed serially and also configured to be written to and read from the memory via a BIST circuit. The method of claim 9.

14. Writing the test data to the memory on the integrated circuit via the interface circuit includes writing the first portion of the test data to the first memory until the first portion of the test data is completely written to the first memory on the integrated circuit, and writing the second portion of the test data to the second memory until the second portion of the test data is completely written to the second memory on the integrated circuit after the first portion of the test data has been completely written. The method of claim 9.

15. Testing the interface circuit based on the test data includes reading the first portion of the test data from the first memory until the first portion of the test data is completely read from the first memory on the integrated circuit, and after the first portion of the test data has been completely read, reading the second portion of the test data from the second memory until the second portion of the test data is completely read from the second memory on the integrated circuit. The method of claim 9.

16. Testing the interface circuit based on the test data written to the memory of the integrated circuit includes reading the test data from the memory of the integrated circuit, inputting the test data to the interface circuit to generate test output data, and comparing the test output data with expected output data. The method of claim 9.

17. An integrated circuit configured to store data, A circuit configured to write a first portion of the data to the first memory via the BIST circuit of the first memory until the first built-in self-test (BIST) counter saturates, The system includes a circuit configured to write a second portion of the data to the second memory via the BIST circuit of the second memory until the second BIST counter is saturated. Integrated circuit.

18. The system includes a circuit configured to trigger the writing of the second portion of the data to the second memory based on the saturation of the first BIST counter, The integrated circuit according to claim 17.

19. The first memory and the second memory are composed of the integrated circuit or integrated circuit die, and the integrated circuit includes a circuit configured to read the data from a memory device located outside the integrated circuit or the integrated circuit die. The integrated circuit according to claim 17.

20. The first memory and the second memory are comprised of an integrated circuit package, and the integrated circuit includes a circuit configured to read the data from a memory device located outside the integrated circuit package. The integrated circuit according to claim 17.

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