RF amplifier package and method for manufacturing the same

Abstract

The transistor device package includes an interconnect structure, a transistor die having a front surface including gate, drain, and source terminals on a first surface of the interconnect structure, and a component assembly comprising one or more passive electrical components electrically coupled to the gate, drain, and / or source terminals by the interconnect structure. A thermally conductive flange is attached to the rear surface of the transistor die, opposite the front surface, by conductive adhesive. Each pattern of conductive adhesive is provided on the first surface of the interconnect structure, and at least one of each pattern of conductive adhesive provides an input, output, or ground signal path for the transistor device package. Related fabrication methods are also discussed.

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims priority under 35 U.S.C. § 119 to U.S. Provisional Patent Application No. 63 / 004,765, filed on April 3, 2020; is a continuation - in - part of U.S. Patent Application No. 16 / 906,610, filed on June 19, 2020, now U.S. Patent No. 11,670,605, and claims priority thereto; is a continuation - in - part of U.S. Patent Application No. 17 / 018,762, filed on September 11, 2020, and claims priority thereto; is a continuation - in - part of U.S. Patent Application No. 17 / 848,546, filed on June 24, 2022, and claims priority thereto; and claims priority from U.S. Patent Application No. 18 / 334,466, filed on June 14, 2023. U.S. Patent Application No. 18 / 334,466 is also a continuation - in - part of each of U.S. Patent Application No. 17 / 018,721, filed on September 11, 2020, and U.S. Patent Application No. 16 / 888,957, filed on June 1, 2020, now U.S. Patent No. 11,356,070, and is a continuation - in - part of U.S. Patent Application No. 17 / 737,054, filed on May 5, 2022, and claims priority thereto. The entire contents of each of these patent applications are incorporated herein by reference.

[0002] This disclosure is directed to integrated circuit devices, and more particularly, to structures for packaging integrated circuit devices.

Background Art

[0003] RF power amplifiers are used in a variety of applications, such as base stations for wireless communication systems and multi-stage, multi-path amplifiers (e.g., Doherty amplifiers). Signals amplified by RF power amplifiers often include those with modulated carriers having frequencies in the megahertz (MHz) to gigahertz (GHz) range. For example, electrical circuits requiring high power handling capabilities while operating at high frequencies such as the R-band (0.5-1 GHz), S-band (3 GHz), X-band (10 GHz), Ku-band (12-18 GHz), K-band (18-27 GHz), Ka-band (27-40 GHz), and V-band (40-75 GHz) are becoming increasingly common. In particular, there is currently a growing demand for radio frequency ("RF") transistor amplifiers used to amplify RF signals at frequencies above 500 MHz (including microwave frequencies). These RF transistor amplifiers may need to exhibit high reliability, good linearity, and handle high output power levels.

[0004] Many RF power amplifier designs utilize semiconductor switching devices as amplification devices. Examples of these switching devices include power transistor devices such as MOSFETs (metal-oxide-semiconductor field-effect transistors), DMOS (dual-diffusion metal-oxide-semiconductor) transistors, HEMTs (high electron-mobility transistors), MESFETs (metal-electron-semiconductor field-effect transistors), and LDMOS (lateral-diffusion metal-oxide-semiconductor) transistors.

[0005] RF amplifiers are typically formed as semiconductor integrated circuit chips. Most RF amplifiers are implemented in silicon or using broad-bandgap semiconductor materials (i.e., having a bandgap greater than 1.40 eV) such as silicon carbide ("SiC") and Group III nitride materials. As used herein, the term "Group III nitride" refers to semiconductor compounds formed between nitrogen and elements in Group III of the periodic table, typically aluminum (Al), gallium (Ga), and / or indium (In). The term also refers to ternary and quaternary compounds such as AlGaN and AlInGaN. These compounds have an empirical formula in which 1 mole of nitrogen is bonded to a total of 1 mole of Group III elements.

[0006] Silicon-based RF amplifiers are typically implemented using LDMOS transistors and can exhibit a high level of linearity while being relatively inexpensive to fabricate. Group III nitride-based RF amplifiers are typically implemented using HEMTs, mainly in applications requiring high power and / or high frequency operation where LDMOS transistor amplifiers may have inherent performance limitations.

[0007] An RF transistor amplifier may comprise one or more amplification stages, each typically implemented as a transistor amplifier. To increase output power and current handling capability, RF transistor amplifiers are typically implemented in a "unit cell" configuration, where a number of individual "unit cell" transistors are electrically arranged in parallel. An RF transistor amplifier may be implemented as a single integrated circuit chip or "die," or may comprise multiple dies. When multiple RF transistor amplifier dies are used, they may be connected in series and / or parallel.

[0008] RF transistor amplifiers often include matching circuits, such as impedance matching circuits designed to improve impedance matching between the active transistor die (e.g., including MOSFETs, HEMTs, LDMOSs, etc.) and the transmission line connected thereto for RF signals at the fundamental operating frequency, as well as harmonic termination circuits designed to at least partially terminate harmonic products that may be generated during device operation, such as second and third harmonic components. The termination of harmonic products also affects the generation of intermodulation distortion products.

[0009] RF amplifier transistor dies and impedance matching and harmonic termination circuits can be encapsulated within a device package. A die or chip can refer to a small block of semiconductor material or other substrate on which electronic circuit elements are fabricated. Integrated circuit packaging can refer to encapsulating one or more dies within a support case or package that protects the dies from physical damage and / or corrosion and supports electrical contacts for connection to external circuits. Input and output impedance matching circuits within an integrated circuit device package typically include an LC network that provides at least a portion of an impedance matching circuit configured to match the impedance of the active transistor die to a fixed value. Electrical leads extend from the package to electrically connect the RF amplifier to external circuit elements such as input and output RF transmission lines and bias voltage sources.

[0010] Some conventional methods for assembling RF power devices may involve assembling some of the transistor die and matching network components within ceramic or overmolded packages on CPC (copper, copper-molybdenum, copper laminate) or copper flanges, which may be used for heat dissipation and, depending on the application, may be mounted on a customer-side heatsink. Transistor dies, capacitors, and input / output leads may be interconnected using wires such as gold and / or aluminum wires (also referred to herein as chip-and-wire configurations). Such assembly processes can be slow and sequential (e.g., packages are bonded one at a time) and can be costly (e.g., due to gold wires and expensive wire bonding machines). Furthermore, as operating frequencies increase, chip-and-wire type RF power devices may suffer performance losses from long, high-impedance connections using wire bonding. [Overview of the Initiative]

[0011] According to some embodiments, the transistor device package includes an interconnect structure, a transistor die having a front surface including gate terminals, drain terminals, and source terminals on a first surface of the interconnect structure, and a component assembly comprising one or more passive electrical components electrically coupled to the gate terminals, drain terminals, and / or source terminals by the interconnect structure. A thermally conductive flange is attached to the rear surface of the transistor die, opposite to the front surface, by conductive adhesive.

[0012] In some embodiments, each pattern of conductive adhesive lies on a first surface of an interconnect structure. At least one of each pattern of conductive adhesive provides an input, output, or ground signal path for a transistor device package.

[0013] In some embodiments, each pattern of the conductive adhesive attaches one or more conductive leads to each conductive pattern on the first surface of the interconnection structure, thereby electrically connecting them.

[0014] In some embodiments, each pattern of conductive adhesive attaches the thermally conductive flange to the conductive pattern on the first surface of the interconnect structure, thereby electrically connecting them.

[0015] In some embodiments, the interconnect structure comprises one or more internally integrated conductive leads that protrude outward from the periphery of the transistor device package.

[0016] In some embodiments, one or more support structures extend from a thermally conductive flange to a first surface of the interconnect structure.

[0017] In some embodiments, the support structures include one or more conductive support structures that are attached to a conductive pattern on a first surface of an interconnection structure by each pattern of conductive adhesive and electrically connected.

[0018] In some embodiments, one or more conductive support structures are integral with a thermally conductive flange and include one or more conductive pillar structures projecting from the thermally conductive flange to a first surface of the interconnect structure.

[0019] In some embodiments, one or more conductive leads are located inside the periphery of the transistor device package and include portions that are bent toward or outward from the first surface of the interconnect structure.

[0020] In some embodiments, an overmolded material is formed on the transistor die between the first surface of the interconnect structure and the thermally conductive flange.

[0021] In some embodiments, one or more passive electrical components are on a second surface of the interconnect structure that is opposite the first surface.

[0022] In some embodiments, at least one of the passive electrical components is on a portion of the second surface of the interconnect structure that overlaps with the transistor die on the first surface.

[0023] In some embodiments, the overmold material is formed on one or more passive electrical components on the second surface of the interconnect structure.

[0024] In some embodiments, a lid member that defines an open cavity around one or more passive electrical components is provided on the second surface of the interconnect structure.

[0025] In some embodiments, one or more passive electrical components include surface mount devices and / or integrated passive devices.

[0026] In some embodiments, the transistor device package has no wire bond connections.

[0027] According to some embodiments, the transistor device package includes a component assembly comprising an interconnect structure and a transistor die having a front face including gate, drain, and source terminals on a first surface of the interconnect structure. Each pattern of conductive adhesive is provided on the first surface of the interconnect structure. At least one of each pattern of conductive adhesive provides an input, output, or ground signal path of the transistor device package.

[0028] In some embodiments, each pattern of conductive adhesive attaches and electrically connects one or more conductive leads to respective conductive patterns on the first surface of the interconnect structure.

[0029] In some embodiments, each pattern of conductive adhesive attaches the thermally conductive flange to the conductive pattern on the first surface of the interconnect structure, thereby electrically connecting them.

[0030] According to some embodiments, a method for fabricating a transistor device package includes providing an interconnect structure, a transistor die having a front surface including gate terminals, drain terminals, and source terminals on a first surface of the interconnect structure, and a component assembly comprising one or more passive electrical components electrically coupled to the gate terminals, drain terminals, and / or source terminals by the interconnect structure. The method further includes attaching the rear surface of the transistor die, opposite to the front surface, to a thermally conductive flange with a conductive adhesive.

[0031] In some embodiments, each pattern of conductive adhesive is provided on a first surface of the interconnect structure. Each pattern of conductive adhesive provides an input, output, or ground signal path for the transistor device package.

[0032] In some embodiments, the method includes applying a conductive adhesive in each pattern onto one or more conductive leads, and then using each pattern of conductive adhesive to attach one or more conductive leads to a conductive pattern on a first surface of an interconnect structure. Each pattern of conductive adhesive electrically connects one or more conductive leads to the conductive pattern of the interconnect structure.

[0033] In some embodiments, the method includes applying a conductive adhesive in each pattern onto each region of the first surface of the interconnect structure, and then attaching a thermally conductive flange to the conductive pattern on each region of the first surface of the interconnect structure. Each pattern of conductive adhesive electrically connects the thermally conductive flange to the conductive pattern of the interconnect structure.

[0034] In some embodiments, the interconnect structure comprises one or more internally integrated conductive leads that protrude outward from the periphery of the transistor device package.

[0035] In some embodiments, the thermally conductive flange comprises one or more conductive pillar structures protruding therefrom, and mounting the thermally conductive flange involves attaching one or more conductive pillar structures to a conductive pattern on a first surface of the interconnect structure by each pattern of conductive adhesive.

[0036] In some embodiments, the interconnection structure includes each interconnection structure of a plurality of interconnection structures of an interconnection array, and the method further includes separating the interconnection array into a plurality of interconnection structures before attaching the thermally conductive flanges.

[0037] In some embodiments, the interconnect array includes slots internally, and mounting the thermal conductive flanges involves inserting a clamping device into one or more of the slots and clamping the thermal conductive flanges to the interconnect structure using the clamping device such that one or more conductive pillar structures contact each area of ​​the first surface of the interconnect structure having each pattern of conductive adhesive thereon.

[0038] In some embodiments, the interconnection structure includes each interconnection structure of a plurality of interconnection structures of an interconnection array. The method further includes separating the interconnection array into a plurality of interconnection structures after attaching thermally conductive flanges.

[0039] In some embodiments, the method includes forming an overmolded material between a first surface of an interconnect structure and a thermally conductive flange on a transistor die.

[0040] In some embodiments, one or more passive electrical components are provided on a second surface of the interconnection structure opposite to the first surface.

[0041] In some embodiments, the method includes forming an overmolded material structure on one or more passive electrical components on a second surface of an interconnection structure.

[0042] In some embodiments, the method includes providing a cover member on a second surface of an interconnect structure that defines an open cavity around one or more passive electrical components.

[0043] In some embodiments, the transistor device package does not have wire bond connections.

[0044] In some embodiments, the transistor die includes a high electron mobility transistor (HEMT) or a lateral diffusion metal-oxide-semiconductor (LDMOS) transistor.

[0045] In some embodiments, the transistor die is a group III nitride-based RF transistor amplifier die.

[0046] Other devices, apparatus, and / or methods in some embodiments will become apparent to those skilled in the art by examining the following drawings and detailed description. All such additional embodiments, in addition to any and all combinations of the above embodiments, are incorporated herein, within the scope of the invention, and are intended to be protected by the appended claims. [Brief explanation of the drawing]

[0047] [Figure 1A] This is a schematic cross-sectional view of a conventional high-electron-mobility transistor. [Figure 1B] This is a schematic side view of a conventional packaged Group III nitride-based RF transistor amplifier. [Figure 1C]This is a schematic cross-sectional view along line 1C-1C in Figure 1B, showing the structure of the upper metallization of the RF transistor amplifier die contained within the RF transistor amplifier in Figure 1B. [Figure 1D] This is a schematic side view of another conventional group III nitride-based RF transistor amplifier. [Figure 2A] This is a schematic side view of a group III nitride-based RF transistor amplifier according to several embodiments of the present invention. [Figure 2B] This is a schematic plan view of the RF transistor amplifier die, which is part of the group III nitride-based RF transistor amplifier shown in Figure 2A, along line 2B-2B in Figure 2A. [Figure 2C] This is a cross-sectional view along line 2C-2C in Figure 2B. [Figure 2D] This is a cross-sectional view along line 2D-2D in Figure 2B. [Figure 2E] This is a cross-sectional view along line 2E-2E in Figure 2B. [Figure 2F] This is a cross-sectional view along line 2F-2F in Figure 2B. [Figure 2G] This is a cross-sectional view of an additional embodiment of the present invention. [Figure 2H] This is a cross-sectional view of an additional embodiment of the present invention. [Figure 2I] This is a cross-sectional view of an additional embodiment of the present invention. [Figure 2J] This is a cross-sectional view of an additional embodiment of the present invention. [Figure 2K] This is a cross-sectional view of an additional embodiment of the present invention. [Figure 2L] This is a cross-sectional view of an additional embodiment of the present invention. [Figure 3A] This is a schematic cross-sectional view of an RF transistor amplifier coupled to a circuit module according to some embodiments of the present invention. [Figure 3B] This is a schematic cross-sectional view of an RF transistor amplifier die coupled to a circuit module according to several embodiments of the present invention. [Figure 3C]This is a schematic cross-sectional view of an RF transistor amplifier die incorporating a redistribution layer coupled to a circuit module, according to some embodiments of the present invention. [Figure 3D] This is a schematic cross-sectional view of a circuit module coupled with multiple RF transistor amplifiers according to some embodiments of the present invention. [Figure 3E] This is a schematic cross-sectional view of a circuit module coupled to multiple RF transistor amplifier dies according to several embodiments of the present invention. [Figure 4A] This is a schematic cross-sectional view of an RF transistor amplifier and circuit module coupled to a carrier substrate according to some embodiments of the present invention. [Figure 4B] This is a schematic cross-sectional view of an RF transistor amplifier and circuit module coupled to a carrier substrate without using coupling elements, according to some embodiments of the present invention. [Figure 4C] This is a schematic cross-sectional view of a plurality of RF transistor amplifier dies coupled to a circuit module and arranged on a carrier substrate, according to some embodiments of the present invention. [Figure 5A] This is a schematic diagram of one of the various packaging options for an RF transistor amplifier according to several embodiments of the present invention. [Figure 5B] This is a schematic diagram of one of the various packaging options for an RF transistor amplifier according to several embodiments of the present invention. [Figure 5C] This is a schematic diagram of one of the various packaging options for an RF transistor amplifier according to several embodiments of the present invention. [Figure 6A] This is a schematic cross-sectional view of an additional embodiment of an RF transistor amplifier coupled to a circuit module, according to some embodiments of the present invention. [Figure 6B] This is a schematic cross-sectional view of an additional embodiment of an RF transistor amplifier coupled to a circuit module, according to some embodiments of the present invention. [Figure 6C]This is a schematic cross-sectional view of an additional embodiment of an RF transistor amplifier coupled to a circuit module, according to some embodiments of the present invention. [Figure 7A] This is a schematic diagram illustrating a method for coupling a circuit module and an RF transistor amplifier die according to a specific embodiment of the present invention. [Figure 7B] This is a schematic diagram illustrating a method for coupling a circuit module and an RF transistor amplifier die according to a specific embodiment of the present invention. [Figure 7C] This is a schematic diagram illustrating a method for coupling a circuit module and an RF transistor amplifier die according to a specific embodiment of the present invention. [Figure 7D] This is a schematic diagram illustrating a method for coupling a circuit module and an RF transistor amplifier die according to a specific embodiment of the present invention. [Figure 7E] This is a schematic diagram illustrating a method for coupling a circuit module and an RF transistor amplifier die according to a specific embodiment of the present invention. [Figure 8A] This is a schematic cross-sectional view of one of the various packaging options for a circuit module according to several embodiments of the present invention. [Figure 8B] This is a schematic cross-sectional view of one of the various packaging options for a circuit module according to several embodiments of the present invention. [Figure 9A] This is a plan view of one embodiment of a circuit module according to several embodiments of the present invention. [Figure 9B] This is a cross-sectional view along line 9B-9B in Figure 9A. [Figure 9C] This is a cross-sectional view along line 9C-9C in Figure 9A. [Figure 9D] This is a cross-sectional view of the circuit module shown in Figure 9A, mounted on a substrate according to some embodiments of the present invention. [Figure 10A] This is a schematic cross-sectional view of one of the various packaging options for a circuit module according to several embodiments of the present invention. [Figure 10B]This is a schematic cross-sectional view of one of the various packaging options for a circuit module according to several embodiments of the present invention. [Figure 11A] This is a schematic cross-sectional view of an additional embodiment of an RF transistor amplifier coupled to a circuit module, according to some embodiments of the present invention. [Figure 11B] This is a schematic cross-sectional view of an additional embodiment of an RF transistor amplifier coupled to a circuit module, according to some embodiments of the present invention. [Figure 11C] This is a schematic cross-sectional view of an additional embodiment of an RF transistor amplifier coupled to a circuit module, according to some embodiments of the present invention. [Figure 11D] This is a schematic cross-sectional view of an additional embodiment of an RF transistor amplifier coupled to a circuit module, according to some embodiments of the present invention. [Figure 12A] This is a schematic cross-sectional view of an additional embodiment of an RF transistor amplifier die coupled to a circuit module, according to some embodiments of the present invention. [Figure 12B] This is a schematic cross-sectional view of an additional embodiment of an RF transistor amplifier die coupled to a circuit module, according to some embodiments of the present invention. [Figure 12C] This is a schematic cross-sectional view of an additional embodiment of an RF transistor amplifier die coupled to a circuit module, according to some embodiments of the present invention. [Figure 12D] This is a schematic cross-sectional view of an additional embodiment of an RF transistor amplifier die coupled to a circuit module, according to some embodiments of the present invention. [Figure 13A] This is a schematic cross-sectional view of an additional embodiment of an RF transistor amplifier die coupled to a circuit module and incorporating a spacer, according to some embodiments of the present invention. [Figure 13B] This is a schematic cross-sectional view of an additional embodiment of an RF transistor amplifier die coupled to a circuit module and incorporating a spacer, according to some embodiments of the present invention. [Figure 13C]This is a schematic cross-sectional view of an additional embodiment of an RF transistor amplifier die coupled to a circuit module and incorporating a spacer, according to some embodiments of the present invention. [Figure 13D] This is a schematic cross-sectional view of an additional embodiment of an RF transistor amplifier die coupled to a circuit module and incorporating a spacer, according to some embodiments of the present invention. [Figure 14A] This is a schematic cross-sectional view of one of the various packaging options for a circuit module according to several embodiments of the present invention. [Figure 14B] This is a schematic cross-sectional view of one of the various packaging options for a circuit module according to several embodiments of the present invention. [Figure 14C] This is a schematic cross-sectional view of one of the various packaging options for a circuit module according to several embodiments of the present invention. [Figure 14D] This is a schematic cross-sectional view of one of the various packaging options for a circuit module according to several embodiments of the present invention. [Figure 15A] This is a schematic cross-sectional view of an additional RF transistor amplifier embodiment, according to some embodiments of the present invention, which includes a circuit module and incorporates a mechanism for coupling a first circuit element and a second circuit element. [Figure 15B] This is a schematic cross-sectional view of an additional RF transistor amplifier embodiment, according to some embodiments of the present invention, which includes a circuit module and incorporates a mechanism for coupling a first circuit element and a second circuit element. [Figure 15C] This is a schematic cross-sectional view of an additional RF transistor amplifier embodiment, according to some embodiments of the present invention, which includes a circuit module and incorporates a mechanism for coupling a first circuit element and a second circuit element. [Figure 15D] This is a schematic cross-sectional view of an additional RF transistor amplifier embodiment, according to some embodiments of the present invention, which includes a circuit module and incorporates a mechanism for coupling a first circuit element and a second circuit element. [Figure 16A] This is a schematic cross-sectional view of one of the various packaging options for a circuit module according to several embodiments of the present invention. [Figure 16B] This is a schematic cross-sectional view of one of the various packaging options for a circuit module according to several embodiments of the present invention. [Figure 16C] This is a schematic cross-sectional view of one of the various packaging options for a circuit module according to several embodiments of the present invention. [Figure 16D] This is a schematic cross-sectional view of one of the various packaging options for a circuit module according to several embodiments of the present invention. [Figure 17] This is a schematic cross-sectional view of an RF transistor amplifier including active and passive component assemblies according to several embodiments of the present invention. [Figure 18] This is a schematic cross-sectional view of an RF transistor amplifier including active and passive component assemblies according to several embodiments of the present invention. [Figure 19A] This is a schematic cross-sectional view of one of several passive component assemblies according to some embodiments of the present invention. [Figure 19B] This is a schematic cross-sectional view of one of several passive component assemblies according to some embodiments of the present invention. [Figure 19C] This is a schematic cross-sectional view of one of several passive component assemblies according to some embodiments of the present invention. [Figure 20A] This is a schematic cross-sectional view of one of several active component assemblies according to some embodiments of the present invention. [Figure 20B] This is a schematic cross-sectional view of one of several active component assemblies according to some embodiments of the present invention. [Figure 20C] This is a schematic cross-sectional view of one of several active component assemblies according to some embodiments of the present invention. [Figure 21A]This is a schematic diagram of one of the various packaging options for an RF transistor amplifier, including active and passive component assemblies according to several embodiments of the present invention. [Figure 21B] This is a schematic diagram of one of the various packaging options for an RF transistor amplifier, including active and passive component assemblies according to several embodiments of the present invention. [Figure 22] This is a schematic diagram of one of the various packaging options for an RF transistor amplifier, including active and passive component assemblies according to several embodiments of the present invention. [Figure 23A] This is a schematic diagram of one of the various packaging options for an RF transistor amplifier, including active and passive component assemblies according to several embodiments of the present invention. [Figure 23B] This is a schematic diagram of one of the various packaging options for an RF transistor amplifier, including active and passive component assemblies according to several embodiments of the present invention. [Figure 24A] This is a schematic diagram of one of the various packaging options for an RF transistor amplifier, including active and passive component assemblies according to several embodiments of the present invention. [Figure 24B] This is a schematic diagram of one of the various packaging options for an RF transistor amplifier, including active and passive component assemblies according to several embodiments of the present invention. [Figure 24C] This is a schematic diagram of one of the various packaging options for an RF transistor amplifier, including active and passive component assemblies according to several embodiments of the present invention. [Figure 24D] This is a schematic diagram of one of the various packaging options for an RF transistor amplifier, including active and passive component assemblies according to several embodiments of the present invention. [Figure 25A]This is a schematic diagram of one of the various packaging options for an RF transistor amplifier, including active and passive component assemblies according to several embodiments of the present invention. [Figure 25B] This is a schematic diagram of one of the various packaging options for an RF transistor amplifier, including active and passive component assemblies according to several embodiments of the present invention. [Figure 25C] This is a schematic diagram of one of the various packaging options for an RF transistor amplifier, including active and passive component assemblies according to several embodiments of the present invention. [Figure 26A] This is a schematic circuit diagram showing one of the various circuit topologies that can be implemented by combinations of active and passive component assemblies according to several embodiments of the present invention. [Figure 26B] This is a schematic circuit diagram showing one of the various circuit topologies that can be implemented by combinations of active and passive component assemblies according to several embodiments of the present invention. [Figure 26C] This is a schematic circuit diagram showing one of the various circuit topologies that can be implemented by combinations of active and passive component assemblies according to several embodiments of the present invention. [Figure 27A] This is a schematic cross-sectional view of a transistor device package including a flip-chip component assembly integrated into a high-power package type according to several embodiments of the present invention. [Figure 27B] This is a schematic cross-sectional view of a transistor device package including a flip-chip component assembly integrated into a high-power package type according to several embodiments of the present invention. [Figure 28A] This flowchart illustrates an exemplary operation for fabricating the transistor device package shown in Figure 27A or Figure 27B. [Figure 28B] This flowchart illustrates an exemplary operation for fabricating the transistor device package shown in Figure 27A or Figure 27B. [Figure 29A]This is a schematic plan view showing an exemplary embodiment of a ground signal path for a transistor device package according to several embodiments of the present invention. [Figure 29B] This is a schematic plan view showing an exemplary embodiment of a ground signal path for a transistor device package according to several embodiments of the present invention. [Figure 30A] This is a schematic cross-sectional view of a transistor device package comprising a flip-chip component assembly integrated into a high-power package type, having package leads provided by an interconnect structure, according to some embodiments of the present invention. [Figure 30B] This is a schematic cross-sectional view of a transistor device package comprising a flip-chip component assembly integrated into a high-power package type, having package leads provided by an interconnect structure, according to some embodiments of the present invention. [Figure 31A] This flowchart illustrates an exemplary operation for fabricating the transistor device package shown in Figure 30A or Figure 30B. [Figure 31B] This flowchart illustrates an exemplary operation for fabricating the transistor device package shown in Figure 30A or Figure 30B. [Figure 32A] This is a schematic plan view illustrating exemplary operation for fabricating a transistor device package according to several embodiments of the present invention. [Figure 32B] This is a schematic plan view illustrating exemplary operation for fabricating a transistor device package according to several embodiments of the present invention. [Figure 32C] This is a schematic side view illustrating exemplary operation for fabricating a transistor device package according to several embodiments of the present invention. [Figure 32D] Figure 32C is a perspective view of the transistor device package formed according to the operation. [Figure 33] This flowchart illustrates exemplary operations for in-strip fabrication of transistor device packages according to several embodiments of the present invention. [Figure 34A]This flowchart illustrates an exemplary operation for in-strip fabrication of the transistor device package shown in Figure 30A or Figure 30B according to several embodiments of the present invention. [Figure 34B] This flowchart illustrates an exemplary operation for in-strip fabrication of the transistor device package shown in Figure 30A or Figure 30B according to several embodiments of the present invention. [Figure 34C] This flowchart illustrates an exemplary operation for in-strip fabrication of the transistor device package shown in Figure 30A or Figure 30B according to several embodiments of the present invention. [Figure 34D] This flowchart illustrates an exemplary operation for in-strip fabrication of the transistor device package shown in Figure 30A or Figure 30B according to several embodiments of the present invention. [Modes for carrying out the invention]

[0048] In the following detailed description, numerous specific details are provided to provide a complete understanding of the embodiments of the Disclosure. However, it will be understood by those skilled in the art that the Disclosure can be implemented without these specific details. In some cases, known methods, procedures, components, and circuits are not described in detail so as not to obscure the Disclosure. It is intended that all embodiments disclosed herein can be implemented separately or in any combination and / or in any way. Aspects described in relation to one embodiment may be incorporated into a different embodiment even if they are not specifically described with respect to that embodiment. That is, features of all embodiments and / or any embodiments can be combined in any way and / or in any way.

[0049] According to embodiments of the present invention, a group III nitride-based RF transistor amplifier is provided, comprising an RF transistor amplifier die in which the gate terminal, drain terminal, and source terminal are all located on the top surface of the RF transistor amplifier die. In some embodiments, the RF transistor amplifier may not include bond wires for the gate and drain connections, thereby reducing the amount of inductance present in the circuit. Top contacts may allow coupling elements to be directly coupled to the gate, drain, and source terminals of the RF transistor amplifier die. The coupling elements may be further connected in a conventional manner to additional circuits such as harmonic termination circuits, input impedance matching circuits, and / or output impedance matching circuits. In certain embodiments where the substrate of the transistor die has high thermal conductivity, such as a SiC grown substrate for a group III nitride-based HEMT, the die may be mounted together with the substrate on a thermally conductive carrier substrate or submount such as a metal slug, lead frame, or flange to provide improved heat dissipation from the amplifier package of the heat generated by the die.

[0050] Figure 1A is a schematic cross-sectional view of a conventional high electron mobility transistor 10. As shown in Figure 1A, the high electron mobility transistor 10 may be formed on a substrate 22 such as silicon carbide, silicon, or sapphire. A channel layer 24 is formed on the substrate 22. A barrier layer 26 is formed on the channel layer 24 on the opposite side of the substrate 22. The channel layer 24 may include, for example, gallium nitride (GaN), and the barrier layer 26 may include, for example, aluminum gallium nitride (AlGaN).

[0051] The channel layer 24 and the barrier layer 26 both form a semiconductor structure 90 on the substrate 22. Source contacts 56 and drain contacts 54 are formed on the upper surface of the barrier layer 26 and spaced laterally apart from each other. The source contacts 56 and drain contacts 54 can form ohmic contacts with respect to the barrier layer 26.

[0052] A gate contact 52 is formed on the upper surface of the barrier layer 26, between the source contact 56 and the drain contact 54. When the HEMT device 10 is biased to its conduction or "on" state, a two-dimensional electron gas (2DEG) layer is formed at the junction between the channel layer 24 and the barrier layer 26. The 2DEG layer acts as a highly conductive layer, located beneath the source contact 56 and the drain contact 54, respectively, allowing current to flow between the source and drain regions of the device.

[0053] The source contact 56 may be coupled to a reference signal, such as a ground voltage. Coupling to the reference signal may be provided by a via 66 extending from the lower surface 22A of the substrate 22 through the substrate 22 to the upper surface 26A of the barrier layer. The via 66 may expose the lower surface 56A of the source contact 56. A back metal layer 35 may be formed on the lower surface 22A of the substrate 22 and on the sidewalls of the via 66. The back metal layer 35 may be in direct contact with the source contact 56. Thus, the back metal layer 35 and the signal coupled to it may be electrically connected to the source contact 56.

[0054] In some embodiments, one or more insulating layers 50 may be in direct contact with the upper surface of the semiconductor structure 90 (for example, in contact with the upper surface 26A of the barrier layer 26). One or more insulating layers 50 may serve as passivation layers of the HEMT device 10. In some embodiments, additional metal contacts (not shown) may be provided to contact the gate contact 52 and / or the drain contact 54.

[0055] As mentioned above, Group III nitride-based RF amplifiers, including the HEMT device shown in Figure 1A, are often used in high-power and / or high-frequency applications. Typically, high levels of heat are generated within the Group III nitride-based RF amplifier die during operation. If the RF die becomes too hot, the performance of the RF amplifier (e.g., output power, efficiency, linearity, gain, etc.) may degrade, and / or the RF amplifier die may be damaged. Therefore, Group III nitride-based RF amplifiers are typically implemented in packages that can be optimized for heat dissipation. Figures 1B and 1C show conventionally packaged Group III nitride-based RF amplifiers. In particular, Figure 1B is a schematic side view of a conventionally packaged Group III nitride-based RF amplifier 100, and Figure 1C is a schematic cross-sectional view of the RF transistor amplifier die contained within the packaged Group III nitride-based RF transistor amplifier 100, with the cross-section taken along line 1C-1C in Figure 1B. Figures 1B to 1C (and various other figures) are highly simplified diagrams, and it should be understood that actual RF amplifiers may include more unit cells and various circuits and elements not shown in the simplified diagrams herein.

[0056] As shown in Figure 1B, the Group III nitride-based RF amplifier 100 includes an RF amplifier die 110 mounted in a package 170. The package 170 includes a gate lead 172, a drain lead 174, a carrier substrate 176, and a housing 178. The RF transistor amplifier die 110 is mounted on the upper surface of the carrier substrate 176, which may include, for example, a metal flange. The RF amplifier die 110 has a top surface 112 and a bottom surface 114. The RF amplifier die 110 includes a continuously stacked bottom (also referred to as the "back") metallization structure 120, a semiconductor layer structure 130, and a top metallization structure 140. The back metallization structure 120 includes a source terminal 126. The RF amplifier 100 may be a HEMT-based RF amplifier, such as the one shown in Figure 1A, in which case the semiconductor layer structure 130 may include at least a channel layer and a barrier layer, typically formed on a semiconductor or insulating growth substrate (such as a SiC, silicon, or sapphire substrate). The growth substrate can be considered part of the semiconductor layer structure 130, even if it is formed from a non-semiconductor material. The top metallization structure 140 includes, among other things, a gate terminal 142 and a drain terminal 144.

[0057] An input matching circuit 190 and / or an output matching circuit 192 may also be mounted within the housing 178. The matching circuits 190, 192 may be impedance matching circuits that match the impedance of the fundamental components of the RF signal input to or output from the RF transistor amplifier 100 to the impedance of the input or output of the RF transistor amplifier die 110, and / or the impedance of a harmonic termination circuit configured to be too short to ground any harmonics of the fundamental RF signal that may be present at the input or output of the RF transistor amplifier die 110, such as second or third harmonics. As schematically shown in Figure 1B, the input and output matching circuits 190, 192 may be mounted on a metal flange 176. The gate lead 172 may be connected to the input matching circuit 190 by one or more first bond wires 182, and the input matching circuit 190 may be connected to the gate terminal 142 of the RF amplifier die 110 by one or more second bond wires 183. Similarly, the drain lead 174 may be connected to an output matching circuit 192 by one or more fourth bond wires 185, and the output matching circuit 192 may be connected to the drain terminal 144 of the RF amplifier die 110 by one or more third bond wires 184. The source terminal 126 of the RF transistor amplifier die 110 may be mounted directly on a metal flange 176. The metal flange 176 may provide an electrical connection to the source terminal 126 and may also serve as a heat dissipation structure. The first to fourth bond wires 182 to 185 may form part of the input and / or output matching circuit. The housing 178 may include a ceramic housing, and the gate lead 172 and drain lead 174 may extend through the housing 178. The housing 178 may include several pieces, such as a frame that forms the lower portion of the side wall and supports the gate lead 172 and drain lead 174, and a lid that is placed on top of the frame. The interior of the device may include an air-filled cavity.

[0058] Figure 1C is a schematic cross-sectional view of the RF amplifier die 110 taken through a portion of the top metallization structure 140. The dielectric layers that separate the various conductive elements of the top metallization structure 140 from each other are not shown in Figure 1C for the sake of simplifying the drawing.

[0059] As shown in Figure 1C, the RF transistor amplifier die 110 includes a group III nitride-based HEMT RF transistor amplifier having a plurality of unit cell transistors 116, each including a gate finger 152, a drain finger 154, and a source finger 156. The gate finger 152 is electrically connected to a common gate manifold 146, and the drain finger 154 is electrically connected to a common drain manifold 148. The gate manifold 146 is electrically connected to a gate terminal 142, which can be implemented as a gate bond pad (for example, through conductive vias extending upward from the gate manifold 146) (see Figure 1B), and the drain manifold 148 is electrically connected to a drain terminal 144, which can be implemented as a drain bond pad (for example, through conductive vias extending upward from the drain manifold 148) (see Figure 1B). The source finger 156 is electrically connected to a source terminal 126 via a plurality of conductive source vias 166 extending through a semiconductor layer structure 130. The conductive source via 166 may include a metal-plated via that extends completely through the semiconductor layer structure 130.

[0060] Referring again to Figure 1B, the carrier substrate 176 (which is here a metal flange) can act as a heat sink to dissipate the heat generated within the RF amplifier die 110. The heat is mainly generated in the upper portion of the RF amplifier die 110 where a relatively high current density is generated, for example, in the channel region of the unit cell transistor 116. This heat can be transferred to the carrier substrate 176 through both the source via 166 and the semiconductor layer structure 130.

[0061] Figure 1D is a schematic side view of a conventional packaged group III nitride-based RF transistor amplifier 100', similar to the RF transistor amplifier described above with reference to Figure 1B. RF transistor amplifier 100' differs from RF transistor amplifier 100' in that it includes a different package 170'. Package 170' includes a metal submount 176 (which may act as a metal heat sink and may be implemented as a metal slug), as well as gate leads 172' and drain leads 174'. In some embodiments, a metal lead frame may be formed, which is then machined to provide the metal submount 176 and / or gate leads 172' and drain leads 174'. RF transistor amplifier 100' also includes a plastic overmolding 178' that at least partially encloses the RF transistor amplifier die 110, leads 172', 174' and the metal submount 176. The plastic overmolding 178' replaces the ceramic sidewalls and lid 178 included in RF transistor amplifier 100.

[0062] Depending on the embodiment, the packaged transistor amplifier 100' may include, for example, a monolithic microwave integrated circuit (MMIC) as the RF transistor amplifier die 110, in which case the RF transistor amplifier die 110 incorporates a plurality of discrete elements. In some embodiments, the packaged RF transistor amplifier 100 may include a plurality of RF transistor amplifier dies connected in series to form a multistage RF transistor amplifier, and / or a plurality of transistor dies arranged in a plurality of paths (e.g., in parallel) to form an RF transistor amplifier having a plurality of RF transistor amplifier dies and a plurality of paths, such that it is in a Doherty amplifier configuration.

[0063] In other instances, Group III nitride-based RF amplifiers may be implemented as MMIC devices in which one or more RF amplifier dies, along with their associated impedance matching and harmonic termination circuits, are implemented within a single integrated circuit die. An example of such a Group III nitride-based RF amplifier is disclosed, for example, in U.S. Patent No. 9,947,616, the entirety of which is incorporated herein by reference. When the RF transistor amplifier die 110 is an MMIC embodiment, the input matching circuit 190 and / or output matching circuit 192 may be omitted (since they may instead be implemented within the RF transistor amplifier die 110), and the bond wires 182 and / or 185 may extend directly from the gate lead 172' and drain lead 174' to the gate terminal 142 and drain terminal 144.

[0064] Conventional Group III nitride-based RF transistor amplifiers, such as the RF transistor amplifier 100 in Figures 1A to 1D, may use bond wires 182 and 184 to connect the RF transistor amplifier die 110 to the rest of the package. These bond wires 182 and 184 have inherent inductances that can be used to perform some of the inductance in the impedance matching and / or harmonic termination circuit of the RF transistor amplifier. The amount of inductance provided can be varied by changing the length and / or cross-sectional area (e.g., diameter) of the bond wires 182 and 184 so that they provide the desired amount of inductance. Unfortunately, as applications move to higher frequencies, the inductance of the bond wires 182 and 184 may exceed the desired amount of inductance for the impedance matching and / or harmonic termination circuit. If this occurs, bond wires 182 and 184 with very short and / or large cross-sectional areas may be used in an attempt to reduce their inductance to an appropriate level. However, very short bond wires 182 and 184 can be difficult to solder in place, which may increase manufacturing costs and / or lead to a higher device failure rate. Bond wires 182 and 184 with larger cross-sectional areas may require larger gate and drain bond pads on the RF transistor amplifier die, which may increase the overall size of the RF transistor amplifier die, and this is also undesirable. Moreover, in some higher frequency applications, even very short bond wires 182 and 184 with large cross-sectional areas may have excessive inductance, resulting in, for example, the matching network being unable to properly terminate second or third harmonics. The RF transistor amplifier can be implemented as an MMIC device to avoid the problem of excessive inductance in bond wires 182 and 184, but MMIC RF amplifiers may be more expensive to manufacture, can only be used within the frequency range of the matching circuit, and have reduced flexibility.

[0065] Furthermore, wire bonding equipment typically used in mass production may have tolerances of ±1 mil, meaning that the length of any given wire bond can vary by 2 mils (i.e., ±1 mil at each end of the bond wire). For high-frequency applications, the inductance variation associated with a 2-mil wire bond can be significant, and therefore, if the bond wire is 1-2 mils too short or too long from the desired nominal length, the performance of the matched circuit can degrade. By forming the gate and drain terminals on the top surface of the device and connecting these terminals to additional circuits using coupling elements, this process variation can be largely eliminated, resulting in improved performance.

[0066] Herein, embodiments of the present invention will be described in further detail with reference to the accompanying drawings.

[0067] Figures 2A to 2G show a group III nitride-based RF transistor amplifier 200 according to a particular embodiment of the present invention. In particular, Figure 2A is a schematic side view of the group III nitride-based RF transistor amplifier 200. Figure 2B is a schematic plan view of the RF transistor amplifier die 210, which is part of the group III nitride-based RF transistor amplifier 200 of Figure 2A, along line 2B-2B in Figure 2A. Figures 2C to 2F are schematic cross-sectional views of the RF transistor amplifier die 210 along lines 2C-2C to 2F-2F in Figure 2B, respectively. Figure 2G is an alternative embodiment of the source terminal shown in Figure 2D. Figures 2H to 2L are cross-sectional views of additional embodiments of the group III nitride-based RF transistor amplifiers 200', 200'' according to a particular embodiment of the present invention.

[0068] As shown in Figure 2A, in some embodiments, the group III nitride-based RF transistor amplifier 200 may include an RF transistor amplifier die 210 mounted on the bottom surface of a coupling element 270. The RF transistor amplifier die 210 has a top surface 212 and a bottom surface 214. The RF transistor amplifier die 210 includes a continuously stacked top metallization structure 220, a semiconductor layer structure 230, and a bottom thermal layer 240. The top metallization structure 220 includes a gate terminal 222, a drain terminal 224, and one or more source terminals 226. The RF transistor amplifier 200 may also be a HEMT-based RF transistor amplifier, in which case the semiconductor layer structure 230 may include at least a channel layer and a barrier layer, as will be described in more detail with reference to Figures 2C and 2D. In some configurations, as will be described further herein, the coupling element 270 may be omitted from the RF transistor amplifier 200.

[0069] The coupling element 270 may be configured to couple to the gate terminal 222, the drain terminal 224, and one or more source terminals 226. In some cases, the coupling element 270 may include a redistribution layer (RDL) stacked structure and / or an interposer. The RDL stacked structure refers to a substrate having conductive layer patterns and / or conductive vias. The RDL stacked structure may be fabricated by using semiconductor processing techniques to deposit conductive and insulating layers and / or patterns on a base material and to form vias and routing patterns within the structure (e.g., from copper) for transmitting signals through the RDL stacked structure. For example, as shown in Figure 2A, the coupling element 270 may include a conductive pattern 273 formed within an encapsulation structure 277.

[0070] A gate connection pad 272, a drain connection pad 274, and a source connection pad 276 are provided on the upper surface of the coupling element 270. Each of these connection pads 272, 274, and 276 may include, for example, an exposed copper pad, but the present invention is not limited thereto. The gate connection pad 272 may be electrically coupled to the gate terminal 222 by one or more conductive patterns 273 within the coupling element 270. Similarly, the drain connection pad 274 may be electrically coupled to the drain terminal 224 by one or more conductive patterns 273 within the coupling element 270, and the source connection pad 276 may be electrically coupled to the source terminal 226 by one or more conductive patterns 273 within the coupling element 270.

[0071] In some embodiments, the conductive pattern 273 of the coupling element 270 may be configured in a fan-out (FO) configuration. The FO configuration may allow for increased spacing between the connections to the respective source, gate, and drain terminals, thereby increasing the isolation of the connections. However, the present invention is not limited to FO connections. In some embodiments, fan-in connections, fan-in and fan-out configurations, or other configurations may be used.

[0072] In some embodiments, the coupling element 270 and / or RDL stacked structure may be formed as part of a wafer-level processing (WLP) operation, but the present invention is not limited thereto. For example, the coupling element 270 can be formed by arranging conductive pillars on a gate terminal 222, a drain terminal 224, and one or more source terminals 226. In some embodiments, the conductive pillars may include copper. For example, the conductive pillars may be formed by electroplating a copper seed using one or more masks to form a pattern. The conductive pillars may form a conductive pattern 273. In addition, gate connection pads 272, drain connection pads 274, and source connection pads 276 may be formed on the conductive pattern 273. The conductive pattern 273, gate connection pads 272, drain connection pads 274, and source connection pads 276 may be arranged in an encapsulation structure 277 which may at least partially include an overmolding material. The overmolding material may include, for example, silicon oxide, silicon nitride, an oxide of the conductive pattern 273, a polymer, a molding compound, and / or a combination thereof. The overmolded material may be processed (e.g., planarized) to expose the gate connection pad 272, the drain connection pad 274, and / or the source connection pad 276. In some embodiments, the formation of the coupling element 270 may be carried out at the wafer level, and the individual RF transistor amplifier dies 210 and / or RF transistor amplifiers 200 may be pieced from the wafer.

[0073] In some embodiments, the coupling element 270 may be formed in a chip-first or chip-last process. In a chip-first process, the RDL structure may be formed on the die 210 (or the wafer containing the die 210). For example, a seed layer may be deposited on one or more of the gate terminal 222, drain terminal 224, and one or more source terminals 226. The seed layer may then be patterned and electroplated to form a layer of conductive material. This process may be repeated multiple times to form the conductive pattern 273 of the coupling element 270. These conductive patterns 273 may then be encapsulated within an encapsulation structure 277 to form the coupling element 270.

[0074] In the chip-last process, the RDL layer of the coupling element 270 may be formed on the primary carrier layer. The conductive pattern 273 may be formed on the primary carrier layer in the same manner as in the chip-first process. Upon completion, the coupling element 270 may be separated from the primary carrier layer and then re-bonded to the die 210. For example, the coupling element 270 may be bonded (e.g., via solder) to one or more of the gate terminal 222, the drain terminal 224, and one or more source terminals 226.

[0075] For example, other coupling elements 270 may be used instead, such as a printed circuit board (e.g., a multilayer printed circuit board), a ceramic substrate including conductive vias and / or pads, or any coupling structure of the RF transistor amplifier die 210 that can make electrical connections to the upper surface 212 of the RF transistor amplifier die 210.

[0076] The arrangement of the conductive pattern 273 shown in Figure 2A is merely an example, and other arrangements are possible without departing from the present invention. For example, in some embodiments, the conductive pattern 273 of the coupling element 270 may extend to adjacent sides of the RF transistor amplifier die 210. In some embodiments, the coupling element 270 may have terminals other than those shown in Figure 2A.

[0077] The thermal layer 240 may be on the back surface 214 of the RF transistor amplifier die 210. The thermal layer 240 may be a thermal conductive layer configured to facilitate heat transfer between the RF transistor amplifier die 210 and the carrier substrate on which the RF transistor amplifier die 210 is mounted. In some embodiments, the thermal layer 240 may be omitted. In some embodiments, the thermal layer 240 may be a die attach layer, such as a eutectic layer. The thermal layer 240 may be on the transistor amplifier die 210 and / or extend to the encapsulation structure 277. The thermal layer 240 may be a metallic layer for forming a eutectic or other metallic bond. In some embodiments, the thermal layer 240 may be a thermal conductive adhesive.

[0078] The RF transistor amplifier die 210 may include a group III nitride-based HEMT RF transistor amplifier comprising a plurality of unit cell transistors 216 electrically connected in parallel with one another. This can be best observed in Figure 2B, which schematically shows a plan view of the RF transistor amplifier die 210 beneath the top metallization structure 220. The top metallization structure 220, which includes a gate terminal 222, a drain terminal 224, and one or more source terminals 226, is shown as a dashed line in Figure 2B.

[0079] As shown in Figure 2B, the RF transistor amplifier die 210 includes a gate manifold 242 and a drain manifold 244, a plurality of gate fingers 252, a plurality of drain fingers 254, and a plurality of source fingers 246, all of which may be formed on the upper surface of the semiconductor layer structure 230. The gate manifold 242 and gate fingers 252 are part of the gate electrode of the RF transistor amplifier die 210. The gate manifold 242 and gate fingers 252 may be implemented as a first monolithic metal pattern, but the present invention is not limited thereto. The drain manifold 244 and drain fingers 254 are part of the drain electrode of the RF transistor amplifier die 210, and may be implemented as a second monolithic metal pattern, but the present invention is not limited thereto.

[0080] The gate finger 252 may be formed from a material capable of creating Schottky contact to a Group III nitride-based semiconductor material, such as Ni, Pt, Cu, Pd, Cr, W, and / or WSiN. The drain finger 254 and source finger 246 may include a metal (e.g., TiAlN, TiSiNi, etc.) capable of forming ohmic contact to a Group III nitride-based material. Dielectric layers (or a series of dielectric layers) that help isolate the gate manifold / fingers 242, 252, drain manifold / fingers 244, 254, and source finger 246 from each other are not shown in Figure 2B in order to better illustrate the elements of the RF transistor amplifier die 210.

[0081] The gate terminal 222, drain terminal 224, and source terminal 226 may be located on the upper surface of the RF transistor amplifier die 210. The gate terminal 222 may be physically and electrically connected to the gate manifold 242 (e.g., by conductive vias), the source terminal 226 may be physically and electrically connected to the source finger 246 (e.g., by conductive vias), and the drain terminal 224 may be physically and electrically connected to the drain manifold 244 (e.g., by conductive vias). While various terminals are shown as being directly connected to the gate / drain manifold and / or source finger, it will be understood that in some embodiments, intermediate elements may be present. For example, in some embodiments, capacitors, inductors, resistors, etc., may be coupled between the terminals and their respective manifolds and / or fingers. As an example, a capacitor may be formed on the surface of the RF transistor amplifier die 210 coupled to the drain manifold 244, and the drain terminal 224 may be coupled to the capacitor.

[0082] One of the unit cell transistors 216 is also shown in Figure 2B. As shown in the figure, the unit cell transistor 216 includes gate fingers 252, drain fingers 254, and source fingers 246, along with the lower portion of the semiconductor layer structure 230. All of the gate fingers 252 are electrically connected to a common gate manifold 242, all of the drain fingers 254 are electrically connected to a common drain manifold 244, and all of the source fingers 246 are electrically connected together via the source terminal 226 (described later), so it can be seen that all of the unit cell transistors 216 are electrically connected together in parallel.

[0083] The unit cell transistor 216 may be a HEMT device. Suitable structures for Group III nitride-based HEMT devices that can utilize embodiments of the present invention include, for example, U.S. Patent Application Publication No. 2002 / 0066908, published June 6, 2002, entitled "Aluminum Gallium Nitride / Gallium Nitride High Electron Mobility Transistors Having A Gate Contact On A Gallium Nitride Based Cap Segment And Methods Of Fabricating Same," by the same applicant; U.S. Patent Application Publication No. 2002 / 0167023, published November 14, 2002, entitled "Group-III Nitride Based High Electron Mobility Transistor (HEMT) With Barrier / Spacer Layer"; and "Nitride-Based Transistors And Methods Of Fabrication Thereof Using Non-Etched Contact," published April 1, 2004. These disclosures are described in U.S. Patent Application Publication No. 2004 / 0061129, entitled “Recesses”, U.S. Patent No. 7,906,799, entitled “Nitride-Based Transistors With A Protective Layer And A Low-Damage Recess,” issued on 15 March 2011, and U.S. Patent No. 6,316,793, entitled “Nitride Based Transistors On Semi-Insulating Silicon Carbide Substrates,” issued on 13 November 2001, and these disclosures are incorporated herein by reference in their entirety.

[0084] Referring to Figures 2C and 2D, the semiconductor layer structure 230 comprises multiple semiconductor layers. In the illustrated embodiment, a total of two semiconductor layers are shown: a channel layer 234 and a barrier layer 236 located on the upper surface of the channel layer 234. The semiconductor layer structure 230 may include additional semiconductor and / or non-semiconductor layers. For example, the semiconductor layer structure 230 may include a growth substrate 232 on which other semiconductor layers are grown. The growth substrate 232 may be a semi-insulating silicon carbide (SiC) substrate, which may be, for example, a 4H polytype of silicon carbide. Other candidate silicon carbide polytypes may include 3C, 6H, and 15R polytypes. The growth substrate 232 may be a high-purity semi-insulating (HPSI) substrate available from Cree, Inc. The term “semi-insulating” is used herein descriptively, not in an absolute sense.

[0085] In some embodiments of the present invention, the silicon carbide bulk crystal of the growth substrate 232 is approximately 1 × 10¹⁶ at room temperature. 5 The resistance may be greater than Ω·cm. Exemplary SiC substrates that may be used in some embodiments of the present invention were manufactured, for example, by Cree, Inc., located in Durham, North Carolina, the assignee of the present invention, and methods for manufacturing such substrates are described in U.S. Reissue Patents 34,861, 4,946,547, 5,200,022, and 6,218,680, the entire disclosures of which are incorporated herein by reference. Although silicon carbide may be used as the substrate material, embodiments of this application may utilize any suitable substrate such as sapphire (Al2O3), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), GaAs, LGO, zinc oxide (ZnO), LAO, indium phosphide (InP), etc. The growth substrate 232 may be a silicon carbide wafer, and the RF transistor amplifier 200 may be formed at least partially by wafer-level processing, and the wafer may then be diced to provide a plurality of individual RF transistor amplifiers 200.

[0086] SiC has much closer crystal lattice matching to Group III nitrides than sapphire (Al2O3) or silicon, which are very common substrate materials for Group III nitride devices. This closer crystal matching of SiC can result in Group III nitride films of higher quality than those commonly available for sapphire or silicon. SiC also has very high thermal conductivity, meaning that the total power output of Group III nitride devices on silicon carbide is not limited by thermal dissipation of the substrate, as is typically the case with the same devices formed on sapphire. Furthermore, the availability of semi-insulating SiC substrates can provide device isolation and reduced parasitic capacitance.

[0087] Optional buffer layers, nucleation layers, and / or transition layers (not shown) may be provided on the growth substrate 232 beneath the channel layer 234. For example, an AlN buffer layer may be included to provide appropriate crystal structure transitions between the SiC growth substrate 232 and the rest of the semiconductor layer structure 230. Additionally, strain-balanced transition layers, such as those described in U.S. Patent Application Publication No. 2003 / 0102482, “Strain Balanced Nitride Heterojunction Transistors And Methods Of Fabricating Strain Balanced Nitride Heterojunction Transistors,” published on June 5, 2003, are also provided, the disclosure of which is incorporated herein by reference as if it were contained in its entirety.

[0088] The channel layer 234 and the barrier layer 236 may each be formed by epitaxial growth in some embodiments. Techniques for epitaxial growth of group III nitrides are described, for example, in U.S. Patents 5,210,051, 5,393,993, and 5,523,589, and their disclosures are expressly incorporated herein by reference in whole. The channel layer 234 may have a band gap smaller than that of the barrier layer 236, and the channel layer 234 may also have a greater electron affinity than that of the barrier layer 236. The channel layer 234 and the barrier layer 236 may comprise a group III nitride-based material.

[0089] In some embodiments, the channel layer 234 is made of Al, provided that the energy of the conduction band edge of the channel layer 234 at the interface between the channel layer 234 and the barrier layer 236 is less than the energy of the conduction band edge of the barrier layer 236. x Ga 1-x The channel layer is a group III nitride material such as N(0≦x<1). In a particular embodiment of the present invention, x=0, which indicates that the channel layer 234 is gallium nitride ("GaN"). The channel layer 234 may also be other group III nitrides such as InGaN, AlInGaN, etc. The channel layer 234 may be undoped or unintentionally doped, and may be grown to a thickness of, for example, more than about 2 nm. The channel layer 234 may also be a multilayer structure such as a superlattice or a combination of GaN, AlInGaN, etc.

[0090] The channel layer 234 may have a bandgap smaller than the bandgap of at least a portion of the barrier layer 236, and the channel layer 234 may also have an electron affinity greater than that of the barrier layer 236. In certain embodiments, the barrier layer 236 is AlN, AlInN, AlGaN or AlInGaN having a thickness of about 0.1 nm to about 10 nm or more. In certain embodiments, the barrier layer 236 is thick enough and has a high enough Al composition and doping to induce a large carrier concentration at the interface between the channel layer 234 and the barrier layer 236.

[0091] The barrier layer 236 may be a group III nitride and may have a bandgap larger than the bandgap of the channel layer 234 and an electron affinity smaller than that of the channel layer 234. Thus, in certain embodiments of the present invention, the barrier layer 236 may include AlGaN, AlInGaN and / or AlN or a combination of those layers. The barrier layer 236 may be, for example, about 0.1 nm to about 30 nm thick. In certain embodiments, the barrier layer 236 is undoped or doped to a concentration of less than about 10 19 cm -3 −1. In some embodiments of the present invention, the barrier layer 236 is Al x Ga 1-x N (0 < x < 1). In certain embodiments, the aluminum concentration is about 25%. However, in other embodiments of the present invention, the barrier layer 236 includes AlGaN with an aluminum concentration of about 5% to about 100%. In certain embodiments of the present invention, the aluminum concentration is greater than about 10%.

[0092] Due to the difference in band gap between the barrier layer 236 and the channel layer 234, and the piezoelectric effect at the interface between the barrier layer 236 and the channel layer 234, a two-dimensional electron gas (2DEG) is induced within the channel layer 234 at the junction between the channel layer 234 and the barrier layer 236. The 2DEG acts as a highly conductive layer enabling conduction between the source region of each unit cell transistor 216 and its associated drain region, where the source region is the portion of the semiconductor layer structure 230 directly beneath the source finger 246, and the drain region is the portion of the semiconductor layer structure 230 directly beneath the corresponding drain finger 254.

[0093] The semiconductor structure 230 is shown for illustrative purposes having a channel layer 234 and a barrier layer 236, but the semiconductor structure 230 may include additional layers / structures / elements such as a buffer and / or nucleation layer between the channel layer 234 and the substrate 232 and / or a cap layer on the barrier layer 236. HEMT structures including the substrate, channel layer, barrier layer, and other layers are discussed, for example, in U.S. Patents 5,192,987, 5,296,395, 6,316,793, 6,548,333, 7,544,963, 7,548,112, 7,592,211, 7,615,774, 7,548,112, and 7,709,269, the entire disclosures of which are incorporated herein by reference. For example, an AlN buffer layer may be formed on the upper surface of the silicon carbide substrate 232 to provide a suitable crystalline structure transition between the silicon carbide substrate 232 and the rest of the RF transistor amplifier 200. Additionally, a strain-balancing transition layer, such as that described in U.S. Patent No. 7,030,428 by the same applicant, may also be provided, and / or alternatively, the disclosure of which is incorporated herein by reference as if it were described in its entirety. Optional buffer / nucleation / transition layers may be deposited by MOCVD, MBE, and / or HVPE.

[0094] An interlayer insulating layer 238 is formed on the gate finger 252, drain finger 254, and source finger 246. The interlayer insulating layer 238 may contain a dielectric material such as SiN or SiO2.

[0095] The coupling element 270 may be on the semiconductor layer structure 230 and / or coupled to the semiconductor layer structure 230. For example, the conductive pattern 273 may be coupled between the gate connection pad 272 and the gate terminal 222, between the drain connection pad 274 and the drain terminal 224, and between the source connection pad 276 and the source terminal 226, respectively. In Figure 2C, the encapsulation structure 277 of the coupling element 270 is omitted for ease of explanation. The gate connection pad 272, drain connection pad 274, and source connection pad 276 of the coupling element 270 may extend perpendicularly to the gate finger 252 and the drain finger 254.

[0096] By arranging all terminals on the upper surface of the RF transistor amplifier die 210, the RF transistor amplifier 200 according to certain embodiments of the present invention may be able to omit vias to the back surface of the RF transistor amplifier die 210. Since there are no vias on the back surface of the RF transistor amplifier die 210 connecting the source to a grounded conductive submount, the conductive submount does not need to be electrically active. Furthermore, the back surface of the substrate 232 of the RF transistor amplifier die 210 may be thermally coupled to a thermally conductive submount such as a heat sink or flange (not shown) to provide improved heat dissipation. In some embodiments, a thermal layer 240 can facilitate this thermal coupling. When SiC is used as the substrate material, the improved thermal conductivity of SiC can further improve the thermal properties of the package.

[0097] Furthermore, by positioning all terminals on the top surface of the RF transistor amplifier die 210, it becomes possible to use coupling elements 270 that can bring all transistor connections to their respective connection pads. This may allow the RF transistor amplifier die 210 to be further coupled to other elements of the circuit (e.g., other routing elements, grounding elements, harmonic and / or input / output impedance matching elements) through the use of connection methods that avoid bonding wires such as solder.

[0098] Figure 2D shows an example of connections between various source fingers 246 and source terminals 226. As shown in Figure 2D, each of the source fingers 246 may be coupled to its respective source terminal 226, but the present invention is not limited thereto. In some embodiments, one or more source terminals 226 may be coupled to two or more source fingers 246. For example, as shown in Figure 2G, in some embodiments, a single source terminal 226 may be provided, and the source terminal 226 may be connected to each of the individual source fingers 246. In some embodiments, a plurality of source terminals 226 may be provided, each connected to a plurality of source fingers 246. One or more source terminals 226 may be coupled to a source connection pad 276 by a conductive pattern 273 of a coupling element 270.

[0099] Figure 2E shows an example of a connection between a gate manifold 242 and a gate terminal 222. As shown in Figure 2E, the gate manifold 242 may be coupled to the gate terminal 222 by, for example, multiple vias. Figure 2F shows an example of a connection between a drain manifold 244 and a drain terminal 224. As shown in Figure 2E, the drain manifold 244 may be coupled to the drain terminal 224 by, for example, multiple vias. In both Figures 2E and 2F, the gate terminal 222 and / or the drain terminal 224 may be coupled to the gate connection pads 272 and / or drain connection pads 274 of the coupling element 270, respectively, by one or more conductive patterns 273.

[0100] Figures 2C, 2E, and 2F show embodiments in which the gate manifold 242 and gate terminal 222 are separate elements, and the drain-gate manifold 244 and drain terminal 224 are separate elements (e.g., connected by vias), but the present invention is not limited thereto. For example, Figures 2H to 2J show examples in which the gate / drain manifold and terminals are a single element. Referring to Figures 2H and 2I, for example, device 200' may be configured such that the gate manifold 242 extends to the surface of the RF transistor amplifier die 210 and acts as the gate terminal 222. Similarly, Figures 2H and 2J show that device 200' may be configured such that the drain manifold 244 extends to the surface of the RF transistor amplifier die 210 and acts as the drain terminal 224.

[0101] In some embodiments, additional conductive elements and / or discrete circuit components may be formed as part of the RF transistor amplifier die. Figure 2K shows an additional embodiment of the RF transistor amplifier die 210' according to some embodiments of the present invention. Figure 2K is an embodiment shown from the view of line 2C-2C of Figure 2A, with modifications as described herein. For example, as shown in Figure 2K, the RF transistor amplifier die 210' may utilize several conductive patterns 223 between the gate manifold 242 and the gate terminal 222, between the drain gate manifold 244 and the drain terminal 222, and / or between one or more of the source fingers 246 and the source terminal 246. The conductive patterns 223 may be formed within the interlayer insulating layer 238 of the RF transistor amplifier die 210'.

[0102] The conductive pattern 223 may be used to form a discrete circuit element integrated with the RF transistor amplifier die 210'. For example, the conductive pattern 223 may form an RDL within the RF transistor amplifier die 210'. Figure 2K shows a fan-in configuration in which the gate manifold 242 / drain manifold 244 and source finger 246 are coupled to the gate terminal 222, drain terminal 224, and source terminal 226, respectively. However, the present invention is not limited thereto. In some embodiments, the conductive pattern 223 may also be coupled to a discrete circuit element within the interlayer insulating layer 238, such as in an MMIC configuration. The use of an on-die RDL can enable more flexible packaging options, as well as the integration of specific circuit functions such as impedance matching and / or harmonic termination.

[0103] Figure 2L shows that the RF transistor amplifier die 210' may also be used together with a coupling element 270 within the RF transistor amplifier 200''. The embodiment in Figure 2L may include a first RDL as part of the RF transistor amplifier die 210' and a second RDL as part of the coupling element 270. In some embodiments, the conductive pattern 223 of the RF transistor amplifier die 210' may provide one or more additional integrated circuits such as impedance matching or harmonic termination, and the conductive pattern 273 of the coupling element 270 may provide fan-in, fan-out, or other configurations. In some embodiments, the combination of the coupling element 270 and the RF transistor amplifier die 210' may be enclosed within an encapsulation structure (not shown).

[0104] Figures 2A to 2L show a semiconductor layer structure 230 including a HEMT, but it will be understood that other types of semiconductor devices may be formed within the semiconductor layer structure 230 without departing from the present invention. For example, the semiconductor layer structure 230 may include MOSFETs, DMOS transistors, MESFETs, and / or LDMOS transistors. It will be recognized by those skilled in the art that it may be possible to improve connectivity and have better thermal performance by arranging all source contacts / drain contacts / gate contacts on a single surface of the semiconductor layer structure 230, including by using coupling elements 270.

[0105] By arranging the gate contact, drain contact, and source contact on the same plane of the RF transistor amplifier 200, connection options that were previously not possible may become available. These connection options can also enable embodiments that can more strongly take advantage of the improved thermal conductivity of the SiC material.

[0106] Figure 3A is a schematic cross-sectional view of an RF transistor amplifier 200 coupled to a circuit module 310 (also referred to herein as an interconnection structure 310) according to several embodiments of the present invention. Figure 3A includes elements of the RF transistor amplifier 200 described above. Therefore, the discussion of Figure 3A will focus on parts of embodiments that differ from those discussed with respect to the previous figures.

[0107] Referring to Figure 3A, the circuit module 310 may be configured to couple to the gate connection pad 272, drain connection pad 274, and source connection pad 276 of the coupling element 270. For example, the circuit module 310 may expose interconnect pads 322, 324, and 326 which may be configured to couple to the gate connection pad 272, drain connection pad 274, and source connection pad 276. For example, the first interconnect pad 322 may be configured to couple to the gate connection pad 272, the second interconnect pad 324 may be configured to couple to the drain connection pad 274, and the third interconnect pad 326 may be configured to couple to the source connection pad 276. In some embodiments, bonding elements (e.g., solder balls and / or bumps 320) may be used to bond the first interconnect pad 322, the second interconnect pad 324, and the third interconnect pad 326 to the gate connection pad 272, the drain connection pad 274, and the source connection pad 276, respectively. Although shown as a single pad, in some embodiments, one or more of the first interconnect pad 322, the second interconnect pad 324, and / or the third interconnect pad 326 may comprise multiple pads.

[0108] Each of the first interconnect pad 322, the second interconnect pad 324, and the third interconnect pad 326 may be coupled to one or more conductive patterns 373 in the circuit module 310. The conductive patterns 373 may provide various routing and / or circuitry within the circuit module 310. For example, the conductive pattern 373 may connect the first interconnect pad 322 to one or more first surface connection pads 372 and one or more gate lead connection pads 382. Thus, the gate connection pad 272 may be electrically coupled to one or more first surface connection pads 372 and one or more gate lead connection pads 382. The conductive pattern 373 may also connect the second interconnect pad 324 to one or more second surface connection pads 374 and one or more drain lead connection pads 384. Thus, the drain connection pad 274 may be electrically coupled to one or more second surface connection pads 374 and one or more drain lead connection pads 384. The conductive pattern 373 may also connect the third interconnect pad 326 to one or more third surface connection pads 376 and one or more source lead connection pads 386. Thus, the source connection pad 276 may be electrically coupled to one or more third surface connection pads 376 and one or more source lead connection pads 386. Thus, the circuit module 310 may have a surface (e.g., an upper surface) having a plurality of first surface connection pads 372, each coupled to the gate connection pad 272 of the coupling element 270, a plurality of second surface connection pads 374, each coupled to the drain connection pad 274 of the coupling element 270, and a plurality of third surface connection pads 376, each coupled to the source connection pad 276 of the coupling element 270.

[0109] The conductive pattern 373 may be sealed within an isolation material 315. In some embodiments, the isolation material 315 may include, for example, silicon oxide, silicon nitride, an oxide of the conductive pattern 273, a polymer, a molding compound, or a combination thereof. In some embodiments, the circuit module 310 may be formed as a printed circuit board (PCB). In the PCB embodiment, the isolation material 315 may be the substrate of the PCB, and the conductive pattern 373 may be a trace formed within the substrate.

[0110] The presence of the conductive pattern 373 and the first surface connection pads 372, second surface connection pads 374, and third surface connection pads 376 allows several different circuits to be coupled to the RF transistor amplifier 200. For example, a circuit element 350 may be coupled between two or more of the first surface connection pads 372, second surface connection pads 374, and third surface connection pads 376 (e.g., via solder or other bonding). The circuit element 350 may provide various electronic functions to the RF transistor amplifier 200. For example, the circuit element 350 may include impedances (e.g., resistive elements, inductive elements, and capacitive elements) which may be used for impedance matching and / or harmonic termination. In some embodiments, the circuit element 350 may provide the RF transistor amplifier 200 with strip line components and / or baseband termination.

[0111] Although shown as being on the surface of the circuit module 310, it will be understood that additional circuit elements 350 may be provided integrally within the circuit module 310. For example, one or more grounding surfaces may be formed as circuit elements 350 within the circuit module 310. Similarly, strip lines may be formed within the circuit module 310 (for example, in relation to one or more grounding surfaces). The configuration of the conductive pattern 373 and circuit elements 350 shown in Figure 3A is merely an example and is not intended to limit embodiments of the present invention. In some embodiments, the circuit elements 350 and / or the conductive pattern 373 may be configured to provide at least a portion of a harmonic termination circuit, matching circuit, branch circuit, combining circuit, and / or bias circuit. Other configurations of the conductive pattern 373 and / or other types of circuit elements 350 may be used without departing from the scope of the present invention.

[0112] In some embodiments, the circuit module 310 and the circuit element 350 may optionally be encapsulated within an encapsulation material 316. In some embodiments, the encapsulation material 316 may include, for example, silicon oxide, silicon nitride, polymer, molding compound, or a combination thereof.

[0113] The gate lead connection pad 382, ​​drain lead connection pad 384, and source lead connection pad 386 may provide terminals for connecting signals to the gate, drain, and source, respectively, of the RF transistor amplifier 200. For example, a connection for providing an input signal to the RF transistor amplifier 200 may be coupled to one or more of the gate lead connection pads 382. In some embodiments, a connection for receiving an output signal from the RF transistor amplifier 200 may be coupled to the drain lead connection pad 384. In some embodiments, a ground signal may be coupled to the source lead connection pad 386, but the present invention is not limited thereto. The gate lead connection pads 382, ​​drain lead connection pad 384, and source lead connection pad 386 are shown as being located on the bottom surface of the circuit module 310, but this is just an example and is not intended to limit the present invention. In some embodiments, various lead connections may be located on the top or other surfaces of the circuit module 310.

[0114] By using the circuit module 310 together with the top contacts of the RF transistor amplifier 200, additional functions such as impedance matching and / or harmonic termination can be easily added to the RF transistor amplifier 200 without using expensive wire bonding. Thus, different functions and / or capabilities can be coupled to the RF transistor amplifier 200 simply by using different circuit modules 310. Since the connection points (e.g., terminals) of the RF transistor amplifier 200 are consistent, changes in the configuration of the RF transistor amplifier 200 can be achieved more efficiently than previously possible. The need for wire bonding is reduced or eliminated, and depending on the application, the die size may also be reduced (if the size of the wire bond pads defines the die size), and therefore, the RF transistor amplifier die according to embodiments of the present invention may also exhibit increased integration density. Thus, the RF amplifier die according to embodiments of the present invention may exhibit improved product assembly consistency, increased yield, increased product integration, reduced costs, and improved RF performance, particularly for products operating at high frequencies such as millimeter-wave frequencies.

[0115] The techniques disclosed herein may be particularly beneficial in higher frequency applications. This is because the inductance required for matching circuits can be much lower in such applications, and therefore, using conventional bond wires may result in too much injected inductance. Additionally, tolerances in bond wire length can have a greater impact at higher frequencies, and in high-frequency applications (especially at lower power), the size of the bond pad may define the size of the die. In some embodiments, any of the RF transistor amplifier dies disclosed herein may be configured to operate at frequencies above 1 GHz. In other embodiments, these RF transistor amplifier dies may be configured to operate at frequencies above 2.5 GHz. In yet another embodiment, these RF transistor amplifier dies may be configured to operate at frequencies above 3.1 GHz. In yet another embodiment, these RF transistor amplifier dies may be configured to operate at frequencies above 5 GHz. In some embodiments, the RF transistor amplifier dies may be configured to operate in at least one of the frequency bands of 2.5–2.7 GHz, 3.4–4.2 GHz, or 5.1–5.8 GHz or lower portions thereof.

[0116] Figure 3B is a schematic cross-sectional view of an RF transistor amplifier die 210 coupled to a circuit module 310 according to several embodiments of the present invention. Figure 3B includes the elements of the circuit module 310, circuit element 350, and RF transistor amplifier die 210 described above. Therefore, the discussion of Figure 3B will focus on parts of embodiments that differ from those discussed with respect to the previous figures.

[0117] Figure 3B shows an embodiment in which the circuit module 310 is directly connected to the RF transistor amplifier die 210 without an intervening coupling element 270. Thus, the circuit module 310 may be configured to couple to the gate terminal 222, the drain terminal 224, and one or more source terminals 226 of the RF transistor amplifier die 210. For example, a first interconnect pad 322 of the circuit module 310 may be configured to couple to the gate terminal 222, a second interconnect pad 324 of the circuit module 310 may be configured to couple to the drain terminal 224, and a third interconnect pad 326 of the circuit module 310 may be configured to couple to one or more source terminals 226. In some embodiments, bonding elements (e.g., solder balls and / or bumps) 320 may be used to couple the first interconnect pad 322, the second interconnect pad 324, and the third interconnect pad 326 to the gate terminal 222, the drain terminal 224, and one or more source terminals 226, respectively. Although shown as a single pad, in some embodiments, one or more of the first interconnection pad 322, the second interconnection pad 324, and / or the third interconnection pad 326 may comprise multiple pads. The configuration shown in Figure 3B may be useful when a fan-in or fan-out configuration of the coupling element 270 is not required to provide a connection between the RF transistor amplifier die 210 and the circuit module 310.

[0118] Figure 3C shows an embodiment in which the circuit module 310 is directly connected to an RF transistor amplifier die 210' incorporating an on-die RDL using the conductive pattern 223 without an intervening coupling element 270. Thus, the circuit module 310 may be configured to couple to the gate terminal 222, drain terminal 224, and one or more source terminals 226 of the RF transistor amplifier die 210'. The RF transistor amplifier die 210' in Figure 3C is illustrated in cross-section to show an example of an internal conductive pattern (e.g., of an RDL) coupled to the gate terminal 222, drain terminal 224, and one or more source terminals 226. In some embodiments, the RF transistor amplifier die 210' may be an MMIC. Although illustrated without the coupling element 270, it will be understood that in some embodiments, a coupling element 270 may also be present between the RF transistor amplifier die 210' and the circuit module 310.

[0119] By using coupling elements 270 utilizing conductive pattern 273 (if present), on-die RDL utilizing conductive pattern 223 (if present), and / or circuit modules 310 utilizing conductive pattern 373, connection structures can be provided between the gate, drain, and source of the RF transistor amplifier die 210 and the gate lead connection pad 382, ​​drain lead connection pad 384, and source lead connection pad 386. By utilizing various combinations of these elements and electrical bonding techniques, semiconductor packages that eliminate or reduce wire bonding can be provided.

[0120] Figure 3D is a schematic cross-sectional view of a circuit module 310' coupled to a plurality of RF transistor amplifiers 200, according to several embodiments of the present invention. Figure 3E is a schematic cross-sectional view of a circuit module 310' coupled to a plurality of RF transistor amplifier dies 210, according to several embodiments of the present invention. Figures 3D and 3E include the aforementioned elements of the circuit module 310', circuit element 350, RF transistor amplifier die 210, and RF transistor amplifier 200. Therefore, the discussion of Figures 3D and 3E will focus on parts of embodiments that differ from those discussed with respect to the previous figures.

[0121] Referring to Figure 3D, the circuit module 310' may be configured to couple to two or more RF transistor amplifiers 200. Figure 3D also shows that the conductive pattern 373, interconnect pads, and surface interconnect pads may be modified without departing from the scope of the present invention. For example, the circuit module 310' may include a plurality of interconnect pads 327. The interconnect pads 327 may be configured to couple to the terminals of the plurality of RF transistor amplifiers 200. For example, the interconnect pads 327 of the circuit module 310' may be configured to couple to the gate connection pad 272, drain connection pad 274, and / or source connection pad 276 of one or more of the plurality of RF transistor amplifiers 200.

[0122] Similarly, the circuit module 310' may have surface connection pads 377 coupled to one or more of the interconnection pads 327 via conductive patterns 373. The circuit element 350 may be coupled to one or more of the surface connection pads 377. By using the conductive patterns 373, interconnection pads 327, surface connection pads 377, and / or circuit element 350, various circuit connections between multiple RF transistor amplifiers 200 can be realized. The configuration shown in Figure 3D is merely a schematic example, and it will be understood that the routing and connections of the various elements of the circuit module 310' can be varied to produce complex circuits including RF transistor amplifiers 200.

[0123] In some embodiments, the circuit module 310' may include one or more gate lead connection pads 382, ​​one or more drain lead connection pads 384, and one or more source lead connection pads 386. The signals supplied to the one or more gate lead connection pads 382, ​​one or more drain lead connection pads 384, and one or more source lead connection pads 386 may be distributed through the conductive pattern 373 to various RF transistor amplifiers 200 via the circuit module 310'.

[0124] Figure 3D shows an embodiment in which each of the multiple RF transistor amplifiers 200 has its own coupling element 270, but it will be understood that other configurations are possible. For example, in some embodiments, a single coupling element 270 may be coupled to the multiple RF transistor amplifier dies 210. By using a single coupling element 270, it may be possible to use a circuit module 310' having fewer interconnections to the transistor elements of the circuit.

[0125] Figure 3D shows an embodiment in which the circuit module 310' is coupled to a plurality of RF transistor amplifiers 200 including coupling elements 270. However, the present invention is not limited thereto. In some embodiments, the circuit module 310' may be directly coupled to a plurality of RF transistor amplifier dies 210, 210' that do not include coupling elements 270. Figure 3E shows an embodiment in which the circuit module 310' is coupled to a plurality of RF transistor amplifier dies 210. It will be understood that the circuit module 310' may also be coupled to a plurality of RF transistor amplifier dies 210' (for example, as shown in Figure 2K) without departing from the present invention. The circuit module 310' may be coupled to the RF transistor amplifier dies 210, 210' by bonding elements (e.g., solder balls and / or bumps) 320. It will be understood that the circuit module 310 may be coupled to a combination of RF transistor amplifiers 200 including coupling elements 270 and RF transistor amplifier dies 210, 210'.

[0126] The circuit module 310' may be used to provide interconnection to an RF transistor amplifier 200, which can be used to implement a multistage and / or multipath amplifier circuit, such as a Doherty amplifier. The conductive pattern 373 may provide an electrical connection for the multistage and / or multipath amplifier circuit, which may be coupled to one of the circuit elements 350 to provide capacitors, inductors, resistors, and / or other circuit elements used in the multistage and / or multipath amplifier circuit. Thus, the circuit module 310' may be configured to provide a modular interconnection that can be easily coupled to multiple RF transistor amplifiers without the use of bond wires.

[0127] Figures 3A to 3E show various combinations of circuit modules 310, 310', coupling element 270, and RF transistor amplifier dies 210, 210', but it will be understood that the present invention is not limited to the specific combinations shown in those drawings. As will be understood by those skilled in the art, the circuit modules 310, 310', coupling element 270, and RF transistor amplifier dies 210, 210' may be combined in a plurality of variations, including those not specifically shown, without departing from the present invention. For example, embodiments of the present invention include transistor amplifier dies 210, 210' directly coupled to circuit modules 310, 310'. Some embodiments of the present invention include transistor amplifier dies 210, 210' coupled to circuit modules 310, 310' via coupling element 270. The coupling element 270 and / or circuit modules 310, 310' may include traces on a PCB or a metal core PCB and patterned dielectric material. In some embodiments, the transistor amplifier die 210' may have a conductive pattern such as an RDL at the die level, which may include a fan-in and / or fan-out configuration that may be connected to a coupling element 270 or other structures such as circuit modules 310, 310'.

[0128] Figure 4A is a schematic cross-sectional view of an RF transistor amplifier 200 and a circuit module 310 coupled to a carrier substrate 410 according to several embodiments of the present invention. Figure 4B is a schematic cross-sectional view of an RF transistor amplifier 200 coupled to the carrier substrate 410 without the coupling element 270 according to several embodiments of the present invention. Figures 4A and 4B include the elements of the RF transistor amplifier 200, coupling element 270, and circuit module 310 described above. Therefore, the discussion of Figures 4A and 4B will focus on parts of embodiments that differ from those discussed with respect to the previous figures.

[0129] Referring to Figure 4A, the RF transistor amplifier 200 may be placed on a carrier substrate 410. The carrier substrate 410 may include any structure that provides a suitable mounting surface for the RF transistor amplifier 200. In some embodiments, the carrier substrate 410 may include a temperature conductive element such as a metal flange. In some embodiments, the carrier substrate 410 may include, for example, an RDL stacked structure or a PCB. In some embodiments, the carrier substrate 410 may include copper, molybdenum, and / or a combination thereof. In some embodiments, the carrier substrate 410 may consist of multiple layers and / or include vias / interconnections. The carrier substrate 410 may be configured to allow the RF transistor amplifier 200 to be easily packaged. As shown in Figure 4A, the circuit module 310 may be coupled to the RF transistor amplifier 200 as discussed herein.

[0130] In some embodiments, the thermal layer 240 may be located between the bottom surface of the RF transistor amplifier 200 and the carrier substrate 410. The thermal layer 240 can assist in the transfer of thermal energy from the RF transistor amplifier 200 to the carrier substrate 410. In embodiments where SiC is used as part of the RF transistor amplifier 200, the excellent thermal conductivity of SiC may allow the carrier substrate 410 to dissipate heat from the device more efficiently. In some embodiments, the thermal layer 240 may include or be replaced by a eutectic layer.

[0131] One or more leads 415 may be coupled to one or more gate lead connection pads 382, ​​one or more drain lead connection pads 384, and one or more source lead connection pads 386 of the circuit module 310. For example, a first input lead 415A may be coupled to one or more gate lead connection pads 382 (e.g., via a bonding layer 420A such as solder) to provide an input signal to the RF transistor amplifier 200, and a second output lead 415B may be coupled to one or more drain lead connection pads 384 (e.g., via a bonding layer 420B such as solder) to receive an output signal from the RF transistor amplifier 200, but the present invention is not limited thereto.

[0132] The lead connections in Figure 4A are merely examples, and other connections and / or connection pads are possible. For example, in Figure 4A, one or more source lead connection pads 386 are shown as being connected to both leads 415A and 415B. However, in some embodiments, one or more source lead connection pads 386 do not have to be coupled to the source of the RF transistor amplifier 200 (for example, through one or more source terminals 226). For example, in some embodiments, one or more of the circuit elements 350 and / or conductive patterns 373 may be configured to control whether one or more source lead connection pads 386 are coupled to the input lead 415A, to the output lead 415B, or not coupled to either. For example, the circuit element 350 may be provided on the circuit module 310 to connect the source terminal 226 of the RF transistor amplifier 200 to lead 415. Similarly, the circuit module 310 may be configured to allow the removal of a circuit element 350 (e.g., a resistor) to disconnect the coupling between lead 415A or 415B and the source terminal 226 of the RF transistor amplifier 200.

[0133] In addition, Figure 4A shows an embodiment with two leads 415A and 415B, but this is merely an example and is not intended to limit the invention. In some embodiments, multiple leads may be provided, each coupled to a gate lead connection pad 382, ​​a drain lead connection pad 384, a source lead connection pad 386, and / or a combination thereof. For example, in some embodiments, an additional lead may be provided configured to provide a ground connection to the source lead connection pad 386. In some embodiments, the source lead connection pad 386 may be configured to couple to a lead of an RF semiconductor package, which may be coupled to ground, for example. Where used herein, the combination of the RF transistor amplifier 200, the circuit module 310, the leads 415A, 415B, and the carrier substrate 410 may be referred to as a packaged RF transistor amplifier, an RF transistor amplifier package, or simply an RF transistor amplifier.

[0134] The leads 415A and 415B may be located between the circuit module 310 and the carrier substrate 410, but the present invention is not limited thereto. In some embodiments, the carrier substrate 410 is located beneath the leads 415A and 415B and, in some embodiments, has a base 410p supporting them, but the present invention is not limited thereto. In some embodiments, the base 410p may contain an insulating material and / or be separated from the leads 415A and 415B by an insulating layer 460. In some embodiments, as further described herein, the leads 415A and 415B may be supported by a portion of the package of the RF transistor amplifier 200.

[0135] Figure 4A shows the use of a coupling element 270, but the present invention is not limited thereto. Figure 4B shows an embodiment in which the coupling element is omitted. In the embodiment of Figure 4B, the circuit module 310 may have a first interconnection pad 322, a second interconnection pad 324, and a third interconnection pad 326 spaced apart from each other by similar distances as those for the gate terminal 222, the drain terminal 224, and one or more source terminals 226. For example, the first interconnection pad 322 may be connected to the gate terminal 222 (e.g., via bonding elements such as solder balls and / or bumps 320), the second interconnection pad 324 may be connected to the drain terminal 224, and the third interconnection pad 326 may be connected to the source terminal 226. Direct connection to the circuit module 310 may be useful when adjustment of the terminal spacing of the RF transistor amplifier 200 (e.g., via fan-in or fan-out structures) is not required. Therefore, in some embodiments, the coupling element 270 can be omitted within the RF transistor amplifier 200.

[0136] Figure 4C shows an embodiment in which multiple RF transistor amplifiers 200 are coupled to a circuit module 310' and placed on a carrier substrate 410. For example, as discussed herein with respect to Figures 3D and 3E, multiple RF transistor amplifier dies 210, 210' may be coupled to a circuit module 310'. Multiple RF transistor amplifier dies 210, 210' may be coupled to the circuit module 310' via coupling elements 270, or they may be directly coupled to the circuit module 310' as shown in Figure 3E. The RF transistor amplifier dies 210, 210' and / or the circuit module 310' may further be placed on the carrier substrate 410, with leads 415A and 415B coupled thereto. In some embodiments, a thermal layer 240 may be placed between the RF transistor amplifier dies 210, 210' and the carrier substrate 410.

[0137] Figures 4A to 4C show various combinations of the circuit modules 310, 310', the coupling element 270, and the RF transistor amplifier dies 210, 210', but it will be understood that the present invention is not limited to the specific combinations shown in those drawings. As will be understood by those skilled in the art, the circuit modules 310, 310', the coupling element 270, and the RF transistor amplifier dies 210, 210' may be combined in a plurality of variations, including those not specifically shown, without departing from the present invention. Each of these combinations may be arranged on the carrier substrate 410, as generally shown in Figures 4A to 4C, and appropriate leads (e.g., leads 415A, 415B) may be connected thereto.

[0138] Figures 5A to 5C are schematic cross-sectional views of various packaging options 500a, 500b, and 500c of the RF transistor amplifier 200 according to several embodiments of the present invention. Figures 5A to 5C include elements of the RF transistor amplifier 200, coupling element 270, and circuit module 310 as described above. Therefore, the discussion of Figures 5A to 5C will focus on parts of embodiments that differ from those discussed with respect to the previous figures.

[0139] Referring to Figure 5A, the semiconductor package 500a may incorporate an RF transistor amplifier 200 according to several embodiments of the present invention. The semiconductor package 500a may be, for example, an open-air or open-cavity package. The semiconductor package 500a may include a carrier substrate 410, a side wall 520, and a lid 525. The carrier substrate 410, the side wall 520, and the lid 525 may define an internal cavity 530. The RF transistor amplifier 200 and the circuit module 310 may be located inside the internal cavity 530. The term “semiconductor package” is not intended to be limiting. As stated above, the combination of the RF transistor amplifier 200, the circuit module 310, the leads 415A, 415B, and the carrier substrate 410 may be referred to as a packaged RF transistor amplifier, a semiconductor package, or simply an RF transistor amplifier.

[0140] The carrier substrate 410 may include a material configured to assist in the thermal management of the semiconductor package 500a. For example, the carrier substrate 410 may include copper and / or molybdenum. In some embodiments, the carrier substrate 410 may consist of multiple layers and / or include vias / interconnections. In one exemplary embodiment, the carrier substrate 410 may be a multilayer copper / molybdenum / copper metal flange including a core molybdenum layer on one of its main surfaces. The provided examples of materials for the carrier substrate 410 are not intended to limit the invention. In some embodiments, a thermal layer 240 may be located between the RF transistor amplifier 200 and the carrier substrate 410.

[0141] The sidewall 520 and / or lid 525 may, in some embodiments, be formed from or include an insulating material. For example, the sidewall 520 and / or lid 525 may be formed from or include ceramic and / or PCB. In some embodiments, the sidewall 520 and / or lid 525 may be formed from, for example, Al2O3. The lid 525 may be bonded to the sidewall 520 using an epoxy adhesive. The sidewall 520 may be attached to the carrier substrate 410, for example, by brazing. The leads 415A and 415B may be configured to extend through the sidewall 520, but the present invention is not limited thereto.

[0142] In some embodiments, the RF transistor amplifier 200 may be disposed on a carrier substrate 410 and leads 415A, 415B, and the circuit module 310 may be disposed on the RF transistor amplifier 200. The leads 415A, 415B may be coupled to the circuit module 310 using, for example, a conductive die attach material. In some embodiments, the leads 415A, 415B may extend from the side wall 520 to contact the circuit module 310. Thus, in some embodiments, the use of wire bonds to connect the RF transistor amplifier 200 to leads 415A, 415B can be avoided and / or reduced.

[0143] Additional circuit elements 350 are mounted on the circuit module 310. These additional components may include, for example, input matching components and output matching components used to impedance match at the fundamental frequency and / or terminate the intermodulation product to ground. These circuit elements 350 may also be passive RF components, including resistors, capacitors and / or inductors, which are (at least partially) implemented in an integrated passive device or printed circuit board. Leads 415A and 415B allow the RF transistor amplifier 200 to be connected to an external device / circuit / power supply. In the illustrated embodiment, the circuit module 310 is used to connect the conductive leads 415A and 415B to the circuit elements 350 on the circuit module 310. The RF signal input to the RF transistor amplifier 200 on the first lead 415A may pass through the circuit module 310 to the circuit element 350, and from there to the gate terminal 222 of the RF transistor amplifier die 210. The amplified output RF signal may pass from the drain terminal 224 of the RF transistor amplifier die 210 to the circuit element 350, and from there through the circuit module 310, where the RF signal is output through lead 415B.

[0144] Referring to Figure 5B, the semiconductor package 500b may incorporate the RF transistor amplifier 200 according to an embodiment of the present invention. The semiconductor package 500b may be, for example, an overmolded plastic (OMP) package. The semiconductor package 500b may include a carrier substrate 410 on which the RF transistor amplifier 200 is placed. The circuit module 310 may be placed on the RF transistor amplifier 200.

[0145] The RF transistor amplifier 200 and the circuit module 310 may be sealed within an overmolded material 540. The overmolded material 540 may be formed from a plastic or plastic polymer compound that is injection molded around the RF transistor amplifier 200 and / or the circuit module 310, thereby providing protection from the external environment.

[0146] A method for manufacturing an OMP semiconductor package 500b, which can be modified to incorporate an RF transistor amplifier 200 and / or a circuit module 310, is described in U.S. Patent No. 9,515,011, entitled “Over-mold plastic packaged wide band-gap power transistors and MMICS,” issued to Wood et al. on December 6, 2016, the disclosure of which is incorporated herein by reference as if it were contained in its entirety. In the semiconductor package 500b according to the present invention, leads 415A, 415B may extend from the outside of the semiconductor package 500b into the overmolded material 540 to connect to the circuit module 310. Thus, in some embodiments, the use of wire bonds to connect the RF transistor amplifier 200 to leads 415A, 415B can be avoided and / or reduced.

[0147] Similar to semiconductor package 500a, the carrier substrate 410 of semiconductor package 500b may include a material configured to assist in thermal management. For example, the carrier substrate 410 may include copper and / or molybdenum. In some embodiments, the carrier substrate 410 may consist of multiple layers and / or include vias / interconnections. In some embodiments, the carrier substrate 410 may include a metal heat sink which is part of a lead frame or metal slug at least partially surrounded by a plastic overmolding 540. The provided examples of materials for the carrier substrate 410 are not intended to limit the invention. In some embodiments, a thermal layer 240 may be located between the RF transistor amplifier 200 and the carrier substrate 410.

[0148] Figure 5C is a schematic cross-sectional view of a packaged RF transistor amplifier 500c, which includes an RF transistor amplifier die within a printed circuit board-based package. The packaged RF transistor amplifier 500c is very similar to the packaged RF transistor amplifier 500a described above with reference to Figure 5A, except that the leads 415A, 415B of the packaged RF transistor amplifier 500c are replaced by a printed circuit board 522 which includes traces 415A, 415B that act as input and output leads. The printed circuit board 522 may be attached to a carrier board 410, for example, via a conductive adhesive. The carrier board 410 may include, for example, a base 410P. The base 410P may be constructed from insulating material and / or metal. The printed circuit board 652 may include a central opening, and the circuit module 310 is mounted within this opening on the carrier board (e.g., a metal flange) 410. The RF transistor amplifier 200 and circuit elements 350 are mounted on the circuit module 310.

[0149] Figures 5A to 5C show the use of an RF transistor amplifier 200 having a coupling element 270, but the present invention is not limited thereto. In some embodiments, semiconductor packages 500a, 500b, and 500c may be configured to include a circuit module 310 directly coupled to an RF transistor amplifier die 210, as shown in Figures 3B, 3C, and 4B. In some embodiments, semiconductor packages 500a, 500b, and 500c may be configured to include a circuit module 310 coupled to a plurality of RF transistor amplifiers 200, 200' and / or a plurality of RF transistor amplifier dies 210, 210, as shown in Figures 3D, 3E, and 4C.

[0150] It will be understood that any of the RF transistor amplifiers according to embodiments of the present invention discussed herein may be implemented in a package such as the package shown in Figures 5A to 5C. Accordingly, the RF transistor amplifier die 210, coupling element 270, and / or circuit module 310 shown in Figures 5A to 5C may be replaced with RF transistor amplifier dies 210, 210', coupling element 270, and / or circuit modules 310, 310' according to any of the embodiments of the present invention discussed herein, in order to provide many further embodiments of packaged RF transistor amplifiers. Depending on the embodiment, the packaged RF transistor amplifier may include a monolithic microwave integrated circuit (MMIC) as the RF transistor amplifier die, in which case the RF transistor amplifier die incorporates a plurality of discrete elements within a single integrated die. Additionally and / or alternatively, the package may include multiple RF transistor amplifier dies in a path that are connected in series to form a multistage RF transistor amplifier, and / or multiple RF transistor amplifier dies arranged in multiple paths (e.g., in parallel) to form an RF transistor amplifier having multiple transistor amplifier dies and multiple paths, as in a Doherty amplifier configuration. In some embodiments, the packaged RF transistor amplifier may include RF transistor amplifier dies according to embodiments of the present invention having conductive gate vias and / or conductive drain vias that provide electrical connections to a back-side interconnect structure, as well as conventional RF transistor amplifier dies having gate and drain terminals connected to other structures via wire bonds.

[0151] In some embodiments described herein, the circuit element 350 may be located on the upper surface of the circuit module 310, but the embodiments described herein are not limited thereto. Figures 6A to 6C are schematic cross-sectional views of additional embodiments of the RF transistor amplifier 200 coupled to the circuit module 610 according to some embodiments of the present invention. Figures 6A to 6C correspond to the cross-section of Figure 3A. Figures 6A to 6C include the elements of the RF transistor amplifier 200 described above. Therefore, the discussion of Figures 6A to 6C focuses on parts of embodiments that differ from those discussed with respect to the previous figures.

[0152] Referring to Figure 6A, the circuit module 610 may be configured to couple to the gate connection pad 272, drain connection pad 274, and source connection pad 276 of the coupling element 270. The coupling element 270 may be coupled to the RF transistor amplifier die 210, for example, as discussed herein with respect to Figures 2A to 2L.

[0153] For example, the circuit module 610 may have exposed interconnect pads 622, 624, and 626, which may be configured to connect to a gate connection pad 272, a drain connection pad 274, and a source connection pad 276, respectively. In some embodiments, bonding elements (e.g., solder balls and / or bumps 320) may be used to connect the first interconnect pad 622, the second interconnect pad 624, and the third interconnect pad 626 to the gate connection pad 272, the drain connection pad 274, and the source connection pad 276, respectively. Although shown as a single pad, in some embodiments, one or more of the first interconnect pad 622, the second interconnect pad 624, and / or the third interconnect pad 626 may comprise multiple pads.

[0154] The circuit module 610 may be coupled to the coupling element 270 on a first surface 601 of the circuit module 610. Multiple pads may be exposed on a second surface 602 of the circuit module 610 opposite to the first surface 601. For example, a gate lead 682, a drain lead 684, and a source lead 686 may be exposed on the second surface 602 of the circuit module 610. Although only a single gate lead 682, a drain lead 684, and a source lead 686 are shown in Figure 6A, it will be understood that multiple leads of each type may be provided. As will be further discussed herein, the gate lead 682, the drain lead 684, and the source lead 686 may be configured to be coupled to the gate terminal 222, the drain terminal 224, and the source terminal 226 of the RF transistor amplifier die 210, respectively. The encapsulation material 625 may be on the surface of the RF transistor amplifier die 210, the coupling element 270, and / or the circuit module 610. The encapsulating material 625 may be formed from a plastic or a plastic polymer compound, but the present invention is not limited thereto. In some embodiments, the encapsulating material 625 may be a polymer having a filler, or may contain one.

[0155] Each of the first interconnection pad 622, the second interconnection pad 624, and the third interconnection pad 626 may be coupled to one or more conductive patterns 673 in the circuit module 610. The conductive patterns 673 may provide various routing and / or circuitry within the circuit module 610. For example, the conductive patterns 673 may connect the first interconnection pad 622 to one or more first surface connection pads 672 and gate leads 682. In some embodiments, the first surface connection pads 672 may be exposed on the first surface 601 of the circuit module 610. In some embodiments, a first circuit element 650a may be coupled to one or more of the first surface connection pads 672 so as to electrically couple the gate lead 682 between the first interconnection pad 622. In some embodiments, the first circuit element 650a may be coupled (e.g., through a coupling element 270) between the gate lead 682 and the gate terminal 222 of the RF transistor amplifier die 210. As a result, the first circuit element 650a can be electrically coupled between the gate and gate lead 682 of the RF transistor amplifier die 210. In some embodiments, the first circuit element 650a may be coupled to the first face 601 of the circuit module 610. Thus, the first circuit element 650a may be coupled to the same face (e.g., the first face 601) of the circuit module 610 as the coupling element 270.

[0156] Similarly, the conductive pattern 673 may connect the second interconnect pad 624 to one or more second surface connection pads 674 and the drain lead 684. In some embodiments, the second circuit element 650b may be coupled to one or more of the second surface connection pads 674 so as to be electrically coupled between the drain lead 684 and the second interconnect pad 624. In some embodiments, the second surface connection pads 674 may be exposed on the first surface 601 of the circuit module 610. In some embodiments, the second circuit element 650b may be coupled between the drain lead 684 and the drain terminal 224 of the RF transistor amplifier die 210 (for example, through a coupling element 270). As a result, the second circuit element 650b may be electrically coupled between the drain of the RF transistor amplifier die 210 and the drain lead 684.

[0157] The first circuit element 650a and / or the second circuit element 650b may provide various electronic functions to the RF transistor amplifier 200. For example, the first circuit element 650a and / or the second circuit element 650b may include impedances (e.g., resistive elements, inductive elements, and capacitive elements) which may be used for impedance matching and / or harmonic termination. In some embodiments, the first circuit element 650a and / or the second circuit element 650b may be or include surface-mount devices. In some embodiments, the first circuit element 650a and / or the second circuit element 650b may be or include integrated passive devices (IPDs). In some embodiments, the first circuit element 650a and / or the second circuit element 650b may be or include harmonic and / or input / output impedance matching elements.

[0158] For example, the first circuit element 650a may be configured to provide an input matching function. Due to its location between the gate lead 682 and the RF transistor amplifier die 210, the first circuit element 650a may be able to influence and / or adjust the signal supplied to the gate of the RF transistor amplifier die 210. Similarly, the second circuit element 650b may be configured to provide an output matching function. Due to its location between the drain lead 684 and the RF transistor amplifier die 210, the second circuit element 650b may be able to influence and / or adjust the signal supplied from the drain of the RF transistor amplifier die 210.

[0159] By using a circuit module 610 having exposed connection pads such as a first surface connection pad 672 and a second surface connection pad 674, surface mount devices can be used to provide circuit elements that can be coupled to the RF transistor amplifier die 210. Surface mount devices can be replaced and / or configured as needed to provide a more flexible solution. For example, when different types of input / output matching and / or harmonic termination are required, the same circuit module 610 may be used, but the first circuit element 650a and / or the second circuit element 650b may be replaced to provide different functions.

[0160] Although the first circuit element 650a and the second circuit element 650b are each shown as single elements, it will be understood that in some embodiments, the first circuit element 650a and / or the second circuit element 650b may comprise multiple discrete elements. Similarly, the interconnection between the first circuit element 650a and the second circuit element 650b and the RF transistor amplifier die 210 is merely an example, and different configurations of the conductive pattern 673 may be provided without departing from the present invention.

[0161] The conductive pattern 673 may also connect a third interconnection pad 626 to one or more source leads 686. Thus, the source connection pad 276 may be electrically coupled to one or more source leads 686.

[0162] The conductive pattern 673 may be sealed within an isolation material 615. In some embodiments, the isolation material 615 may include, for example, silicon oxide, silicon nitride, an oxide of the conductive pattern 673, a polymer, a molding compound, or a combination thereof. In some embodiments, the circuit module 610 may be formed as a printed circuit board (PCB). In the PCB embodiment, the isolation material 615 may be the substrate of the PCB, and the conductive pattern 673 may be a trace formed within the substrate.

[0163] Figure 6A shows the use of a circuit module 610 to couple to an RF transistor amplifier die 210 using a coupling element 270, but the present invention is not limited thereto. As shown in Figure 6B, in some embodiments, the RF transistor amplifier die 210 may be directly coupled to the circuit module 610. For example, the gate terminal 222, drain terminal 224, and source terminal 226 of the RF transistor amplifier die 210 may be coupled to interconnection pads 622, 624, and 626 of the circuit module 610, respectively, using a bonding element 320, for example.

[0164] Similarly, it will be understood that other configurations of the circuit module 610 and RF transistor amplifier die 210 are possible, such as those shown in Figures 3C to 3E. In some embodiments, the circuit module 610 may be configured to couple with an RF transistor amplifier die 210' incorporating an internal conductive pattern, such as the one shown in Figure 3C. In some embodiments, the circuit module 610 may be configured to couple with multiple RF transistor amplifier dies 210, such as those shown in Figures 3D and 3E.

[0165] It will be understood that the RF transistor amplifier die 210 may have various different configurations. For example, the RF transistor amplifier die 210 has top gate, drain, and source terminals 222, 224, and 226, but in some embodiments they may also have one or more of the back gate, drain, and source terminals 222', 224', and 226'. Such a configuration is schematically shown in Figure 6C, which is a schematic cross-sectional view of the RF transistor amplifier die 210''. As shown in Figure 6, gate vias 211, drain via 213, and / or source via 215 connected to the respective gate terminals 222', drain terminal 224', and source terminal 226' may be formed through the semiconductor layer structure 230. Including the gate and drain terminals on the back surface of the RF transistor amplifier die has various advantages, such as enabling more flexible impedance matching circuit embodiments, as described in, for example, U.S. Provisional Patent Application No. 63 / 004,985 ("Application 985") filed on April 3, 2020. The entire contents of application 985 are incorporated herein by reference. It will be understood that back gate, drain, and source terminals 222', 224', 226' and / or corresponding gate, drain, and source vias 211, 213, 215 may be included in any of the RF transistor amplifier dies disclosed herein.

[0166] Figures 3A to 3E show embodiments in which the circuit element 350 is located on the upper surface of the circuit module 310 (for example, on the side of the circuit module 310 opposite the RF transistor amplifier die 210), and Figures 6A to 6C show embodiments in which the circuit element 650 is located on the bottom surface of the circuit module 610 (for example, between the circuit module 610 and the RF transistor amplifier die 210), although it will be understood that other combinations are available. In some embodiments, the circuit elements 350 / 650 may be located on both sides of the circuit module 310 / 610. In some embodiments, the circuit elements 350 / 650 may be located on the side surfaces of the circuit module 310 / 610.

[0167] As shown in Figures 6A to 6C, multiple configurations of the RF transistor amplifier die 210 and / or RF transistor amplifier 200 may be coupled to the circuit module 610. In the subsequent figures, the discussion will focus on embodiments in which the RF transistor amplifier die 210 is directly coupled to the circuit module 610. However, this convention is merely for the sake of clarity, and it will be understood that the subsequent discussion relating to the circuit module 610 can be equally applied to other types of interconnections between the RF transistor amplifier 210 (e.g., using coupling element 270) and / or RF transistor amplifier 200 without departing from the present invention.

[0168] Figures 7A to 7E are schematic diagrams illustrating a method for coupling a circuit module and an RF transistor amplifier die according to a particular embodiment of the present invention. A circuit module 610 may be provided as shown in Figure 7A. The circuit module 610 may have a first surface 601 and a second surface 602. In some embodiments, the first surface 601 may expose a first interconnect pad 622, a second interconnect pad 624, and a third interconnect pad 626, as well as a first surface connection pad 672 and a second surface connection pad 674. In some embodiments, the second surface 602 may have exposed gate leads 682, drain leads 684, and source leads 686.

[0169] Referring to Figure 7B, the first circuit element 650a and the second circuit element 650b may be provided on the first surface 601 of the circuit module 610. For example, bonding elements (e.g., solder balls and / or bumps 320) may be used to bond the first circuit element 650a to the first surface connection pad 672. Similarly, bonding elements (e.g., solder balls and / or bumps 320) may be used to bond the second circuit element 650b to the second surface connection pad 674.

[0170] Referring to Figure 7C, the RF transistor amplifier die 210 may be mounted on the first surface 601 of the circuit module 610. For example, bonding elements (e.g., solder balls and / or bumps) 320 may be used to couple the gate terminal 222, drain terminal 224, and source terminal 226 of the RF transistor amplifier die 210 to the first interconnection pad 622, the second interconnection pad 624, and the third interconnection pad 626, respectively. It will be understood that the order of Figures 7B and 7C may be reversed so that the RF transistor amplifier die 210 is coupled to the circuit module 610 before the first circuit element 650a and the second circuit element 650b.

[0171] As shown in Figure 7D, a capillary underfill process may be used to inject encapsulation material 625 between the conductive structures of the RF transistor amplifier die 210, the first circuit element 650a and the second circuit element 650b, and / or the circuit module 610. The encapsulation material 625 can help prevent short circuits, improve the structural integrity of the resulting device, and provide proper impedance matching. In some embodiments, the encapsulation material 625 may also encapsulate the RF transistor amplifier die 210 within a protective material.

[0172] Figure 7E shows an additional optional step in which the thermal layer 240 is placed on the back surface of the RF transistor amplifier die 210. In some embodiments, an additional thermal management structure 642, such as a metal flange, metal fin, heat sink, or other structure, may be provided on the thermal layer 240. In some embodiments, the thermal management structure 642 may be part of a larger semiconductor package (e.g., a carrier substrate), as will be discussed further below. The thermal layer 240 may be a thermal conductive layer configured to facilitate heat transfer between the RF transistor amplifier die 210 and the thermal management structure 642 on which the RF transistor amplifier die 210 is mounted. In some embodiments, the thermal layer 240 and / or the thermal management structure 642 may be omitted. In some embodiments, the thermal layer 240 may be a die attach layer, such as a eutectic layer. The thermal layer 240 may be on the transistor amplifier die 210 and / or extend to the encapsulation material 625 and / or the first circuit element 650a and the second circuit element 650b. The thermal layer 240 can be a metal layer for forming a eutectic or other metallic bond. In some embodiments, the thermal layer 240 can be a thermally conductive adhesive.

[0173] The embodiments in Figures 6A to 6C provide a common gate lead 682, drain lead 684, and source lead 686 on a common surface (e.g., a second surface 602) of the circuit module 610. This allows the circuit module 610 to be mounted with the second surface 602 facing upward in various different configurations. For example, Figures 8A and 8B are schematic cross-sectional views of various packaging options 800a, 800b of the circuit module 610 according to some embodiments of the present invention. Figures 8A and 8B include the aforementioned elements of the RF transistor amplifier 210 and the circuit module 610. Therefore, the discussion of Figures 8A and 8B focuses on parts of embodiments that differ from those discussed with respect to the previous figures.

[0174] Referring to Figure 8A, the semiconductor package 800a may be similar to the semiconductor package 500a discussed herein with respect to Figure 5A, and any redundant explanation already discussed with respect to that figure will be omitted. The semiconductor package 800a may be, for example, an open-air or open-cavity package. The semiconductor package 800a may include a carrier substrate 410, a side wall 520, and a lid 525. The carrier substrate 410, the side wall 520, and the lid 525 may define an internal cavity 530. The RF transistor amplifier die 210 and the circuit module 610 may be located inside the internal cavity 530. In some embodiments, a thermal layer 240 may be located between the RF transistor amplifier die 210 and the carrier substrate 410.

[0175] The leads 415A and 415B may be configured to extend through the side wall 520, but the present invention is not limited thereto. In some embodiments, the RF transistor amplifier 210 may be located on the carrier substrate 410 and the leads 415A and 415B, and the circuit module 610 may be located on the RF transistor amplifier die 210. The leads 415A and 415B may be coupled to the circuit module 610 using, for example, a conductive die attach material. In some embodiments, the leads 415A and 415B may extend from the side wall 520 to contact and / or connect to the circuit module 610. For example, lead 415a may be coupled to the gate lead 682, and lead 415b may be coupled to the drain lead 684. In some embodiments, additional leads and / or connectors (not shown) may be coupled to the source lead 686. Thus, in some embodiments, the use of wire bonds to connect the RF transistor amplifier die 210 to the leads 415A and 415B can be avoided and / or reduced.

[0176] Referring to Figure 8B, the semiconductor package 800b may incorporate an RF transistor amplifier 210 and a circuit module 610 according to an embodiment of the present invention. The semiconductor package 800b may be similar to the semiconductor package 500b discussed herein with respect to Figure 5B, and any redundant explanations already discussed with respect to that figure will be omitted. The semiconductor package 800b may be, for example, an overmolded plastic (OMP) package.

[0177] In the semiconductor package 800b according to the present invention, leads 415A and 415B may extend from the outside of the semiconductor package 800b into the overmolding material 540 to connect to a circuit module 610. For example, lead 415a may be coupled to the gate lead 682, and lead 415b may be coupled to the drain lead 684. In some embodiments, additional leads and / or connectors (not shown) may be coupled to the source lead 686. In some embodiments, a thermal layer 240 may be located between the RF transistor amplifier die 210 and the carrier substrate 410 within the semiconductor package 800b.

[0178] In addition to the semiconductor packages 800a and 800b shown in Figures 8A and 8B, it will be understood that other packaging configurations are possible without departing from the present invention. For example, the circuit module 610 may be used with a semiconductor package and other configurations similar to that of Figure 5C.

[0179] In Figures 6A to 6C, the circuit elements 650a, 650b and the RF transistor amplifier die 210 are on the same plane of the circuit module 610, while the gate lead 682, drain lead 684, and source lead 686 are on the opposite plane, but this embodiment is not limited thereto. Figure 9A is a plan view of one embodiment of the circuit module 610B according to some embodiments of the present invention, in which leads 682, 684, 686, circuit elements 650a, 650b, and the RF transistor amplifier die 210 are all on the same plane of the circuit module 610B. Figure 9B is a cross-sectional view along line 9B-9B in Figure 9A. Figure 9C is a cross-sectional view along line 9C-9C in Figure 9A. Figures 9A to 9C include the RF transistor amplifier die 210 and the elements of the circuit module 610 as described above. Therefore, the discussion of Figures 9A to 9C will focus on parts of embodiments that differ from those discussed with respect to the previous figures.

[0180] Referring to Figures 9A to 9C, the circuit module 610B may be mounted on the RF transistor amplifier die 210. The RF transistor amplifier die 210 is mounted below the circuit module 610B in the schematic plan view of Figure 9A and is therefore indicated using a dashed line. The circuit module 610B may be configured to couple to the gate terminal 222, drain terminal 224, and / or source terminal 226 of the RF transistor amplifier die 210. While Figures 9A to 9C show the circuit module 610B being directly coupled to the RF transistor amplifier die 210, it will be understood that other types of connections are possible, including other configurations of the RF transistor amplifier 200, including those shown with respect to Figures 2A to 2L. For example, a coupling element 270 may be coupled between the circuit module 610B and the RF transistor amplifier die 210.

[0181] For example, the circuit module 610B may have exposed interconnect pads 622, 624, and 626 which may be configured to couple to the gate terminal 222, drain terminal 224, and source terminal 226 of the RF transistor amplifier die 210, respectively. For example, the first interconnect pad 622 may be configured to couple to the gate terminal 222, the second interconnect pad 624 may be configured to couple to the drain terminal 224, and the third interconnect pad 626 may be configured to couple to the source terminal 226. In some embodiments, bonding elements (e.g., solder balls and / or bumps 320) may be used to couple the first interconnect pad 622, the second interconnect pad 624, and the third interconnect pad 626 to the gate terminal 222, the drain terminal 224, and the source terminal 226, respectively. Although shown as a single pad, in some embodiments, one or more of the first interconnection pad 622, the second interconnection pad 624, and / or the third interconnection pad 626 may comprise multiple pads.

[0182] The circuit module 610B may be coupled to the RF transistor amplifier die 210 on the first surface 601 of the circuit module 610B. In addition, the gate lead 682B, drain lead 684B, and source lead 686B may be exposed on the first surface 601 of the circuit module 610B. As will be further discussed herein, the gate lead 682B, drain lead 684B, and source lead 686B may be configured to be coupled to the gate terminal 222, drain terminal 224, and source terminal 226 of the RF transistor amplifier die 210, respectively. The encapsulation material 625 may be on the surface of the RF transistor amplifier die 201 and / or the circuit module 610B.

[0183] Each of the first interconnection pad 622, the second interconnection pad 624, and the third interconnection pad 626 may be coupled to one or more conductive patterns 673B within the circuit module 610B. The conductive patterns 673B may provide various routing and / or circuitry within the circuit module 610B. For example, the conductive patterns 673B may connect the first interconnection pad 622 to one or more first surface connection pads 672 and gate lead 682B. In some embodiments, the first surface connection pads 672 may be exposed on the first surface 601 of the circuit module 610B. In some embodiments, the first circuit element 650a may be coupled to one or more of the first surface connection pads 672 so as to electrically couple between the gate lead 682B and the first interconnection pad 622. In some embodiments, the first circuit element 650a may be coupled between the gate lead 682B and the gate terminal 222 of the RF transistor amplifier die 210. As a result, the first circuit element 650a may be electrically coupled between the gate of the RF transistor amplifier die 210 and the gate lead 682B. In some embodiments, the first circuit element 650a may be coupled to the first surface 601 of the circuit module 610B. Thus, the first circuit element 650a may be coupled to the same surface (e.g., the first surface 601) of the circuit module 610B as the RF transistor amplifier die 210 and the gate lead 682B.

[0184] Similarly, the conductive pattern 673B may connect the second interconnect pad 624 to the drain terminal 224 and the drain lead 684B. In some embodiments, the second circuit element 650b may be coupled to one or more of the second surface connection pads 674 so as to be electrically coupled between the drain lead 684B and the second interconnect pad 624. In some embodiments, the second surface connection pads 674 may be exposed on the first surface 601 of the circuit module 610B. In some embodiments, the second circuit element 650b may be coupled between the drain lead 684B and the drain terminal 224 of the RF transistor amplifier die 210. As a result, the second circuit element 650b may be electrically coupled between the drain of the RF transistor amplifier die 210 and the drain lead 684B.

[0185] The conductive pattern 673B may also connect a third interconnect pad 626 to one or more source leads 686B. The source leads 686B may be on the same first surface 601 as the third interconnect pad 626 and the RF transistor amplifier die 210. In some embodiments, as shown in Figure 9A, the gate lead 682B and drain lead 684B may be on two opposing surfaces of the RF transistor amplifier die 210, and the source leads 686B may be on a surface of the RF transistor amplifier die 210 that is different from the two opposing surfaces. In other words, in some embodiments, the gate lead 682B may be adjacent to a first surface of the RF transistor amplifier die 210, the drain lead 684B may be adjacent to a second surface of the RF transistor amplifier die 210, and one or more source leads 686B may be adjacent to a third surface of the RF transistor amplifier die 210 that is different from the first and second surfaces of the RF transistor amplifier die 210.

[0186] The circuit module 610B in Figures 9A-9C may differ from the circuit module 610 in Figures 6A-6C in that the circuit module 610B provides the gate lead 682B, drain lead 684B, and source lead 686B on the same plane as the RF transistor amplifier die 210 of the circuit module 610B. That is, the conductive pattern 673 of the circuit module 610B may be configured to allow the gate lead 682B, drain lead 684B, and source lead 686B to be exposed on different parts of the circuit module 610B. Additional packaging options are possible by shifting the plane on which the gate lead 682B, drain lead 684B, and source lead 686B are located.

[0187] Figure 9D is a cross-sectional view of the circuit module 610B of Figure 9A mounted on a carrier substrate 410 according to some embodiments of the present invention. As shown in Figure 9D, the circuit module 610B may be coupled on an RF transistor amplifier die 210, and the RF transistor amplifier die 210 may be located on the carrier substrate 410.

[0188] In some embodiments, the thermal layer 240 may be located between the RF transistor amplifier die 210 and the carrier substrate 410. In some embodiments, an additional thermal management structure 642, such as a metal flange, metal fin, heat sink, or other structure, may be provided on and / or between the thermal layer 240 and the carrier substrate 410. The thermal layer 240 may be a thermal conductive layer configured to facilitate heat transfer between the RF transistor amplifier die 210 and the carrier substrate 410 on which the RF transistor amplifier die 210 is mounted. In some embodiments, the thermal layer 240 and / or the thermal management structure 642 may be omitted. In some embodiments, the thermal layer 240 may be a die attach layer, such as a eutectic layer. The thermal layer 240 may be located on the RF transistor amplifier die 210 and / or extend to the encapsulation material 625 and / or the first circuit element 650a and the second circuit element 650b. The thermal layer 240 may be a metallic layer for forming a eutectic or other metallic bond. In some embodiments, the thermal layer 240 can be a thermally conductive adhesive.

[0189] In some embodiments, additional contacts may be provided within the carrier substrate 410, but the present invention is not limited thereto. For example, a gate connector 982, a drain connector 984, and / or a source connector (not shown) may be provided on and / or within the carrier substrate 410. For example, the gate lead 682B of the circuit module 610B may be configured to be coupled to the gate connector 982 (e.g., via bonding elements such as solder balls and / or bumps 320), the drain lead 684B may be configured to be coupled to the drain connector 984, and the source lead 686B may be configured to be coupled to a source connector (not shown).

[0190] The packaging example in Figure 9B is merely an example, and it will be understood that the present invention is not limited thereto. In some embodiments, the circuit module 610B in Figures 9A-9C can be coupled in other semiconductor packages described herein, such as those discussed with respect to Figures 5A-5C and Figures 8A and 8B. For example, Figures 10A and 10B are schematic cross-sectional views of various packaging options 1000a, 1000b for the circuit module 610B according to some embodiments of the present invention. Figures 10A and 10B include the aforementioned RF transistor amplifier die 210 and elements of the circuit module 610B. Therefore, the discussion of Figures 10A and 10B will focus on parts of embodiments that differ from those discussed with respect to the previous figures.

[0191] Referring to Figure 10A, the semiconductor package 1000a may be similar to the semiconductor packages 500a and 800a discussed herein with respect to Figures 5A and 8A, respectively, and any redundant explanations already discussed with respect to those figures will be omitted. The semiconductor package 1000a may be, for example, an open-air or open-cavity package. The semiconductor package 1000a may include a carrier substrate 410, a side wall 520, and a lid 525. The carrier substrate 410, the side wall 520, and the lid 525 may define an internal cavity 530. The RF transistor amplifier die 210 and the circuit module 610B may be located inside the internal cavity 530. In some embodiments, a thermal layer 240 may be located between the RF transistor amplifier die 210 and the carrier substrate 410.

[0192] Leads 415A and 415B may be configured to extend through the side wall 520, but the present invention is not limited thereto. In some embodiments, the RF transistor amplifier 210 may be located on the carrier substrate 410 and leads 415A and 415B, and the circuit module 610B may be located on the RF transistor amplifier die 210. Leads 415A and 415B may be coupled to the circuit module 610B using, for example, a conductive die attach material. For example, lead 415a may be coupled to the gate lead 682B, and lead 415b may be coupled to the drain lead 684B. In some embodiments, additional leads and / or connectors (not shown) may be coupled to the source lead 686B. Thus, in some embodiments, the use of wire bonds to connect the RF transistor amplifier die 210 to leads 415A and 415B can be avoided and / or reduced.

[0193] Referring to Figure 10B, the semiconductor package 1000b may incorporate the RF transistor amplifier 210 and circuit module 610B according to an embodiment of the present invention. The semiconductor package 1000b may be similar to the semiconductor packages 500b and 800b discussed herein with respect to Figures 5B and 8B, and any redundant explanations already discussed with respect to those figures will be omitted. The semiconductor package 1000b may be, for example, an overmolded plastic (OMP) package.

[0194] In the semiconductor package 1000b according to the present invention, leads 415A and 415B may extend from the outside of the semiconductor package 800b into the overmolding material 540 to connect to the circuit module 610B. For example, lead 415a may be coupled to the gate lead 682B, and lead 415b may be coupled to the drain lead 684B. In some embodiments, additional leads and / or connectors (not shown) may be coupled to the source lead 686B.

[0195] In addition to the semiconductor packages 1000a and 1000b shown in Figures 10A and 10B, it will be understood that other packaging configurations are possible without departing from the present invention. For example, the circuit module 610B may be used with a semiconductor package and other configurations similar to that of Figure 5C.

[0196] As discussed herein, a circuit module may include circuit elements on its surface, or it may include circuit elements within the circuit module itself. Figures 11A to 11D are schematic cross-sectional views of additional embodiments of an RF transistor amplifier die 210 coupled to a circuit module 610C according to some embodiments of the present invention. Figures 11A to 11D include the aforementioned elements of the RF transistor amplifier die 210 and the circuit module 610C. Therefore, the discussion of Figures 11A to 11D will focus on parts of embodiments that differ from those discussed with respect to the previous figures.

[0197] Referring to Figure 11A, the circuit module 610C may be mounted on the RF transistor amplifier die 210. The circuit module 610C may be configured to couple to the gate terminal 222, drain terminal 224, and source terminal 226 of the RF transistor amplifier die 210. While Figure 11A shows the circuit module 610C being directly coupled to the RF transistor amplifier die 210, it will be understood that other types of connections are possible, including other configurations of the RF transistor amplifier 200, including those shown with respect to Figures 2A to 2L. For example, a coupling element 270 may be coupled between the circuit module 610C and the RF transistor amplifier die 210.

[0198] The circuit module 610C may have exposed interconnect pads 622, 624, 626 which may be configured to be coupled to the gate terminal 222, the drain terminal 224, and the source terminal 226, respectively. In some embodiments, bonding elements (e.g., solder balls and / or bumps 320) may be used to couple the first interconnect pad 622, the second interconnect pad 624, and the third interconnect pad 626 to the gate terminal 222, the drain terminal 224, and the source terminal 226, respectively. Although shown as a single pad, in some embodiments, one or more of the first interconnect pad 622, the second interconnect pad 624, and / or the third interconnect pad 626 may comprise multiple pads.

[0199] The circuit module 610C may be coupled to the RF transistor amplifier die on the first surface 601 of the circuit module 610C. In addition, a gate lead 682C, a drain lead 684C, and / or a source lead (not shown) may be exposed on the first surface 601 of the circuit module 610C. The gate lead 682C, the drain lead 684C, and / or the source lead may be configured to be coupled to the gate terminal 222, the drain terminal 224, and the source terminal 226 of the RF transistor amplifier die 210, respectively.

[0200] The circuit module 610C may include one or more conductive patterns 1173, a first circuit element 1150a, and a second circuit element 1150b. The first circuit element 1150a and the second circuit element 1150b are schematically shown in Figure 11A. The circuit module 610C may differ from the circuit modules 610, 610B described herein in that the first circuit element 1150a and the second circuit element 1150b may be incorporated into the structure of the circuit module 610C. For example, a plane capacitor, a comb electrode capacitor, and / or a capacitor may be implemented in the circuit module 610C using the conductive pattern 1173. Similarly, a spiral inductor or other inductive element may also be implemented in the circuit module 610C. Resistive elements may be formed on or within the circuit module 610C, for example, by forming trace segments or conductive vias using a conductive material with higher resistance.

[0201] In some embodiments, the first circuit element 1150a and the second circuit element 1150b and / or the conductive pattern 1173 may be configured to provide at least a portion of a harmonic termination circuit, matching circuit, branch circuit, combining circuit, and / or bias circuit. Other configurations of the conductive pattern 1173 and / or other types of circuit elements 1150a, 1150b may be used without departing from the scope of the present invention. It should be understood that the configuration of the conductive pattern 1173 and circuit elements 1150a, 1150b shown in Figure 11A is merely an example and is not intended to limit embodiments of the present invention.

[0202] In some embodiments, the circuit module 610C may be formed as a PCB module, and the first circuit element 1150a and the second circuit element 1150b may be formed from traces within the PCB. In some embodiments, the circuit module 610C may be formed from an insulating material 615, and the conductive pattern 1173 may be a conductive material within the insulating material 615, such as conductive pillars and / or vias (e.g., copper pillars).

[0203] Each of the first interconnection pad 622, the second interconnection pad 624, and the third interconnection pad 626 may be coupled to one or more conductive patterns 1173 in the circuit module 610C. The conductive patterns 1173 may provide various routing and / or circuitry within the circuit module 610C. For example, the conductive pattern 1173 may connect the first interconnection pad 622 to the gate lead 682C via the first circuit element 1150a. The first circuit element 1150a may provide input matching and / or harmonic termination between the gate lead 682C and the first interconnection pad 622.

[0204] Similarly, the conductive pattern 1173 may connect the second interconnect pad 624 to the drain lead 684C via the second circuit element 1150b. The second circuit element 1150b may provide output matching and / or harmonic termination between the drain lead 684C and the second interconnect pad 624.

[0205] As shown in Figure 11A, in some embodiments, the encapsulation material 1125 may be formed on the RF transistor amplifier die 210, the circuit module 610C, the gate lead 682C, and / or the drain lead 684C. The encapsulation material 1125 can help prevent short circuits, improve the resulting structural integrity of the device, and provide proper impedance matching. In some embodiments, the encapsulation material 1125 may also encapsulate the RF transistor amplifier die 210 within the protective material.

[0206] In some embodiments, through vias 1115 may be formed within the encapsulation material 1125. The through vias 1115 may contain a conductive material and provide conductive paths to the gate lead 682C and / or the drain lead 684C. For example, the through vias 1115 may expose the gate connection portion 1182 and / or the drain connection portion 1184 on the bottom surface of the encapsulation material 1125. The gate connection portion 1182 and / or the drain connection portion 1184 may provide connection points for the gate lead 682C and the drain lead 684C, respectively.

[0207] In some embodiments, the gate connection 1182 and the drain connection 1184 may be substantially coplanar. In some embodiments, the encapsulation material 1125 may be configured to expose the bottom surface of the RF transistor amplifier die 210, and the gate connection 1182 and the drain connection 1184 may also be substantially coplanar with the bottom surface of the RF transistor amplifier die 210, but the present invention is not limited thereto. Although only the gate connection 1182 and the drain connection 1184 are shown in Figure 11A, it will be understood that a source connection may also be provided in a similar manner.

[0208] By using the gate connector 1182 and the drain connector 1184, direct bonding may be used between the RF transistor amplifier die 210 and the circuit module 610C and other pad and / or die combinations. For example, as shown in Figure 11B, the gate connector 1182 may be coupled to the gate pad 1192 (e.g., via a bonding element such as solder), and the drain connector 1184 may be coupled to the gate pad 1194. In some embodiments, a thermal layer 240 may also be provided beneath the RF transistor amplifier die 210, but the present invention is not limited thereto. In some embodiments, the thermal layer 240 may be omitted. In some embodiments, additional contacts may be provided for connection to a third interconnection pad 626 and / or the source terminal 226 of the RF transistor amplifier die 210.

[0209] The packaging example in Figure 11B is merely an example, and it should be understood that the present invention is not limited thereto. Figures 11C and 11D show the use of packaging similar to that discussed herein with respect to Figures 5A-5C, 8A, 8B, 10A, and 10B. For example, a circuit module 610C including a gate connector 1182 and a drain connector 1184, an RF transistor amplifier die 210, and an encapsulation material 1125 may be placed in an open cavity semiconductor package 1100a (Figure 11C) or an OMP package 1100b (Figure 11D). Elements of semiconductor packages 1100a and 1100b in Figures 11C and 11D, which are the same as those described above with respect to Figures 5A-5C, 8A, 8B, 10A, and 10B, are omitted for brevity.

[0210] In some embodiments, the gate connection portion 1182 may be coupled to the gate lead 415A by bonding elements (e.g., solder balls and / or bumps), and the drain connection portion 1184 may also be coupled to the drain lead 415B. The gate lead 415A and the drain lead 415B may be electrically insulated from the carrier substrate 410 (e.g., by an insulating layer and / or overmolding material 540). In some embodiments, a thermal layer 240 may be located between the RF transistor amplifier die 210 and the carrier substrate 410. In some embodiments, the thermal layer 240 may be omitted. In some embodiments, the thermal layer 240 may be a die attach layer, such as a eutectic layer. The thermal layer 240 may be on the transistor amplifier die 210 and / or extend to the encapsulation material 1125. The thermal layer 240 may be a metallic layer for forming a eutectic or other metallic bond. In some embodiments, the thermal layer 240 may be a thermally conductive adhesive. Although not shown in Figures 11C and 11D, additional thermal management structures, such as those shown in Figures 7E and 9D, may be used in some embodiments.

[0211] The packaging embodiments shown in Figures 11C and 11D are merely examples intended to illustrate how the circuit module 610C and the RF transistor amplifier die 210 may be coupled within a semiconductor package. It will be understood that multiple other possible configurations and / or orientations of the semiconductor package are possible without departing from the present invention.

[0212] In some embodiments, the through-vias 1115 and / or encapsulation material 1125 may be omitted. For example, Figures 12A to 12D are schematic cross-sectional views of additional embodiments of an RF transistor amplifier die 210 coupled to a circuit module 610C according to some embodiments of the present invention. As shown in Figure 12A, the circuit module 610C may be substantially the same as that of Figures 11A and 11D, and therefore its redundant description is omitted. For example, the embodiment in Figure 12A may omit the encapsulation material 1125, the through-vias 1115, and / or the gate / drain connections 1182, 1184, and the gate lead 682C and drain lead 684C may be directly exposed. Figure 12A shows that all encapsulation material 1125 is removed, but it will be understood that in some embodiments, some encapsulation material 1125 may be present. For example, in some embodiments, the encapsulation material 1125 may be located on the RF transistor amplifier die 210 and the portion of the circuit module 610C, but the gate lead 682C and drain lead 684C may be exposed.

[0213] The embodiment shown in Figure 12A may be used for multiple packaging configurations. Figures 12B and 12C show the use of packaging similar to that discussed herein with respect to Figures 5A-5C, 8A, 8B, 10A, and 10B. For example, the circuit module 610C and the RF transistor amplifier die 210 may be placed in an open cavity semiconductor package 1200a (Figure 12B) or an OMP package 1200b (Figure 12C). Elements of semiconductor packages 1200a and 1200b in Figures 12B and 12C, which are the same as those described above with respect to Figures 5A-5C, 8A, 8B, 10A, and 10B, are omitted for brevity. In some embodiments, the gate lead 682C may be coupled to the gate lead 415A by bonding elements (e.g., solder balls and / or bumps 320), and the drain lead 684C may also be coupled to the drain lead 415B. Without departing from the present invention, it will be understood that several other possible configurations and / or orientations of the semiconductor package are possible.

[0214] While many of the embodiments described herein have reduced and / or omitted wire bonds, it will be understood that the present invention can still utilize wire bonds to improve the configuration. For example, Figure 12D shows a semiconductor package 1200c utilizing a circuit module 610C that utilizes wire bonds. Referring to Figure 12D, the semiconductor package 1200c may be, for example, an open-air or open-cavity package. The semiconductor package 1200c may include a carrier substrate 410, sidewalls 520, and a lid 525. The carrier substrate 410, sidewalls 520, and lid 525 may define an internal cavity 530. The RF transistor amplifier die 210 and the circuit module 610C may be located inside the internal cavity 530.

[0215] Leads 415A and 415B may be configured to extend through the side wall 520, but the present invention is not limited thereto. In some embodiments, the circuit module 610C may be located on the carrier substrate 410 and leads 415A and 415B, and the RF transistor amplifier die 210 may be located on the circuit module 610C. Leads 415A and 415B may be coupled to the circuit module 610C using, for example, wire bonds 1280. For example, lead 415a may be coupled to the gate lead 682C, and lead 415b may be coupled to the drain lead 684C. The semiconductor package 1200c utilizes wire bonds 1280 but still benefits from a direct connection between the RF transistor amplifier die 210 and the circuit module 610C. Furthermore, the circuit module 610C incorporates first circuit elements 1150a and second circuit elements 1150b which may enable additional intrinsic functions such as harmonic termination and / or input / output impedance matching. In addition, the use of circuit module 610C increases flexibility, as different performance characteristics (for example, to address harmonics at different frequencies, different impedances, etc.) can be achieved simply by replacing the circuit module 610C.

[0216] Figure 12D utilizes circuit module 610C, but it will be understood that wire bond 1280 may be incorporated into other semiconductor packaging configurations that utilize any of the circuit modules and / or RF transistor amplifiers described herein.

[0217] Referring back to Figures 6A to 6C, various embodiments of an RF transistor amplifier die 210 coupled to a circuit module 610 are shown. In some embodiments, the RF transistor amplifier die 210 is directly coupled to the circuit module 610 (e.g., Figure 6B), and in some embodiments, the RF transistor amplifier die 210 is coupled to the circuit module 610 via a coupling element 270 (e.g., Figure 6A). In embodiments such as those in Figures 6A to 6C, an encapsulation material 625 may be present on one or more surfaces of the RF transistor amplifier die 210, thereby protecting / encapsulating the RF transistor amplifier die 210. In some embodiments, as shown in Figures 6A to 6C, the bottom surface of the RF transistor amplifier die 210 may be exposed by the encapsulation material 625, but the present invention is not limited thereto.

[0218] Figures 13A to 13D are schematic cross-sectional views of additional embodiments of an RF transistor amplifier die 210 coupled to a circuit module 610 and incorporating a spacer, according to several embodiments of the present invention. The previously mentioned parts of Figures 13A to 13D are not described again here for brevity. Referring to Figure 13A, in some embodiments, the spacer 245 may be located on the bottom surface 210a of the RF transistor amplifier die 210. The encapsulation material 625 may expose the bottom surface 245a of the spacer 245.

[0219] In some embodiments, the spacer 245 may be formed from an electrically and / or thermally conductive material, such as a metal. In some embodiments, the spacer 245 may be gold (Au), copper (Cu), Cu alloy, gold-tin (AuSn), and / or epoxy, or may contain these, but the present invention is not limited thereto. In some embodiments, the spacer 245 may be electrically insulating and / or may be a dielectric material, such as silicon oxide, silicon nitride, polymer, molded compound, or a combination thereof, or may contain these, but the present invention is not limited thereto. In some embodiments, the spacer 245 may be thermally conductive. Therefore, the spacer 245 may be configured to dissipate heat transferred from the RF transistor amplifier die 210. In some embodiments, the spacer 245 may consist of multiple layers, but the present invention is not limited thereto. In some embodiments, the spacer 245 may perform a similar function to the thermal layer 240 described herein, or may be composed of similar materials. By incorporating a spacer 245 into the RF transistor amplifier die 210 within the encapsulation material 625, a packaging option that facilitates distribution and installation may be provided. Figure 13A shows an embodiment in which the RF transistor amplifier die 210 is directly coupled to a circuit module 610, but the present invention is not limited thereto. In some embodiments, the transistor amplifier die 210 may be coupled to the circuit module 610 via a coupling element 270 in a manner similar to that shown in Figure 6B. Similarly, in some embodiments, the RF transistor amplifier die 210 may incorporate an on-die RDL, such as the RF transistor amplifier die 210' in Figure 3C.

[0220] As shown in FIG. 13A, the encapsulation material 625 may be on the RF transistor amplifier die 210 and also on the first circuit element 650a and the second circuit element 650b. However, the present invention is not limited to such a configuration. Depending on the electrical and thermal requirements for the first circuit element 650a and the second circuit element 650b, alternative and / or additional terminal / bonding / spacer structures may be utilized with at least one of the first circuit element 650a and the second circuit element 650b to provide electrical connection, thermal connection, and / or mechanical interface to one or more of the first circuit element 650a and the second circuit element 650b.

[0221] In some embodiments, the surfaces of the first circuit element 650a and the second circuit element 650b may be exposed and / or may be coupled to auxiliary spacers as part of the RF transistor amplifier. For example, FIG. 13B is a schematic cross-sectional view of an RF transistor amplifier die 210 coupled to a circuit module 610 according to some embodiments of the present invention. As shown in FIG. 13B, the circuit module 610 and / or the RF transistor amplifier die 210 may be substantially the same as the embodiments described above, and thus, the overlapping description thereof is omitted. The embodiment shown in FIG. 13B may include, for example, a first auxiliary spacer 246a and a second auxiliary spacer 246b.

[0222] In some embodiments, the first auxiliary spacer 246a may be formed on the first circuit element 650a. In some embodiments, the second auxiliary spacer 246b may be formed on the second circuit element 650B. For example, the first auxiliary spacer 246a may be formed to be on and / or in contact with the first circuit element 650a, and the second auxiliary spacer 246b may be formed to be on and / or in contact with the second circuit element 650b. In some embodiments, the first auxiliary spacer 246a and / or the second auxiliary spacer 246b may be formed from an electrically and / or thermally conductive material, such as a metal. In some embodiments, the surfaces of the first auxiliary spacer 246a and / or the second auxiliary spacer 246b may be exposed from the encapsulation material 625. In some embodiments, the first auxiliary spacer 246a and / or the second auxiliary spacer 246b may be gold (Au), copper (Cu), Cu alloy, gold-tin (AuSn), and / or epoxy, or may include these, but the present invention is not limited thereto. The first auxiliary spacer 246a and / or the second auxiliary spacer 246b may be configured to be electrically coupled to the first circuit element 650a and / or the second circuit element 650b, for example, to provide a mechanism for providing a ground signal to the first circuit element 650a and / or the second circuit element 650b. In some embodiments, the first auxiliary spacer 246a and / or the second auxiliary spacer 246b may be thermally conductive. Thus, the first auxiliary spacer 246a and / or the second auxiliary spacer 246b may be configured to dissipate heat transferred from the first circuit element 650a and / or the second circuit element 650b. In some embodiments, the first auxiliary spacer 246a and / or the second auxiliary spacer 246b may be electrically insulating and / or be a dielectric material such as silicon oxide, silicon nitride, polymer, molded compound, or a combination thereof, or may include such a material, but the present invention is not limited thereto.In some embodiments, the first auxiliary spacer 246a and / or the second auxiliary spacer 246b may be composed of multiple layers, but the present invention is not limited thereto.

[0223] In some embodiments, the first auxiliary spacer 246a and / or the second auxiliary spacer 246b may be composed of the same material as the spacer 245, but the present invention is not limited thereto. In some embodiments, the first auxiliary spacer 246a and / or the second auxiliary spacer 246b may be composed of a material different from that of the spacer 245. In some embodiments, the first auxiliary spacer 246a and / or the second auxiliary spacer 246b may be electrically disconnected from the spacer 245. Forming the first auxiliary spacer 246a and / or the second auxiliary spacer 246b from a material different from that of the spacer 245 and / or being electrically disconnected from the spacer 245 can help limit current sharing and / or eddy currents between the RF transistor amplifier die 210 and the first circuit element 650a and / or the second circuit element 650b. The first auxiliary spacer 246a, the second auxiliary spacer 246b, and the spacer 245 are shown as separate individual elements, but the present invention is not limited thereto. In some embodiments, the first auxiliary spacer 246a, the second auxiliary spacer 246b, and the spacer 245 may be connected together as an integral layer (see, for example, FIG. 13C).

[0224] The material / thickness of the first auxiliary spacer 246a and the second auxiliary spacer 246b can be the same as or different from that of spacer 245. In some embodiments, spacer 245, as well as the first auxiliary spacer 246a and the second auxiliary spacer 246b, may have different thicknesses so that the bottoms of the first auxiliary spacer 246a and the second auxiliary spacer 246b are coplanar with the bottom of spacer 245 to facilitate packaging / manufacturing / bonding of the RF transistor amplifier die 210 and the circuit module 610 to the package substrate or circuit board. In some embodiments, spacer 245, as well as the first auxiliary spacer 246a and the second auxiliary spacer 246b, may have the same thickness. In other embodiments, spacer 245 extends, for example, to the RF transistor amplifier die 210, as well as at least one or all of the first circuit element 650 and the second circuit element 650b, to provide the advantage of a flat interface.

[0225] Additional and / or intervening spacers, bonds, and other layers can be provided to offer the desired electrical, thermal, and mechanical interfaces. Depending on the desired electrical, thermal, and / or mechanical properties, the layers can be made from electrically and / or thermally conductive and / or insulating materials. For example, in some embodiments, spacer 245 may be thermally conductive and electrically insulating, while the first auxiliary spacer 246a and the second auxiliary spacer 246b may be conductive both electrically and thermally. In some embodiments, only spacer 245 may be present on the RF transistor amplifier die 210. In some embodiments, only the first auxiliary spacer 246a may be present on the first circuit element 650a. In some embodiments, only the second auxiliary spacer 246b may be present on the second circuit element 650b. In other embodiments, any combination of spacer 245, the first auxiliary spacer 246a, and the second auxiliary spacer 246b may be present.

[0226] In some embodiments, the exposed surfaces of the first auxiliary spacer 246a, the second auxiliary spacer 246b, and the spacer 245 may be substantially coplanar. That is, the exposed surfaces of the first auxiliary spacer 246a, the second auxiliary spacer 246b, and the spacer 245 may be configured to be mounted on separate substrates (e.g., via a mounting method such as soldering).

[0227] The manufacturing methods for the embodiments shown in Figures 13A to 13C may be the same as those shown with respect to Figures 7A to 7D. For example, manufacturing an RF transistor amplifier device may include placing a spacer 245 on the RF transistor amplifier die 210, placing a first auxiliary spacer 246a on the first circuit element 650a, and placing a second auxiliary spacer 246b on the second circuit element 650b. For example, the spacer 245 may be electrically and / or thermally connected to the RF transistor amplifier die 210 (e.g., via a die attach material). For example, the first auxiliary spacer 246a and the second auxiliary spacer 246b may be electrically and / or thermally connected to the first circuit element 650a and the second circuit element 650b, respectively (e.g., via a die attach material). This step may be performed, for example, after the first circuit element 650a and the second circuit element 650b and the RF transistor amplifier die 210 have been placed on the circuit module 610 (as shown with reference to Figures 7B and 7C). In some embodiments, the placement of the spacer 245, the first auxiliary spacer 246a, and the second auxiliary spacer 246b may be performed before or after the encapsulation material 625 is formed on the RF transistor amplifier die 210 (as shown with reference to Figure 7D). In some embodiments, the placement of the spacer 245 may be performed by a different process than that of the first auxiliary spacer 246a and / or the second auxiliary spacer 246b.

[0228] As described above, in some embodiments, the first auxiliary spacer 246a, the second auxiliary spacer 246b, and the spacer 245 may be interconnected and / or formed integrally. Figure 13C shows an embodiment having an integrated spacer layer 245'. The integrated spacer layer 245' may be connected to and / or extend into contact with the first circuit element 350a, the second circuit element 350b, and the RF transistor amplifier die 10 (e.g., the source terminal 26 of the RF transistor amplifier die 10). In some embodiments, the surface 245a' of the integrated spacer layer 245' may be exposed from the encapsulation material 325. In some embodiments, the integrated spacer layer 245' may be formed from the same or similar material as the first auxiliary spacer 246a, the second auxiliary spacer 246b, and / or spacer 245 described in relation to the embodiments described above. For example, the integrated spacer layer 245' may be formed from an electrically and / or thermally conductive material, such as a metal. In some embodiments, the integrated spacer layer 245' may be gold (Au), copper (Cu), Cu alloy, gold-tin (AuSn), and / or epoxy, or may contain thereof, but the present invention is not limited thereto. In some embodiments, the integrated spacer layer 245' may be electrically insulating and / or may be a dielectric material such as silicon oxide, silicon nitride, polymer, molded compound, or a combination thereof, or may contain thereof, but the present invention is not limited thereto. In some embodiments, the integrated spacer layer 245' may consist of multiple layers, but the present invention is not limited thereto. As used herein, “integrated” spacer layer 245' refers to a spacer layer 245' that is not necessarily uniform in composition but is substantially continuous. In some embodiments, different portions of the integrated spacer layer 245' may be composed of different materials. For example, the portion of the integrated spacer layer 245' on the first auxiliary spacer 246a and / or the second auxiliary spacer 246b may be different from the portion of the integrated spacer layer 245' on the RF transistor amplifier die 210.

[0229] The integrated spacer layer 245' is shown as a uniform layer having a relatively flat upper surface 245b', but the present invention is not limited thereto. In some embodiments, the upper surface 245b' of the integrated spacer layer 245' does not have to be flat. For example, in some embodiments, the first circuit element 650a, the second circuit element 650b, and the RF transistor amplifier die 210 may have different heights, and the integrated spacer layer 245' may be formed to have an upper surface 245b' having portions at each of the different heights of the first circuit element 650a, the second circuit element 650b, and the RF transistor amplifier die 210.

[0230] Figure 13D shows an exemplary embodiment of an RF transistor amplifier device in which the first auxiliary spacer 246a and the second auxiliary spacer 246b are omitted. Referring to Figure 13D, the surfaces 650a_s of the first circuit element 650a and / or the surfaces 650b_s of the second circuit element 650b may be exposed by the encapsulation material 625. The exposure of the surfaces 650a_s, 650b_s of the first circuit element 650a and / or the second circuit element 650b may allow additional external connections to be applied to the first circuit element 650a and / or the second circuit element 650b. For example, separate electrical connections, such as for a ground signal, may be connected to the first circuit element 650a and / or the second circuit element 650b by their respective exposed surfaces 650a_s, 650b_s.

[0231] The RF transistor amplifier device in Figure 13D may be formed, for example, by constructing an embodiment similar to that in Figure 13A, and then performing a planar operation on the portion of the encapsulating material 625 to expose the surfaces 650a_s, 650b_s of the first circuit element 650a and / or the second circuit element 650b.

[0232] The RF transistor amplifier die 210 coupled to the circuit module 610 shown in Figures 13A to 13D may be used in multiple packaging configurations. Figures 14A to 14D show the use of packaging similar to that discussed herein with respect to Figures 8A and 8B. For example, the circuit module 610 and the RF transistor amplifier die 210 may be placed in open cavity semiconductor packages 1400a_1, 1400a_2 (Figures 14A and 14B) or OMP packages 1400b_1, 1400b_2 (Figures 14C and 14D). The elements of semiconductor packages 1400a_1 and 1400a_2 in Figures 14A and 14B, which are similar to those described above with respect to Figure 8A, etc., will not be discussed further for brevity. The elements of semiconductor packages 1400b_1 and 1400b_2 in Figures 14C and 14D, which are the same as those described above with respect to Figure 8B, will not be discussed further for the sake of brevity.

[0233] In Figures 14A and 14C, semiconductor packages 1400a_1 and 1400b_1 illustrate the use of a circuit module 610 coupled to an RF transistor amplifier die 210 within an open cavity package and an OMP package. Figure 14A shows the open cavity semiconductor package 1400a_1, and Figure 14C shows the OMP semiconductor package 1400b_1. Semiconductor packages 1400a_1 and 1400b_1 further include spacers 245, a first auxiliary spacer 246a, and a second auxiliary spacer 246b, such as those illustrated and described in relation to Figure 13B. The circuit module 610 may expose gate leads 682 and drain leads 684, which may be connected to leads 415A and 415B, respectively. In some embodiments, semiconductor packages 1400a_1 and 1400b_1 may include a first auxiliary spacer 246a, a second auxiliary spacer 246b, and spacer 245 that are substantially coplanar. Depending on the electrical and thermal requirements for the first circuit element 650a and the second circuit element 650b, additional terminal / bonding / spacer structures may be used in conjunction with at least one of the first circuit element 650a and the second circuit element 650b to provide an electrical, thermal, and / or mechanical interface between the first circuit element 650a and the second circuit element 650b and at least one of the carrier substrate 410.

[0234] In some embodiments, the first auxiliary spacer 246a and the second auxiliary spacer 246b may be made of a different material than spacer 245. For example, in some embodiments, the first auxiliary spacer 246a and the second auxiliary spacer 246b may be conductive so as to be electrically coupled to the carrier substrate 410. For example, the first auxiliary spacer 246a and the second auxiliary spacer 246b may provide electrical connections (e.g., ground signals) to the first circuit element 650a and the second circuit element 650b. In some embodiments, spacer 245 may be thermally conductive but electrically insulating. This may allow spacer 245 to dissipate heat from the RF transistor amplifier die 210. In some embodiments, the first auxiliary spacer 246a and the second auxiliary spacer 246b may be electrically insulating or conductive, but the first circuit element 650a and the second circuit element 650b may be thermally connected to the carrier substrate 410 so as to dissipate thermal energy (e.g., heat) from the first circuit element 650a and the second circuit element 650b.

[0235] Figures 14B and 14D show exemplary semiconductor packages 1400a_2 and 1400b_2 incorporating an integrated spacer layer 245 within an open cavity package and an OMP package. Figure 14B shows the open cavity semiconductor package 1400a_2, and Figure 14D shows the OMP semiconductor package 1400b_2. The semiconductor packages 1400a_2 and 1400b_2 may utilize an integrated spacer layer 245' as discussed herein with respect to Figure 13C. The integrated spacer layer 245' may be connected to and / or in direct contact with the carrier substrate 410. The integrated spacer 245' may be coupled to a first circuit element 650a, a second circuit element 650b, and / or an RF transistor amplifier die 210. In some embodiments, the integrated spacer layer 245' may be configured to have a non-planar surface (e.g., an upper surface) to couple with the first circuit element 650a, the second circuit element 650b, and the RF transistor amplifier die 210. The present invention is not limited thereto, and in some embodiments, the upper surface of the integrated spacer layer 245' may be flat. In some embodiments, different portions of the integrated spacer layer 245' may be made of different materials. In some embodiments, additional layers may be placed between the first circuit element 650a and the second circuit element 650b and the integrated spacer layer 245', or between the integrated spacer layer 245' and the carrier substrate 410 (e.g., an additional spacer layer).

[0236] In Figures 14A to 14D, the RF transistor amplifier die 210 is shown as being directly coupled to the circuit module 610 in semiconductor packages 1400a_1, 1400a_2, 1400b_1, and 1400b_2. However, it will be understood that the RF transistor amplifier die 210 may also be coupled to the circuit module via coupling elements 270 or using on-die RDL, with modifications as appropriate.

[0237] Figures 15A to 15D are schematic cross-sectional views of additional RF transistor amplifier embodiments according to several embodiments of the present invention, including a circuit module 610B and incorporating a mechanism for coupling a first circuit element 650a and a second circuit element 650b. The portions of the RF transistor amplifier die 210 and the circuit module 610B may be substantially the same as those in Figures 9A to 9D and other aforementioned figures, and therefore their redundant descriptions are omitted. The embodiments in Figures 15A to 15D may incorporate a circuit module 610B that exposes the gate lead 682B and / or drain lead 684B on the same surface 601 (e.g., the lower surface) of the circuit module 610B to which the RF transistor amplifier die 210 is coupled. The RF transistor amplifier embodiments in Figures 15A to 15D may include embodiments similar to those in Figure 9B, for example, with the addition of a spacer 245, a first auxiliary spacer 246a, and / or a second auxiliary spacer 246b.

[0238] For example, Figure 15A shows an RF transistor amplifier die 210 coupled to a circuit module 610B, with a spacer 245 positioned on the bottom surface 210a of the RF transistor amplifier die 210. The encapsulation material 625 may expose the bottom surface 245a of the spacer 245.

[0239] In some embodiments, the spacer 245 may be formed from an electrically and / or thermally conductive material, such as a metal. In some embodiments, the spacer 245 may be gold (Au), copper (Cu), Cu alloy, gold-tin (AuSn), and / or epoxy, or may include them, but the present invention is not limited thereto. In some embodiments, the spacer 245 may be electrically insulating and / or may be a dielectric material, such as silicon oxide, silicon nitride, polymer, molded compound, or a combination thereof, or may include them, but the present invention is not limited thereto. In some embodiments, the spacer 245 may be thermally conductive. Therefore, the spacer 245 may be configured to dissipate heat transferred from the RF transistor amplifier die 210. In some embodiments, the spacer 245 may perform a similar function to the thermal layer 240 described herein, or may be composed of a similar material. In some embodiments, the spacer 245 may be composed of multiple layers, but the present invention is not limited thereto. Figure 15A shows an embodiment in which the RF transistor amplifier die 210 is directly coupled to the circuit module 610, but the present invention is not limited thereto. In some embodiments, the transistor amplifier die 210 may be coupled to the circuit module 610 via a coupling element 270 in a manner similar to that shown in Figure 6B. Similarly, in some embodiments, the RF transistor amplifier die 210 may incorporate an on-die RDL, similar to the RF transistor amplifier die 210' in Figure 3C.

[0240] Figure 15B shows an embodiment similar to that of Figure 15A, with the addition of a first auxiliary spacer 246a and a second auxiliary spacer 246b. In some embodiments, the first auxiliary spacer 246a may be formed to be on and / or in contact with the first circuit element 650a, and the second auxiliary spacer 246b may be formed to be on and / or in contact with the second circuit element 650b. In some embodiments, the first auxiliary spacer 246a and / or the second auxiliary spacer 246b may be formed from an electrically and / or thermally conductive material, such as a metal. In some embodiments, the surfaces of the first auxiliary spacer 246a and / or the second auxiliary spacer 246b may be exposed from the encapsulation material 625. In some embodiments, the first auxiliary spacer 246a and / or the second auxiliary spacer 246b may be gold (Au), copper (Cu), Cu alloy, gold-tin (AuSn), and / or epoxy, or may include these, but the present invention is not limited thereto. The first auxiliary spacer 246a and / or the second auxiliary spacer 246b may provide a ground signal to the first circuit element 650a and / or the second circuit element 650b, or a mechanism for dissipating thermal energy from the first circuit element 650a and / or the second circuit element 650b, as discussed herein with respect to other embodiments.

[0241] In some embodiments, the first auxiliary spacer 246a and / or the second auxiliary spacer 246b may be made of the same material as the spacer 245, but the present invention is not limited thereto. In some embodiments, the first auxiliary spacer 246a and / or the second auxiliary spacer 246b may be made of a different material than the spacer 245. In some embodiments, the first auxiliary spacer 246a and / or the second auxiliary spacer 246b may be electrically disconnected (e.g., isolated) from the spacer 245. In some embodiments, the first auxiliary spacer 246a and / or the second auxiliary spacer 246b may be made of multiple layers, but the present invention is not limited thereto.

[0242] The first auxiliary spacer 246a, the second auxiliary spacer 246b, and the spacer 245 are shown as separate individual elements, but the present invention is not limited thereto. In some embodiments, the first auxiliary spacer 246a, the second auxiliary spacer 246b, and the spacer 245 may be formed as an integrated (e.g., interconnected) spacer layer 245'. Such an embodiment is shown in Figure 15C, which represents an RF transistor amplifier die 210 coupled to a circuit module 610B including the integrated spacer layer 245'. The integrated spacer layer 245' may be similar to that discussed herein with respect to Figure 13C. The integrated spacer layer 245' may extend to contact the first circuit element 650a, the second circuit element 650b, and / or the RF transistor amplifier die 210. In some embodiments, the surface 245a of the integrated spacer layer 245' may be exposed from the encapsulation material 625. In some embodiments, the integrated spacer layer 245' may be formed from the same or similar material as the first auxiliary spacer 246a, the second auxiliary spacer 246b, and / or spacer 245. In some embodiments, the upper surface 245b' of the integrated spacer layer 245' may or may not be flat. For example, in some embodiments, the first circuit element 650a, the second circuit element 650b, and / or the RF transistor amplifier die 210 may have different heights, and the integrated spacer layer 245' may be formed to have an upper surface 245b' having portions at each of the different heights of the first circuit element 650a, the second circuit element 650b, and the RF transistor amplifier die 210.

[0243] FIG. 15D shows an embodiment of an RF transistor amplifier device in which the first auxiliary spacer 246a and the second auxiliary spacer 246b are omitted. The RF transistor amplifier die 210 may be coupled to the circuit module 610B in the same manner as in FIG. 15A, and thus its redundant description is omitted. Referring to FIGS. 15A and 15D, the upper surface 650a_s of the first circuit element 650a and / or the upper surface 650b_s of the second circuit element 650b may be exposed from the encapsulation material 625. The exposure of the surfaces 650a_s, 650b_s of the first circuit element 650a and / or the second circuit element 650b may enable additional external connections to be applied to the first circuit element 650a and / or the second circuit element 650b. For example, separate electrical connections for a ground signal or the like may be connected to the first circuit element 650a and / or the second circuit element 650b by their respective exposed surfaces 650a_s, 650b_s.

[0244] The RF transistor amplifier device of FIG. 15D may be formed, for example, by constructing the RF transistor amplifier device of FIG. 15A and then performing a planarization operation on a portion of the encapsulation material 625 to expose the surfaces 650a_s, 650b_s of the first circuit element 650a and / or the second circuit element

[0245] The RF transistor amplifier devices shown in Figures 15A to 15D may be used in multiple packaging configurations. Figures 16A to 16D show the use of packaging similar to that discussed herein with respect to Figures 10A, 10B, and 14A to 14D. For example, the circuit module 610B and the RF transistor amplifier die 210 may be placed in open cavity semiconductor packages 1600a_1, 1600a_2 (Figures 16A, 16B) or OMP packages 1600b_1, 1600b_2 (Figures 16C, 16D). In some embodiments, the spacer layer 245 may be used in conjunction with a first auxiliary spacer 246a and a second auxiliary spacer 246b within the open cavity semiconductor package 1600a_1 (Figure 16A) or the OMP package 1600b_1 (Figure 16C). In some embodiments, the integrated spacer layer 245' may be used with an open cavity semiconductor package 1600a_2 (Figure 16B) or an OMP package 1600b_2 (Figure 16D). The elements in Figures 16A-16D of semiconductor packages 1600a_1, 1600a_2, 1600b_1, and 1600b_2, which are the same as those described above with respect to other figures such as Figures 10A and 10B, will not be discussed further for the sake of brevity. In some embodiments, semiconductor packages 1600a_1, 1600a_2, 1600b_1, and 1600b_2 may also house an RF transistor amplifier device, where the gate lead pad 682B and drain lead pad 684B are exposed on the lower surface of the circuit module 610B. In Figures 16A to 16D, the RF transistor amplifier die 210 is shown as being directly coupled to circuit modules 610B within semiconductor packages 1600a_1, 1600a_2, 1600b_1, and 1600b_2. However, it will be understood that the RF transistor amplifier die 210 may also be coupled to the circuit modules via coupling elements 270 or using on-die RDL, with modifications as appropriate.

[0246] Referring to Figures 16A and 16C, the first auxiliary spacer 246a and the second auxiliary spacer 246b may be connected to and / or in direct contact with the carrier substrate 410. In this manner, the first auxiliary spacer 246a and the second auxiliary spacer 246b may thermally dissipate heat from the first circuit element 650a and the second circuit element 650b and / or provide electrical signals (e.g., ground signals) to the first circuit element 650a and the second circuit element 650b. Depending on the electrical and thermal requirements for the first circuit element 650a and the second circuit element 650b, additional terminal / bonding / spacer structures may be used with at least one of the first circuit element 650a and the second circuit element 650b to provide an electrical, thermal, and / or mechanical interface between at least one of the first circuit element 650a and the second circuit element 650b and the substrate 410.

[0247] Referring to Figures 16B and 16D, the first auxiliary spacer 246a and the second auxiliary spacer 246b may be replaced by an integrated spacer layer 245' coupled to the first circuit element 650a, the second circuit element 650b, and / or the RF transistor amplifier die 210. The integrated spacer layer 245' may be connected to and / or in direct contact with the carrier substrate 410. The integrated spacer layer 245' may have a flat or non-flat upper surface. In some embodiments, additional layers may be placed between the first circuit element 650a and the second circuit element 650b and the integrated spacer layer 245', or between the integrated spacer layer 245' and the carrier substrate 410 (e.g., an additional spacer layer).

[0248] Embodiments described herein provide improved RF transistor amplifiers and improved packaging incorporating such RF transistor amplifiers. By avoiding and / or reducing the use of back-side vias, some embodiments of the present invention provide improved thermal management of the power amplifier. Furthermore, interconnect structures or circuit modules can be utilized that reduce the need for wire bonding by locating the contacts of the power amplifier on the same face of the device. As a result, the RF transistor amplifier and associated package may exhibit improved performance and thermal characteristics superior to conventional devices. The advantages of direct bonding provided by embodiments of the present invention include reduced form factor, lower electrical resistance, and increased communication speed.

[0249] As described above, according to embodiments of the present invention, the group III nitride-based RF transistor amplifiers 200, 200', 200'' (collectively referred to as 200) may include a transistor die 210 having gate terminals, drain terminals, and source terminals, all located on the same surface (e.g., top or front) or surface 212 of the RF transistor amplifier die 210, which is also referred to herein as a transistor die 210 or die 210. The RF transistor amplifier 200 does not need to include bond wires for the gate and / or drain connections, thereby reducing the amount of inductance present in the circuit. Since all three terminals, gate terminals, drain terminals, and source terminals are on the top surface 212 of the transistor die 210, the RF transistor amplifier according to embodiments of the present invention may be mounted in a flip-chip configuration where the transistor die 210 is mounted on another substrate, such as on the surface of an interconnect structure 310, 610, as described above. In some embodiments, the opposite (e.g., back) or front 214 of the transistor die 210 may be mounted on a thermally conductive carrier substrate or submount 410, such as a metal slug, lead frame, or flange, to provide improved heat dissipation from the amplifier package of the heat generated by the die.

[0250] The interconnect structure may be implemented by any of the circuit modules discussed herein (e.g., 310, 310', 310'' (collectively 310) or 610, 610', 610A-C (collectively 610)). The interconnect structure may be an interposer structure such as a dielectric-based structure having circuit-integrated conductive traces, vias and / or circuits extending therein and / or on it, or other multilayer laminate or PCB structure. Conductive traces or patterns (e.g., 373, 673, 1173) may provide various routing and / or circuits within the interconnect structure.

[0251] The interconnect structure may include circuit elements of an RF transistor amplifier (e.g., 350a-b (collectively 350) or 650a-b (collectively 650)) on one or more surfaces. The circuit elements may be configured to provide, for example, impedance matching and / or harmonic termination circuits. For example, conductive traces or patterns of the interconnect structures 310, 610 may electrically couple the circuit elements between the gate terminal 222 and the input lead 415A, and / or between the drain terminal 224 and the output lead 415B.

[0252] As described above, circuit elements 350, 650 may include passive electrical components, including resistors / transmission lines, capacitors, and / or inductors, which may be implemented (at least partially) in surface mount devices (SMDs), integrated passive devices (IPDs), and combinations thereof. IPDs may include inductors, capacitors, and / or other passive electrical components and may be fabricated using standard semiconductor processing techniques such as thin film and / or photolithography. IPDs can be flip-chip mountable or wire-bondable components and may include thin-film substrates such as silicon, alumina, or glass.

[0253] In further embodiments described herein, an interposer or other interconnect structure and its passive electrical components on its surface may collectively implement a “passive module,” also referred herein as a passive component assembly. An active transistor die and any conductive structure (e.g., pillars or coupling elements thereon) may collectively implement an “active module,” also referred herein as an active component assembly. The active component assembly may be provided on the surface of the passive component assembly (e.g., on the top surface or the bottom surface). The active module and the passive module may be coupled by a flip-chip connection and, in some embodiments, have standoffs for mechanical support and / or heat conduction. The active module may include an active GaN and an RDL or heat spreader on a SiC die. Examples of active modules are shown with reference to Figures 20A to 20C and described herein. The passive module may include various passive components, such as IPDs, SMDs, laminate-based transmission lines, for impedance matching and / or harmonic termination. Examples of passive modules are shown with reference to Figures 19A–19C and are described herein. Passive modules described herein may be electrically tested and screened before integration with active modules, which may improve yield and reduce costs.

[0254] Embodiments of the present invention may also allow for stacked component connections (e.g., in the Z direction) and separate electrical grounding paths from the main heat conduction paths, which in other ways may be difficult or impossible without using a flip-chip interconnect system. Separating the active and passive modules of the package device may also allow for electrical testing and / or screening before final packaging / assembly, thereby improving yield and reducing costs. The standoff structure can not only provide mechanical support to the laminate or interposer for assembly flexibility, but can also provide an alternative heat extraction path if a material with high thermal conductivity is selected.

[0255] In some embodiments, the passive component assembly or module may include a transistor die 210 on the same face or surface as the passive electrical component of the interconnect structure. For example, as described above with reference to Figures 6A-6B, 7C-7E, and 8A-8B, the circuit element 650 and die 210 are located on the same face of the interconnect structure 610, which may be referred to herein as an active module on the same face as the passive module (AMSPM). In some embodiments, the passive component assembly or module may include a transistor die 210 on the opposite face of the interconnect structure from the passive electrical component. For example, with reference to Figures 3A-3E, 4A-4C, and 5A-5C, the circuit element 350 and die 210 are located on the opposite face or surface of the interconnect structure 310, which may be referred herein as an active module on the back surface of the passive module (AMBPM).

[0256] The AMSPM and AMBPM configurations described herein may include many variations of active and passive component assemblies. Figures 19A, 19B, and 19C show various examples of passive component assemblies 1905a, 1905b, 1905c (collectively 1905) according to several embodiments of the present invention. As shown in Figures 19A to 19C, each passive component assembly 1905 includes a circuit module or other interconnection structure 310''. The circuit module 310'' includes an internal conductive pattern 373 and one or more passive electrical components 1750a, 1750b, 1750c / c' / c'' (collectively 1750) on a first surface 312. In some embodiments, the circuit module 310'' may be formed as a printed circuit board (PCB) or redistribution layer (RDL) laminate structure, and the conductive pattern 373 is implemented as a conductive structure within the substrate of the PCB or RDL laminate structure.

[0257] The conductive pattern 373 may provide various routing and / or circuits within the circuit module 310'', and as a result, the die 210 can be mounted on the first surface 312 (in the case of an AMSPM configuration) and / or on the second surface 314 (in the case of an AMBPM configuration) of the interconnection structure 310''. For example, the conductive pattern 373 may electrically connect interconnection pads 372, 374, 376 on the first surface 312 of the circuit module 310'' to each other and / or to interconnection pads 322, 324, 326 on the second surface 314 of the circuit module 310''.

[0258] In particular, in Figures 19A, 19B, and 19C, interconnection pads 322, 324, and 326 are configured to couple to the gate terminal 222'', drain terminal 224'', and source terminal 226'' of the die 210 mounted on the second surface 314 opposite to the passive component 1750. In some embodiments, interconnection pads 372, 374, and 376 may be configured to couple to the gate terminal 222'', drain terminal 224'', and source terminal 226'' of the die 210 mounted on the first surface 312 adjacent to the passive component 1750. Although shown as a single pad as an example, one or more of the interconnection pads 322, 324, 326, 372, 374, and 376 may be implemented by multiple pads.

[0259] The passive electrical components 1750 may include resistors / transmission lines, capacitors, and / or inductors implemented within the SMD and / or IPD. In the example in Figures 19A to 19C, the passive electrical component 1750a is configured to be positioned for electrical connections to the input leads of the package, the passive electrical component 1750b is configured to be positioned for electrical connections to the output leads of the package, and the passive electrical component 1750c is configured to be positioned for electrical connections between components 1750a and 1750b and one or more terminals 222'', 224'', 226'', of the die 210.

[0260] The passive electrical components 1750 may be mounted on their respective interconnection pads 372, 374, 376 on the first surface 312 of the circuit module 310'' in a surface mount configuration (e.g., 1750c), a wire bond configuration (e.g., 1750c'), or a flip-chip configuration (e.g., 1750c''). In particular, Figure 19A shows each of the passive electrical components 1750a, 1750b, and 1750c in a surface mount configuration. Figure 19B shows a combination of surface mount components 1750a, 1750b and wire bond component 1750c'. Figure 19C shows a combination of surface mount components 1750a, 1750b and flip-chip component 1750''. In a flip-chip configuration, the passive electrical component 1750c'' may include conductive pads that are positionally aligned with and electrically coupled to one or more interconnection pads 372, 374, 376. In any of the examples in Figures 19A to 19C, the passive electrical component 1750 may be pre-assembled on the first surface 312 of the circuit module 310'' and may be sealed in a separate mold structure (e.g., 2240 as shown in Figure 22) from the package overmolding material (e.g., 1740).

[0261] Conductive leads 415A and 415B (as shown in Figures 17-18 and 21A-24C) allow the RF transistor amplifier 200 to be connected to an external device / circuit / power supply. Leads 415A and 415B may be coupled to the circuit module 310'' using, for example, wire bonds or conductive die attach material. In some embodiments (e.g., Figure 18), leads 415A and 415B may be coupled to interconnect pads on the first surface 312 of the circuit module 310'' (e.g., to interconnect pads 372 and 374, respectively). In some embodiments (e.g., Figure 17), leads 415A and 415B may be coupled to interconnect pads on the second surface 314 (e.g., to interconnect pads 322 and 324, respectively). In some embodiments, leads 415A and 415B may be directly coupled to interconnect pads so as to avoid and / or reduce the use of wire bonds to connect the RF transistor amplifier 200 to leads 415A and 415B. While primarily illustrated with reference to two leads 415A and 415B, embodiments of the present invention are not limited thereto. In some embodiments, three or more leads may be provided, for example, coupled to interconnect pads 322 or 372 (e.g., as gate leads), 324 or 374 (e.g., as drain leads), and 326 or 376 (e.g., as source leads).

[0262] As a result, the passive electrical component 1750 may be electrically coupled between its gate terminal 222'' and the first (e.g., input) lead 415A of the transistor amplifier, and / or between its drain terminal 224'' and the second (e.g., output) lead 415B of the transistor amplifier. In particular, the RF signal input to the RF transistor amplifier 200 on the input lead 415A may pass through the circuit module 310'' to the passive electrical components 1750a and 1750c, and from there to the gate terminal 222'' of the transistor die 210, and the amplified output RF signal may pass from the drain terminal 224'' of the transistor die 210 to the passive electrical components 1750c and 1750b, and from there through the circuit module 310'', where the RF signal is output through the output lead 415B.

[0263] The passive electrical component 1750 coupled by the circuit module 310'' may be configured to provide, for example, an input matching circuit, an output matching circuit, and / or a harmonic termination circuit used for impedance matching at the fundamental frequency and / or terminating the intermodulation product to ground. Thus, by using the passive component assembly 1905 described herein, greater flexibility may be provided in that different performance characteristics (e.g., to address harmonics at different frequencies, different impedances, etc.) can be achieved for different applications by swapping the passive component assembly 1905 and / or the passive electrical component 1750. In addition, the passive component assembly 1905 may be electrically tested before being integrated with the active component assembly described herein, which may improve yield and reduce production costs. Thus, the passive component assembly 1905 according to embodiments of the present invention may be configured to provide a modular approach to achieving an RF transistor amplifier with desired performance characteristics.

[0264] The AMSPM and AMBPM configurations described herein may also include variations of the active component assembly. Figures 20A, 20B, and 20C show various examples of active component assemblies 2005a, 2005b, and 2005c (collectively 2005) according to several embodiments of the present invention. As shown in Figure 20A, the exemplary active component assembly 2005a may include an active die 210 (e.g., a group III nitride or SiC-based semiconductor die). The gate terminal 222'', drain terminal 224'', and / or source terminal 226'', may be implemented by conductive pillar structures (e.g., copper pillars). In the example in Figure 20A, the conductive pillar structures 222'', 224'', and 226'', all protrude from the first surface or active surface 212 of the die 210, i.e., the “upper” or front surface 212 adjacent to the active channel 2 (e.g., the 2DEG layer). Therefore, Figure 20A shows a flip-chip configuration of the active die 210, with contacts 222'', 224'', and 226'', located on one side 212 of the die 210 (for example, facing "down" when connected to the circuit module 310'', and the growth substrate on the opposite side 214 (for example, facing "up" when connected to the circuit module 310'',). However, it will be understood that one or more of the gate terminal 222'', drain terminal 224'', and source terminal 226'', may protrude from the second surface or inert surface 214 of the die 210, or may be otherwise implemented on it.

[0265] Figure 20B shows an exemplary active component assembly configuration 2005b in which a die 210 including conductive pillar structures 222'', 224'', 226'', is electrically connected to a coupling element 270. The coupling element 270 includes a gate connection pad 272, a drain connection pad 274, a source connection pad 276, and a conductive pattern 273. The conductive pattern 273 electrically connects the gate connection pad 272 and the drain connection pad 274, as well as the source connection pad 276, to the gate terminal 222'', the drain terminal 224'', and the source terminal 226'', of the die 210 (which may be implemented by the conductive pillar structures as mentioned above). An encapsulation structure 277 provides a package containing the die 210 and the coupling element 270. For example, the die 210, the conductive pillar structures 222'', 224'', 226'', and the coupling element 270 may be implemented within a redistribution layer (RDL) package. The encapsulation material 277 may be formed from a plastic or a plastic polymer compound, but the present invention is not limited thereto. In some embodiments, the encapsulation material 277 may include a polymer having a filler. In the example shown in Figure 20B, the connection pads 272, 274, 276 and the conductive pattern 273 are arranged in a fan-out configuration to increase the isolation of the connection from the respective source, gate, and drain terminals, but it will be understood that other configurations (e.g., a fan-in configuration) may be implemented in a similar manner.

[0266] Figure 20C shows an exemplary active component assembly configuration 2005c in which conductive pillar structures 222'', 224'', and 226'', protrude from the first surface or active surface 212 of the die 210, and the second surface or inert surface 214 of the die 210 is mounted on a thermally conductive substrate 410 (such as a metal slug, lead frame, flange, or other heat sink). The thermally conductive substrate 410 can provide improved heat dissipation from the amplifier package of heat generated by the die 210.

[0267] In any of the exemplary active component assemblies 2005a, 2005b, and 2005c, the die 210 may be mounted in a flip-chip configuration on the first surface 312 (in the case of an AMSPM configuration) or the second surface 314 (in the case of an AMBPM configuration) of the interconnection structure 310'', i.e., the gate terminal 222'', the drain terminal 224'', and the source terminal 226'' face the surface 312 or 314 of the interconnection structure 310''. In the example in Figure 20B, the coupling element 270 may be provided between the first surface 212 of the die and the interconnection structure 310''. Also, although specific examples are shown in Figures 20A to 20C, elements of one or more exemplary active component assemblies 2005a, 2005b, and 2005c may be combined in some embodiments. For example, the inert surface 214 of the die 210 may be exposed by the encapsulation structure 277 in the active component assembly 2005b in Figure 20B, or it may be mounted on the thermally conductive substrate 410 in Figure 20C.

[0268] Further embodiments of the present invention are described below with reference to various combinations of active component assemblies (e.g., 2005a, 2005b, 2005c) and passive component assemblies (e.g., 1905a, 1905b, 1905c) mounted on the first face 312 or the second face 314 of the passive component assembly. These embodiments are provided as examples, not limitations, and it will be understood that any configuration of the passive component assembly 1905 and the active component assembly 2005 falls within the scope of the present invention.

[0269] Figure 17 is a schematic cross-sectional view of a semiconductor package 1700 for an RF transistor amplifier according to several embodiments of the present invention. In particular, Figure 17 shows an exemplary package 1700 including an active component assembly 2005 coupled to a passive component assembly 1905 in an AMSPM configuration, in which the die 210 is located on the surface 312 of an interconnect structure or circuit module 310'' adjacent to one or more passive electrical components 1750 on the same surface 312. The description of Figure 17 will focus on elements of an RF transistor amplifier that may differ from those described in detail above.

[0270] As shown in Figure 17, an active component assembly 2005 (e.g., active component assembly 2005b) is provided on the passive component assembly 1905 such that the exposed interconnect pads 372, 374, and 376 on the first surface 312 of the circuit module 310'' are electrically coupled to the gate connection pad 272, drain connection pad 274, and source connection pad 276 of the coupling element 270, respectively (and thus electrically coupled to the gate terminal 222'', drain terminal 224'', and source terminal 226'' of the die 210, respectively). However, it will be understood that the coupling element 270 may be omitted in some active component assemblies (e.g., 2005a, 2005c), and the transistor die 210 may be mounted on the first surface 312 with the gate terminal 222'', drain terminal 224'', and source terminal 226'' directly coupled to the interconnect pads 322, 324, and 326. The passive electrical components 1750 are mounted adjacent to the active component assembly 2005 on their respective interconnection pads 372, 374, 376 on the surface 312 of the circuit module 310'' in a surface mount configuration (e.g., 1750a, 1750b), a wire bond configuration (e.g., 1750c'), and / or a flip-chip configuration.

[0271] In the exemplary AMSPM configuration of Figure 17, a thermally conductive substrate 410 (e.g., a metal slug, lead frame, or flange) is mounted on the surface of the active component assembly 2005 opposite to the passive component assembly 1905 (in particular, on the surface of the encapsulation material 277) to improve the thermal dissipation of heat generated by the die 210. The active component assembly 2005 and the passive component assembly 1905 may be encapsulated, at least partially, within an overmolding material 1740. The overmolding material 1740 may be formed from a plastic or plastic polymer compound that may be injection molded around the active component assembly 2005 and / or the passive component assembly 1905, thereby providing protection from the external environment.

[0272] In Figure 17, conductive leads 415A and 415B are mounted on the passive component assembly 1905 opposite the die 210 to provide an input RF signal to the die (e.g., to the gate terminal 222'' via passive components 1750a, 1750c' and coupling element 270) and an amplified output RF signal from the die 210 (e.g., from the drain terminal 224'' via coupling element 270 and passive components 1750c', 1750b). (In particular, they are mounted on the second surface 314 of the circuit module 310'' and electrically coupled to the exposed interconnect pads 322 and 324, respectively). However, in some embodiments, leads 415A and 415B may be mounted on the same surface as the die 210 (e.g., they may be mounted on the first surface 312 of the circuit module 310'' and protrude from the overmolding material 1740).

[0273] Figure 18 is a schematic cross-sectional view of a semiconductor package 1800 for an RF transistor amplifier according to several embodiments of the present invention. In particular, Figure 18 shows an exemplary package 1800 including an active component assembly 2005 coupled to a passive component assembly 1905 in an AMBPM configuration, in which the die 210 is on the opposite surface 314 of the interconnect structure or circuit module 310'', with the passive electrical component 1750 on the surface 312. The description of Figure 18 focuses on elements of the RF transistor amplifier that may differ from those described in detail above.

[0274] As shown in Figure 18, an active component assembly 2005 (e.g., active component assembly 2005a) is provided on a passive component assembly 1905 (e.g., passive component assembly 1905b) such that the exposed interconnect pads 322, 324, and 326 on the second surface 314 of the circuit module 310'' are electrically coupled to the gate terminal 222'', drain terminal 224'', and source terminal 226'' of the die 210, respectively. In particular, the transistor die 210 is mounted on the surface 314 of the circuit module 310'' with conductive pillars 222'', 224'', and 226'' (defining the gate terminal, drain terminal, and source terminal) directly coupled to the interconnect pads 322, 324, and 326, respectively. The passive electrical components 1750 are mounted on their respective interconnection pads 372, 374, and 376 on the opposite surface 312 of the circuit module 310'' in a surface mount configuration (e.g., 1750a, 1750b), a wire bond configuration (e.g., 1750c'), and / or a flip-chip configuration.

[0275] In the exemplary AMBPM configuration shown in Figure 18, a thermally conductive substrate 410 (e.g., a metal slug, lead frame, or flange) is mounted on the surface opposite to the passive component assembly 1905 of the active component assembly 2005 (e.g., using a thermal layer 240) to improve the thermal dissipation of heat generated by the die 210. In some embodiments, the thermal layer 240 may be omitted.

[0276] The active component assembly 2005 and the passive component assembly 1905 are sealed within the overmolded material 1740. Conductive leads 415A and 415B protrude from the overmolded material 1740 to provide an input RF signal to the die 210 (e.g., to the gate terminal 222'') and an amplified output RF signal from the die 210 (e.g., from the drain terminal 224''). In the example in Figure 18, leads 415A and 415B are mounted on the first surface 312 of the circuit module 310'', opposite the second surface 314 which has the die 210 on top, and are electrically coupled to exposed interconnect pads 372 and 374. However, in some embodiments, leads 415A and 415B may be mounted on the same surface as the die 210 (e.g., mounted on the second surface 314 of the circuit module 310'' and electrically coupled to exposed interconnect pads 322 and 324).

[0277] Figures 21A–24D show various exemplary packages for an RF transistor amplifier in an AMBPM configuration according to several embodiments of the present invention. Examples in Figures 21A–24B include package leads 415A and 415B that are electrically coupled to a passive component assembly module 1905 by wire bond connections 2115, and may also be referred to herein as wire bond-lead packages. Examples in Figures 24C and 24D show package leads 415A and 415B implemented on the laminate structure of the circuit module 310'' itself in an overmolded configuration and an open cavity configuration, respectively. Leads 415A and 415B are shown electrically connected to interconnect pads 372 and 374 on the upper surface 312 of the circuit module 310'', although one or more of leads 415A and 415B may, in some embodiments, also be connected to interconnect pads on the bottom surface 314. The explanation of Figures 21A to 24D focuses on elements of an RF transistor amplifier that may differ from those described in detail above.

[0278] In particular, Figure 21A is a schematic cross-sectional view of a semiconductor package 2100 including an active component assembly 2005 (e.g., active component assembly 2005a) provided on a passive component assembly 1905 (e.g., passive component assembly 1905b) in an AMBPM configuration, and Figure 21B is a schematic plan view thereof, wherein in the AMBPM configuration, the die 210 is on the surface 314 of the interconnect structure or circuit module 310'' opposite to the surface 312 having the passive electrical components 1750 on it. The exposed interconnect pads 322, 324, and 326 on the second surface 314 of the circuit module 310'' are electrically coupled to the gate terminal 222'', drain terminal 224'', and source terminal 226'' of the die 210, respectively. The passive electrical components 1750 are mounted on their respective interconnection pads 372, 374, and 376 on the opposite surface 312 of the circuit module 310'' in a surface mount configuration (e.g., 1750a, 1750b), a wire bond configuration (e.g., 1750c'), and / or a flip-chip configuration.

[0279] Referring to Figures 21A and 21B, a thermally conductive substrate 410 (e.g., a metal slug, lead frame, or flange) is mounted on the surface opposite to the passive component assembly 1905 of the active component assembly 2005 (e.g., using a thermal layer 240) to improve the thermal dissipation of heat generated by the die 210. In some embodiments, the thermal layer 240 may be omitted.

[0280] The active component assembly 2005 and the passive component assembly 1905 are sealed within the overmolded material 1740. As shown in Figure 21B, the passive component assembly 1905 includes one or more cavities 2140 (e.g., holes or openings 2140 in the circuit module 310''). The overmolded material 1740 may extend into the openings 2140 or otherwise be provided therein, thereby enhancing adhesion. Conductive leads 415A and 415B are electrically coupled to the exposed interconnect pads 372 and 374 of the circuit module 310'' by wire bonds 2115 and protrude from the overmolded material 1740 to provide input RF signals to the die 210 (e.g., to the gate terminal 222'') and amplified output RF signals from the die 210 (e.g., from the drain terminal 224'').

[0281] Figure 22 is a schematic cross-sectional view of a semiconductor package 2200 including an active component assembly 2005 (e.g., active component assembly 2005a) mounted on a passive component assembly 1905 (e.g., passive component assembly 1905b) in an AMBPM configuration, where the die 210 is on the surface 314 of the interconnect structure or circuit module 310'' opposite to the surface 312 having the passive electrical component 1750 on it. As shown in Figure 22, the passive electrical component 1750 is pre-assembled into an initial mold structure 2240, which is mounted on the surface 312 of the circuit module 310''. The mold structure 2240 is clearly distinguished from the overmolding material 1740, which is later formed to encapsulate the active component assembly 2005 and the passive component assembly 1905 within the package 2200 (e.g., on a thermally conductive substrate 410). Therefore, the surface 314 including the die 210 may not have a mold structure 2240. In some embodiments, the mold structure 2240 may be formed from a material that is harder or softer than the overmolding material 1740. The exemplary package 2200 in Figure 22 may include other components or may be similar in other ways to the wire bond-lead package 2100 in Figures 21A and 21B.

[0282] Figures 23A and 23B are schematic cross-sectional views of semiconductor packages 2300a and 2300b, which include an active component assembly 2005 (specifically, active component assemblies 2005a and 2005b, respectively) mounted on a passive component assembly 1905 (specifically, passive component assembly 1905b) in an AMBPM configuration, where the die 210 is on the surface 314 of the interconnect structure or circuit module 310'' opposite to the surface 312 having the passive electrical component 1750 on it. Packages 2300a and 2300b are implemented as open-air or open-cavity packages.

[0283] As shown in Figures 23A and 23B, packages 2300a and 2300b may include a carrier substrate (e.g., a thermally conductive substrate 410), a side wall 2320, and a lid 2325. The substrate 410, the side wall 2320, and the lid 2325 may define an internal cavity 2330. The active component assembly 2005 and the passive component assembly 1905 may be located inside the internal cavity 2330 and may be enclosed within the side wall 2320 and the lid 2325, thereby protecting them. The side wall 2320 may provide mechanical support for leads 415A, 415B that are electrically connected to exposed interconnect pads 372, 374 by wire bond connections 2115. In some embodiments, the passive component assembly 1905 may include a passive electrical component 1750 that is pre-assembled into a molded structure 2240 on the surface 312 of the circuit module 310''. Therefore, packages 2300a and 2300b may include characteristics of both molded packages and open cavity packages. The exemplary packages 2300a and 2300b in Figures 23A and 23B may include other components or may be similar in other ways to the wire-bonded-lead packages 2100 and 2200 described herein.

[0284] Figure 24A is a schematic cross-sectional view of a semiconductor package 2400 including an active component assembly 2005 (e.g., active component assembly 2005a) provided on a passive component assembly 1905 (e.g., passive component assembly 1905b) in an AMBPM configuration, and Figure 24B is a schematic plan view thereof, wherein in the AMBPM configuration, the die 210 is on the surface 314 of the interconnect structure or circuit module 310'' opposite to the surface 312 having the passive electrical component 1750 on it. In some embodiments, the passive component assembly 1905 may include the passive electrical component 1750 pre-assembled in a mold structure 2240 on the first surface 312 of the circuit module 310''.

[0285] The package 2400 further includes one or more mechanical support structures 2000s on the second surface 314 of the circuit module 310'' adjacent to the die 210. The mechanical support structures 2000s (also referred herein as standoff assemblies 2000s) extend between the substrate (e.g., the thermally conductive flange 410) and the second surface 314 of the circuit module 310''. The mechanical support structures 2000s may extend along or adjacent to one or more faces of the die 210 and may have a thickness substantially similar to that of the active component assembly 2005, and can provide improved mechanical support for the passive component assembly 1905 laminated thereon. In some embodiments, the mechanical support structures 2000s may be formed from one or more materials that can improve thermal conductivity to conduct heat outward from the active component assembly 2005 and / or the passive component assembly 1905 toward the thermally conductive substrate 410. The overmolded material 1740 is subsequently formed to encapsulate the active component assembly 2005 and the passive component assembly 1905 within the package 2400.

[0286] Figure 24C is a schematic cross-sectional view of a semiconductor package 2400' in an AMBPM configuration, which includes an active component assembly 2005 (e.g., active component assembly 2005a) mounted on a passive component assembly 1905 (e.g., passive component assembly 1905c), where in the AMBPM configuration, the die 210 is on the surface 314 of the interconnect structure or circuit module 310'' opposite to the surface 312 having the passive electrical components 1750 on it. Package 2400' is similar to package 2400 (including mechanical support structures 2000s between the flange 410 and the second surface 314 of the circuit module 310''), except that the package leads 415A and 415B are implemented on the circuit module 310'' itself (rather than being coupled to the passive component assembly module 1905 by wire bond connections).

[0287] In Figures 24A to 24C, an overmolded package 2400 including an overmolded material 1740 is shown as an example, but packages 2400, 2400' may be implemented as open-air or open-cavity packages in some embodiments, as shown in Figure 24D. In particular, Figure 24D is a schematic cross-sectional view of an open-cavity package 2400'' in which package leads 415A and 415B are implemented on a circuit module 310'' (rather than being coupled to a passive component assembly module 1905 by wire bond connections). The open-cavity package 2400'' is similar in other embodiments to package 2400' in Figure 24C (including mechanical support structures 2000s between the flange 410 and the second surface 314 of the circuit module 310''), but the active component assembly 2005 and the passive component assembly 1905 are located inside the internal cavity 2330 and are enclosed and protected within the side walls 2320 and the lid 2325.

[0288] The exemplary packages 2400, 2400', and 2400'' in Figures 24A to 24D may include other components or may be otherwise similar to the wire bond-lead packages 2100, 2200, 2300a, and 2300b described herein.

[0289] Figures 25A, 25B, and 25C illustrate various exemplary packages for an RF transistor amplifier in an AMBPM configuration according to several embodiments of the present invention. In particular, Figures 25A, 25B, and 25C are schematic cross-sectional views of semiconductor packages 2500a, 2500b, and 2500c, which include an active component assembly 2005 (in particular, active component assembly 2005a in Figures 25A and 25B, and active component assembly 2005b in Figure 25C) provided on a passive component assembly 1905 (in particular, passive component assembly 1905b) in an AMBPM configuration, where the die 210 is on a surface 314 of the interconnect structure or circuit module 310'' opposite to the surface 312 having the passive electrical component 1750 on it. The description of Figures 25A to 25C will focus on elements of the RF transistor amplifier that may differ from those described in detail above.

[0290] Examples in Figures 25A to 25C include package leads 415A and 415B that are directly mounted on the passive component assembly 1905, i.e., without wire bond connections. For example, Figure 25A shows an exemplary package 2500a in which leads 415A and 415B are mounted adjacent to the active component assembly 2005 on the second surface 314 of the circuit module 310'' of the passive component assembly 1905. Figure 25B shows an exemplary package 2500b in which leads 415A and 415B are mounted adjacent to the passive component assembly 1750 on the first surface 312 of the circuit module 310'' of the passive component assembly 1905. Figure 25C shows an exemplary package 2500c in which leads 415A and 415B are mounted adjacent to the active component assembly 2005, including the die 210 and coupling element 270 within the RDL package, on the second surface 314 of the circuit module 310''.

[0291] In Figures 25A to 25C, the passive component assembly 1905 includes a passive electrical component 1750 that is pre-assembled into a molded structure 2240 on the first surface 312 of the circuit module 310'', although it will be understood that the molded structure 2240 may be omitted in some embodiments. Similarly, packages 2500a, 2500b, and 2500c are shown as overmolded packages including the overmolding material 1740 as an example, but may be implemented as open-air or open-cavity packages in some embodiments. The exemplary packages 2500a, 2500b, and 2500c in Figures 25A to 25C may include other components or may be similar in other ways to the package 1800 described herein.

[0292] More generally, embodiments of the present invention may include, and are not limited to, the examples specifically shown in the figures, any combination of the active component assemblies shown in Figures 20A to 20C and the passive component assemblies shown in Figures 19A to 19C. Such combinations of active and passive component assemblies may be used to provide various electronic functions to the RF transistor amplifier 200. For example, circuit elements 1750a, 1750b, and 1750c may implement impedances (including, for example, resistive, inductive, and capacitive elements) which may be used for impedance matching and / or harmonic termination. As mentioned above, circuit elements 1750a, 1750b, and 1750c may be, or include, surface mount devices, IPDs, and / or other passive electrical components which may implement harmonic and / or input / output impedance matching elements.

[0293] Figures 26A, 26B, and 26C are schematic schematics illustrating one of the various circuit topologies that can be implemented by combinations of active and passive component assemblies according to several embodiments of the present invention. For example, circuit elements 1750a and 1750c may be configured to provide input impedance matching functionality. Due to the coupling between input lead 415A and transistor die 210, circuit elements 1750a and 1750c may be able to influence and / or modulate the signal supplied to the gate terminal of transistor die 210. Similarly, circuit elements 1750b and 1750c may be configured to provide output impedance matching functionality. Due to the coupling between output lead 415B and transistor die 210, circuit elements 1750b and 1750c may be able to influence and / or modulate the signal supplied from the drain terminal of transistor die 210. More generally, the circuit element 1750 may be configured to provide an input impedance matching circuit, an output impedance matching circuit, and / or a harmonic termination circuit for a packaged transistor amplifier as described herein.

[0294] The passive component assembly 1905 can facilitate the assembly of RF transistor amplifier packages with different characteristics and / or additional functions, such as impedance matching and / or harmonic termination. For example, by providing the passive component assembly 1905 including a circuit module 310'' having exposed interconnect pads, one or more of the circuit elements 1750a, 1750b, and 1750c can be replaced and / or configured to provide impedance characteristics for a particular application. That is, the transistor package may be designed and / or reconfigured to provide different input / output matching and / or harmonic termination characteristics using the same circuit module 310'' on which different arrangement configurations and / or combinations of passive electronic components 1750 on the exposed interconnect pads 322, 324, 326, 372, 374, and 376 are implemented. Therefore, different functions and / or capabilities may be coupled to the RF transistor amplifier 200 of the active component assembly 2005 simply by using different passive component assemblies 1905, and / or by separately implementing different combinations and / or arrangement configurations of the passive electrical components 1750 in the passive component assembly 1905.

[0295] In further embodiments, an interconnect structure and active and / or passive electrical components on one or more of its surfaces (e.g., a combination of the active component assembly 2005 and the passive component assembly 1905 described above) may collectively implement a flip-chip module or component assembly (e.g., 2905 as described herein). In a flip-chip component assembly, an active transistor die and any conductive structure (e.g., pillars or coupling elements thereon) may be coupled to an interconnect structure (e.g., a PCB or other substrate having a conductive interconnect pattern) by flip-chip connections, i.e., with the gate terminal, drain terminal, and source terminal of the die facing the surface of the interconnect structure. This provides the possibility of adding and connecting matching components (e.g., baseband termination capacitors, matching networks, etc.) in close proximity to the transistor die. The flip-chip modules or component assemblies described herein may be electrically tested and screened before being integrated with the rest of the packaging, which may improve yield and reduce costs. The flip-chip module may be assembled within a high-power package that includes a thermal conductive flange (e.g., a copper-based or other solid metal coin) to allow heat to dissipate outward from the device package. Depending on the application, the thermal conductive flange may be soldered or bonded to a customer heatsink.

[0296] In contrast, some conventional high-power application forms may mount one or more transistor dies to a heatsink, typically with the source facing downwards, using chip and wire connections to implement matched networks, terminations, etc. Also, some conventional flip-chip embodiments may have power limitations due to thermal management issues (as heat may need to be dissipated through the PCB to which the transistor die is mounted), but embodiments of the present invention may reorient the flip-chip module for assembly into a high-power package by positioning the rear surface of the transistor die to face a thermally conductive flange (i.e., by rotating the flip-chip component assembly 180 degrees) and by mounting it "upside down" to the conductive flange using a thermally and electrically conductive adhesive (e.g., solder, conductive epoxy, or silver and copper nanoparticle material).

[0297] In particular, a transistor device package according to a further embodiment of the present invention includes a component assembly that is rotated (or "inverted") by 180 degrees so that the rear surface 214 of the transistor die 210 is attached to a thermally conductive flange 410 by a conductive adhesive 240'' and integrated within the package. The component assembly includes an interconnect structure 310'', a transistor die, and one or more passive electrical components 1750. The front surface 212 of the transistor die 210 includes a gate terminal 222'', a drain terminal 224'', and a source terminal 226'' which are attached to the first surface 312 of the interconnect structure 310'' (i.e., in a flip-chip configuration). The passive electrical components may be on the first surface 312 and / or the opposite second surface 314 of the interconnect structure 310'' and may be electrically coupled to the gate terminal 222'', the drain terminal 224'', and / or the source terminal 226'' by the interconnect structure 310''. For example, the interconnection structure 310'' may be a multilayer structure including conductive patterns (including conductive pads and traces) and / or vias that electrically couple one or more passive electrical components 1750 to the gate terminal 222'', drain terminal 224'', and / or source terminal 226'' of a transistor die on the first surface 312 of the interconnection structure 310''. The passive electrical components 1750 may include surface mount devices (SMDs) and / or integrated passive devices (IPDs) and may be mounted on their respective conductive patterns (e.g., interconnection pads 372, 374, 376) on one or more surfaces 312, 314 of the interconnection structure 310'' in a surface mount configuration, a wire bond configuration, and / or a flip-chip configuration.

[0298] In addition, as shown in more detail in Figures 27A to 34D, the transistor device package includes, for example, a pattern 240p of conductive adhesive 240'' (e.g., droplets or other distributed portions of conductive adhesive material) provided on the interconnect structure 310'' adjacent to the transistor die 210 on the first surface 312. The conductive adhesive pattern 240p mechanically couples the interconnect structure 310'' to one or more components of the transistor device package (e.g., conductive leads 415A, 415B and / or thermal conductive flange 410). Alternatively, one or more of the conductive adhesive patterns 240p may electrically couple the gate terminal, drain terminal, or source terminal of the transistor die 210 to one or more components of the transistor device package (e.g., conductive leads 415A, 415B and / or thermal conductive flange 410) to provide input, output, or ground signal paths for the transistor device package. In addition, as mentioned above, the conductive adhesive 240'' on the rear surface 214 of the transistor die 210 thermally bonds the die to the thermally conductive flange 410. Thus, the conductive adhesive pattern 240p described herein may be used to integrate a component assembly into a desired transistor device package form factor and may provide (i) mechanical bonding, (ii) thermal bonding, and / or (iii) electrical bonding between the components of the package.

[0299] Figures 27A and 27B are schematic cross-sectional views of transistor device packages 2700a, 2700b, including a flip-chip component assembly 2905 integrated into a high-power package type according to several embodiments of the present invention. In particular, Figures 27A and 27B show a double-sided component assembly 2905 in which the passive electrical component 1750 is located on the opposing first surface 312 and second surface 314 of the interconnect structure 310'', and the transistor die 210 is mounted in a flip-chip configuration on one of the opposing first surface 312 and second surface 314. The component assembly 2905 (also referred to as the flip-chip module) is mounted "upside down" (i.e., so that the rear surface 214 of the transistor die 210 is attached to the surface of the flange 410) on the thermally conductive flange 410 by a conductive adhesive 240'' such as a silver (Ag) nanoparticle sintered material (also referred to herein as silver nano), conductive epoxy, or solder material. Therefore, a heat dissipation path is provided at the bottom of packages 2700a and 2700b through the flange 410, while input and output signal paths are provided by conductive leads 415A and 415B protruding from the package housing 278.

[0300] Furthermore, as shown in Figures 27A and 27B, each pattern 240p of the conductive adhesive 240'' may attach and electrically connect the conductive leads 415A, 415B to a conductive pattern on the first surface 312 of the interconnect structure 310'' (e.g., exposed interconnect pads 322 / 382, 324 / 384, 326) which is electrically coupled to the gate 222'' and drain terminals 224'' (as shown in Figures 27A and 27B) and / or source terminal 226'' (as shown in Figure 29A) of the transistor die, in order to provide input RF signals, RF output signals, and / or ground signals to and from the transistor die 210. Thus, the conductive adhesive pattern 240p may provide at least a portion of the input, output, and / or ground signal paths between the conductive leads 415A, 415B and the gate, drain, and / or source terminals of the transistor die. It will be understood that in some embodiments, leads 415A and 415B may be mounted on the surface opposite to die 210 (for example, on the second surface 314).

[0301] Additionally or alternatively, each pattern 240p of the conductive adhesive 240'' may attach and electrically connect the thermal conductive flange 410 to the first surface 312 of the interconnect structure 310'', in particular to a conductive pattern on the first surface 312 that is electrically coupled to the source terminal 226'' of the transistor die. For example, the thermal conductive flange 410 may include one or more conductive pillar portions 2410 protruding from its surface, which may be attached to the first surface 312 of the interconnect structure 310'' by each conductive adhesive pattern 240p (as shown in Figures 28 and 29B) and electrically coupled to a conductive pad thereon. Thus, the conductive adhesive pattern 240p may provide at least a portion of a ground signal path between the thermal conductive flange 410 and the source terminal 226'' of the transistor die. In some embodiments, the electrical connections between the transistor die 210, the passive electrical components, the input and output lead terminals, and the thermally conductive flange 410 may be implemented such that there are no wire bond connections in packages 2700a and 2700b.

[0302] The passive electrical components 1750 may be provided on the first surface 312 of the interconnect structure 310'' (i.e., the surface adjacent to the transistor die 210), on the second surface 314 of the interconnect structure 310'' (i.e., the surface opposite to the surface on which the transistor die 210 is located), or on both the first surface 312 and the second surface 314 of the interconnect structure 310''. As shown in Figure 27A, in some embodiments, one or more of the passive electrical components 1750 may be configured to be located on the portion of the second surface 314 of the interconnect structure 310'' that overlaps with the transistor die 210 on the first surface 312. Such a configuration can provide passive electrical components that are closer to the transistor die 210, thereby reducing and / or minimizing the length of the electrical connection between them. For example, by placing the transistor die 210 and its baseband termination and / or matching circuit on opposite surfaces of the interconnect structure 310'', extremely low impedance (and low impedance fluctuation) can be provided between them, which may be important for achieving and maintaining desired performance at higher frequencies.

[0303] In Figures 27A and 27B, an encapsulation material (such as an overmolding material 1740) is provided on the interconnect structure 310'', the transistor die, and the thermal conductive flange 410 to form the molded structure 2240. Conductive leads 415A and 415B may protrude outside the molded structure 2240, beyond the periphery of the package housing 278. In Figure 27A, the conductive leads 415A and 415B are substantially flat structures spaced from the thermal conductive flange 410 by a uniform distance inside and outside the periphery of the package housing 278, as defined by the molded structure 2240.

[0304] In contrast, in Figure 27B, the conductive leads 415A, 415B include portions that are bent inward into the package housing 278 (e.g., toward or outward from the first surface 312 of the interconnect structure) to accommodate differences in transistor die heights while exiting package 2700b at a height or level H corresponding to other standardized packages, or to otherwise meet customer requirements. In particular, the conductive leads 415A, 415B (e.g., input and / or output RF leads) may include first portions 415Ai, 415Bi that overlap the surface of flange 410 and are separated therefrom by a first spacing or gap G1, and second portions 415Ae, 415Be that extend beyond the surface of flange 410 and are separated or spaced apart from the plane of the surface of flange 410 by a second spacing or gap G2 different from the first spacing or gap G1.

[0305] Figures 28A and 28B are flowcharts illustrating exemplary operations for fabricating transistor device packages according to several embodiments. In particular, Figures 28A and 28B provide a component assembly 2905 (including an interconnect structure 310'', a transistor die, and one or more passive electrical components 1750 electrically coupled to the gate terminal 222'' and / or drain terminal 224'' of the transistor die 210 by the interconnect structure) and show a method for attaching the rear surface 214 of the transistor die 210 to a thermal conductive flange 410 by conductive adhesive 240'' as shown in Figure 27A or Figure 27B. However, it will be understood that the operations shown in Figures 28A and 28B are not limited to the fabrication of packages 2700a and 2700b in Figure 27A or Figure 27B.

[0306] In block 2805, as shown in Figures 28A and 28B, solder or other conductive bonding material is provided on the first surface 312 of the interconnect structure 310'', for example, using a printing process. The interconnect structure 310'' may be a multilayer structure including conductive pads, traces, and / or vias extending on or between the opposing first surface 312 and second surface 314. In block 2810, the transistor die and passive electrical component 1750 are attached to a conductive pattern on the first surface 312 of the interconnect structure 310'' by bonding material (for example, using a solder reflow process), and are electrically connected, which is also referred to as the implementation of the interconnect structure 310''. The transistor die is attached to the interconnect structure 310'' in a flip-chip manner, i.e., with the gate terminal, drain terminal, and source terminal facing the first surface 312 and electrically connected to the conductive pattern thereon. The passive electrical components 1750 (such as SMDs and / or IPDs) are similarly mounted on the first surface 312 and electrically connected to the conductive pattern, so that the passive electrical components 1750 are electrically coupled on their first surface 312 to the gate terminal 222'', drain terminal 224'', and / or source terminal 226'' of the transistor die.

[0307] In block 2815, the implemented interconnect structure 310'' is pieced using, for example, a sawing or dicing process to provide a plurality of individual component assemblies 2905. Each component assembly 2905 may include the interconnect structure 310'', one or more transistor dies, and one or more passive electrical components 1750 electrically connected by the interconnect structure 310'' to the gate terminal 222'', drain terminal 224'', and / or source terminal 226'' of the transistor die 210. The individual component assemblies 2905 may be electrically tested before performing the rest of the packaging operation (and defective component assemblies 2905 may be repaired or discarded), thereby improving the yield of the package device which may contain multiple such component assemblies.

[0308] In block 2820, conductive adhesive 240'' (e.g., solder or silver nanoparticles) may be distributed to provide each pattern 240p of conductive adhesive 240'' on one or more surfaces of the thermal conductive flange 410 (e.g., Cu coins) of packages 2700a, 2700b. The conductive adhesive patterns 240p may also be distributed on the surface of one or more conductive leads 415A, 415B of packages 2700a, 2700b. In some embodiments, one or more conductive leads 415A, 415B may be bent to accommodate differences in transistor die heights as they exit the package at a height or level corresponding to other standardized packages. In some embodiments, the thermal conductive flange 410 may include one or more conductive pillar portions (e.g., extruded Cu pillars) protruding from its surface, and the conductive adhesive patterns 240p may be distributed on the surface of each of the protruding conductive pillars.

[0309] In block 2825, the component assembly 2905 is rotated (or "inverted") so that the first surface 312 of the interconnect structure 310'' (including the transistor die 210 and the passive electrical components thereon) faces the thermal conductive flange 410, and the component assembly 2905 is attached to the thermal conductive flange 410 and conductive leads 415A, 415B by respective patterns 240p of conductive adhesive 240'' (e.g., by sintering or other mounting processes). In particular, the rear surfaces 214 of one or more transistor dies are attached to the surface of the thermal conductive flange 410 by patterns 240p of conductive adhesive 240'', and the conductive leads 415A, 415B are attached to the first surface 312 of the interconnect structure 310'' by patterns 240p of conductive adhesive 240''. The conductive leads 415A, 415B may be held in place or supported by one or more support members or other support tools during the mounting process. For example, the support member may be a retractable support member that extends between one or more conductive leads 415A, 415B and the thermal conductive flange 410 to support one or more conductive leads 415A, 415B during the mounting process, and can be retracted after the mounting process.

[0310] Thereafter, the conductive leads 415A, 415B may be mechanically attached to the interconnect structure 310'' by conductive adhesive patterns 240p and electrically connected, so that one or more of the conductive adhesive patterns 240p provide input, output, and / or ground signal paths for the transistor device packages 2700a, 2700b. For example, the conductive leads 415A, 415B may include input and output leads for the packages 2700a, 2700b, and may be mechanically attached to the first surface 312 of the interconnect structure 310'' and electrically connected by each pattern 240p of the conductive adhesive 240'' to conductive pads on the first surface 312 (coupled to the gate 222'' and drain terminal 224'' of the transistor die 210) to provide input and output signal paths. In some embodiments (for example, as shown in Figure 29A), the conductive leads 415A, 415B may further include ground leads for packages 2700a, 2700b, which may be mechanically attached to the first surface 312 of the interconnect structure 310'' and electrically connected to conductive pads on the first surface 312 (coupled to the source terminals 226'' of the transistor die 210) by each pattern 240p of the conductive adhesive 240'' to provide a ground signal path. In other embodiments (for example, as shown in Figure 29B), one or more conductive pillar structures 2410 protruding from the surface of the thermal conductive flange 410 may be mechanically attached to the first surface 312 of the interconnect structure 310'' and electrically connected to conductive pads on the first surface 312 (coupled to the source terminals 226'' of the transistor die 210) by each pattern 240p of the conductive adhesive 240'' to provide a ground signal path.

[0311] As shown in (optional) block 2830, solder or other conductive bonding material may be provided on the opposite second surface 314 of the interconnect structure 310'', and one or more passive electrical components 1750 may be mounted on the second surface 314 and electrically connected to a conductive pattern, so that the passive electrical components 1750 are electrically coupled to the gate terminal 222'', drain terminal 224'', and / or source terminal 226'' of the transistor die on its first surface 312. In some embodiments, the passive electrical components may be on the portion of the second surface 314 that overlaps with the transistor die 210 on the first surface 312, reducing or minimizing the distance or length of the electrical connection between them. In some embodiments, the first surface 312 of the interconnect structure 310'' may not have any passive electrical components 1750, so that the first surface 312 includes only one or more transistor dies on it, and the second surface 314 includes only one or more passive components on it. That is, the component assembly 2905 may be a passive component assembly (e.g., 1905) as described herein, or it may be assembled with an active component assembly (e.g., 2005) as described herein for integration into the transistor device packages 2700a, 2700b. In some embodiments, as shown in (optional) block 2835, one or more wire bonds 282 may be attached (e.g., to the second surface 314) to provide additional electrical connections. In other embodiments, the packages 2700a, 2700b may not have wire bond connections.

[0312] In block 2840, the package housing 278 is formed on the component assembly 2905 to complete the transistor device packages 2700a, 2700b. In particular, encapsulation material 625 (such as overmolding material 1740) is formed on the surfaces of the interconnect structure 310'', the transistor die 210, and the thermal conductive flange 410 to form the mold structure 2240. In some embodiments, the overmolding material 1740 may be a plastic or plastic polymer compound highly filled with silica or other inorganic material. The mold structure 2240 may provide the package housing 278 for environmental protection of the component assembly 2905. Conductive leads 415A, 415B may protrude beyond or outside the periphery of the package housing 278 defined by the mold structure 2240, and the bottom surface of the thermal conductive flange 410 may be exposed by the mold structure 2240 to provide a heat dissipation path to the bottom of the packages 2700a, 2700b. Alternatively, the lid member 2325 may be provided as a package housing 278 instead of (or in addition to) the encapsulating material. In an embodiment in which the flange 410 includes one or more extruded pillar portions that provide conductive grounding pins, as shown in block 2840, the bottom surface of the flange 410 may include a recess 410r on the bottom surface at a location corresponding to the location of the extruded pillar portion 2410 on the opposite surface of the flange 410.

[0313] Figures 29A and 29B are schematic plan views illustrating exemplary embodiments of ground signal paths in a transistor device package according to several embodiments of the present invention. Figure 29A shows an embodiment of a ground signal path using ground-signal-ground (GSG) leads as conductive leads 415A and 415B. In particular, each input lead 415A includes an input conductor 415Ain between two ground conductors 415Ag, which are attached by conductive adhesive pattern 240p to their respective conductive patterns on the first surface 312 or the second surface 314 of the interconnect structure 310'' and electrically connected, with the central conductive pattern electrically coupled to the gate terminal 222'' of the transistor die. Similarly, each output lead 415B includes an output conductor 415Bout between two ground conductors 415Bg, which are attached by conductive adhesive pattern 240p to their respective conductive patterns on the first surface 312 or the second surface 314 of the interconnect structure 310'' and electrically connected, with the central conductive pattern electrically coupled to the drain terminal 224'' of the transistor die. Figure 29B shows an embodiment of a grounding signal path that uses a grounding conductive pad 386' on the first surface 312 of the interconnect structure 310'' for mounting and electrical connection to a conductive pillar structure (as described later with reference to Figure 30B) or other conductive support structure using conductive adhesive 240p, in order to provide an electrical grounding signal between the source terminal 226'' of the transistor die 210 and the thermal conductive flange 410.

[0314] Figures 30A and 30B are schematic cross-sectional views of transistor device packages 3000a and 3000b, which include a flip-chip component assembly 2905 integrated into a high-power package type and having package leads provided by an interconnect structure 310'', according to several embodiments of the present invention. In particular, Figures 30A and 30B show a double-sided component assembly 2905 (with passive electrical components 1750 on opposing first and second surfaces 312 and 314 of the interconnect structure 310'', and a transistor die 210 mounted in a flip-chip configuration on one of the opposing first and second surfaces 312 and 314), and conductive leads 415A and 415B integrated into portions of the interconnect structure 310'' that protrude outward from the periphery of the package housing 278. Similar to packages 2700a and 2700b in Figures 27A and 27B, the interconnect structure 310'' is mounted "upside down" on the thermally conductive flange 410, and the rear surface 214 of the transistor die 210 is attached to the surface of the flange 410 by a conductive adhesive 240'' (e.g., Ag or Cu nano, conductive epoxy or solder). Thus, a heat dissipation path is provided at the bottom of the package through the flange 410, while input and output signal paths are provided by conductive leads 415A and 415B integrated within the portion of the interconnect structure 310'' that protrudes from the package housing 278. Figure 30A shows an exemplary package 3000a including components on both sides of an interconnect structure 310'' sealed within a molded structure 2240 as a package housing 278, while Figure 30B shows an exemplary package 3000b including components on one surface (e.g., 312) sealed within an overmolded material 1740, with components on the other surface (e.g., 314) covered by a lid member 2325. Thus, package 3000b may include characteristics of both a molded package and an open cavity package.

[0315] Furthermore, as shown in Figures 30A and 30B, one or more support structures 2000s extend from the thermally conductive flange 410 to the first surface 312 of the interconnect structure 310'' and are attached to one or more areas of the first surface 312 of the interconnect structure 310'' by respective patterns 240p of the conductive adhesive 240''. In some embodiments, the support structures 2410 may include conductive components or, in other manner, may be formed from a conductive material. For example, one or more of such conductive support structures 2410 may be electrically connected to the source terminal 226'' of the transistor die 210 by the interconnect structure 310'' and thus may function as a grounding pin that electrically connects the source terminal 226'' of the transistor die 210 to the thermally conductive flange 410.

[0316] In some embodiments, the support structure may include conductive pillar portions of the thermally conductive flange 410 projecting from the surface of the flange 410 to the first surface 312 of the interconnection structure 310''. For example, as shown in Figure 30B, the conductive pillar structure 2410 may be extruded from the thermally conductive flange 410 or, in other ways, may be integral with the thermally conductive flange 410. In particular, an extrusion process may be used to form the conductive pillar structure 2410 as a projection extending from the surface of the thermally conductive flange 410 (e.g., a Cu pillar extruded from the surface of the Cu flange 410), leaving a recess 410r within the surface of the flange 410 at a position corresponding to the position of the extruded conductive pillar portion 2410 on the opposite surface of the flange 410. Each pattern 240p of the conductive adhesive 240'' may attach the conductive pillar structure 2410 of the flange 410 to the conductive pattern on the first surface 312 of the interconnect structure 310'' and electrically connect them, so that the conductive adhesive pattern 240p may provide at least a portion of an electrical ground signal path between the transistor die 210 on the first surface 312 of the interconnect structure 310'' and the flange 410.

[0317] Figures 31A and 31B are flowcharts illustrating exemplary operations for fabricating transistor device packages according to several embodiments. In particular, Figures 31A and 31B provide a component assembly 2905 (including an interconnect structure 310'', a transistor die, and one or more passive electrical components 1750 electrically coupled to the gate terminal 222'' and / or drain terminal 224'' of the transistor die 210 by the interconnect structure) and show a method for attaching the rear surface 214 of the transistor die 210 to a thermally conductive flange 410 by conductive adhesive 240'', as shown in Figures 30A and 30B. However, it will be understood that the operations shown in Figures 31A and 31B are not limited to the fabrication of packages 3000a and 3000b in Figures 30A and 30B.

[0318] In block 310''5, as shown in Figures 31A and 31B, solder or other conductive bonding material is provided on the first surface 312 of the interconnect structure 310'', for example, using a printing process. In block 3110, the interconnect structure 310'' is implemented by attaching the transistor die and passive electrical component 1750 to a conductive pattern on the first surface 312 of the interconnect structure 310'' using bonding material (for example, using a solder reflow process) and electrically connecting them. The transistor die is attached to the interconnect structure 310'' in a flip-chip manner, and the passive electrical component 1750 is similarly attached to the first surface 312 and electrically connected to the conductive pattern, so that the passive electrical component 1750 is electrically coupled to the gate terminal 222'', drain terminal 224'', and / or source terminal 226'' of the transistor die on its first surface 312. In block 3115, to provide a plurality of individual component assemblies 2905, the implemented interconnect structure 310'' may be pieced using, for example, a sawing or dicing process, and the plurality of individual component assemblies 2905 may be electrically tested before performing the remaining packaging operations.

[0319] In block 3120, a conductive adhesive 240'' (e.g., solder or silver nanoparticles) may be distributed in each component assembly 2905 to provide each pattern 240p of the conductive adhesive 240'' on each region of the first surface 312 of the interconnect structure 310'' and on the rear surface 214 of the transistor die 210. A thermally conductive flange 410 is also provided for each component assembly 2905. The flange 410 includes a conductive support structure 2410 (e.g., a conductive pillar structure 2410) protruding from its surface. The conductive pillar structure 2410 may be extruded from the thermally conductive flange 410 or may otherwise be integral with the thermally conductive flange 410.

[0320] In block 3125, each component assembly 2905 is attached to its respective thermal conductive flange 410 by conductive adhesive 240'' (e.g., by sintering or other mounting process). In particular, the rear surfaces 214 of one or more transistor dies are attached to the surface of the thermal conductive flange 410 by conductive adhesive 240'' on them, and the conductive pillar structures 2410 protruding from the thermal conductive flange 410 are attached to the respective regions of the first surface 312 of the interconnect structure 310'' by conductive adhesive patterns 240p on them. Each pattern 240p of the conductive adhesive 240'' may provide a ground signal path for the transistor device packages 3000a, 3000b. For example, conductive pillar portions protruding from the surface of the thermal conductive flange 410 may be mechanically attached to the first surface 312 of the interconnection structure 310'' and electrically connected to conductive pads on the first surface 312 (coupled to the source terminal 226'' of the transistor die 210) by each pattern 240p of the conductive adhesive 240'' to provide a portion of the ground signal path between the source terminal 226'' of the transistor die 210 and the thermal conductive flange 410.

[0321] As shown in block 3130, after the flange 410 is attached to the first surface 312 of the interconnect structure 310'', the assembly is rotated or inverted by 180 degrees. As shown in (optional) block 3135, solder or other conductive bonding material may be provided on the opposite second surface 314 of the interconnect structure 310'', and one or more passive electrical components 1750 may be attached to the second surface 314 and electrically connected to a conductive pattern, so that the passive electrical components 1750 are electrically coupled to the gate terminal 222'', drain terminal 224'', and / or source terminal 226'' of the transistor die on its first surface 312. In some embodiments, the passive electrical components may be located on the portion of the second surface 314 that overlaps with the transistor die 210 on the first surface 312, reducing or minimizing the distance or length of the electrical connections between them. In some embodiments, there may be no passive electrical components 1750 on the first surface 312. In some embodiments, one or more wire bonds may be attached to provide additional electrical connections. In other embodiments, packages 3000a and 3000b may not have wire bond connections.

[0322] In block 3140, the package housing 278 is formed on the component assembly 2905 to complete the transistor device packages 3000a and 3000b. In particular, an encapsulation material 625 (such as the overmolding material 1740) is formed on the surfaces of the interconnect structure 310'', the transistor die 210, and the thermal conductive flange 410 to form the mold structure 2240. The overmolding material 1740 may be a plastic or plastic polymer compound highly filled with silica or other inorganic material, and may provide the package housing 278 for environmental protection of the component assembly 2905. The interconnect structure 310'' may protrude beyond or outside the periphery of the package housing 278 defined by the mold structure 2240. The portion of the interconnect structure 310'' that lies outside the package housing 278 may include conductive leads 415A, 415B (e.g., input and / or output leads) integrated therein, such that these are carried out by exposed contact patterns on the portions of the first surface 312 and / or second surface 314 of the interconnect structure 310'' that lies outside the mold structure 2240. The bottom surface of the thermal conductive flange 410 may be exposed by the mold structure 2240 to provide a heat dissipation path to the bottom of the packages 3000a, 3000b. Additionally or alternatively, as shown in Figure 30B, a lid member 2325 may be provided as part of the package housing 278 (i.e., instead of or in addition to the encapsulation material 1740).

[0323] As described above, before integrating the component assemblies 2905 into their respective transistor device packages (each including its own thermally conductive flange 410 and package housing 278), the array 310a of the mounted interconnect structures 310'' is separated into individual component assemblies 2905. However, Figures 32A–32C show that further operations for fabricating the transistor device packages 3000a, 3000b may be performed in array format. In particular, Figures 32A and 32B show that, in some embodiments, instead of performing the separation operation in block 3115 before attaching the flanges 410 in block 3125 of Figure 31, the array 310a containing multiple interconnect structures 310'' (collectively referred to as interconnect array 310a) may be provided with dicing or snapping lines that demarcate the boundaries of each interconnect structure 310'', and multiple flanges 410 may be attached to their respective interconnect structures 310'' in order to form an array of component assemblies 2905 before performing the separation operation. As shown in Figure 32B, in some embodiments, the interconnect array 310a may contain one or more slots sized to accommodate a clamping device used during the molding process, and / or otherwise configured to do so. As shown in Figure 32C, the clamping device is configured to clamp the thermal conductive flange 410 to the bottom of the mold chase during molding. In some embodiments, conductive pillars 2410 extruded from the flange material itself may be used to provide stability and appropriate spacing between the conductive flange 410 and the interconnect structure 310. That is, the attachment of the interconnect structure 310'' to the flange 410, as shown in block 3125 of Figure 31, may, in some embodiments, be performed before the piecemaking operation shown in block 3115. Similarly, the attachment of the passive electrical components 1750 in (optional) block 3135, and / or the formation of the package housing 278 shown in block 3140, may, in some embodiments, be performed before the piecemaking operation shown in block 3115.The slots may include end-face plating to improve solderability at the edges. Also, as shown in Figure 32D, a portion of the package housing 278 (e.g., mold structure 2240) may include recessed features 3240 along one or more edges, each recessed feature 3240 having dimensions corresponding to at least one dimension of a clamping device used to secure the flange 410 during the formation of the housing 278.

[0324] Figure 33 is a flowchart illustrating exemplary operations (also referred to as instrip manufacturing) for fabricating transistor device packages (e.g., 3000a, 3000b) in an array format according to several embodiments of the present invention. As shown in Figure 33, in block 3305, solder or other conductive bonding material is provided on the first surface 312 of the interconnect array 310a (e.g., using a printing process). The interconnect array 310a may include a plurality of mechanically connected interconnect structures 310'', which in some embodiments include dicing or snapping lines configured for separation along the boundaries between each interconnect structure 310''. In block 3310'', passive electrical components 1750 are mounted on the first surface 312 of the interconnect array 310a, and in block 3315, transistor dies are mounted on the first surface 312 of the interconnect array 310a (e.g., in a flip-chip manner), thereby mounting each interconnect structure 310''. In block 3320, a reflow process is performed to attach the passive electrical component 1750 and the transistor die to a conductive pattern on the first surface 312 of the interconnect array 310a using bonding material and to electrically connect them, so that the passive electrical component 1750 is electrically coupled to the gate terminal 222'', drain terminal 224'', and / or source terminal 226'' of the transistor die.

[0325] Referring to Figure 33, in block 3325, a conductive adhesive 240'' (e.g., solder or silver nanoparticles) may be distributed to provide each pattern 240p of the conductive adhesive 240'' on each region of the first surface 312 of the interconnection array 310a and on the rear surface 214 of the transistor die. In block 3330, a thermal conductive flange 410 is provided on each interconnection structure 310'' of the interconnection array 310a. In block 3335, a sintering or other thermal process is performed on the thermal conductive flange 410 to attach and electrically connect it to the conductive pattern on each interconnection structure 310'' by the pattern 240p of the conductive adhesive 240'', so that the conductive adhesive pattern 240p can provide at least a portion of a ground signal path between the transistor die 210 and the corresponding thermal conductive flange 410. In block 3340, a molding process (e.g., using a single-sided or double-sided cavity molding process) is performed to encapsulate the transistor die, the passive electrical component 1750, and the thermal conductive flange 410. In block 3345, an exposure process (e.g., polishing or laser cutting) is performed to expose the bottom surface of each thermal conductive flange 410. In block 3350, a plating process (e.g., an Ag plating process) is performed (e.g., on the portions of the conductive leads 415A, 415B that protrude outward from the periphery of the package housing 278). In block 3355, a laser marking process is performed. In block 3360, the interconnection array 310a is mounted on a tape and in block 3365, it is pieced (e.g., by dicing, sawing, laser cutting, etc.) to provide the respective transistor device packages 3000a, 3000b.In some embodiments, the operation (for single-piece processing) may continue by transferring each transistor device package 3000a, 3000b from tape to a tray (e.g., using a pick-and-place operation) in block 3370, performing an electrical (e.g., RF and / or DC) test in block 3375, performing a dehumidification process (e.g., baking) in block 3380, and transferring each transistor device package 3000a, 3000b to tape or reel in block 3385.

[0326] Figures 34A to 34D are flowcharts illustrating more specific operations for fabricating transistor device packages in an array format, according to several embodiments of the present invention, where passive components are located on both the upper surface / first surface 312 and the bottom surface / second surface 314 of the interconnect structure 310''. For example, the operations shown in Figures 34A to 34D are illustrated with reference to an in-strip fabrication process for fabricating the transistor device package 3000a in Figure 30A (having a mold structure 2240 providing at least a portion of the package housing 278) and the package 3000b in Figure 30B (having a lid member 2325 providing at least a portion of the package housing 278). However, it will be understood that the operations shown in Figures 34A to 34D are not limited to the fabrication of the packages 3000a and 3000b in Figures 30A and 30B.

[0327] As shown in Figure 34A, in block 3405, solder or other conductive bonding material is provided on the second surface 314 of the interconnect array 310a (for example, by performing a first printing process). As mentioned above, the interconnect array 310a may include a plurality of mechanically connected interconnect structures 310'', which in some embodiments include dicing or snapping lines configured for separation along the boundary lines between each interconnect structure 310''. In block 3410, the passive electrical component 1750 is attached to the second surface 314 of the interconnect array 310a, and in block 3415, a first reflow process is performed to attach the passive electrical component 1750 to a conductive pattern on the second surface 314 of the interconnect array 310a by bonding material and to electrically connect them. As shown in (optional) block 3420, in some embodiments, one or more wire bonds may be attached to the second surface 314 to provide additional electrical connections. In other embodiments, packages 3000a and 3000b may not have wire bond connections.

[0328] As shown in Figure 34B, in block 3425, one or more operations are performed to provide environmental protection for the passive electrical components 1750 on the second surface 314 of the interconnect array 310a. For example, in some embodiments, overmolding, glob topping, and / or dam-and-fill operations may be performed to encapsulate the passive electrical components 1750 of each component assembly 2905 on the second surface 314 of the interconnect array 310a. Additionally or alternatively, each lid member 2325 (e.g., a ceramic lid) may be provided on the second surface 314 of the interconnect array 310a to provide their respective open cavities around the passive electrical components 1750 of each component assembly 2905. Thus, the encapsulation material 1740 and / or lid member 2325 may be formed on the passive electrical components 1750 of each component assembly 2905 on the second surface 314 of their respective interconnect structure 310''.

[0329] In block 3430, the interconnect array 310a is rotated or inverted, and solder or other conductive bonding material is applied to the first surface 312 of the interconnect array 310a (for example, by performing a second printing process). In block 3435, the passive electrical component 1750 and the transistor die are mounted (for example, in a flip-chip manner) to the first surface 312 of the interconnect array 310a, and a second reflow process is performed to attach the passive electrical component 1750 and the transistor die to the conductive pattern on the first surface 312 of the interconnect array 310a by bonding material and to electrically connect them, so that the passive electrical component 1750 on the first surface 312 and / or the second surface 314 are electrically coupled to the gate terminal 222'', drain terminal 224'', and / or source terminal 226'' of the transistor die, respectively. In some embodiments, as mentioned above, one or more passive electrical components 1750 may be located on the portion of the second surface 314 that overlaps with the transistor die 210 on the first surface 312, thereby reducing or minimizing the distance or length of the electrical connections between them.

[0330] Referring to Figure 34B, in block 3440, conductive adhesive 240'' (e.g., solder or silver nanoparticles) is distributed to provide each pattern 240p of conductive adhesive 240'' on each region of the first surface 312 of the interconnection array 310a and on the rear surface 214 of the transistor die. As shown in Figure 34C, in block 3445, a thermal conductive flange 410 is provided on the first surface 312 of each interconnection structure 310'' of the interconnection array 310a, i.e., on each component assembly 2905 for the respective transistor device packages 3000a, 3000b. The flange 410 includes a conductive pillar structure 2410 or other support structure that is extruded from the surface of the thermal conductive flange 410 (or otherwise integral with the thermal conductive flange 410). The rear surface 214 of the transistor die 210 on each interconnect structure 310'' is in contact with the surface of the thermal conductive flange 410 (by conductive adhesive 240'' between them), and the conductive pillar structures 2410 protruding from the thermal conductive flange 410 are in contact with each region of the first surface 312 of the corresponding interconnect structure 310'' (by conductive adhesive pattern 240p between them). In block 3445, a sintering or other thermal process is performed to attach the conductive support structures 2410 of each thermal conductive flange 410 to the conductive patterns on the respective interconnect structure 310'' by the conductive adhesive pattern 240p and to electrically connect them. Thereafter, the conductive pillar portions protruding from the surface of the thermal conductive flange 410 may be mechanically attached to the first surface 312 of the corresponding interconnect structure 310'' and electrically connected to conductive pads on the first surface 312 (coupled to the source terminal 226'' of the transistor die 210) by the respective patterns 240p of the conductive adhesive 240''. As a result, the conductive adhesive pattern 240p provides at least a portion of the ground signal path between the source terminal 226'' of the transistor die 210 and the corresponding thermally conductive flange 410 of each interconnection structure 310''.

[0331] As shown in block 3450, after the flange 410 is attached to the first surface 312 of the interconnect array 310a, the array 310a is rotated or inverted by 180 degrees, and one or more operations are performed to provide environmental protection for the transistor die, the passive electrical component 1750, and the thermally conductive flange 410 on the first surface 312 of the interconnect array 310a. For example, in some embodiments, a molding operation (shown using encapsulation material 1740) may be performed to encapsulate the components on the first surface 312 of the interconnect array 310a. Thus, each package housing 278 may be provided for each implemented interconnect structure 310'', and each package housing 278 may include encapsulation material 1740 (e.g., defining a mold structure 2240) and / or a lid member 2325 (e.g., a ceramic lid).

[0332] In block 3455, the interconnect array 310a is rotated or inverted 180 degrees and laminated onto tape T (e.g., PVC or Mylar tape) with the thermal conductive flange 410 facing the tape. In some embodiments, a laser marking process may be performed on the surface of the package housing 278 (e.g., mold structure 2240 or lid 2325) opposite to the thermal conductive flange 410. As shown in Figure 34D, in block 3460, the interconnect array 310a may be removed from the tape and rotated or inverted again 180 degrees. In block 3465a or 3456b, the interconnect array 310a may be placed on a carrier C (shown on the left) or on tape T (shown on the right). In either configuration, an exposure process (e.g., polishing or laser cutting) is performed to expose the bottom surface of each thermal conductive flange 410. In block 3470a or 3470b, a piecewise process (e.g., dicing, sawing, laser cutting, etc.) is performed to isolate each interconnect structure 310'' of the interconnect array 310a, thereby providing the respective transistor device packages 3000a, 3000b on carrier C (shown on the left) or tape T (shown on the right) in block 3475a or 3475b by an in-strip manufacturing process. In some embodiments, operations for single-piece processing (e.g., pick-and-place operations, electrical testing, dehumidification processes) may be further performed, as mentioned with reference to Figure 33.

[0333] As described herein, several embodiments of the present invention incorporate the advantages of flip-chip modules and integrate them into large, high-power-compatible packages that can visually conform to the form factors of several conventional chip-and-wire high-power device packages. Flip-chip component mounting according to the embodiments described herein can provide more accurate, repeatable, and reduced-inductance connections compared to wire-bonded connections, which can be affected by process and material variations (which can become increasingly problematic as operating frequencies increase) (therefore potentially providing improved performance, particularly at higher operating frequencies). In particular, flip-chip component assemblies using very low-impedance connections (e.g., using Cu bumps) can provide significantly lower impedance and lower impedance variation compared to chip-and-wire connections.

[0334] In addition to reducing inductance and tolerances, flip-chip component assemblies as described herein may enable non-uniform integration, thereby allowing the inclusion of various passive electrical components (e.g., IPDs, SMDs) that are attached to the interconnect structure of the component assembly, for example, using epoxy or soldering, to implement termination and / or matched networks by the shortest possible electrical connections. For example, one or more passive components may be used to implement a baseband termination circuit that overlaps perpendicularly with the transistor die (for example, positioned on the surface of a PCB or other interconnect structure just above or below the die's position on the opposite surface).

[0335] Integrating such flip-chip component assemblies into transistor device packages, as described herein, can also offer cost advantages. In particular, some conventional chip-and-wire package embodiments may use 2-mil (50 μm) gold wires to implement input / output and matched network connections, which can incur significant costs per unit. Also, as mentioned, such conventional packages may be subject to process variations, which can limit performance due to consistency and high impedance on wire bond connections. Thus, embodiments of the present invention can achieve improved performance and may be cost-competitive (or even cheaper) than some conventional chip-and-wire assembly methods.

[0336] Embodiments of the present invention can be used in high-power RF transistors for cellular or aerospace and defense (A&D) applications, such as RF transistors with an average output power of 20W or more for 5G base station applications at 3.5GHz or higher. Embodiments of the present invention can also provide lower-cost and higher-performance products at higher frequencies, particularly in the case of low-impedance integration of matching circuits such as baseband termination circuits. Such embodiments may enable implementation within the range in which monolithic microwave integrated circuits (MMICs) are typically used, which can provide significant cost improvements for devices operating at such high frequencies.

[0337] Various embodiments have been described herein with reference to the accompanying drawings illustrating exemplary embodiments. However, these embodiments can be embodied in multiple different forms and should not be construed as being limited to the embodiments described herein. Rather, these embodiments are provided to ensure that this disclosure is thorough and complete and that the concepts of the invention are fully conveyed to those skilled in the art. Various modifications to the exemplary embodiments and general principles and features described herein will readily become apparent. In the drawings, the sizes and relative sizes of layers and areas are not shown to actual size and may, in some cases, be exaggerated for clarity.

[0338] In this specification, various elements may be described using terms such as "first," "second," etc., but it will be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of the invention, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. Where used herein, the term "and / or" includes any combination of one or more of the items listed in relation to it.

[0339] The terms used herein are intended solely to describe specific embodiments and are not intended to be limitations of the invention. Where used herein, the singular forms “a” and “an” and “the” are intended to include the plural form unless otherwise explicitly indicated by the context. Where used herein, the terms “comprises,” “comprising,” “includes,” and / or “including,” specify the existence of the described features, integers, steps, actions, elements, and / or components, but not exclude the ...

Claims

1. A transistor device package, An interconnection structure, a transistor die having a front surface including a gate terminal, a drain terminal, and a source terminal on a first surface of the interconnection structure, and a component assembly comprising one or more passive electrical components electrically coupled to the gate terminal, the drain terminal, and / or the source terminal by the interconnection structure, A thermally conductive flange attached to the rear surface of the transistor die, opposite to the front surface, is attached by conductive adhesive. A transistor device package comprising the above features.

2. The transistor device package according to claim 1, further comprising each of the patterns of the conductive adhesive on the first surface of the interconnection structure, wherein at least one of the patterns of the conductive adhesive provides an input, output, or ground signal path for the transistor device package.

3. The transistor device package according to claim 2, wherein each of the patterns of the conductive adhesive has one or more conductive leads attached to each of the conductive patterns on the first surface of the interconnection structure and electrically connected.

4. The transistor device package according to claim 2, wherein each of the patterns of the conductive adhesive attaches the thermally conductive flange to the conductive pattern on the first surface of the interconnection structure and electrically connects them.

5. The transistor device package according to claim 4, wherein the interconnection structure comprises one or more internally integrated conductive leads that protrude outward from the periphery of the transistor device package.

6. The transistor device package according to claim 4, further comprising one or more support structures extending from the thermally conductive flange to the first surface of the interconnection structure.

7. The transistor device package according to claim 6, comprising one or more conductive support structures that are attached to the conductive patterns on the first surface of the interconnection structure by the respective patterns of the conductive adhesive and electrically connected.

8. The transistor device package according to claim 7, wherein the one or more support structures are integral with the thermal conductive flange and include one or more conductive pillar structures protruding from the thermal conductive flange to the first surface of the interconnection structure.

9. The transistor device package according to claim 3, wherein the one or more conductive leads are located inside the periphery of the transistor device package and include portions that are bent toward or outward from the first surface of the interconnection structure.

10. The transistor device package according to claim 1, further comprising an overmolded material on the transistor die between the first surface of the interconnection structure and the thermally conductive flange.

11. The transistor device package according to claim 1, wherein the one or more passive electrical components are located on a second surface of the interconnection structure opposite to the first surface.

12. The transistor device package according to claim 11, wherein at least one of the passive electrical components is located on the portion of the second surface of the interconnection structure that overlaps with the transistor die on the first surface.

13. The transistor device package according to claim 11, further comprising an overmolded material on one or more passive electrical components on the second surface of the interconnection structure.

14. The transistor device package according to claim 11, further comprising a cover member that defines an open cavity around one or more passive electrical components on the second surface of the interconnection structure.

15. The transistor device package according to claim 1, wherein the one or more passive electrical components include a surface mount device and / or an integrated passive device.

16. The transistor device package according to claim 1, wherein the transistor device package does not have wire bond connections.

17. The transistor device package according to claim 1, wherein the transistor die includes a high electron mobility transistor (HEMT) or a lateral diffusion metal-oxide-semiconductor (LDMOS) transistor.

18. The transistor device package according to claim 1, wherein the transistor die is a group III nitride-based RF transistor amplifier die.

19. A transistor device package, A component assembly comprising an interconnection structure, and a transistor die having a front surface including a gate terminal, a drain terminal, and a source terminal on a first surface of the interconnection structure, Each of the conductive adhesive patterns on the first surface of the interconnection structure, wherein at least one of the conductive adhesive patterns provides an input, output, or ground signal path for the transistor device package. A transistor device package comprising the above features.

20. The transistor device package according to claim 19, wherein each of the patterns of the conductive adhesive is used to attach one or more conductive leads to each of the conductive patterns on the first surface of the interconnection structure and to electrically connect them.

21. The transistor device package according to claim 19, wherein each of the patterns of the conductive adhesive attaches the thermally conductive flange to the conductive pattern on the first surface of the interconnection structure and connects them electrically.

22. A method for fabricating a transistor device package, To provide an interconnection structure, a transistor die having a front surface including a gate terminal, a drain terminal, and a source terminal on a first surface of the interconnection structure, and a component assembly comprising one or more passive electrical components electrically coupled to the gate terminal, the drain terminal, and / or the source terminal by the interconnection structure, The rear surface of the transistor die, opposite to the front surface, is attached to the thermally conductive flange with a conductive adhesive. Methods that include...

23. The method according to claim 22, further comprising each pattern of the conductive adhesive on the first surface of the interconnection structure, wherein each pattern of the conductive adhesive provides an input, output, or ground signal path for the transistor device package.

24. The conductive adhesive in each of the above patterns is applied to one or more conductive leads, and then Using the respective patterns of the conductive adhesive, one or more conductive leads are attached to the conductive patterns on the first surface of the interconnection structure. It further includes, Each of the patterns of the conductive adhesive electrically connects one or more conductive leads to the conductive patterns of the interconnection structure. The method according to claim 23.

25. Apply the conductive adhesive in each of the patterns onto each region of the first surface of the interconnection structure, and then The thermally conductive flange is attached to the conductive pattern on each of the regions of the first surface of the interconnection structure, Includes, Each of the patterns of the conductive adhesive electrically connects the thermally conductive flange to the conductive pattern of the interconnection structure. The method according to claim 23.

26. The method according to claim 25, wherein the interconnection structure comprises one or more internally integrated conductive leads that protrude outward from the periphery of the transistor device package.

27. The method according to claim 26, wherein the thermal conductive flange comprises one or more conductive pillar structures protruding therefrom, and attaching the thermal conductive flange includes attaching the one or more conductive pillar structures to the conductive pattern on the first surface of the interconnection structure by the respective patterns of the conductive adhesive.

28. The aforementioned interconnection structure includes each of the interconnection structures of a plurality of interconnection structures of an interconnection array, The further step includes separating the interconnection array into the plurality of interconnection structures before attaching the thermally conductive flange, The method according to claim 27.

29. The aforementioned interconnection array has slots inside, Attaching the aforementioned heat-conducting flange means Inserting the clamp device into one or more of the aforementioned slots, The thermal conductive flange is clamped to the interconnect structure using the clamping device such that one or more conductive pillar structures contact the respective regions of the first surface of the interconnect structure having the respective patterns of the conductive adhesive thereon, The method according to claim 28, including the method described in claim 28.

30. The aforementioned interconnection structure includes each of the interconnection structures of a plurality of interconnection structures of an interconnection array, The process further includes, after attaching the thermally conductive flange, separating the interconnection array into the plurality of interconnection structures, The method according to claim 27.

31. The method according to claim 22, further comprising forming an overmolded material between the first surface of the interconnection structure and the thermally conductive flange on the transistor die.

32. The method according to claim 22, wherein the one or more passive electrical components are provided on a second surface of the interconnection structure opposite to the first surface.

33. The method according to claim 32, further comprising forming an overmolded material structure on the one or more passive electrical components on the second surface of the interconnection structure.

34. The method according to claim 32, further comprising providing a cover member on the second surface of the interconnection structure that defines an open cavity around one or more passive electrical components.

35. The method according to claim 22, wherein the transistor device package does not have wire bond connections.

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