Processor, instruction processing unit, electronic device, and instruction processing method

Abstract

Disclosed are a processor, an instruction processing unit, an electronic device, and an instruction processing method, belonging to the field of computers. The processor includes an instruction acquisition unit, an instruction analysis unit, a DQ instruction execution unit, and a CA instruction execution unit, the instruction acquisition unit, the instruction analysis unit, and a first target unit form a first instruction pipeline, the instruction acquisition unit, the instruction analysis unit, and a second target unit form a second instruction pipeline, the first and second instruction pipelines execute in parallel when the target conditions are met, the first target unit includes a DQ instruction execution unit, and the second target unit includes the CA instruction execution unit.

Description

Technical Field

[0001] This application belongs to the field of computers, and specifically relates to processors, instruction processing devices, electronic devices, and instruction processing methods.

[0002] [Cross-reference to Related Applications] This application claims priority based on a Chinese application filed with the China National Intellectual Property Administration on June 18, 2024, with an application number of 202410782583.1 and a title of "Processor, Instruction Processing Device, Electronic Device, and Instruction Processing Method", and all of its content is incorporated herein by reference.

Background Art

[0003] To meet the requirements of data storage, flash technology emerged. As the requirements for the bandwidth of the flash die interface increase, the data transmission speed of the flash interface is increasing, but the transmission speed of the command / address of the flash interface has not changed. In the conventional flash interface transmission protocol (ONFi or Toggle), commands / addresses and data are transmitted on the same set of transmission lines. As the data transmission speed increases, the proportion of the transmission time of commands / addresses increases, which has become a bottleneck for the bandwidth of the flash die interface. To solve the problem of improving the bandwidth of the flash interface, in a new flash die protocol, such as the Separate Command Address (SCA for short) protocol, the transmission of commands / addresses and the transmission of data are separated and assigned to two different transmission buses. The commands / addresses are transmitted on the Command and Address (CA for short) bus, and the data is transmitted on the Data (also called DQ) bus, thereby realizing that while the commands / addresses are transmitted on the CA bus, the data is transmitted on the DQ bus.

[0004] In related technologies, the SCA protocol is typically implemented using a dedicated state machine during the process of processing instructions on a flash die chip. However, this approach suffers from the problem of low instruction processing efficiency. [Overview of the project]

[0005] The embodiments of this application provide a processor, an instruction processing unit, an electronic device, and an instruction processing method that can solve the problem of low instruction processing efficiency when implementing the SCA protocol using a state machine in related technologies.

[0006] In a first embodiment, an embodiment of the present application provides a processor comprising an instruction acquisition unit, an instruction analysis unit, a DQ instruction execution unit, and a CA instruction execution unit, wherein the instruction acquisition unit is configured to acquire a target instruction and transmit it to the instruction analysis unit, the target instruction being an instruction that fits a flash die chip, the instruction analysis unit is configured to perform an analysis on the target instruction to determine the instruction type of the target instruction, the instruction type including a command / address CA operation instruction or a data DQ operation instruction, and the DQ instruction execution unit, if the instruction type is a DQ operation instruction, transmits target data to the flash die chip via a DQ bus. The CA instruction execution unit is configured to transmit CA information or CA-related configuration information to a flash die chip via the CA bus when the instruction type is a CA operation instruction. The instruction acquisition unit, the instruction analysis unit, and the first target unit form a first instruction pipeline, and the instruction acquisition unit, the instruction analysis unit, and the second target unit form a second instruction pipeline. If the target conditions are met, the first instruction pipeline and the second instruction pipeline execute in parallel, the first target unit includes the DQ instruction execution unit, and the second target unit includes the CA instruction execution unit.

[0007] In a second embodiment, the embodiment of the present application provides an instruction processing device. The instruction processing device includes a flash die chip and a processor according to the first embodiment, wherein the processor is connected to the flash die chip by a CA bus and the processor is connected to the flash die chip by a DQ bus.

[0008] In a third embodiment, the embodiments of this application provide a storage device, the storage device including an apparatus according to the second embodiment.

[0009] In a fourth embodiment, the embodiment of the present application provides an electronic device, the electronic device including a storage device according to the third embodiment.

[0010] In a fifth embodiment, an embodiment of the present application provides an instruction processing method. The instruction processing method is executed by a processor and includes the steps of obtaining a target instruction, The process includes: performing an analysis on the target instruction to determine the instruction type of the target instruction, and the instruction type including a command / address CA operation instruction or a data DQ operation instruction; if the instruction type is a DQ operation instruction, transmitting target data to the flash die chip via the DQ bus; if the instruction type is a CA operation instruction, transmitting CA information or CA-related setting information to the flash die chip via the CA bus; if the DQ operation instruction is a write-back, obtaining first information from the flash die chip via the DQ bus and writing the first information to the data storage space in the processor; and if the CA operation instruction is a write-back, obtaining second information from the flash die chip via the CA bus and writing the second information to the data storage space in the processor.

[0011] In the sixth embodiment, the embodiment of the present application provides a storage medium. A program is stored in the storage medium, and when the program is executed, the method according to the fifth embodiment is realized.

[0012] An embodiment of this application provides a processor. The processor includes an instruction acquisition unit, an instruction analysis unit, a DQ instruction execution unit, and a CA instruction execution unit, wherein the instruction acquisition unit is configured to acquire a target instruction and transmit it to the instruction analysis unit, the target instruction being an instruction that fits a flash die chip, the instruction analysis unit is configured to perform analysis on the target instruction to determine the instruction type of the target instruction, the instruction type including a CA operation instruction or a DQ operation instruction, and the DQ instruction execution unit is configured to transmit target data to the flash die chip via the DQ bus if the instruction type is a DQ operation instruction. The CA instruction execution unit is configured to transmit CA information or CA-related configuration information to the flash die chip via the CA bus when the instruction type is a CA operation instruction. The instruction acquisition unit, the instruction analysis unit, and the first target unit form a first instruction pipeline, and the instruction acquisition unit, the instruction analysis unit, and the second target unit form a second instruction pipeline. When the target conditions are met, the first and second instruction pipelines execute in parallel, the first target unit includes the DQ instruction execution unit, and the second target unit includes the CA instruction execution unit. In this way, the SCA protocol is implemented in the process of processing instructions on the flash die chip by the processor, improving the processing speed of target instructions. When the target conditions are met, the processor can process instructions freely in parallel using the first and second instruction pipelines, thereby further improving the instruction processing efficiency. Furthermore, in the processor according to the embodiment of this application, since the first and second instruction pipelines share the instruction acquisition unit and the instruction analysis unit, the number of components and hardware area in the processor can be reduced to some extent.

[0013] To more clearly explain the technical concept of the embodiments of the present invention, the drawings used in the embodiments will be briefly described below. The drawings described are merely illustrations of some embodiments of the present invention and do not limit its scope. Those skilled in the art can obtain other relevant drawings based on these drawings without employing inventive capabilities. [Brief explanation of the drawing]

[0014] [Figure 1] This is a block diagram of the configuration of one type of processor according to an embodiment of this application. [Figure 2] This is a block diagram of the configuration of another type of processor according to an embodiment of this application. [Figure 3] This is an architectural diagram of the target format according to an embodiment of this application. [Figure 4] This is a block diagram of the configuration of the instruction processing device according to an embodiment of this application. [Figure 5] This is a flowchart of the instruction processing method according to the embodiment of this application. [Figure 6] This is an architectural diagram of the external environment of the processor according to the embodiment of this application. [Figure 7] This is an architecture diagram of a processor according to an embodiment of this application. [Figure 8] This is an architectural diagram of the target instruction processing process according to an embodiment of this application. [Modes for carrying out the invention]

[0015] To clarify the purpose, technical proposal, and advantages of the embodiments of the present invention, the technical proposal in the embodiments of the present invention will be clearly and completely described below with reference to the drawings used in the embodiments of the present invention. The embodiments described are only some embodiments of the present invention, not all embodiments. The components in the embodiments of the present invention shown herein with reference to the drawings can be arranged and designed in various ways.

[0016] The terms "first," "second," etc., in the specification and claims of this application are merely for distinguishing similar subjects and do not limit any particular order or sequence. The data used in this manner can be appropriately interchanged, meaning that the embodiments of this application described herein can be carried out in an order other than the order illustrated or described. Furthermore, the subjects distinguished by "first," "second," etc., are usually of the same kind and do not limit the number of subjects. For example, the first subject may be one or more. Also, "and / or" in the specification and claims means at least one of the subjects connected by it, and the symbol " / " generally indicates that the preceding and following related subjects have an "or" relationship.

[0017] Therefore, the following detailed description of the embodiments of the present invention shown in the drawings is merely to illustrate selected embodiments of the present invention and does not limit the scope of the present invention that is to be protected. All other embodiments that a person skilled in the art could obtain without using their inventive ability based on embodiments of the present invention also fall within the scope of protection of the present invention.

[0018] As explained in the background technology section, related technologies typically implement the SCA protocol using a dedicated state machine in the process of processing flash die chip instructions. However, this approach suffers from the problem of low instruction processing efficiency.

[0019] In an embodiment of the present application, a processor is provided. The processor includes an instruction fetch unit, an instruction decoding unit, a DQ instruction execution unit, and a CA instruction execution unit. The instruction fetch unit, the instruction decoding unit, and a first target unit form a first instruction pipeline, and the instruction fetch unit, the instruction decoding unit, and a second target unit form a second instruction pipeline. When a target condition is satisfied, the first instruction pipeline and the second instruction pipeline execute in parallel. The first target unit includes the DQ instruction execution unit, and the second target unit includes the CA instruction execution unit. In this way, the SCA protocol is realized in the process of the processor processing the instructions of the flash chip, and the processing speed of the target instructions is improved. When the target condition is satisfied, the processor can freely process instructions in parallel by the first instruction pipeline and the second instruction pipeline, thereby further improving the processing efficiency of the instructions. In addition, in the processor according to the embodiment of the present application, since the first instruction pipeline and the second instruction pipeline share the instruction fetch unit and the instruction decoding unit, the number of components and the hardware area in the processor can be reduced to a certain extent.

[0020] Also, in the related art, before transmission is performed by two transmission buses, instructions are usually processed by scalar pipeline design (one instruction pipeline). The processor according to the embodiment of the present application can more freely and efficiently process target instructions by implementing superscalar design by the first instruction pipeline and / or the second instruction pipeline.

[0021] In related technologies, when considering conforming to instructions of multiple types of flash chips, generally, a large number of hardware circuits are pre-designed. Even with such design, it is still impossible to support new instructions that have not been pre-designed, and there are still problems of poor compatibility, large area, and high cost. In contrast, in the embodiments of the present application, the processor has an instruction storage space for storing various instructions conforming to the flash chip, and the instruction storage space is for storing the target instruction. In this way, by changing the target instruction in the instruction storage space in the processor, the processor can conform to different flash chips manufactured by different manufacturers, and the processor can conform to flash chips manufactured by more manufacturers. Compared with related technologies, the processor according to the embodiments of the present application has better compatibility and conformability, and can reduce costs.

[0022] In the embodiments of the present application, the target instruction is an instruction that conforms to a target format. The target format includes a bus type field, a data field, a write-back instruction field, a length field, a waveform instruction field, and a lock field. With the target format, the processor can better control the execution operation between the CA bus and the DQ bus (the waveform between the interfaces of the CA bus and / or the DQ bus, that is, the signal operation of the target instruction), data, parallel or exclusive operations, etc.

[0023] In the embodiments of the present application, the processor can further realize simultaneous control of the CA bus and / or the DQ bus by simultaneously controlling the first instruction pipeline and / or the second instruction pipeline. And because the processor simultaneously controls the CA bus and / or the DQ bus, based on the operation of any one of the transmission buses, the operation of the other transmission bus can be appropriately designed, and the mutual exclusion relationship of the instruction operations between the two transmission buses can be more easily controlled.

[0024] In the embodiments of this application, descriptions of the same terms or situations can be referenced sequentially. That is, as long as there is no logical contradiction, a description of a term or situation in one embodiment can also be used to describe the same term or situation in another embodiment.

[0025] The method according to the embodiment of this application will be described in detail below, with reference to the drawings, using specific examples and their application scenarios.

[0026] In the embodiments of this application, the flash die chip is a NAND flash memory (NAND flash), and the processor according to the embodiments of this application is used to control the operation of the flash die chip, for example, to enable read / write operations to the flash die chip by the application layer, or to enable operations such as setting the flash die chip.

[0027] Figure 1 is a block diagram of the configuration of one type of processor according to an embodiment of the present application. As shown in Figure 1, the processor 100 according to an embodiment of the present application includes an instruction acquisition unit 110, an instruction analysis unit 120, a DQ instruction execution unit 130, and a CA instruction execution unit 140.

[0028] The instruction acquisition unit 110 is configured to acquire a target instruction and transmit it to the instruction analysis unit, wherein the target instruction is an instruction that fits the flash die chip.

[0029] The instruction analysis unit 120 is configured to perform analysis on the target instruction to determine the instruction type of the target instruction, and the instruction type includes a CA operation instruction or a DQ operation instruction.

[0030] The DQ instruction execution unit 130 is configured to transmit target data to the flash die chip via the DQ bus when the instruction type is a DQ operation instruction.

[0031] The CA instruction execution unit 140 is configured to send CA information or CA-related configuration information to the flash die chip via the CA bus when the instruction type is a CA operation instruction.

[0032] The instruction acquisition unit, the instruction analysis unit, and the first target unit form a first instruction pipeline, and the instruction acquisition unit, the instruction analysis unit, and the second target unit form a second instruction pipeline.

[0033] If the target conditions are met, the first instruction pipeline and the second instruction pipeline execute in parallel, the first target unit includes the DQ instruction execution unit, and the second target unit includes the CA instruction execution unit.

[0034] In the embodiment of this application, the processor 100 is a hardware device, and each unit in the processor 100 may also have a corresponding hardware module. In the processor according to the embodiment of this application, the hardware modules corresponding to each unit are connected by circuits, thereby enabling data transmission between each unit.

[0035] In the embodiments of this application, the expression method of the instruction for the same operation, for example, a "write operation," may differ depending on the flash die chip manufacturer. In the embodiments of this application, the target instruction is any operation on the flash die chip and is an instruction that is compatible with the flash die chip, and examples include instructions relating to read / write operations on the flash die chip or self-configuration operations on the flash die chip. The instruction acquisition unit 110 in the processor 100 can acquire the target instruction from outside the processor 100, for example, from the application layer. The instruction acquisition unit 110 can also acquire the target instruction from inside the processor 100, for example, from an instruction storage area inside the processor 100 (i.e., the instruction storage space described later). In the embodiments of this application, the method by which the instruction acquisition unit 110 acquires a target instruction compatible with the flash die chip is not specifically limited.

[0036] In the embodiments of this application, the target instruction may be one instruction or multiple instructions. The number of target instructions is not specifically limited in the embodiments of this application. Furthermore, the target instruction may be one instruction on the same flash die chip, multiple instructions on the same flash die chip, or multiple instructions on multiple flash die chips, and the correspondence between the number of target instructions and the number of flash die chips is not specifically limited in the embodiments of this application.

[0037] In the embodiments of this application, the processor according to the embodiments of this application processes operation instructions to a flash die chip based on the SCA protocol and classifies the operation instructions to the flash die chip into CA operation instructions and DQ operation instructions. Specifically, the instruction analysis unit 120 performs analysis on the target instruction to determine the instruction type of the target instruction, and the instruction type includes either a CA operation instruction or a DQ operation instruction. The CA operation instruction may be an operation instruction relating to the settings of the flash die chip itself, for example, an instruction to read the state of the flash die chip, or an instruction to change the state of a register in the flash die chip. The DQ operation instruction may be an instruction relating to data information stored in the flash die chip, for example, a read / write operation instruction to the flash die chip.

[0038] In the embodiments of this application, the target instruction includes a field that directly represents the instruction type. The instruction analysis unit 120 performs an analysis on the target instruction and determines the instruction type of the target instruction based on the field that directly represents the instruction type contained in the target instruction. The instruction analysis unit 120 may also analyze the target instruction and determine the instruction type of the target instruction based on the proportion of data in the target instruction. In the embodiments of this application, the method by which the instruction analysis unit 120 determines the instruction type of the target instruction is not specifically limited.

[0039] Referring to Figure 1, which shows an embodiment of this application, the instruction analysis unit 120 determines the instruction type of the target instruction, and then different instruction execution units execute the target instruction based on the instruction type. The processor 100 can control the flash die chip by controlling the waveform operation at the input / output (I / O) interface on the flash die chip.

[0040] In the embodiment of this application, the DQ instruction execution unit 130, when the instruction type of the target instruction is a DQ operation instruction, converts the operation content of the target instruction into a waveform operation of the I / O interface in the processor, and converts the digital signal of the target instruction into an analog signal. The DQ bus transmits the waveform operation of the I / O interface in the processor 100 to the I / O interface in the flash die chip, so that the flash die chip acquires target data based on the waveform operation of the I / O interface in the flash die chip.

[0041] In the embodiments of this application, the target data may be any data to be stored on the flash die chip. The target data may originate from the target instruction itself, or it may be obtained from within the processor 100 by the DQ instruction execution unit 130 based on the instructions of the target instruction. For example, a storage space where data is stored (e.g., a data storage space described later) is provided inside the processor 100, and the target data is obtained from the storage space where data is stored inside the processor 100 by the DQ instruction execution unit 130 based on the instructions of the target instruction.

[0042] Accordingly, the CA instruction execution unit 140, when the instruction type of the target instruction is a CA operation instruction, converts the operation content of the target instruction into a waveform operation of the I / O interface in the processor, and converts the digital signal of the target instruction into an analog signal. By transmitting the waveform operation of the I / O interface in the processor 100 to the I / O interface in the flash die chip via the CA bus, the flash die chip acquires CA information or setting information related to CA based on the waveform operation of the I / O interface in the flash die chip and executes a command related to CA.

[0043] In the embodiment of this application, the CA information is setting information relating to the flash die chip itself, for example, the register information of the flash die chip after modification. The flash die chip obtains the CA information or setting information relating to CA through the waveform operation of the I / O interface, and then performs an operation corresponding to the CA instruction, for example, to change the register information.

[0044] In the embodiments of this application, the first target unit (DQ instruction execution unit 130) in the first instruction pipeline is associated with the DQ bus. Correspondingly, the second target unit in the second instruction pipeline is associated with the CA bus. The target condition indicates whether the DQ bus and the CA bus can process target instructions in parallel. Specifically, the target condition is that the first instruction pipeline and the second instruction pipeline each process target instructions for different flash die chips, or that there is no mutual exclusion relationship between the instruction currently being processed by the first instruction pipeline and the instruction currently being processed by the second instruction pipeline. In this case, the first instruction pipeline and the second instruction pipeline can be executed in parallel, improving the processing efficiency of target instructions. In the embodiments of this application, when the first instruction pipeline and the second instruction pipeline are executed in parallel, the target instructions in the first instruction pipeline and the target instructions in the second instruction pipeline may be instructions for different flash die chips or instructions for the same flash die chip, and are not specifically limited in the embodiments of this application.

[0045] In the embodiments of this application, the parallel execution of the first instruction pipeline and the second instruction pipeline means that any one unit in the first instruction pipeline (e.g., instruction acquisition unit 110) can execute in parallel with any one unit in the second instruction pipeline that is different from the unit operating in the first instruction pipeline (e.g., instruction analysis unit 120 or second target unit). For example, the instruction acquisition unit in the first instruction pipeline can acquire target instruction X while the second target unit (CA instruction execution unit 140) in the second instruction pipeline can execute target instruction Y. In the embodiments of this application, any alphabetical notation for a target instruction represents a different target instruction, such as target instruction X and target instruction Y above, or target instruction A and target instruction B below.

[0046] In the embodiment of this application, when the DQ instruction execution unit in the first instruction pipeline is executing a target instruction, if the instruction acquisition unit and / or instruction analysis unit are in an idle period, the instruction acquisition unit and / or instruction analysis unit can execute other instructions in parallel. The other instructions and the target instruction may be instructions for the same flash die chip or instructions for different flash die chips. For example, after the instruction acquisition unit sends target instruction A for flash die chip A to the instruction analysis unit, it further acquires target instruction B for flash die chip A, thereby making the first and second instruction pipelines two parallel instruction pipelines that perform heterogeneous processing. In addition, the instruction acquisition unit can acquire target instruction A for flash die chip B as well as target instruction B for flash die chip A, and is not specifically limited to the embodiment of this application.

[0047] In the embodiment of this application, if the target condition is met, the CA instruction execution unit in the second instruction pipeline executes target instruction A. Simultaneously, the DQ instruction execution unit in the first instruction pipeline receives and processes target instruction B, thereby enabling the first and second instruction pipelines to execute in parallel.

[0048] In the embodiments of this application, if the target conditions are not met, the DQ bus and the CA bus cannot process the target instruction in parallel. For example, if the instruction currently being processed by the first instruction pipeline (which may be considered as the instruction corresponding to the target data currently being transmitted by the DQ bus) and the instruction currently being processed by the second instruction pipeline mutually reject each other and cannot be processed in parallel, in this case the CA instruction execution unit in the second target unit of the second instruction pipeline waits for the completion of the target instruction in the first instruction pipeline.

[0049] For example, in the embodiment of this application, the CA instruction execution unit executes target instruction C. Because the target condition is not met, the DQ instruction execution unit cannot execute target instruction D in parallel, and the DQ instruction execution unit of the first instruction pipeline executes target instruction D after the execution of target instruction C in the second instruction pipeline is completed.

[0050] In the embodiment of this application, the SCA protocol is implemented in the process of processing instructions on the flash die chip by the processor, thereby improving the processing speed of target instructions. When the target conditions are met, the processor implements heterogeneous pipelines using the first instruction pipeline and the second instruction pipeline, thereby improving the instruction processing efficiency. Furthermore, in the processor according to the embodiment of this application, since the first instruction pipeline and the second instruction pipeline share the instruction acquisition unit 110 and the instruction analysis unit 120, the number of components and hardware area in the processor can be reduced to some extent.

[0051] Figure 2 is a block diagram of the configuration of one type of processor according to an embodiment of the present application. As shown in Figure 2, the processor 100 according to an embodiment of the present application further includes a DQ write-back unit 150 and a CA write-back unit 160. The DQ write-back unit 150 is configured to acquire first information from the flash die chip via the DQ bus and write the first information to the data storage space within the processor when the DQ operation instruction is written back. The CA write-back unit 160 is configured to acquire second information from the flash die chip via the CA bus and write the second information to the data storage space within the processor when the CA operation instruction is written back. The first target unit further includes the DQ write-back unit 150, and the second target unit further includes the CA write-back unit 160.

[0052] In the embodiments of this application, the target instruction further includes a write-back operation, the write-back operation writing back configuration information or data information from the flash die chip to the processor 100 for the next processing of the processor 100. For example, the processor 100 stores the configuration information written back from the flash die chip, or transmits the data information written back from the flash die chip to the user. In the embodiments of this application, the DQ operation instruction is executed by the DQ write-back unit 150 when a write-back is performed, and the CA operation instruction is executed by the CA write-back unit 160 when a write-back is performed.

[0053] In the embodiment of this application, when the DQ operation command performs a write-back, the DQ write-back unit 150 acquires first information from the flash die chip via the DQ bus. The DQ write-back unit 150 acquires the first information by converting the analog signal transmitted by the flash die chip via the DQ bus into a data signal of the first information. In the embodiment of this application, the first information may be any data stored in the flash die chip, for example, valid data information stored in the flash die chip by a user.

[0054] After the DQ write-back unit 150 acquires the first information, it writes the first information to the data storage space 170 within the processor 100. The data storage space 170 is a space within the processor 100 dedicated to storing data content, and any data within the processor can also be stored in the data storage space 170. In addition to writing data information, the data storage space 170 can also write data information outside the processor 100. For example, the area outside the processor 100 may include a transmission path or data path dedicated to data processing, and the data storage space 170 may write data information unrelated to the processor 100 to a data path outside the processor 100. Furthermore, in the process of the DQ instruction execution unit 130 transmitting target data to the flash die chip via the DQ bus, the target data may originate from the data storage space 170. If the data storage space 170 cannot provide the target data, the target data may be obtained from data information outside the processor 100 via the data storage space 170.

[0055] Accordingly, in the embodiment of this application, when the CA operation command is written back, the CA write-back unit 160 acquires second information from the flash die chip via the CA bus. The CA write-back unit 160 acquires the second information by converting the analog signal transmitted by the flash die chip via the CA bus into a data signal of the second information. In the embodiment of this application, the second information may be setting information relating to the flash die chip.

[0056] After the CA write-back unit 160 acquires the second information, it writes the second information to the data storage space 170 in the processor 100. Since the data storage space 170 contains the second information relating to the CA operation instruction, the instruction analysis unit 120 can also acquire data information from the data storage space 170 during the process of analyzing the target instruction, for example, by acquiring the register information of the modified flash die chip.

[0057] In the embodiment of this application, the DQ write-back unit and the CA write-back unit enable the write-back operation of the target instruction, thereby widening the instruction range of the target instruction to the flash die chip and enabling the flash die chip to perform more operations.

[0058] In the embodiment of this application, as shown in Figure 2, a first instruction pipeline is formed by an instruction acquisition unit 110, an instruction analysis unit 120, a DQ instruction execution unit 130, and a DQ write-back unit 150, and a second instruction pipeline is formed by an instruction acquisition unit 110, an instruction analysis unit 120, a CA instruction execution unit 140, and a CA write-back unit 160. When the target conditions are met, the first designation unit in the first target unit of the first instruction pipeline and the second designation unit in the second target unit of the second instruction pipeline are executed in parallel. The first designation unit includes at least one of the DQ instruction execution unit 130 and the DQ write-back unit 150, and the second designation unit includes at least one of the CA instruction execution unit 140 and the CA write-back unit 160.

[0059] In the embodiment of this application, if the target condition is met, within the first clock cycle, the CA write-back unit in the second instruction pipeline executes the target instruction E. Simultaneously, the DQ instruction execution unit in the first instruction pipeline executes the target instruction F, which also includes a write-back operation. Within the second clock cycle, the CA write-back unit in the second instruction pipeline still executes the target instruction E, and the DQ write-back unit in the first instruction pipeline executes the target instruction F, thereby achieving parallel execution of the first designation unit in the first target unit of the first instruction pipeline and the second designation unit in the second target unit of the second instruction pipeline.

[0060] In the embodiment of this application, if the target condition is not met, while the target instruction is being executed by any one instruction pipeline (e.g., the first instruction pipeline), another instruction pipeline (e.g., the second instruction pipeline) does not execute an instruction. For example, the DQ write-back unit of the first instruction pipeline executes the target instruction G. Because the target condition is not met, the CA instruction execution unit in the second instruction pipeline cannot execute the target instruction H, and the CA instruction execution unit executes the target instruction H after the execution of the target instruction G is completed.

[0061] In the embodiment of this application, the parallel execution method of the first designation unit in the first target unit of the first instruction pipeline and the second designation unit in the second target unit of the second instruction pipeline makes the processor more efficient at processing target instructions, and by limiting the target conditions, the processor according to the embodiment of this application can set the logical order of processing target instructions more rationally.

[0062] In the embodiments of this application, the processor further has an instruction storage space for storing various instructions compatible with a flash die chip, the instruction storage space for storing the target instruction. The instruction storage space may include the logic of an instruction compatible with a flash die chip, which is pre-configured based on the flash die chip manufacturer's instruction manual. For example, the target instruction is coded and assembled based on the flash die chip manufacturer's instruction manual to obtain the target instruction corresponding to the instruction manual, i.e., a target instruction compatible with a flash die chip. The instruction storage space can store target instructions compatible with flash die chips from multiple manufacturers, thereby enabling compatibility with a greater number of flash die chips.

[0063] In the embodiment of this application, an application layer instruction is obtained from the instruction storage space and a corresponding target instruction is obtained by matching, thereby enabling the instruction acquisition unit (110 in Figure 1 or Figure 2) to acquire the target instruction from the instruction storage space. In the embodiment of this application, after the instruction acquisition unit acquires an instruction from the application layer, a target instruction corresponding to the application layer instruction may be obtained by performing a match in the instruction storage space.

[0064] By modifying the target instructions stored in the instruction memory space of the processor, it becomes possible to more freely adapt the processor to different flash die chips from different memory device manufacturers. Compared to related technologies, the processor according to the embodiment of this application has better compatibility and adaptability, as well as cost reduction.

[0065] In the embodiments of this application, the target instruction is an instruction that conforms to the target format. Figure 3 is an architectural diagram of the target format according to the embodiments of this application. As shown in Figure 3, the target format of the target instruction according to the embodiments of this application includes a bus type field, a data field, a write-back instruction field, a length field, a waveform instruction field, and a lock field. The bus type field (BUS_type) indicates whether the type of bus used for the target instruction is a CA bus or a DQ bus. The data field (Data) indicates the content of the data to be transmitted, and the data content is from the target instruction and / or data storage space. The write-back instruction field (R / W) indicates whether the target instruction has a write-back operation. The length field (Length) indicates the length of the current operation. The waveform instruction field (BUS_wave) indicates the signal timing operation of the target instruction. The lock field (Lock) indicates whether the target instruction is executed in synchronization with the next instruction on a different bus.

[0066] In the embodiments of this application, the instruction analysis unit of the processor determines the instruction type of the target instruction based on the bus type field in the target format. If the bus type field indicates that the bus type used by the target instruction is a CA bus, the target instruction is sent to the CA instruction execution unit. If the bus type field indicates that the bus type used by the target instruction is a DQ bus, the target instruction is sent to the DQ instruction execution unit.

[0067] In the embodiments of this application, the data field (Data) is for indicating the content of the data to be transmitted. Depending on the indication, the data content may be from the data storage space. If the data content to be transmitted by the target instruction is not in the data storage space, the instruction analysis unit may obtain the target data from outside the processor (e.g., from a data path) using the data storage space.

[0068] In the embodiment of this application, the write-back instruction field (R / W) indicates whether or not the target instruction has a write-back operation. If the write-back instruction field (R / W) indicates that the target instruction has a write-back operation, after the instruction execution unit (DQ instruction execution unit and / or CA instruction execution unit) has executed, the write-back unit (DQ write-back unit and / or CA write-back unit) acquires the write-back target information (first information and / or second information) from the flash die chip. If the write-back instruction field (R / W) indicates that there is no write-back operation for the target instruction, after the execution of the instruction execution unit is completed, it is considered that the execution of the target instruction has already been completed.

[0069] In the embodiments of this application, the Length field indicates the length of the current operation. Furthermore, the Length field indicates the length of the waveform operation of the DQ bus and / or CA bus I / O interface on the processor side.

[0070] In the embodiment of this application, the waveform instruction field (BUS_wave) indicates the signal timing operation of the target instruction, controls the transition of each physical line in the transmission bus connected to the flash die, and by causing different physical line transitions, different waveform operations are formed, and furthermore, the flash die chip executes different target instructions.

[0071] In the embodiments of this application, the waveform behavior of the I / O interface of the DQ bus and / or CA bus on the processor side is determined by at least one of the length field and the waveform instruction field (BUS_wave).

[0072] In the embodiments of this application, the Lock field indicates whether the target instruction is to be executed synchronously with the next instruction on a different bus, and the next instruction on a different bus and the target instruction may be instructions on the same flash die chip or instructions on different flash die chips, and is not specifically limited in the embodiments of this application. If the Lock field of the target instruction indicates that the target instruction is not to be executed synchronously with the next instruction on a different bus, it can be understood that the target instruction currently being processed locks the transmission bus at the current time, preventing instructions on different transmission buses from being executed simultaneously.

[0073] In the embodiments of this application, the target format allows the processor to better control the execution operation between the CA bus and the DQ bus (waveforms between the CA bus and / or DQ bus interfaces, i.e., the signal operation of the target instruction), data, parallel or exclusive operations, etc.

[0074] In embodiments of this application, the target condition can be associated with the lock field. The target condition includes the lock field indicating that the target condition is to be executed synchronously with the next instruction on a different bus. If the lock field indicates that the target instruction is executable synchronously with the next instruction on a different bus, then the first target unit in the first instruction pipeline and the second target unit in the second instruction pipeline according to embodiments of this application can be executed in parallel, that is, the DQ bus and the CA bus can transmit data information simultaneously, and the target instruction of the flash die chip can be processed with high efficiency.

[0075] In the embodiment of this application, the instruction analysis unit can determine the instruction type and also determine whether or not the target condition is met based on the lock field (BUS lock), thereby solving the problem of instruction exclusion.

[0076] In the embodiment of this application, the processor can simultaneously control the CA bus and / or DQ bus by simultaneously controlling the first instruction pipeline and / or the second instruction pipeline. Since the processor simultaneously controls the CA bus and / or DQ bus, the operation of the other transmission bus can be appropriately set based on the operation of any one of the transmission buses, and the mutually exclusive relationship of instruction operations between these two transmission buses can be controlled more easily.

[0077] In the embodiments of this application, each unit in the first instruction pipeline can execute a plurality of first target instructions in parallel. The plurality of first target instructions are different instructions for different flash die chips, for example, when the CA instruction execution unit executes a first target instruction for a first flash die chip, the instruction analysis unit executes a first target instruction for a second flash die chip, and the instruction acquisition unit executes a first target instruction for a third flash die chip. Accordingly, each unit in the second instruction pipeline can execute a plurality of second target instructions in parallel, the plurality of second target instructions are different instructions for different flash die chips, and the target instruction includes a first target instruction and a second target instruction.

[0078] In the embodiment of this application, each unit in the first instruction pipeline sequentially executes a plurality of third target instructions, and the plurality of third target instructions are different instructions for the same flash die chip (i.e., instructions for one die (DIE)). For example, for the same flash die chip, this may include a CA instruction to start data read transmission, a DQ instruction to read transmission, and a CA instruction to end data read transmission. Within the first clock cycle, the instruction acquisition unit acquires the CA instruction to start data read transmission. Within the second clock cycle, the instruction analysis unit analyzes the CA instruction to start data read transmission, and the instruction acquisition unit acquires the DQ instruction to read transmission. Within the third clock cycle, the CA instruction execution unit of the second instruction pipeline executes the CA instruction to start data read transmission, the instruction analysis unit analyzes the DQ instruction to read transmission, and the instruction acquisition unit acquires the CA instruction to end data read transmission. In this way, each unit in the first instruction pipeline sequentially executes a plurality of third target instructions, and the plurality of third target instructions are different instructions for the same flash die chip. Accordingly, each unit in the second instruction pipeline sequentially executes a plurality of fourth target instructions, where the plurality of fourth target instructions are different instructions for the same flash die chip. In the embodiment of this application, the heterogeneous processing of the first instruction pipeline and / or the second instruction pipeline in the processor enables more efficient processing of target instructions.

[0079] Figure 4 is a block diagram of the configuration of an instruction processing unit according to an embodiment of the present application. As shown in Figure 4, the instruction processing unit 300 according to an embodiment of the present application includes a flash die chip 320 and a processor 310, wherein the processor 310 is connected to the flash die chip 320 by a CA bus and the processor 310 is connected to the flash die chip 320 by a DQ bus. The processor 310 in the instruction processing unit 300 according to an embodiment of the present application may be the processor 100 shown in Figure 1 or Figure 2, and therefore, a specific implementation of this embodiment can be made by referring to the implementation of the processor described above, and a redundant explanation will be omitted. In the embodiment of the present application, the instruction processing unit may be a device that includes the hardware equipment of the processor and the hardware equipment of the flash die chip shown in Figure 1 or Figure 2.

[0080] In the instruction processing device shown in Figure 4 according to an embodiment of this application, the number of flash die chips is N, each of the N flash die chips is connected to the processor by a CA bus, and each of the N flash die chips is connected to the processor by a DQ bus, where N is a positive integer of 1 or more. There is a one-to-one correspondence between the flash die chips and the dies (DIEs), and target instructions for the same flash die chip can be executed sequentially. When the CA bus executes a CA instruction for the first flash die chip, the DQ bus executes a DQ instruction for the second flash die chip, thereby enabling parallel transmission and highly efficient processing of target instructions.

[0081] In embodiments of this application, the waveform instruction field in the target instruction includes a chip selection instruction field. The chip selection instruction field is used by the processor to identify a target flash die chip from N flash die chips, and the chip selection instruction field is used to instruct the target flash die chip to execute the target instruction. Based on the chip selection instruction field, the instruction analysis unit in the processor identifies the chip selection line of the target flash die chip from the bus and controls the chip selection line to generate fluctuations, thereby enabling the pins of the target flash die chip to receive signals, thus enabling the processor to identify the target flash die chip from N flash die chips. When the target flash die chip receives the waveform of the target instruction via its pins, it can execute the target instruction. The chip selection instruction field improves the accuracy of identifying the target flash die chip from N flash die chips.

[0082] In the embodiment of this application, the instruction processing device shown in Figure 4 may be a control device that includes the processor and flash die chip shown in Figure 1 or Figure 2.

[0083] Embodiments of this application further provide a storage device. The storage device may be a solid-state drive (SSD), a universal flash storage (UFS), or the like, including the control device described above.

[0084] Embodiments of this application further provide electronic devices. The electronic devices include the above-mentioned storage devices. The electronic devices may be terminal devices (e.g., such as laptop computers) of the above-mentioned solid-state drives or universal flash storage, or they may be servers including the above-mentioned storage devices.

[0085] Furthermore, the embodiments of this application provide an instruction processing method, which is executed by a processor. The processor may be the processor according to the embodiments of this application shown in Figure 1 or Figure 2, or it may be another processor capable of implementing the SCA protocol. Figure 5 is a flowchart of the instruction processing method according to the embodiments of this application. As shown in Figure 5, the instruction processing method according to the embodiments of this application includes the following steps.

[0086] In step 410, the target instruction is obtained.

[0087] In step 420, an analysis process is performed on the target instruction to determine the instruction type of the target instruction, and the instruction type includes either a CA operation instruction or a DQ operation instruction.

[0088] If the instruction type is a CA operation instruction, step 440 is executed; if the instruction type is a DQ operation instruction, step 430 is executed.

[0089] In step 420 according to the embodiment of this application, the target instruction is an instruction that conforms to a target format. The target format includes a lock field to indicate whether the target instruction is to be executed synchronously with the next instruction on a different bus. The instruction type of the target instruction is determined, and based on the lock field of the target instruction, it is determined whether steps 430 and 440 can be executed in parallel. If the lock field indicates a lock, steps 430 and 440 cannot be executed in parallel. If the lock field indicates no lock, steps 430 and 440 can be executed in parallel.

[0090] In step 430, if the instruction type is a DQ operation instruction, the target data is transmitted to the flash die chip via the DQ bus.

[0091] In step 440, if the instruction type is a CA operation instruction, CA information or CA-related configuration information is transmitted to the flash die chip via the CA bus.

[0092] If the CA operation command performs a write-back, step 460 is executed, and if the DQ operation performs a write-back, step 450 is executed.

[0093] In step 450, if the DQ operation instruction performs a write-back, it obtains first information from the flash die chip via the DQ bus and writes the first information to the data storage space within the processor.

[0094] In step 460, if the CA operation command performs a write-back, it obtains second information from the flash die chip via the CA bus and writes the second information to the data storage space within the processor.

[0095] In the embodiments of this application, by performing the above method with the processor according to the embodiments of this application, the processing speed of target instructions can be improved, the exclusion relationship between the DQ bus and the CA bus can be controlled, and the problem of mutual exclusion between instructions can be solved.

[0096] To better understand the processor according to the embodiments of this application, examples are provided below. These examples are illustrative and not limiting.

[0097] Figure 6 is an architectural diagram of the external environment of the processor according to an embodiment of this application. As shown in Figure 6, in the embodiment of this application, after the SCA protocol processor shown in Figure 1 or Figure 2 receives an operation request from the application layer, it converts the application layer operation into an operation on the DQ bus and CA bus. The processor enables synchronous control of the CA bus and DQ bus of the flash die interface, and enables parallel execution of transmission on the two buses. In the process of processing a target instruction by the SCA protocol processor shown in Figure 1 or Figure 2, target data can be obtained from the data path. After the SCA protocol processor receives the digital signal in which the target instruction has been executed, the physical layer bus (DQ bus and CA bus) converts the digital signal into an analog signal, which the flash die chip then reads. Accordingly, in the write-back process, the physical layer bus converts the analog signal fed back from the flash die chip into a digital signal.

[0098] Figure 7 is an architecture diagram of a processor according to an embodiment of the present application. As shown in Figure 7, the processor according to an embodiment of the present application (i.e., the SCA protocol processor shown in Figure 7) includes control by two different instruction pipelines through a superscalar pipeline design. The roles of each unit of the processor shown in Figure 7 are as follows:

[0099] The instruction retrieval unit reads instructions from the instruction memory space.

[0100] The instruction analysis unit processes the instruction, determines whether the instruction is a CA operation instruction or a DQ operation instruction, and then sends it to the CA instruction execution unit and the DQ instruction execution unit, respectively, based on the instruction type.

[0101] The processor shown in Figure 7 can execute two execution units in parallel. The DQ instruction execution unit sends data to the flash die via the DQ bus physical layer. The CA instruction execution unit sends commands and address setting data to the flash die via the CA bus physical layer.

[0102] The processor shown in Figure 7 can have two write-back units running in parallel. The DQ write-back unit reads data from the flash die using the DQ bus physical layer and writes it to the internal storage space of the main control chip (i.e., the data storage space shown in Figure 7). The CA write-back unit reads data information such as settings and IDs from the flash die using the CA bus physical layer and writes it to the internal space of the main control chip (i.e., the data storage space shown in Figure 7).

[0103] The instruction execution pipeline operation in the processor shown in Figure 7 is illustrated as follows:

[0104] The application layer's operations on the flash die are executed according to instructions in the SCA protocol processor shown in Figure 7.

[0105] Instructions in a processor are executed in a pipeline in four stages: instruction acquisition, instruction analysis, instruction execution, and write-back.

[0106] Processor instructions are classified into two types: CA bus operations and DQ bus operations.

[0107] During the instruction execution phase, the CA bus and DQ bus of the flash die interface are controlled, respectively.

[0108] Write-back operations read data or configuration information from the flash die and write it to the data storage space of the main control chip; however, some instructions do not require writing back.

[0109] In the processor according to the embodiment of this application, the instruction storage space controls and interacts with the application layer, and the data storage space interacts with the data path. Data stored in the data storage space that is not related to the processor itself is written back to the data path. During the execution of a DQ instruction, the system first considers reading data from the data storage space, and if the data storage space is unavailable, it reads from the data path using the data storage space. The data information written back by the CA instruction is further stored in the data storage space, so that the instruction analysis unit can read the result of the previous instruction's execution if it needs it.

[0110] Furthermore, the processor according to the embodiment of this application can use a general-purpose instruction architecture, for example, the instruction architecture shown in Figure 3. Based on the instruction format shown in Figure 3, the processor can control whether instructions on the DQ bus and CA bus can be executed in parallel, that is, it can control whether there is an exclusion relationship between instructions, and can also control the waveform operation, transmitted and received data and operation of each instruction at the I / O interface.

[0111] To better understand the instruction processing method according to the embodiments of this application, an example will be given below. This example is illustrative and not limiting.

[0112] Figure 8 is an architectural diagram of the target instruction processing process according to an embodiment of this application. As shown in Figure 8, in the target instruction processing process according to an embodiment of this application, the processor shown in Figure 1 or Figure 2 sequentially executes the following instructions A to I using instruction sequence and double instruction pipeline.

[0113] Instructions B and F are data transmission instructions (DQ instructions) and are transmitted on the DQ bus (BUS). Here, B is a data read instruction and requires the DQ BUS data to be written back, while F is a data write instruction and does not require the data to be written back.

[0114] Instructions A, C, D, E, H, and I are command and address-related instructions (CA instructions) and are transmitted via the CA BUS. Here, H is a state read instruction via the CA BUS, and requires the writing back of CA BUS data. The other instructions only require the transmission of CA signals and do not require the writing back of data.

[0115] Instructions B and C can be executed in parallel because they do not interfere with each other regarding the interface BUS resources they request.

[0116] Instructions F and H can be executed in parallel because they do not interfere with each other regarding the interface BUS resources they request.

[0117] Commands A, B, and D are each DIE 1 instructions, and these three operations can be executed sequentially, but not in parallel. However, while B is being executed on the DQ BUS, the CA BUS operation of C-DIE2 can be executed.

[0118] Commands E, F, and I are each DIE n instructions, and these three operations can be executed sequentially but not in parallel. However, while F is being executed on the DQ BUS, the H-DIE m CA BUS operation can be executed.

[0119] Specifically, within the first clock cycle (considering the period between the two dotted lines above and below as one clock cycle), the instruction acquisition unit of the processor acquires the data transmission start command A of DIE 1.

[0120] Within the second clock cycle, the processor's instruction acquisition unit acquires the data read transmission instruction B of DIE 1, and the processor's instruction analysis unit acquires instruction A, which was acquired by the instruction acquisition unit within the first clock cycle.

[0121] Within the third clock cycle, the processor's instruction acquisition unit acquires the command + address C of DIE 2, the processor's instruction analysis unit acquires instruction B acquired by the instruction acquisition unit within the second clock cycle, and the CA instruction execution unit of the second instruction pipeline executes instruction A.

[0122] Within the fourth clock cycle, the processor's instruction acquisition unit acquires the data transmission termination instruction D of DIE 1, the processor's instruction analysis unit acquires instruction C acquired by the instruction acquisition unit within the third clock cycle, the DQ instruction execution unit of the first instruction pipeline executes instruction B, and the CA bus acquires the data transmission start instruction (i.e., SCE) of DIE 1.

[0123] In this way, the design method for a superscalar processor using heterogeneous pipelines enables control of the SCA protocol, synchronous control of the CA bus and DQ bus of the flash die interface, and parallel execution of transmission on the two buses.

[0124] In the embodiment of this application, the processor configuration converts application layer control into SCA protocol waveforms for the NAND chip I / O interface, improving flexibility and allowing the instruction memory space to accommodate standard protocols and custom commands from various manufacturers' memory chips (Flash). The superscalar design provides two heterogeneous pipelines, each handling the control of the CA bus and DQ bus, enabling parallel execution of signal transmission on the two buses. Since the two pipelines share instruction acquisition and analysis units, the processor hardware area can be reduced. Furthermore, controlling the operation of both the CA and DQ buses with the same processor makes it easier to control the mutually exclusive relationship between instruction operations on these two buses. In the embodiment of this application, a general-purpose instruction architecture is used to control the execution operation (waveforms), data, and parallel or exclusive operations of the CA and DQ buses.

[0125] Processing target instructions using the embodiment of this application also offers the following advantages: 1. Synchronous control of the operation of the DQ bus and CA bus is possible, allowing control over the possibility of parallel execution between I / O operations and the mutual exclusion relationship between the two buses. 2. Depending on the processor method, the sequence and timing of command / address and data transmission can be freely specified, supporting various flexible flash operations and allowing for greater flexibility in adapting to various operation commands from different manufacturers. 3. The superscalar design requires only one execution unit and one write-back unit, resulting in a relatively smaller resource area compared to an approach where the CA bus and DQ bus are controlled by two independent processors.

[0126] Embodiments of this application further provide a computer-readable storage medium. When a program or instruction is stored in the readable storage medium and the program or instruction is executed by a processor, each step according to the embodiment of the above method is realized, achieving similar technical effects, and to avoid redundant explanation, the description is omitted here.

[0127] The aforementioned readable storage medium includes computer-readable storage media such as computer read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0128] Embodiments of this application provide a computer program product. The program product is stored in a storage medium, and each process according to the embodiment of the above method is realized by the execution of the program product by at least one processor, thereby achieving similar technical effects. To avoid redundant explanation, the details are omitted here.

[0129] The terms “having,” “including,” and any variations thereof are intended to encompass non-exclusive inclusion. Thus, a process, method, article, or apparatus comprising a set of elements is not necessarily limited to these elements and may include other elements not explicitly stated or specific to these processes, methods, articles, or apparatus. Unless otherwise specified, the expression “including” does not exclude situations where a process, method, article, or apparatus comprising such element also has other similar elements. Furthermore, the scope of methods and apparatus in embodiments of this application is not limited to performing functions in the order shown or described, but may include performing functions essentially simultaneously or in reverse order depending on the functions involved. For example, a described method may be performed in a different order than described, and various steps may be added, omitted, or combined. Also, features described with reference to one example may be combined in other examples.

[0130] As those skilled in the art will see from the above description of the embodiments, the methods according to the above embodiments can be implemented by adding a general-purpose hardware platform to the software. Of course, it is also possible to implement it with hardware, but in many cases the former is a more preferred embodiment. With this understanding, the technical proposal of this application itself, or the parts that can contribute to the prior art, can be implemented in the form of a computer software product. The computer software product is stored on a storage medium (ROM / RAM, magnetic disk, optical disk) and includes a plurality of commands for executing the methods according to each embodiment of this application by a terminal (mobile phone, computer, server, or internet device, etc.).

[0131] While embodiments of this application have been described above with reference to the drawings, this application is not limited to the specific embodiments described above. The specific embodiments described above are illustrative and not limiting. A person skilled in the art can design many more forms based on the suggestions of this application, as long as they do not deviate from the spirit and claims of this application, and all of these will fall within the scope of protection of this application.

Claims

1. Includes an instruction acquisition unit, an instruction analysis unit, a DQ instruction execution unit, and a CA instruction execution unit. The instruction acquisition unit is configured to acquire a target instruction and transmit it to the instruction analysis unit. The instruction analysis unit is configured to perform analysis on the target instruction to determine the instruction type of the target instruction, and the instruction type includes a command / address CA operation instruction or a data DQ operation instruction. The DQ instruction execution unit is configured to transmit target data to the flash die chip via the DQ bus when the instruction type is a DQ operation instruction. The CA instruction execution unit is configured to transmit CA information or CA-related configuration information to the flash die chip via the CA bus when the instruction type is a CA operation instruction. The instruction acquisition unit, the instruction analysis unit, and the first target unit form a first instruction pipeline, and the instruction acquisition unit, the instruction analysis unit, and the second target unit form a second instruction pipeline. If the target conditions are met, the first instruction pipeline and the second instruction pipeline execute in parallel, the first target unit includes the DQ instruction execution unit, and the second target unit includes the CA instruction execution unit. A processor characterized by the following features.

2. The processor further includes a DQ write-back unit and a CA write-back unit, The DQ write-back unit is configured to, when the DQ operation command is written back, acquire first information from the flash die chip via the DQ bus and write the first information to the data storage space within the processor. The CA write-back unit is configured to, when performing a write-back of the CA operation command, acquire second information from the flash die chip via the CA bus and write the second information to the data storage space within the processor. The first target unit further includes the DQ write-back unit, and the second target unit further includes the CA write-back unit. The processor according to feature 1.

3. If the target condition is met, the first designation unit in the first target unit of the first instruction pipeline and the second designation unit in the second target unit of the second instruction pipeline execute in parallel. The first designated unit includes at least one of the DQ instruction execution unit and the DQ write-back unit, and the second designated unit includes at least one of the CA instruction execution unit and the CA write-back unit. The processor according to feature 2.

4. The processor has an instruction storage space for storing various instructions that fit the flash die chip, and the instruction storage space is for storing the target instruction. The processor according to any one of claims 1 to 3.

5. The target instruction is an instruction that conforms to the target format, the target format including a bus type field, a data field, a write-back instruction field, a length field, a waveform instruction field, and a lock field. The aforementioned bus type field is for indicating whether the type of bus used for the target instruction is a CA bus or a DQ bus. The aforementioned data field is intended to indicate the content of the data to be transmitted. The aforementioned write-back instruction field is for indicating whether or not the target instruction has a write-back operation. The aforementioned length field is for indicating the length of the current operation, The waveform instruction field is for indicating the signal timing operation of the target instruction, The aforementioned lock field is intended to indicate whether the target instruction is executed in sync with the next instruction on a different bus. The processor according to any one of claims 1 to 3.

6. The aforementioned target condition includes indicating that the lock field will execute the target instruction in sync with the next instruction on a different bus. The processor according to feature 5.

7. Each unit in the first instruction pipeline executes a plurality of first target instructions in parallel, wherein the plurality of first target instructions are different instructions for different flash die chips, and each unit in the second instruction pipeline executes a plurality of second target instructions in parallel, wherein the plurality of second target instructions are different instructions for different flash die chips, and the target instruction includes a first target instruction and a second target instruction. or, Each unit in the first instruction pipeline sequentially executes a plurality of third target instructions, the plurality of third target instructions being different instructions for the same flash die chip, and each unit in the second instruction pipeline sequentially executes a plurality of fourth target instructions, the plurality of fourth target instructions being different instructions for the same flash die chip, and the target instruction includes a third target instruction and a fourth target instruction. The processor according to any one of claims 1 to 3.

8. The system comprises a flash die chip and a processor according to any one of claims 1 to 7, wherein the processor is connected to the flash die chip by a CA bus and the processor is connected to the flash die chip by a DQ bus. An instruction processing device characterized by the following:

9. The number of flash die chips is N, each of the N flash die chips is connected to the processor by a CA bus, and each of the N flash die chips is connected to the processor by a DQ bus, and N is a positive integer of 1 or more. The instruction processing device according to claim 8.

10. The target instruction is an instruction that conforms to the target format, the target format including a bus type field, a data field, a write-back instruction field, a length field, a waveform instruction field, and a lock field. The waveform instruction field in the target instruction includes a chip selection instruction field, which is used by the processor to determine a target flash die chip from N flash die chips, and which is used to instruct the target flash die chip to execute the target instruction. The instruction processing device according to feature 9.

11. The instruction processing device is a control device. The instruction processing device according to any one of claims 8 to 10.

12. The instruction processing apparatus includes the one described in claim 11. A memory device characterized by the following features.

13. Includes the storage device described in claim 12. An electronic device characterized by the following features.

14. A method for processing instructions executed by a processor, The instruction processing method described above is: Steps to obtain the target instruction, The steps include performing an analysis on the target instruction, determining the instruction type of the target instruction, and determining that the instruction type includes a command / address CA operation instruction or a data DQ operation instruction, If the instruction type is a DQ operation instruction, the steps include: transmitting target data to the flash die chip via the DQ bus; If the instruction type is a CA operation instruction, the steps include transmitting CA information or CA-related setting information to the flash die chip via the CA bus, When the DQ operation instruction performs a write-back, it includes the steps of obtaining first information from the flash die chip via the DQ bus and writing the first information to the data storage space within the processor. When performing a write-back, the CA operation command includes the steps of obtaining second information from the flash die chip via the CA bus and writing the second information to the data storage space within the processor. A method for processing instructions characterized by the following:

15. A storage medium, When a program is stored in the storage medium and the program is executed, the instruction processing method described in claim 14 is realized. A storage medium characterized by the following features.

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