Semiconductor device package with improved cooling

Abstract

This disclosure relates to a semiconductor package. The semiconductor package includes a semiconductor die having a first side and a second side, the second side being opposite to the first side; a lead frame on the first side of the semiconductor die; and a heat spreader on the second side of the semiconductor die. The lead frame is embedded in a molding material. The heat spreader has a thickness greater than the thickness of the lead frame in order to dissipate heat associated with power surges through the heat spreader.

Description

Technical Field

[0001] [Cross - Reference to Related Applications] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 511,826, filed on July 3, 2023, entitled "SEMICONDUCTOR DEVICE PACKAGE WITH IMPROVED COOLING", the disclosure of which is hereby incorporated by reference in its entirety for all purposes.

[0002] This application relates to semiconductor device packages. In particular, some embodiments relate to semiconductor packages having a cooling structure on one side of a semiconductor die and filled with a molding material within the semiconductor package.

Background Art

[0003] Semiconductor devices are used in a wide variety of applications. In some applications, semiconductor devices may be subject to high electrical loads that can result in significant heating of the semiconductor device. There may be technical problems associated with high electrical loads, such as harmful heating of the semiconductor device from high loads. In addition, such significant heating generated from the semiconductor die can cause thermal stress on a carrier such as a printed circuit board on which the semiconductor devices are integrated.

Summary of the Invention

[0004] The technological innovations described in the claims each have several aspects, and no single one of them alone bears all of its desirable attributes. Without limiting the claims, some of the prominent features of this disclosure are briefly described here.

[0005] One aspect of the present disclosure is a packaged integrated circuit device with power surge heat dissipation. The packaged integrated circuit device includes a semiconductor die having a first side and a second side, the second side being opposite to the first side; a lead frame on the first side of the semiconductor die, which is embedded in a molding material; and a heat spreader on the second side of the semiconductor die, which has a thickness of at least 2.5 millimeters.

[0006] In one embodiment, the heat spreader and lead frame may be configured to maintain the semiconductor die at a temperature below 200 degrees Celsius when subjected to a surge load of up to 160 watts for 1 second from a steady state.

[0007] In one embodiment, the thickness of the heat spreader may be at least four times the thickness of the semiconductor die. The area of ​​the heat spreader may be larger than the area of ​​the semiconductor die, and the heat spreader may extend beyond the semiconductor die. In addition, the thickness of the heat spreader may be between four and twenty times the thickness of the semiconductor die.

[0008] In one embodiment, the thickness of the heat spreader may be at least 2.5 times the thickness of the lead frame.

[0009] In one embodiment, the packaged integrated circuit device may have a recess in the molding material on the side of the packaged integrated circuit device opposite to the heat spreader.

[0010] In one embodiment, both the lead frame and the heat spreader can be bonded to the semiconductor die.

[0011] In one embodiment, the semiconductor die may include a field-effect transistor. In addition, the field-effect transistor may be a gallium nitride field-effect transistor.

[0012] In one embodiment, the lead frame may include a main frame, and a plurality of leads may extend from the main frame. In addition, each of the plurality of leads may be flat on the outside of the molding material. Furthermore, each of the plurality of leads may include a wettable flank.

[0013] In one embodiment, the heat spreader may be a solid layer that may contain copper.

[0014] In one embodiment, the heat spreader may have a multilayer structure that includes a first metal layer, a second metal layer, and a ceramic layer positioned between the first and second metal layers.

[0015] Another aspect of the present disclosure is an integrated circuit assembly with power surge heat dissipation. The integrated circuit assembly includes a printed circuit board, a packaged integrated circuit device on the printed circuit board including a semiconductor die, a lead frame positioned between the semiconductor die and the printed circuit board, and a heat spreader positioned on the side of the semiconductor die opposite to the lead frame, and a cooling structure that is in thermal contact with the heat spreader. The heat spreader has a thickness of at least 2.5 millimeters.

[0016] In one embodiment, the packaged integrated circuit device may include a molding material or other separator to provide electrical and / or thermal insulation between the printed circuit board and the lead frame. In addition, the packaged integrated circuit device may have recesses in the molding material on the side facing the printed circuit board.

[0017] In one embodiment, the packaged integrated circuit device may further include a second packaged integrated circuit device on a printed circuit board, the second packaged integrated circuit device may include a second heat spreader that is in thermal contact with a cooling structure.

[0018] In one embodiment, the cooling structure may include a heat sink and / or a cooling plate.

[0019] Another aspect of the present disclosure is a packaged integrated circuit device with power surge heat dissipation. The packaged integrated circuit device includes a semiconductor die having a first side and a second side, the second side being opposite to the first side; a lead frame on the first side of the semiconductor die, which is embedded in a molding material; and a cooling structure on the second side of the semiconductor die, the cooling structure comprising two metal layers and a ceramic layer positioned between the two metal layers. The semiconductor die includes a field-effect transistor. In addition, the thickness of the cooling structure exceeds 2.5 millimeters.

[0020] For the purpose of summarizing this disclosure, specific aspects, advantages, and novel features of the technological innovation are described herein. It should be understood that not all of such advantages can necessarily be achieved according to any particular embodiment. Thus, the technological innovation may be embodied or performed to achieve or optimize one or more advantages or groups of advantages as taught herein, without necessarily achieving other advantages as taught or suggested herein. [Brief explanation of the drawing]

[0021] Some features, aspects, and advantages of this disclosure are described with reference to drawings of specific embodiments, which are intended to illustrate but not limit this disclosure. It should be understood that the accompanying drawings incorporated herein and forming part of this specification are for illustrative purposes only and may not be to scale.

[0022] [Figure 1A] This is a temperature-time plot of a packaged integrated circuit (IC) device according to several embodiments.

[0023] [Figure 1B] This includes heatmaps of the temperature distribution of conventional packaged IC devices and packaged devices according to several embodiments.

[0024] [Figure 2] Schematic cross-sectional view of an example of a packaged IC device utilizing double-sided cooling according to some embodiments.

[0025] [Figure 3A] Schematic cross-sectional view of an example of a packaged IC device using single-sided cooling according to some embodiments.

[0026] [Figure 3B] Schematic plan view of an example of an electrical path through the packaged IC device of FIG. 3A.

[0027] [Figure 4] Schematic cross-sectional view of a semiconductor die connected to a heat slug by solder on a first side and to a printed circuit board (PCB) facing a lead frame by solder on a second side opposite the first side.

[0028] [Figure 5] Schematic cross-sectional view of an example of a surface mount device mounted on a printed circuit board according to some embodiments.

[0029] [Figure 6] Schematic cross-sectional view of an exemplary embodiment of a packaged IC device including a local recess.

[0030] [Figure 7] Shows a bottom perspective view of a packaged IC device including a local recess according to some embodiments.

[0031] [Figure 8] Schematic cross-sectional view of an exemplary embodiment of an IC assembly including a plurality of packaged IC devices according to some embodiments.

[0032] [Figure 9A] These are schematic cross-sectional views of various cross-sections of exemplary embodiments of packaged IC devices including a multilayer cooling structure, according to several embodiments. [Figure 9B] These are schematic cross-sectional views of various cross-sections of exemplary embodiments of packaged IC devices including a multilayer cooling structure, according to several embodiments. [Figure 9C] These are schematic cross-sectional views of various cross-sections of exemplary embodiments of packaged IC devices including a multilayer cooling structure, according to several embodiments.

[0033] [Figure 10A] Figure 9A is a schematic diagram of an example of a three-dimensional view of a packaged IC device.

[0034] [Figure 10B] Figure 10A is an exploded view of a packaged IC device.

[0035] [Figure 11A] This is a schematic cross-sectional view of an exemplary embodiment of a packaged IC device, including an exemplary cooling structure, according to several embodiments.

[0036] [Figure 11B] This is a schematic cross-sectional view of an exemplary embodiment of a packaged IC device, including an exemplary cooling structure, according to several other embodiments.

[0037] [Figure 12] Figure 11B is a schematic diagram of an example exploded view of a packaged IC device.

[0038] [Figure 13] This is a schematic cross-sectional view of an exemplary embodiment of a packaged IC device, including an exemplary cooling structure and lead frame, according to several other embodiments.

[0039] [Figure 14]This is a schematic cross-sectional view of an exemplary embodiment of a packaged IC device, including an exemplary cooling structure and lead frame, according to several other embodiments.

[0040] [Figure 15A] Several other embodiments illustrate various examples of cooling structures. [Figure 15B] Several other embodiments illustrate various examples of cooling structures. [Figure 15C] Several other embodiments illustrate various examples of cooling structures. [Modes for carrying out the invention]

[0041] The following detailed descriptions of specific embodiments present various descriptions of those specific embodiments. However, novel ideas described herein may be embodied in many different ways, for example, as defined and covered by the claims. In this description, similar reference numerals and / or terms refer to drawings in which identical or functionally similar elements may be shown. It will be understood that elements shown in the drawings are not necessarily drawn to scale. It will also be understood that a particular embodiment may include more elements and / or subsets of elements shown in the drawings than those shown. Furthermore, some embodiments may incorporate any suitable combination of features from two or more drawings. The headings provided herein are for convenience only and do not necessarily affect the claims or their meaning. introduction

[0042] Electronic components containing one or more integrated circuit (IC) dies can be deployed in a wide variety of applications. For example, such components can form part of a power electronics system. In some cases, such power electronics systems may be used as part of stationary energy storage systems such as heating, ventilation, and air conditioning (HVAC) systems, electric vehicles, or systems for storing solar energy, or to supply power to other applications where power supply is required. For example, in electric vehicles, such systems may be used to convert alternating current (AC) to direct current (DC) for charging, or to convert DC to AC to provide power output. Power electronics systems may be used, for example, to convert DC to AC from solar panels or batteries. In some cases, such power electronics systems may be used in utility applications such as grid-tie inverters that convert DC to AC for insertion into the power grid. There are many other applications for such systems. In some cases, the components may include diode switches, field-effect transistors (FETs) such as metal-oxide-semiconductor field-effect transistors (MOSFETs) (e.g., gallium nitride (GaN) MOSFETs), insulated-gate bipolar transistors (IGBTs), other bipolar transistors, or any suitable combination thereof. In certain applications, such switches may be included in inverters that convert direct current (DC) voltage to alternating current (AC) voltage. These components may generate considerable heat during operation.

[0043] Electronic systems, such as power electronics systems, can generate considerable amounts of heat under both steady-state load conditions and surge conditions. Such heat can pose significant problems. For example, excessive heat can lead to component damage, reduced lifespan, decreased reliability, reduced performance, or one or more of the following. For instance, heat can cause excessive thermal stress on one or more components of an electronic system, leading to weakening of solder joints and / or damage to semiconductor components. In some applications, power surge loads can result in rapid temperature increases. High-power surge loads can be encountered in a variety of applications, for example, when starting portable compressors, HVAC systems, refrigeration systems, electric motors, power converters, or similar devices.

[0044] Even short power surge loads lasting approximately half a second to one second can cause significant temperature changes in electronic systems. Conventional cooling solutions may present technical limitations in managing such rapid temperature increases (e.g., rapid heat generation) resulting from power surge loads. Exemplary, a semiconductor die under steady-state operation, cooled using a conventional top heatsink, may consume 18 watts (W) and reach approximately 100°C. If a 100W power surge load is applied for half a second, the die temperature can rise significantly. For example, after approximately one second, the die temperature may rise to approximately 100°C. In some implementations, smaller dies (e.g., approximately 9 square millimeters (mm)) are used. 2 A die with an area of ​​) is a larger die (for example, about 24 mm). 2A die with a certain surface area can experience a greater temperature rise than a die with a certain surface area. For example, one second after a power surge, the die temperature can rise to approximately 200°C, approximately 220°C, or even higher, depending on the specific cooling solution provided by conventional cooling solutions, and also including additional factors such as die size, package size, and package design. In some cases, the semiconductor die is mounted directly to a lead frame or die paddle (which may act as a heat spreader within the molded package). The package may have a heat sink, heat spreader, cooling plate, or similar attached to assist in heat dissipation. However, adding mass to the heat slag (e.g., by adding a pedestal on top of the heat slag, or otherwise by increasing the mass of the heat slag), and / or adding an external heat spreader may not be very helpful in managing the semiconductor die temperature under power surge conditions. Such semiconductor die packages may lack good thermal contact with the added mass and therefore may not be able to utilize the added heat capacity in a short time. For example, in response to power surges, heat may not reach the heat slag, and as a result, heat may move through the thermal interface material before reaching the heat sink, which can limit the heat transfer rate. This can play a significant role in managing die temperature during power surge loads.

[0045] In some cases, electronic components may be designed to operate under steady-state conditions. For example, the heat transfer material inside an electronic component may be sized to manage heat dissipation under typical load conditions. Such an approach can offer many advantages, such as minimizing size and reducing cost, as it can use less material. However, such techniques may not be suitable for certain types of use cases, such as managing large loads and / or power surge loads.

[0046] Electronic components may be designed to be cooled from one side, such as the bottom, which is cooled through a printed circuit board (PCB). However, heat conduction through the PCB may be insufficient for certain applications. In the case of heat conduction through the PCB, coins containing copper or another thermally conductive material may be embedded in the PCB beneath the electronic component to facilitate cooling. However, such techniques may add additional cost and complexity to the PCB and may reduce the density of components on the PCB. Also, power electronics systems may raise the temperature of the PCB assembly to temperatures above 100°C, which may limit the flow of heat away from the electronic component through the PCB. Alternatively, in some cases, the PCB may be configured with holes that expose the bottom surface of the IC, and a heat sink or other heat transfer device may make thermal contact with the bottom surface of the IC through the holes. In some cases, top-side cooling may be used to cool the IC, as described, for example, in U.S. Patent No. 10,658,276 entitled “Device with top-side base plate,” the entire disclosure of which is incorporated herein by reference for all purposes.

[0047] Aspects of this disclosure relate to semiconductor packages having cooling solutions designed to effectively dissipate heat in a variety of operating environments, including heavy loads and / or sustained loads, as well as relatively short-duration power surge loads. Accordingly, the cooling solutions disclosed herein are designed to have large heat capacity and rapid heat transport (e.g., dissipation) capabilities. This disclosure describes examples of systems and technologies for providing solutions to effectively dissipate heat in a variety of operating environments, including relatively short-duration power surges. Examples of such systems and technologies can be used without further modification or complexity of PCB design or component assembly processes. In some cases, such cooling solutions can be manufactured using established and efficient manufacturing methods.

[0048] In some embodiments of this disclosure, a PCB is used as a carrier for a semiconductor package. For example, various semiconductor components, including packaged IC devices, may be mounted on a PCB. In some embodiments, the application of various cooling solutions and techniques of this disclosure may result in a PCB having a lower temperature than the integrated circuit (IC) package mounted on the PCB. In some embodiments, the PCB may be utilized to assist in heat dissipation from the packaged IC device. In some embodiments, a lead frame may be attached near the bottom surface of the packaged IC device. The lead frame may be used to provide electrical connections to the die and / or other components of the packaged IC device. In some embodiments, the lead frame may be exposed or partially exposed, which may facilitate heat transfer from the packaged IC device to the PCB. Packaged IC devices with power surge heat dissipation

[0049] Figure 1A shows the temperature change of a semiconductor die included in a packaged IC device having a heat dissipation structure (e.g., a cooling structure) according to embodiments disclosed herein. The heat dissipation structure or cooling structure may include, for example, a top heat slag (also referred to herein as a die paddle or heat spreader) and an encapsulating lead frame according to embodiments disclosed herein. A die paddle in one or more embodiments of this disclosure may be referred to as a heavy clip, heat spreader, heat slugger, cooling solution, etc. Therefore, any of the die paddles disclosed herein may be referred to as a heat spreader, heavy clip, heat slugger, or cooling solution. In embodiments of this disclosure, a packaged IC device may be manufactured using a die paddle mounted on a semiconductor die as the last or near-last step. This may be referred to as a flip-die assembly. The front of the semiconductor die may be electrically bonded to a lead frame with the front facing downwards, and then a heavy clip may be assembled on the semiconductor die. As shown in Figure 1A, a packaged IC device operating in a steady state in state region 102 and consuming approximately 35 W of power may have a semiconductor die operating at a temperature of approximately 116°C. When exposed to a surge load of approximately 160 W for approximately 1 second in surge load region 104, the temperature of the semiconductor die may rise to approximately 212°C, as shown in Figure 1A. When exposed to a surge load of approximately 160 W for a duration of approximately 1 second in surge load region 104, the temperature of the semiconductor die may rise to approximately 188°C in some other applications. Both of these temperatures under steady-state and power surge conditions provide significantly better thermal management compared to conventional methods.

[0050] Figure 1B shows an example of the temperature distribution of a packaged IC device. Heatmap 112 shows the temperature distribution of a packaged IC device disclosed in some embodiments of the present disclosure, for example, by using a clip-bond die package having a thin lead frame of about 0.9 mm and a heat slag of about 2.5 mm according to some embodiments of the present disclosure. Heatmap 114 shows an example of the temperature distribution of a conventional packaged IC device. Such a conventional packaged IC device may use a traditional wire bonding and mounting structure having a thickness of about 1.27 mm.

[0051] Heatmaps 112 and 114 show the temperature of the semiconductor device after a steady-state condition with 30W of power and then after a surge load of 160W of power for 1 second. As shown in heatmap 112 of a packaged IC device (e.g., having a heat dissipation structure according to an embodiment of the present disclosure), the temperature in region 112A of the packaged IC device may remain below about 200°C, as shown in temperature range 112B. In a conventional packaged IC device, heatmap 114 shows that the temperature in the external region 114A of the packaged IC device exceeds 240°C, corresponding to temperature range 114B. In addition, the semiconductor die region 114C of a conventional packaged IC device has a temperature of about 300°C. Such high temperatures can cause thermal stress on the components of the packaged IC device, potentially damaging the packaged IC device and / or the die attach solder (e.g., Pb which may have a melting point of about 296°C to about 301°C). 93.5 Sn5Ag 1.5 Pb, or Pb which may have a melting point of about 299°C to about 304°C. 95.5 Sn 2.5 Ag 2.5 There is a risk of exceeding the melting temperature of high-melting-point solders (such as those mentioned above).

[0052] Figure 2 shows examples of packaged IC devices 200 utilizing double-sided cooling according to several embodiments. The packaged IC device 200 may include a lead frame 202, a die clip 204, a semiconductor die 208, a die paddle 212, and a housing 214. The die paddle 212 may comprise one or more thermally conductive materials such as copper, lead, or steel. The die paddle 212 may be referred to as a heat dissipation structure (e.g., a cooling structure). As shown in Figure 2, the bottom surface of the lead frame 202 may be partially or completely exposed. In some embodiments, the lead frame 202 may be in contact with the PCB (e.g., direct contact). In some embodiments, a thermal compound or solder joint may be included between the lead frame 202 and the PCB to improve heat conduction to the PCB. Thus, the lead frame 202 may be in thermal contact with the PCB. The housing 214 may include or be essentially composed of a molding material. For example, a molding material may form the housing 214.

[0053] In some embodiments, the die paddle 212 includes a thermally conductive material and can dissipate heat generated from the semiconductor die 208. For example, one side of the semiconductor die 208 (e.g., the top surface of the semiconductor die 208 as shown in Figure 2) is joined to the die paddle 212 by a thermal compound or solder joint. Heat generated from the semiconductor die 208 can flow to the die paddle 212. In some embodiments, the die paddle 212 and lead frame 202 can be thick enough to dissipate heat associated with power surges. Such thicknesses can be significantly greater than conventional thicknesses sufficient to achieve steady-state heat dissipation only at a stable maximum die temperature. The thickness 252 of the die paddle 212 can be twice or more than twice the thickness 256 of the lead frame 202. The lead frame 202 can be molded to function as a thin die paddle 212. In some embodiments, the thickness 252 of the die paddle 212 can be in the range of 4 to 20 times the thickness 254 of the semiconductor die 208. In some embodiments, the thickness 252 of the die paddle 212 may be twice or more than twice the thickness 259 of the die clip 204. The die paddle 212 and the lead frame 202 may each have an area larger than the area of ​​the die 208. The die paddle 212 and the lead frame 202 may each extend beyond the die 208.

[0054] The thermal capacity and thermal conductivity of the die paddle 212 and lead frame 202 can attenuate the temperature rise of the semiconductor die 208 in the presence of instantaneous power surges. Thus, the packaged IC device 200 can maintain the die 208 and package within thermal specifications, including during power surges. In certain embodiments, the die paddle 212 and lead frame 202 together may have sufficient thermal mass to maintain the die 208 at a temperature below 200°C, 190°C, 180°C, 170°C, 160°C, or 150°C when the die 208 is subjected to a surge load of up to 100W or up to 160W from a steady state for 0.5 seconds. In some embodiments, the die paddle 212 and lead frame 202 together may have sufficient thermal mass to maintain the die 208 at a temperature below 200°C, below 190°C, or below approximately 180°C when the die 208 is subjected to a surge load of up to 100W or up to 160W from a steady state for 1 second.

[0055] In some embodiments, the thickness 252 of the die paddle 212 and the thickness 256 of the lead frame 202 can be designed to meet various technical specifications. In some cases, the thicknesses 252 and 256 of the die paddle 212 and lead frame 202 can preferentially remove heat from the bottom or top of the packaged IC device, respectively. For example, in an application where heat is to be absorbed by the die 208 and more heat dissipated through the top of the packaged IC device 200, a thinner thickness 256 of the lead frame 202 and a thicker thickness 252 of the die paddle 212 may be included. In this example, the thickness 252 of the die paddle 212 can be at least four times thicker than the thickness 256 of the lead frame 202. Furthermore, in this example, it is desirable that more heat be absorbed from the semiconductor die 208 and removed through the top of the packaged IC device, while a thicker lead frame 202 and a thinner die paddle 212 may result in more heat being absorbed from the die and removed through the bottom of the package. In some examples, more heat can be dissipated through the bottom surface of the packaged IC device 200 than in previous examples. This application may involve a thicker lead frame 202. In this example, the thickness 252 of the die paddle 212 can be between 2 and 3.5 times the thickness 256 of the lead frame 202. Furthermore, in this example, since it is desirable that more heat be absorbed from the semiconductor die 208 and removed through the top surface of the packaged IC device, a thicker lead frame 202 and a thinner die paddle 212 may result in more heat being absorbed from the semiconductor die 208 and removed through the bottom surface of the package. The ratio between thicknesses 252 and 256 may be adjusted to maximize heat absorption with minimal die temperature rise.

[0056] Figure 2 shows a lead frame 202 that is at least partially exposed, but in some embodiments, the lead frame 202 may not be exposed. For example, in some applications, the lead frame 202 may not be exposed in order to avoid electrical contact between the electrical contacts of the PCB and the exposed lead frame 202. For example, the PCB may have one or more exposed areas such as high-voltage vias, low-voltage vias, traces, or the like. If an exposed lead frame 202 is present, it may be desirable to route around the packaged IC device rather than passing under the packaged IC device in order to avoid electrical contact with the lead frame 202. For example, an exposed lead frame 202 may result in electrical interference between the packaged IC device and any signals passing under the packaged IC device 200.

[0057] In some cases, the PCB may be at a temperature similar to or higher than the dies mounted on the PCB (e.g., dies located within an integrated circuit (IC) package attached to the PCB). Therefore, cooling from the bottom side of the packaged IC device (e.g., the side facing the PCB) may be of limited effectiveness in such cases. In some other cases, for example, if the PCB is hotter than the dies, heat transfer through the bottom of the packaged IC device can result in an increase in the temperature of the semiconductor dies within the package. Therefore, in some embodiments, the thickness of any metal component near the bottom of the packaged IC device may preferably be relatively thin, while any metal component near the side facing the outside of the packaged IC device may be thicker to provide greater thermal mass, thereby increasing heat transfer toward the outer surface of the packaged IC device opposite the PCB. For example, the thickness 252 of the die paddle 212 may be greater than the thickness 256 of the lead frame 202, thereby allowing the thickness 252 of the die paddle 212 to be at least five times thicker than the thickness 252 of the die paddle 212.

[0058] In some embodiments, thermally insulating the lead frame of a packaged IC device from the PCB (e.g., a high-temperature PCB) can reduce the temperature of the lead frame relative to the PCB and increase the heat absorption by the combination of the lead frame and die paddle. For example, insulating the lead frame 202 to thermally isolate it from contact with the PCB (which has a high temperature) can prevent the temperature of the lead frame 202 from further increasing due to heat dissipation from the semiconductor die 208 and further from the PCB.

[0059] In some embodiments, the molding material for the packaged IC device may provide such thermal insulation between the lead frame and the PCB. In some embodiments, but not limited to, the molding material may not be used, and / or another separator may be used. In some embodiments, the separation from the PCB may be provided by a gap between the PCB and the packaged IC device.

[0060] Figure 3A shows an exemplary packaged IC device 300 using single-sided cooling according to several embodiments. The packaged IC device 300 may include a lead frame 302, lead mounting solder 304, a semiconductor die 208, paddle mounting solder 310, a die paddle 312, and a housing 314. The die paddle 312 may be made of a thermally conductive material such as copper, lead, or steel. The die paddle 312 may be called a heat dissipation structure (e.g., a cooling structure). The packaged IC device 300 may include a conductive spacer 316 that can replicate the thickness of the semiconductor die 208 so as to keep the interface surfaces of other components that engage with the semiconductor die 208 on the same plane. In some embodiments, the housing 314 may include a molding material or may be essentially composed of a molding material. For example, a molding material may form the housing 314.

[0061] In some embodiments, the packaged IC device 300 may include additional circuitry. In some embodiments, the packaged IC device 300 may include a thermistor die 318. The thermistor die 318 may be configured to sense the temperature of components such as the packaged IC device 300, the semiconductor die 208, the lead frame 302, and / or other components contained within the packaged IC device 300. In some embodiments, the lead frame 302 may include a group of leads 302A (e.g., a group of leads extending to side A of the lead frame 302) for electrical connection to the terminals of the semiconductor die 208 and the thermistor die 318. For illustrative purposes, Figure 3A shows one lead 302A connected to the thermistor die 318, but the group of leads 302A may include additional leads connected to the terminals of the semiconductor die 208, for example, as shown in Figure 3B.

[0062] In some embodiments, the lead frame 302 may include a main frame 302C and a plurality of leads extending from the main frame 302C. In some examples, as further illustrated in Figure 3B, the plurality of leads extend to side A of the packaged IC device 300, and the leads extending to side A may include a group of leads 302A, which include two source leads and one gate lead. In some cases, the group of leads 302A may further include at least one of a Kelvin source lead, a thermistor lead (e.g., one of the leads 302A connected to a thermistor die), or a sensing lead (configured to monitor the voltage and / or current of the lead frame 302). In some embodiments, each lead is located outside the housing 314, and each lead of the plurality of leads is a flat lead. Furthermore, the end of each lead of the plurality of leads (e.g., outside the housing 314) may include a wettable flank. Furthermore, the wettable flank may be soldered to the corresponding contact point on the PCB.

[0063] In some embodiments, the lead frame 302 may be embedded within the housing 314 with only the electrical contacts exposed. The housing 314 may comprise a molding material 322. In certain applications, a group of leads 302B may also extend from the lead frame 302. In some examples, a group of leads 302B may be electrically coupled to the drain terminal of the semiconductor die 208 via a die paddle 312. For example, two leads 302B (only one lead 302B is shown in Figure 3A) may be exposed outside the housing 314 by providing electrical contact with the terminal of the semiconductor die 208 (the drain terminal of the semiconductor die 208). For example, the drain terminal of the semiconductor die 208 is electrically coupled to the die paddle 312, and the die paddle 312 is connected to the leads 302B. In some examples, the die paddle 312 and the leads 302B are connected via a passive electronic component 320, such as a capacitor. In some embodiments, the molding material 322 may be embedded inside the housing 314. As shown in Figure 3A, the molding material 322 may be included between the lead frame 302 and the bottom surface of the packaged IC device 300.

[0064] As shown in Figure 3A, the die paddle 312 may extend to the upper surface of the packaged IC device 300. The die paddle 312 may be at least partially exposed on the upper surface of the packaged IC device 300. In some embodiments, the die paddle 312 may be referred to as a heat slag, heat spreader, or similar.

[0065] In some embodiments, heat transfer across the top of the packaged IC device 300 can be achieved without using a separate heat spreader by using a thick die paddle 312 that extends to the top of the packaged IC device 300. If a separate heat spreader is used, for example, since the die paddle 312 does not extend to the top of the packaged IC device 300, a thermal interface material may be applied between the die paddle 312 and the heat spreader. However, typical thermal interface materials may have a lower thermal conductivity than the metal used to form the lead frame, heat spreader, heat slag, or die paddle, and thus may act as a thermal bottleneck.

[0066] For certain applications, the die paddle 312 may contain copper and / or be mostly copper. The lead frame 302 may contain copper and / or be mostly copper.

[0067] The semiconductor die 208 and other dies disclosed herein may be integrated circuit dies. These dies may include power switching devices that can generate a significant amount of heat.

[0068] The die paddle 312 may be thick enough to dissipate the heat associated with power surges. The die paddle 312 may attenuate the temperature rise of the semiconductor die 208 in the presence of power surges. Thus, the packaged IC device 300 may maintain the semiconductor die 208 and package within temperature specifications during power surge conditions. The thickness 352 of the die paddle 312 may be at least 2.5 mm. For example, the thickness 352 of the die paddle 312 may be in the range of 2.5 mm to 5 mm. In certain cases, the thickness 352 of the die paddle 312 may be in the range of 2.5 mm to 3 mm. In some examples, the thickness 352 of the die paddle 312 is at least three times the thickness 354 of the lead frame 302. In some embodiments, the separation portion 356 between the lead frame 302 and the bottom surface of the packaged IC device 300 may be thicker than the thickness 354 of the lead frame. In some cases, the molding material 322 may be included between the lead frame 302 and the bottom surface of the packaged IC device 300. In some cases, the main frame 302C of the lead frame 302 is separated from the bottom surface of the packaged IC device 300 by a separation portion 356. In some examples, the molding material 322 provides a separation portion between the main frame 302C of the lead frame 302 and the bottom surface of the packaged IC device 300.

[0069] In some configurations of the packaged IC device 300 where the PCB operates at a higher temperature than the packaged IC device 300, the lead frame 302 may be repositioned relatively far away from the PCB (e.g., from the bottom of the packaged IC device 300). For example, moving the lead frame 302 upward and away from the PCB can reduce heat transfer from the PCB to the lead frame 302. However, there may be limits to how far above the PCB the lead frame 302 can be positioned. For example, a large isolation can result in an undesirably large inductance loop. In some cases, a large isolation can result in undesirable voltage losses when signals, power, etc., flow between the packaged IC device and the lead frame. In some embodiments, when there is a relatively large isolation, the long leads used to make the connection can affect performance, such as when operating at higher switching frequencies.

[0070] In these embodiments, the isolation portion 356 can be further increased by reducing the thickness 352 of the die paddle 312 relative to the overall height of a given packaged IC device. Therefore, in some cases, a larger isolation portion from the PCB can result in a smaller thermal mass above the die. A lower thermal mass profile of the die paddle 312 can reduce heat dissipation. To enhance and / or optimize the thermal mass profile and heat dissipation of the die paddle 312, the thickness 352 of the die paddle 312 can be at least 1.25 mm. In various applications, the thickness 352 of the die paddle 312 can also be determined based on various surge load conditions, such as various power levels in the range of 60 W to 160 W. In these applications, the thickness 352 of the die paddle 312 can increase as the power level increases. For example, a thickness 352 of 1.25 mm of the die paddle 312 can effectively dissipate heat when the power surge load is about 60 W.

[0071] In some embodiments, the thickness 354 of the lead frame 302 can be reduced, thereby increasing the separation 356 between the lead frame 302 and the bottom surface of the packaged IC device 300. For example, the thickness 354 of the lead frame 302 may be 0.5 mm. A thinner lead frame 302 may be advantageous because it may allow for a larger separation between the lead frame 302 and the PCB, but electrical considerations may limit the thinness of the lead frame. For example, if the lead frame 302 is too thin, the voltage may drop due to the resistance of the electrical connection with the PCB, causing the die to deviate from the design specifications and / or tolerance limits.

[0072] Therefore, in some embodiments, the thickness 354 of the lead frame 302, the thickness 352 of the die paddle 312, the separation portion 356 between the lead frame 302 and the PCB, and the overall height of the device may be taken into consideration. For example, these parameters may be modified based on the operating environment or specifications of the packaged IC device 300, such as one or more switching speeds, cooling needs, power demands, resistive losses, or one or more other appropriate parameters.

[0073] Figure 3B shows an example of an electrical path through the packaged IC device 300 shown in Figure 3A. The lead frame 302 (for example, contained inside the packaged IC device 300 as shown in Figure 3A) may contain multiple leads connected to the terminals of the semiconductor die 208 and thermistor die 318 (for example, contained inside the packaged IC device 300 as shown in Figure 3A). In Figure 3B, sides A and B of the bottom view may correspond to sides A and B of the packaged IC device 300 shown in Figure 3A, respectively. In some examples, source leads 302AA and 302AB are electrically connected to the source terminal of the semiconductor die 208. The gate lead 302AD of the multiple leads is connected to the gate terminal of the semiconductor die 208. In addition, the Kelvin source lead 302AE of the multiple leads is connected to the Kelvin source terminal of the semiconductor die 208. In some examples, the lead frame 302 may include additional sensing circuits (or dies) for sensing electrical properties of the semiconductor die, such as voltage, current, power, and similar values. In these examples, the sense leads 302AC of multiple leads are connected to the sense terminals of the sensing circuit. In some cases, the lead frame 302 may also be connected to additional dies, such as a thermistor die 318. Thermistor die 318 is an example of a sensor die. Thermistor die 318 can sense the temperature of the die and may be electrically coupled to lead 302AF. The number and types of additional dies and leads are shown as examples only, and two or more additional dies and leads may be used in specific applications.

[0074] The drain lead 302B may include leads 302BA and 302BB. Leads 302BA and 302BB may be electrically connected to the drain terminal of the semiconductor die 208. For example, the die paddle 312 may be a conductive material structure and can provide an electrical connection between the drain terminal of the semiconductor die 208 and the two drain leads 302BA and 302BB.

[0075] Figure 4 schematically shows an example block diagram of a packaged IC device. In some examples, the semiconductor die 208 is connected by solder 410 to a die paddle 312 (e.g., commonly also called a heat sink, heat slag, die paddle, thermal conductor, or similar) on a first side and by solder 420 to a lead frame 302 facing the PCB on a second side opposite the first side. In some embodiments, the thickness of the die paddle 312 can be maximized to extract heat from the semiconductor die 208 (e.g., having a high temperature) through the die paddle 312. For example, in some embodiments, the lead frame 302 facing the PCB can be insulated by embedding the lead frame 302 in a molding material to achieve electrical insulation, thermal insulation, etc., from the PCB. In some embodiments, the lead frame 302 facing the PCB can be maintained at a temperature of less than about 120°C, for example, about 85°C. In some embodiments, contact between the packaged IC device and the PCB can be minimized.

[0076] While the above describes soldering the lead frame 302, die paddle 312, etc., to the semiconductor die 208, it will be understood that other approaches are also possible. For example, in some embodiments, components can generally be bonded to the semiconductor die by bonding, sintering, or other methods. Surface mount epoxy recess

[0077] Packaged IC devices can be subjected to a variety of non-ideal conditions. For example, they can be subjected to significant heat, vibration, etc. In some cases, packaged IC devices may be installed in vehicles such as automobiles, airplanes, or heavy machinery that are subjected to significant vibration or thermal cycling between low and high temperatures. Such conditions can lead to premature failure of the device. For example, packaged IC devices subjected to significant thermal stress, vibration stress, etc., may detach from the PCB due to fatigue fracture stress. Internal stress can lead to delamination or other failure of the packaged IC device.

[0078] In some embodiments, the packaged IC device may be a soldered surface mount device. In some embodiments, the surface mount device may have one or more recessed areas where epoxy or other material may be distributed. Using epoxy in such recesses can help secure the surface mount device to the PCB and may provide stress relief. In some embodiments, such recesses may be used to achieve coplanarity of multiple devices. Coplanarity of multiple devices can be advantageous by allowing the use of a single flat heat sink to cool multiple devices. Although surface mount devices are considered in this description, it will be understood that similar approaches may be used for packaged IC devices using through-hole mounting and / or other suitable techniques.

[0079] In some embodiments, epoxy may be more viscous than the solder paste used to mount surface mount devices to electrical contacts on a PCB. The use of epoxy can offer several advantages, such as preventing or mitigating high centering of the package body, lifting of soldered leads, or both. Epoxy can prevent or mitigate tilting of the package body relative to the PCB, or it can hold SMD components to a seat designed with the PCB. Epoxy can prevent or mitigate height misalignment or variation that occurs during the assembly process. For example, height alignment can enable coplanarity of two or more devices. Therefore, a heat spreader or heat sink with a flat bottom surface can be used to provide thermal management for two or more surface mount devices. Since two or more surface mount devices are coplanar, the thickness of thermal gap filler on the devices between the devices and the heat sink or heat spreader can be reduced, thereby improving thermal performance. This approach can offer significant advantages, as thermal gap filler can be a major source of thermal resistance. Therefore, thermal performance can be improved by reducing or eliminating the need to use thick thermal gap filler, which may be required if the surface mount devices are not coplanar.

[0080] Figure 5 shows an example of a surface mount device 502 mounted on a printed circuit board 504 according to several embodiments. In Figure 5, the surface mount device 502 is mounted on the PCB 504. The PCB 504 may include a solder mask 506 and solder pads 508 on the side facing the surface mount device 502. The surface mount device 502 can be electrically connected to the PCB 504 via the solder pads 508. For example, the surface mount device 502 may be mounted to the solder pads 508 of the PCB 504 using solder 510. As mentioned above, if solder alone is used, the solder 510 may not be uniformly distributed over all the solder pads 508, which could cause the surface mount device 502 to tilt relative to the PCB 504. Epoxy 512 may be used to attach the surface mount device 502 to the PCB 504. The height of the epoxy 512 can define the separation distance between the bottom surface of the surface mount device 502 and the top surface of the PCB 504.

[0081] In some embodiments, surface mount devices may have relatively large recesses, as shown, for example, in Figure 5. However, other configurations are also possible. For example, a surface mount device may have one or more clearly defined local recesses for receiving epoxy. Such an approach can improve the coplanarity of multiple surface mount devices by partially restricting the flow of epoxy in some embodiments. The use of local recesses may have one or more other advantages. For example, local recesses may be advantageous during manufacturing processes in which suction is used to hold the device package during the top grinding process. Recesses may be positioned so that epoxy 512 approaches solder 510 in order to allow strain relaxation to reduce stress on solder 510.

[0082] Figure 6 shows an exemplary embodiment of a packaged IC device 600 including a local recess 610. As shown in Figure 6, the packaged IC device 600 may include a die paddle 602, a lead frame 604, a semiconductor die 208, and a housing 608. The housing 608 may have a local recess 610 located on the bottom surface of the housing 608. The packaged IC device 600 is a packaged IC device. In some embodiments, the local recess 610 may have a recess depth of about 50 micrometers to about 500 micrometers, for example, about 100 micrometers. The recess depth of the local recess 610 may be any depth suitable for a particular application. For example, the depth of the local recess 610 can be any appropriate value, constrained by the overall height of the packaged IC device 600 and the space for other components of the packaged IC device 600, such as the die paddle 602, lead frame 604, semiconductor die 606, solder used to make electrical connections between components of the packaged IC device 600, and any cooling embedded in the packaged IC device 600 (for example, if a separate heat spreader is used instead of a thick die paddle).

[0083] Furthermore, in Figure 6, in some examples, the thickness 652 of the die paddle 602 is at least five times the thickness 654 of the lead frame 604. In some embodiments, the separation portion 656 between the lead frame 604 and the bottom surface of the packaged IC device 600 (in some examples, the thickness of the molding material filled between the lead frame 604 and the bottom surface of the packaged IC device 600) may be at least twice the thickness 654 of the lead frame. In some embodiments, the distance of the separation portion 656 may be determined based on the fluidity and viscosity of the molding resin. The shape of the separation portion 656 from the bottom surface facing the printed circuit board may include a shape such as the local recess 610 shown in Figure 6. In some examples, the separation portion 656 may be equal to or thinner than the thickness 654 of the semiconductor die 606.

[0084] Figure 7 shows a bottom perspective view of a packaged IC device 600 including a local recess 610 according to several embodiments. In Figure 7, the packaged IC device 600 may include a housing 608 having a local recess 610 located on the bottom surface of the housing 608. The packaged IC device 600 may include a source lead 612, additional leads 614 (e.g., gate lead, sense lead, Kelvin source lead, thermistor lead, etc.), and a drain lead 616. The structure shown in Figure 7 may be used, for example, in a power integrated circuit.

[0085] Figure 7 is an example. The number and type of leads are not necessarily limited. For example, a device package may contain more leads, fewer leads, and / or different leads than those shown in Figure 7. Figure 7 shows that the source and drain leads are larger than the other leads, but this is not necessarily true for all applications. In some embodiments, all leads may be the same size. According to some other embodiments, some leads may be different in size from one or more other leads.

[0086] Figure 8 shows exemplary embodiments of an IC assembly comprising a plurality of packaged IC devices 802, 804 according to several embodiments. The packaged IC devices 802, 804 may be, for example, surface mount devices. In Figure 8, the first packaged IC device 802 and the second packaged IC device 804 are mounted on a PCB 806. The PCB 806 may have a solder mask 808 and contact pads 810. The first packaged IC device 802 and the second packaged IC device 804 may be electrically connected to the PCB 806 (for example, to the contact pads 810 of the PCB 806) using solder 812. Epoxy 814 may be used to mount the first packaged IC device 802 and the second packaged IC device 804 to the PCB 806. The first packaged IC device 802 may be mounted according to any suitable principles and advantages disclosed herein. The second packaged IC device 804 may be implemented according to any suitable principles and advantages disclosed herein. For example, the first packaged IC device 802 and the second packaged IC device 804 may each include a lead frame and a relatively thick die paddle configured to dissipate heat associated with power surges. As stated above, epoxy 814 may help maintain a consistent vertical orientation of the packaged IC device.

[0087] The upper surfaces of the first packaged IC device 802 and the second packaged IC device 804 may be coplanar. A heatsink 816 having a flat bottom surface may be in contact with the upper surfaces of the first packaged IC device 802 and the second packaged IC device 804. In some embodiments, a thermal interface material 818 may be placed between the heatsink 816 and the upper surfaces of the packaged IC devices 802 and 804. The thermal interface material 818 can be relatively thin (e.g., compared to the thickness of the thermal interface that may be required if the packaged IC devices are not coplanar), allowing for more efficient heat transfer from the first packaged IC device 802 and the second packaged IC device 804 to the heatsink 816. The heatsink 816 is an example of a cooling structure. Other suitable cooling structures, such as cooling plates, may be implemented instead of or in addition to the heatsink 816.

[0088] Figure 9A shows an example of a packaged IC device 900. In some embodiments, the packaged IC device may have various configurations of heat dissipation or cooling structures. For example, the packaged IC device 300 in Figure 3A includes a die paddle 312 as the cooling structure of the packaged IC device 300. The packaged IC device 900 includes a die paddle 912 having a multilayer cooling structure. As shown, the packaged IC device 900 and the packaged IC device 300 may have the same components except that (1) these two packaged IC devices have different die paddles, and (2) the IC device 900 includes a recess where epoxy can be distributed. For example, the packaged IC device 300 includes a die paddle 312, and the packaged IC device 900 includes a die paddle 912 which is a multilayer cooling structure.

[0089] As shown in Figure 9A, the dipaddle 912 comprises three layers: an upper layer 912A, an intermediate layer 912B, and a bottom layer 912C. In some embodiments, the upper layer 912A may consist of copper active metal brazing (Cu AMB). The bottom layer 912C may consist of or essentially consist of copper (Cu). In some embodiments, the upper layer 912A and the bottom layer 912C may contain the same material, such as copper, Cu AMB, or similar. The intermediate layer 912B may consist of a ceramic such as silicon nitride or other suitable material.

[0090] The thickness 952 of the die paddle 912 can be at least 2.5 mm. For example, the thickness 952 of the die paddle 912 can be in the range of 2.5 mm to 5 mm. In certain cases, the thickness 952 of the die paddle 912 can be in the range of 2.5 mm to 3 mm. As an example, the thickness 952 of the die paddle 912 can be approximately 2.75 mm. In some examples, the thickness 952 of the die paddle 912 is at least 2.5 times the thickness 954 of the lead frame 302. For example, the die paddle 912 can be in the range of 2.5 to 10 times the thickness 954 of the lead frame 302. As another example, the die paddle 912 can be in the range of 4 to 10 times the thickness 954 of the lead frame 302.

[0091] In some embodiments, the thicknesses 952A and 952C of the uppermost layer 912A and the lowermost layer 912C, respectively, are at least twice the thickness 952B of the intermediate layer 912B. In these embodiments, thicknesses 952A and 952C may be the same. In some examples, thicknesses 952A and 952C may differ, such that thickness 952A may be thicker or thinner than thickness 952C.

[0092] In some examples, the area 962B of the intermediate layer 912B may be larger than the areas 962A and 962C of the uppermost layer 912A and the lowermost layer 912C, respectively. In these examples, area 962C may be larger than area 962A. In addition, the uppermost layer 912A, the intermediate layer 912B, and the lowermost layer 912C are contained within the housing 314.

[0093] In some cases, the lead frame 302 is separated from the bottom surface of the packaged IC device 300 by the distance of the separation portion 956. In some embodiments, the separation portion 956 between the lead frame 302 and the bottom surface of the packaged IC device 900A may be thicker than the thickness 354 of the lead frame. In some cases, a molding material may be filled between the lead frame 302 and the bottom surface of the packaged IC device 900A.

[0094] Figures 9B and 9C show other cross-sectional views of the packaged IC device 900. The cross-sectional view in Figure 9B may be substantially parallel to the cross-sectional view in Figure 9A. In the cross-sectional view in Figure 9A, the two leads shown include a source lead 302A and a drain lead 302B. In the cross-sectional view in Figure 9B, the shown lead 302A1 may be located between the two source leads, and the packaged IC device 900 does not have a lead on the opposite side of the lead 302A1 shown in Figure 9B. The lead 302A1 shown in Figure 9B may be, for example, a gate lead, a sensing lead, or a Kelvin source lead. The cross-sectional view in Figure 9C is substantially perpendicular to the cross-sectional view in Figure 9A and may extend through the central portion of the packaged IC device 900.

[0095] Figure 10A shows a three-dimensional assembly diagram of the packaged IC device 900 shown in Figures 9A to 9C. As shown in Figure 10A, the packaged IC device 900 includes a die paddle 912 having an upper layer 912A, an intermediate layer 912B, and a bottom layer 912C, respectively.

[0096] As illustrated, the lead frame 302 may include multiple leads (shown in Figure 9A) to terminals on the semiconductor die 208. In some examples, source leads 302AA, 302AB are electrically connected to the source terminals of the semiconductor die 208. Of the multiple leads, the gate lead 302AD is connected to the gate terminal of the semiconductor die 208. In addition, of the multiple leads, the Kelvin source lead 302AE is connected to the Kelvin source terminal of the semiconductor die 208. In some examples, the lead frame 302 may include one or more leads connected to a sensing circuit (or die) for sensing electrical characteristics of the semiconductor die, such as voltage, current, power, and similar. In these examples, a sense lead (not shown in Figure 10A) is connected to the sense terminal of the sensing circuit. The number and types of additional dies and leads are shown as examples only, and two or more additional dies and leads may be used in specific applications.

[0097] The drain lead 302B can be electrically connected to the drain terminal of the semiconductor die 208. For example, the die paddle 912 may be a conductive material structure and can provide an electrical connection between the drain terminal of the semiconductor die 208 and the two drain leads 302B.

[0098] In some embodiments, each lead of the plurality of leads (e.g., outside the housing 314) is a flat lead. Furthermore, the end of each lead of the plurality of leads (e.g., outside the housing 314) includes a wettable flank. Furthermore, the wettable flank can be soldered to the corresponding contact point on the PCB.

[0099] Figure 10B shows an exploded view of the components of an example of a packaged IC device 900 according to several embodiments. As shown in Figure 10B, the packaged semiconductor component 1100 may be mounted on a lead frame 302. In some embodiments, the lead frame 302 may provide electrical contacts for electrical connection to terminals of the semiconductor die 208, such as drain, source, gate, and / or Kelvin source terminals.

[0100] As shown in Figure 10B, the packaged semiconductor component 1100 may include a die paddle 912, a bonding layer 1004 (e.g., die back and spacer solder), a spacer 1006, a semiconductor die 208, and a bonding layer 1010 (e.g., die back and spacer solder). In some examples, the bonding layers 1004, 1010 may be formed based on a pattern that may include multiple regions for providing electrical connections to corresponding die connection terminals (e.g., contact terminals) such as the source, Kelvin source, drain, and gate of the semiconductor die 208. In some examples, the bonding layers 1004, 1010 may be formed from a conductive material such as solder, conductive epoxy, or the like, but are not limited to these. The lead frame 302 may include any suitable configuration disclosed herein.

[0101] Figures 11A and 11B show packaged IC devices having examples of heat spreaders 1112 (shown in Figure 11A) and 1122 (shown in Figure 11B) according to embodiments of the present disclosure.

[0102] Referring to Figure 11A, the heat spreader 1112 may be formed from a solid conductive material. The heat spreader 1112 may contain copper or may be essentially composed of copper. As shown in Figure 11A, the packaged IC device 1100A may include a heat spreader 1112 having a first portion 1112A and a second portion 1112B. The first portion 1112A and the second portion 1112B may be formed by using the same material, such as copper. In some embodiments, the first portion 1112A and the second portion 1112B may have a securely bonded electrical insulating material 1113 between them, such as an activated metal junction (AMB) structure, thereby allowing the production of a copper AMB using a silicon nitride ceramic sheet. The electrical insulating material 1113 may be ceramic. In some examples, the thickness 1152A of the first portion 1112A and the thickness 1152B of the second portion 1112B can be 2 to 5 times the thickness of the electrical insulating material 1113. In some embodiments, the AMB can be used as a substrate for mounting semiconductor dies.

[0103] As shown in Figure 11B, the packaged IC device 1100B may include a heat spreader 1122 having a first portion 1122A and a second portion 1122B. In some embodiments, the first portion 1122A and the second portion 1122B may be formed by using the same material, such as copper. In some embodiments, the first portion 1122A may be formed of copper and the second portion 1122B may be formed of copper AMB, so the first portion 1122A and the second portion 1122B may be formed of different materials. In some examples, the thickness 1162A of the first portion 1122A may be 2 to 5 times the thickness 1162B of the second portion 1122B.

[0104] Figure 12 shows an exploded view of the components of an example of the packaged IC device 1100B of Figure 11B, according to several embodiments. As shown in Figure 12, the packaged semiconductor component 1200 may be mounted on a lead frame 302. In some embodiments, the lead frame 302 may provide electrical contacts for electrical connection to terminals of the semiconductor die 208, such as drain, source, gate, and / or Kelvin source terminals.

[0105] As shown in Figure 12, the packaged semiconductor component 1200 may include a heat spreader 1122, a bonding layer 1004 (e.g., die back and spacer solder), a spacer 1006, a semiconductor die 208, and a bonding layer 1010 (e.g., die back and spacer solder). The heat spreader 1122 may be a die paddle. In some examples, the bonding layers 1004, 1010 may be formed based on a pattern that may include multiple regions for providing electrical connections to corresponding die connection terminals (e.g., contact terminals) such as the source, Kelvin source, drain, and gate of the semiconductor die 208. In some examples, the bonding layers 1004, 1010 may be formed from a conductive material such as solder, conductive epoxy, or the like, but are not limited to these. The lead frame 302 may include any suitable configuration disclosed herein.

[0106] Figure 13 shows an example of a packaged IC device 1300 having an uppermost layer 912A, an intermediate layer 912B, and a bottommost layer 912C. An example of the configuration of the uppermost layer 912A, the intermediate layer 912B, and the bottommost layer 912C, as well as their respective thicknesses and compositions, will be described with reference to Figure 9A. In some embodiments, the bottommost layer 912C may include one or more notches, such as notches 912CA and 912CB. The lead frame 302D may include a plurality of leads 302D1 that can extend directly from one or more terminals outside the housing 314 (e.g., one or more of source terminals, gate terminals, or Kelvin source terminals). In some embodiments, the leads 302D1 may be flat leads.

[0107] Figure 14 shows an example of a packaged IC device 1400 having the heat spreader 1112 (e.g., heat spreader) from Figure 11A and the lead frame 302D from Figure 13.

[0108] Figures 15A to 15C show various examples of heat spreaders (e.g., heat spreaders) having various shapes. For example, as shown in Figure 15A, a heat spreader 1512A may have a notch 1512AA. Figures 15B and 15C show that a solid copper clip can be replaced with an AMB having a lower notch. Figure 15B shows one side of the AMB clip, and Figure 15C shows the opposite side of the AMB clip. As shown in Figure 15B, on the top surface, the thickness of the heat spreader 1512B may gradually decrease towards the middle of the heat spreader 1512B and gradually increase from the middle towards the outer part of the heat spreader 1512B. As shown in Figure 15C, the bottom surface 1512C of the heat spreader 1512B may have a notch 1512CA and a second square notch 1512CB. Further embodiments

[0109] In the aforementioned specification, this disclosure has been described with reference to specific embodiments. However, it will be apparent that various modifications and changes can be made without departing from the broader spirit and scope of this disclosure. Accordingly, this specification and the drawings should be considered illustrative rather than restrictive.

[0110] In fact, while this disclosure is in the context of specific embodiments and examples, it will be understood by those skilled in the art that the present invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or the use of the present invention and its equivalents. Furthermore, while several variations of the embodiments have been shown and described in detail, other modifications within the scope of this disclosure will be readily apparent to those skilled in the art based on this disclosure. It is also conceivable that various combinations or partial combinations of specific features and aspects of the embodiments may be made and still fall within the scope of this disclosure. It should be understood that various features and aspects of the disclosed embodiments may be combined with or substituted for each other to form various forms of the embodiments disclosed herein. None of the methods disclosed herein need to be performed in the order listed. Therefore, it is not intended that the scope of this disclosure should be limited by the specific embodiments described above.

[0111] Each of the systems and methods disclosed herein has several innovative aspects, and it will be understood that not just one of them alone is responsible for or requires the desirable characteristics disclosed herein. The various functions and processes described above may be used independently of each other or combined in various ways. All combinations and partial combinations are intended to be within the scope of this disclosure.

[0112] Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable subcombination. Furthermore, even if features are described above as acting in a particular combination and were initially claimed as such, one or more features from the claimed combination may, in some cases, be removed from the combination, and the claimed combination may be subject to partial combinations or partial combinations. A single feature or group of features is not required or essential to every embodiment.

[0113] Unless otherwise noted or understood within the context in which they are used, conditional language used herein, such as “can,” “might,” “may,” and “e.g.,” is generally intended to suggest that certain embodiments include certain features, elements, and / or steps, while other embodiments do not. Therefore, such conditional language is not generally intended to imply that features, elements, and / or steps are required in any way in one or more embodiments, nor is it intended to imply that one or more embodiments necessarily include logic for determining whether these features, elements, and / or steps should be included in or performed in any particular embodiment, with or without input from the author. Terms such as “comprising,” “including,” and “having” are synonymous and are used comprehensively and in an open-ended manner, without precluding additional components, features, actions, behaviors, etc. In addition, the term "or" is used in an inclusive sense (not an exclusive sense), and for example, when used to connect a list of elements, the term "or" means one, some, or all of the elements in the list. Furthermore, the articles "a" (indefinite article), "an" (indefinite article), and "the" (definite article) used in this application and the attached claims should be interpreted as meaning "one or more" or "at least one" unless otherwise specified. Similarly, while actions are shown in the drawings in a particular order, it should be recognized that such actions do not need to be performed in the particular order shown or in a sequential order, or that not all shown actions need to be performed, in order to achieve the desired result. Furthermore, drawings may schematically illustrate further exemplary processes in the form of flowcharts. However, other actions not illustrated may be incorporated into the exemplary methods and processes schematically shown. For example, one or more additional actions may be performed before, after, simultaneously with, or in between any of the illustrated actions.Furthermore, the operations may be rearranged or reordered in other embodiments. In certain situations, multitasking and parallel processing may be advantageous. Also, the separation of various system components in the above embodiments should not be understood as requiring such separation in all embodiments, and the program components and systems described may generally be integrated together in a single software product or packaged in multiple software products. Furthermore, other embodiments are within the scope of the following claims. In some cases, the operations enumerated in the claims may be executed in a different order and may still achieve the desired results.

[0114] Furthermore, while various modifications and alternative forms are possible for the methods and apparatus described herein, specific examples are shown in the drawings and described in detail herein. However, it should be understood that this disclosure is not limited to any particular form or method disclosed, but rather encompasses all modifications, equivalents, and alternatives that fall within the spirit and scope of the various embodiments and accompanying claims described herein. Furthermore, any particular features, aspects, methods, characteristics, properties, qualities, attributes, elements, or similar disclosures relating to an implementation or embodiment may be used in all other implementations or embodiments described herein. None of the methods disclosed herein need to be performed in the order listed. The methods disclosed herein may include specific actions performed by practitioners, however, the methods may include any third-party instructions for those actions, expressly or implicitly. The scope disclosed herein also includes any overlaps, sub-scopes, and combinations thereof. Language such as “up to,” “at least,” “greater than,” “less than,” and “between” includes the numbers listed. Numbers preceded by terms such as "about" or "approximately" include the listed numbers and should be interpreted on a contextual basis (e.g., as accurately as reasonably possible under the circumstances, e.g., ±5%, ±10%, ±15%). Phrases preceded by terms such as "substantially" include the listed phrases and should be interpreted on a contextual basis (e.g., as accurately as reasonably possible under the circumstances). For example, "substantially constant" includes "constant". Unless otherwise specified, all measurements are under standard conditions, including temperature and pressure.

[0115] Where used herein, the phrase “at least one of” in a list of items refers to any combination of those items, including a single component. For example, “at least one of A, B, or C” is intended to include A, B, C, A and B, A and C, B and C, and A, B and C. Conjunctions such as the phrase “at least one of X, Y, and Z” are understood, unless otherwise specified, to be used in contexts where they are commonly used to convey that an item, term, etc., may be at least one of X, Y, or Z. Thus, such conjunctions are not generally intended to imply that a particular embodiment requires at least one of X, at least one of Y, and at least one of Z to exist, respectively. Headings provided herein, where present, are for convenience only and do not necessarily affect the scope or meaning of the apparatus and methods disclosed herein.

[0116] Accordingly, the claims are not intended to be limited to the embodiments shown herein, but should be given the broadest scope that is consistent with the disclosures, principles, and novel features disclosed herein.

Claims

1. A packaged integrated circuit device with heat dissipation for power surges, A semiconductor die having a first side and a second side, wherein the second side is on the opposite side from the first side, The lead frame of the first side surface of the semiconductor die, which is embedded in the molding material, A heat spreader on the second side surface of the semiconductor die, having a thickness of at least 2.5 millimeters, A packaged integrated circuit device comprising the above features.

2. The packaged integrated circuit device according to claim 1, wherein the heat spreader and the lead frame are configured to maintain the semiconductor die at a temperature of less than 200 degrees Celsius when subjected to a surge load of up to 160 watts for one second from a steady state.

3. The packaged integrated circuit device according to claim 1 or 2, wherein the thickness of the heat spreader is at least four times the thickness of the semiconductor die, the area of ​​the heat spreader is larger than the area of ​​the semiconductor die, and the heat spreader extends beyond the semiconductor die.

4. The packaged integrated circuit device according to claim 3, wherein the thickness of the heat spreader is 4 to 20 times the thickness of the semiconductor die.

5. The packaged integrated circuit device according to claim 1, wherein the thickness of the heat spreader is at least 2.5 times the thickness of the lead frame.

6. The packaged integrated circuit device according to any one of claims 1 to 5, wherein the packaged integrated circuit device has a recess in the molding material on the side of the packaged integrated circuit device opposite to the heat spreader.

7. The packaged integrated circuit device according to any one of claims 1 to 6, wherein both the lead frame and the heat spreader are bonded to the semiconductor die.

8. The packaged integrated circuit device according to any one of claims 1 to 7, wherein the semiconductor die comprises a field-effect transistor.

9. The packaged integrated circuit device according to claim 8, wherein the field-effect transistor is a gallium nitride field-effect transistor.

10. The packaged integrated circuit device according to any one of claims 1 to 9, wherein the lead frame comprises a main frame and a plurality of leads extending from the main frame, and each of the plurality of leads is flat on the outside of the molding material.

11. The packaged integrated circuit device according to claim 10, wherein each of the plurality of leads has a wettable flank.

12. The packaged integrated circuit device according to any one of claims 1 to 11, wherein the heat spreader is a solid layer containing copper.

13. The packaged integrated circuit device according to any one of claims 1 to 11, wherein the heat spreader has a multilayer structure comprising a first metal layer, a second metal layer, and a ceramic layer positioned between the first metal layer and the second metal layer.

14. An integrated circuit assembly with power surge heat dissipation, Printed circuit board and A packaged integrated circuit device on a printed circuit board, wherein the packaged integrated circuit device comprises a semiconductor die, a lead frame positioned between the semiconductor die and the printed circuit board, and a heat spreader positioned on the side of the semiconductor die opposite to the lead frame, the thickness of the heat spreader being at least 2.5 millimeters, A cooling structure that is in thermal contact with the heat spreader, An integrated circuit assembly comprising:

15. The integrated circuit assembly according to claim 14, wherein the packaged integrated circuit device comprises a molding material or other separator for providing electrical and / or thermal insulation between the printed circuit board and the lead frame.

16. The integrated circuit assembly according to claim 15, wherein the packaged integrated circuit device has a recess in the molding material on the side facing the printed circuit board.

17. The integrated circuit assembly according to claim 14, further comprising a second packaged integrated circuit device on the printed circuit board, the second packaged integrated circuit device comprising a second heat spreader that is in thermal contact with the cooling structure.

18. The integrated circuit assembly according to any one of claims 14 to 17, wherein the cooling structure comprises a heat sink and / or a cooling plate.

19. A packaged integrated circuit device with heat dissipation for power surges, A semiconductor die having a first side and a second side, wherein the second side is on the opposite side from the first side, and comprising a field-effect transistor, The lead frame of the first side surface of the semiconductor die, which is embedded in the molding material, A cooling structure for the second side surface of the semiconductor die, wherein the cooling structure comprises two metal layers and a ceramic layer positioned between the two metal layers, and the thickness of the cooling structure exceeds 2.5 millimeters. A packaged integrated circuit device comprising the above features.

20. The packaged integrated circuit device according to claim 19, wherein the thickness of the cooling structure is at least 2.5 times the thickness of the lead frame.

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